JP2011003265A - Circuit and method for controlling voltage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage control circuit which holds a predetermined voltage over a long time by reducing a leak current.SOLUTION: The circuit includes: a plurality of capacitors; a first switch provided corresponding to each capacitor to alternatively connect each capacitor to predetermined node; and a reset transistor which resets the node in accordance with a reset signal and can apply a back-bias when the reset signal is not supplied. Thus, the leak current is made minimum and the predetermined voltage is held in long time.

Description

  The present invention relates to a voltage control circuit and a semiconductor device. More specifically, the present invention relates to a voltage control circuit capable of accurately controlling a constant voltage and a semiconductor device including the same.

  In a nonvolatile semiconductor memory device, data is written by a program operation for injecting charges into the gate of the memory cell transistor, and data is erased by an erase operation for removing charge from the gate of the memory cell transistor. This program operation and erase operation are executed by applying a predetermined voltage corresponding to each operation to the gate, drain and source terminals of the memory cell transistor.

  In order to inject charges into the gate or to extract charges from the gate, generally a voltage higher than an external power supply voltage supplied from the outside of the nonvolatile semiconductor memory device is required. It is generated by boosting the external power supply voltage by an internal booster circuit. When a boosted voltage generated by the booster circuit consumes a current accompanying an erase operation or a program operation in the memory cell array circuit, the potential drops due to the influence of the current consumption. Therefore, it is necessary to monitor the boosted voltage to check whether a predetermined potential is maintained at any time. A voltage control circuit is used for this purpose. Patent Documents 1 and 2 have been proposed as conventional techniques using such a voltage control circuit.

  Some voltage control circuits use a capacitance dividing circuit for high voltage control. FIG. 1 is a diagram showing a voltage control circuit including a conventional capacity dividing circuit. As shown in FIG. 1, the conventional voltage control circuit 1 includes a PMOS transistor 2, NMOS transistors 3 to 5, a comparison circuit 6, selection transistors 7 to 12, capacitors CA and CB, and capacitors CC to CC32. Here, the capacitance of the capacitor CC is CC, and the capacitance of the capacitor CCk (for example, CC16) is k × CC (for example, 16CC). Reference numeral 13 denotes an internal booster circuit. The selection transistors 7 to 12 are constituted by NMOS transistors. Cpara represents the source / drain junction parasitic capacitance of the selection transistors 7 to 12 (hereinafter simply referred to as “junction parasitic capacitance”).

The capacitors CC to CC32 are connected to the node N1 via the selection transistors 7 to 12. Divided voltage VPPDIV is generated by capacitively dividing boosted voltage VPP.
This divided voltage VPPDIV is input to the comparison circuit 6. The comparison circuit 6 compares the reference voltage VREF and the divided voltage VPPDIV and outputs a signal Vout. When the divided voltage VPPDIV is higher than the reference voltage VREF, the signal Vout becomes, for example, High, and the boosted potential is too high, so that the voltage is lowered by the discharge operation.

  In the step program method, the signals SEL1 to SEL6 for controlling the gates of the selection transistors 7 to 12 are counted in binary, and the boosted voltage VPP increases in equal steps. Here, the voltage that is the target of the boosted voltage VPP is calculated as shown in the following equation (1) assuming an ideal circuit.

  VPP = VREF (1+ (CB + (CC + 2CC +...) / CA) (1)

Japanese Patent Publication JP-A-6-259799 US Pat. No. 5,291,446

  However, if the junction parasitic capacitance of the selection transistors 7 to 12 is Cpara, the actually generated boosted voltage VPP is expressed by the following equation (2).

VPP = VREF (1+ (CB + (CC + 2CC +...) + Cpara) / CA) (2)
Since the junction parasitic capacitance Cpara of the selection transistors 7 to 12 is caused by the layout, it is very difficult to adjust the target voltage in consideration of this capacitance. As described above, the junction parasitic capacitance Cpara of the selection transistor increases as the number of selection transistors increases. For example, in the case of adding a 3CC capacitor to the node N1, the signals SEL1 and SEL2 are set High (transistors 7 and 8 are on), and the other transistors are off. Then, all the junction capacitances of the four off transistors for the capacitors CC4 to CC32 that are not used are added to the node N1. For this reason, it is difficult for a conventional voltage control circuit to control and maintain a constant voltage with accuracy in mv units. Therefore, the boosted voltage VPP cannot be accurately controlled.

  In addition, since the total number of capacitors is increased, the reset transistor 3 is also large, and there is a problem that the divided voltage is not kept constant for a long time due to an off-state leakage current.

  Accordingly, the present invention has been made in view of the above problems, and an object thereof is to provide a voltage control circuit and a semiconductor device capable of accurately controlling and holding a constant voltage. It is another object of the present invention to provide a voltage control circuit and a semiconductor device that can keep the divided voltage constant for a long time.

  The present invention provides a plurality of capacitors, a first switch provided corresponding to each of the capacitors and selectively connecting the capacitors to a predetermined node, and resetting the node in response to a reset signal. A voltage control circuit including a reset transistor that is back-biased when no signal is supplied. According to the present invention, by applying a back bias to the reset transistor connected to the node, the leakage current can be minimized and a constant voltage can be maintained for a long time.

  According to the present invention, in the above configuration, each of the first switches includes a transistor to which a potential obtained by boosting an external potential is supplied to a gate. According to the present invention, the junction capacitance of the transistor can be further reduced, and a constant voltage can be accurately controlled and maintained. In the above structure, a potential obtained by boosting the external potential is supplied to the gate of the reset transistor.

  The present invention further includes a step of controlling a plurality of first switches provided in each of the plurality of capacitors and selectively connecting the plurality of capacitors to a predetermined node; and the predetermined node in response to a reset signal. Back-biasing the reset transistor to be reset when there is no reset signal. This configuration may further include a step of setting a gate of a transistor included in each of the plurality of first and second switches to a potential obtained by boosting an external voltage.

  According to the present invention, it is possible to provide a voltage control circuit and a semiconductor device that can accurately control and hold a constant voltage. Further, it is possible to provide a voltage control circuit and a semiconductor device that can keep the divided voltage constant for a long time.

It is a figure which shows the voltage control circuit containing the conventional capacity | capacitance division circuit. It is a block diagram which shows schematic structure of the semiconductor device which concerns on a present Example. It is a figure which shows the voltage control circuit which concerns on a present Example. It is a figure which shows the comparison circuit which concerns on a present Example. It is a figure which shows the internal voltage booster circuit which concerns on a present Example. It is a clock waveform of signals PHI1 to PHI2B. It is a figure which shows the voltage shift circuit which concerns on a present Example. It is a figure which shows the voltage control circuit which concerns on a present Example.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 2 is a block diagram showing a schematic configuration of the semiconductor device according to the present embodiment. As shown in FIG. 2, the semiconductor device 20 includes a control circuit 21, a command register 22, an I / O control circuit 23, an address register 24, a status register 25, a memory cell array 26, a row address decoder 27, a row address buffer 28, It includes a column decoder 29, a data register 30, a sense amplifier 31, a column address buffer 32, a logic control 33, a ready / busy register 34, an internal booster circuit 35, a voltage control circuit 36, an internal booster circuit 100, and a voltage control circuit 101.

  The semiconductor device 20 may be a semiconductor memory device such as a flash memory packaged alone, or may be incorporated as a part of the semiconductor device like a system LSI. The logic control 33 receives control signals such as chip enable / CE, command latch enable CLE, address latch enable ALE, write enable / WE, read enable / RE, write protect / WP, spare area enable / SE from the outside, and these A logic control signal is supplied to the control circuit 21 based on the control signal.

  The I / O control circuit 23 exchanges input / output signals I / O0 to I / O7 with the outside. The I / O control circuit 23 receives an address signal, a data signal, and a command signal from the outside, and supplies the address signal to the address register 24, the data signal to the data register 30, and the command signal to the command register 22. The address register 24 supplies the row address to the row address buffer 28 and supplies the column address to the column address buffer 32.

  The control circuit 21 receives a logic control signal from the logic control 33 and also receives a command from the command register 22 and operates as a state machine based on these logic control signal and command, and controls the operation of each part of the semiconductor device 20. To do. The control circuit 21 controls the memory cell array 26, the row address decoder 27, the column decoder 29, and the like in order to read data from the address of the memory cell array 26 indicated by the address register 24.

  In addition, the control circuit 21 controls the memory cell array 26, the row address decoder 27, the column decoder 29, and the like in order to write data to the write address of the memory cell array 26. In addition, the control circuit 21 controls the memory cell array 26, the row address decoder 27, the column decoder 29, and the like in order to erase a specified area of the memory cell array 26 in a predetermined unit.

  The memory cell array 26 includes an array of memory cell transistors having different threshold values, word lines, bit lines, and the like, and stores data in each memory cell transistor. At the time of data reading, data from the memory cell specified by the activated word line is read to the bit line. At the time of programming or erasing, the word line and the bit line are set to appropriate potentials according to the respective operations, thereby executing the charge injection or charge extraction operation for the memory cells.

  The sense amplifier 31 operates under the control of the control circuit 21, and the data current supplied from the memory cell array 26 is compared with the reference current according to the designation by the row address decoder 27 and the column decoder 29, so that the data becomes 0. Or 1 is determined. The determination result is stored as read data in the data register 30 and is further supplied from the data register 30 to the I / O control circuit 23.

  Further, in the verify operation accompanying the program operation and the erase operation, the current of data supplied from the memory cell array 26 in accordance with the designation by the row address decoder 27 and the column decoder 29 is compared with the reference current for program verify and erase verify. Is done. In the program operation, write data is stored in the data register 30, and charge injection into the memory cell is executed by setting the word line and bit line of the memory cell array 26 to appropriate potentials based on this data. The status register 25 is a register for storing status information related to the operation of the semiconductor device 20. By reading the contents of the register from the outside via the I / O control circuit 23, the device is in a ready state or a write protection mode. Or whether a program / erase operation is in progress. The ready / busy register 34 stores a flag indicating whether the device is ready or busy, and in response to this, a ready / busy signal is output to the outside.

  The internal booster circuit 35 is a circuit that generates a boosted voltage VPP used for a program operation and an erase operation based on an external potential. The boosted voltage VPP generated by the internal booster circuit 35 is supplied to the row address decoder 27, the memory cell array 26, and the like, and is also supplied to the voltage control circuit 36. The voltage control circuit 36 monitors the boosted potential VPP generated by the internal booster circuit 35 and controls the internal booster circuit 35 so that the boosted potential VPP maintains a predetermined potential. For example, when the boosted potential is higher than a predetermined potential, the voltage step-down circuit is operated and the boosted potential is stepped down by the discharge operation.

  The internal booster circuit 100 generates a 9v boosted potential VDD based on, for example, a 3v external potential VCC. This boosted voltage VDD is supplied to the column decoder 29 and the selection transistor of the voltage control circuit 36. The voltage control circuit 101 monitors the boosted potential VDD generated by the internal booster circuit 100, and controls the internal booster circuit 100 so that the boosted potential VDD maintains a predetermined potential.

  Next, the voltage control circuit 36 will be described. FIG. 3 is a diagram showing a voltage control circuit 36 according to the embodiment. As shown in FIG. 3, the voltage control circuit 36 includes a PMOS transistor 50, NMOS transistors 51 to 53, a comparison circuit 54, an inverter 55, selection transistors 56 to 66, capacitors CA and CB, capacitors CC to CC32, a circuit 67, and 68. The voltage control circuit 36 is a circuit that divides the boosted voltage VPP by capacitance, compares it with a reference voltage, controls the boosted voltage to a constant voltage, and holds it.

  Capacitors CA and CB have one end connected to node N1, the other end connected to a boosted voltage (VPP) line via PMOS transistor 50, and the other end connected to ground voltage line. . Capacitors CA and CB form a divider circuit that generates divided potential VPPDIV at node N1 by dividing boosted potential (first potential) VPP received by the boosted voltage line (first terminal). Capacitor CA is arranged on the high voltage side of divided potential VPPDIV, and capacitor CB is arranged on the low voltage side of divided potential VPPDIV. A resistor may be used in place of the capacitors CA and CB. The capacitors CC to CC32 are connected to the node N1 through selection transistors 56 to 66. Here, the capacitance of the capacitor CC is CC, and the capacitance of the capacitor CCk (for example, CC16) is k × CC (for example, 16CC). Therefore, the plurality of capacitors includes a capacitor having a power value that is a power of the capacitor CC having the minimum capacitance value.

  The selection transistors 56 to 66 are NMOS transistors. The selection transistors 56 to 61 connect only the capacitor to be used among the capacitors CC to CC32 to the node N1. The selection transistors 62 to 66 are arranged so that only the transistors to be used among the selection transistors 56 to 61 are connected to the node N1. For example, the selection transistor 56 for selecting the capacitor CC is connected to the node N1 via the corresponding selection transistor 62, and the selection transistor 57 for selecting the capacitor CC2 is connected to the node N1 via the corresponding selection transistor 63 and the selection transistor 62. It is connected to the. In the case where the capacitor 3CC is attached to the node N1, the transistors 56, 57, 62, and 63 are on and the other selection transistors are off. However, the junction capacitance of only the transistor 64 is added to the node N1 as the off transistor. No other off-transistor capacitance is added. In this way, the influence of the junction parasitic capacitance Cpara of the selection transistors 56 to 61 can be minimized. The gates of the selection transistors 56 to 66 are controlled by signals SEL1 to SEL6 or signals SELG1 to SELG5. The signals SEL1 to SEL6 are supplied from the control circuit 21.

  The circuits 67 and 68 are supplied to the selection transistors 62 to 66 from the first control signals SEL1 to SEL6 supplied to the selection transistors 56 to 61 in order to select the capacitor connected to the node N1 from among the capacitors CC to CC32. This is a circuit for generating the second control signals SELG1 to SELG5. The circuit 67 includes NOR circuits 671 to 673 and inverters 674 to 676. Inverter 674 receives signal SEL5 and signal SEL6 subjected to NOR processing by NOR circuit 671, and generates signal SELG5. Inverter 675 receives signal SELG5 and signal SEL4 subjected to NOR processing by NOR circuit 672, and generates signal SELG4. Inverter 676 receives signal SELG4 and signal SEL3 subjected to NOR processing by NOR circuit 673, and generates signal SELG3.

  Circuit 68 includes NOR circuits 681 and 682 and inverters 683 and 684. Inverter 683 receives signal SELG3 and signal SEL2 subjected to NOR processing by NOR circuit 681, and generates signal SELG2. Inverter 684 receives signal SELG2 and signal SEL1 subjected to NOR processing by NOR circuit 682, and generates signal SELG1. By changing the control signals SEL1 to SEL6 or the control signals SELG1 to SELG5 and connecting the capacitors CC to CC32 to the node N1, the divided voltage VPPDIV decreases according to the added capacitance value.

  When the capacitor CC is connected to the node N1, the selection transistors 56 and 62 are turned on. When the capacitors CC and CC2 are connected to the node N2, the selection transistors 56, 57, 62 and 63 are turned on. Further, when the capacitors CC to CC4 are connected to the node N1, the selection transistors 56, 57, 58, 62, 63 and 64 are turned on. In order to connect the capacitors CC to CC32 to the node N1, the selection transistors 56 to 66 are similarly turned on. In this embodiment, when only the capacitor CC is selected, that is, when only the signal SEL1 and the signal SELG1 are High, the junction parasitic capacitance Cpara of the selection transistor is minimized, and only the capacitor CC16 or CC32 is selected, that is, the signal SEL60 and the signals SELG62 to 66 or When the signals SEL61 to 66 are set to High, the junction parasitic capacitance Cpara is maximized. Further, in the case where all the capacitors CC to CC32 are selected, even if all the selection transistors are selected, the total capacitance of the capacitors used is considerably large, so that the influence of the parasitic capacitance becomes relatively invisible. That is, the allowable junction parasitic capacitance Cpara of the select transistor increases as the total capacitance of the used capacitors increases.

  In this embodiment, the number of selection transistors connected to the node N1 is larger than the conventional example in some cases, but the junction capacitance of the transistor is much smaller when it is on than when it is off. The influence on the boosted voltage VPP due to the increase in the number of select transistors in the on state is relatively small. Accordingly, the boosted voltage VPP can be held for a long time by the configuration of the present invention.

  Further, in the present embodiment, by applying a back bias to the reset transistor 51 connected to the node N1, a leakage current flowing from the node N1 to the ground voltage line VSS during a period in which the voltage is controlled and held is suppressed. The reset transistor 51 resets the node N1 in response to the reset signal, and is back biased when the reset signal is not supplied. In order to maintain the boosted voltage VPP for a long time with accuracy in units of mv, it is very effective to minimize this leakage current. The gates of the selection transistors 56 to 66 are controlled by, for example, a 9v boosted potential VDD obtained by boosting a 3v external potential VCC. The boosted potential VDD is supplied from the internal booster circuit 100 as a power source for the voltage shift circuit 102 shown in FIG. 7 and the circuits 67 and 68 shown in FIG. The VCC level signal SEL from the control circuit 21 is input to the input IN of the voltage shift circuit 102 to generate a VDD level signal SEL. Further, a signal SELG of the VDD level is generated from the signal SEL. In this way, by controlling the gates of the selection transistors 56 to 66 with the 9v boost voltage VDD obtained by boosting the 3v power supply voltage VCC, the junction capacitances of the selection transistors 56 to 66 can be further reduced. Further, the gate of the reset transistor 51 may be controlled by a boosted potential obtained by boosting the external potential VCC.

  Comparison circuit 54 compares reference voltage VREF and divided voltage VPPDIV, and outputs signal Vout. When the divided voltage VPPDIV is higher than the reference voltage VREF, the signal Vout becomes, for example, High, and the boosted potential is too high, so that the voltage is lowered by the discharge operation. Feedback control is performed so that the divided voltage VPPDIV becomes equal to the reference voltage VREF.

  Next, the comparison circuit 54 will be described. FIG. 4 shows a comparison circuit 54 according to the present embodiment. As shown in FIG. 4, the comparison circuit 54 includes PMOS transistors 541 to 546, NMOS transistors 547 to 551, and inverters 552 to 574. NMOS transistor 550 is an input transistor that receives divided potential VPPDIV in FIG. In this configuration, when the divided potential VPPDIV is higher than the reference potential VREF, the output potential Vout becomes High due to the differential amplification operation.

  Next, the internal booster circuit 35 will be described. FIG. 5 shows an internal booster circuit 35 according to the present embodiment. FIG. 6 shows clock waveforms of the signals PHI1 to PHI2B. As shown in FIG. 5, the internal booster circuit 35 includes capacitors 363 to 370.

  Like the clock waveform in the figure, the signal PHI1, the signal PHI2, and the signals PHI1A to PHI2A are input to one electrode of the capacitors 363 to 370. A more efficient step-up operation is possible by slightly shifting the phases.

  Each basic pump cell includes a pair of capacitors 363 and 364, 365 and 366, 367 and 368, 369 and 370, and three NMOS transistors 350-352, 353-355, 356-358, 359-361. The step-up operation is repeated from the basic pump cell at the first stage to the basic pump cell at the final stage, and the high voltage high_voltage is output from the output through the transistor 362 for preventing the backflow of current.

  Next, the voltage control circuit 101 will be described. FIG. 8 is a diagram showing the voltage control circuit 101. As shown in FIG. 8, the voltage control circuit 101 includes PMOS transistors 102 and 113, NMOS transistors 103 to 105, a comparison circuit 106, selection transistors 107 to 112, capacitors CA and CB, and capacitors CC to CC32. The voltage control circuit 101 is connected to the internal booster circuit 100 and the voltage shift circuit 120. In FIG. 2, the voltage shift circuit 120 is omitted.

  The divided voltage VDDDIV is generated by capacitively dividing the boost voltage VDD. This divided voltage VDDDIV is input to the comparison circuit 106. Comparing circuit 106 compares reference voltage VREF and divided voltage VPPDIV, and outputs signal Vout. When the divided voltage VDDDIV is higher than the reference voltage VREF, the signal force Vout becomes, for example, High, and the boosted potential is too high, so that the voltage is lowered by the discharge operation. The gate of the PMOS transistor 113 is controlled by the voltage shift circuit 120. The voltage shift circuit 120 is configured in the same manner as the voltage shift circuit 102 shown in FIG. That is, voltage shift circuit 120 includes PMOS transistors 250 and 251, NMOS transistors 252 and 253, and inverters 254 and 255.

  The gates of the selection transistors 56 to 66 of the voltage control circuit 36 described above are controlled by the boosted voltage VDD from the PMOS transistor 113. As described above, the gates of the selection transistors 56 to 66 of the voltage control circuit 36 are controlled by the boost voltage VDD of 9v higher than the power supply voltage VCC of 3v, for example, thereby further reducing the junction capacitance of the selection transistors 56 to 66. Can do. The internal booster circuit 100 can be configured in the same manner as the internal booster circuit 35 shown in FIG.

  This embodiment has the following effects. Since the boosted voltage VPP is used for various purposes such as programming and erasing, it is controlled to various voltage values. In particular, in a product having multi-valued memory cells, a method of increasing the step-up voltage VPP at the time of programming step by step is frequently used, so that a large number of capacitors added to the divided voltage VPPDIV and their selection transistors are required. It is coming. Here, as the number of selection transistors increases, the boost voltage VPP does not match the calculated value due to the junction parasitic capacitance of the selection transistor, and the boost voltage VPP is held constant for a long time due to the junction leakage of the selection transistor. Becomes increasingly difficult.

  If the total capacitance of the capacitor increases, the size of the transistor for resetting it must also be increased, and the minute leakage current in the OFF state of the reset transistor makes it difficult to maintain the boosted voltage VPP for a long time. In the present invention, the number of selection transistors is minimized by contriving the connection method to solve the problems of parasitic capacitance and junction leakage. Further, the boost voltage VPP can be held for a long time by applying a back bias to the reset transistor in the off state and minimizing the leakage current.

  The capacitors CC to CC32, transistors 56 to 61, and transistors 62 to 66 correspond to the capacitance, the first switch, and the second switch in the claims, respectively.

  Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. Is possible.

Claims (5)

Multiple capacities,
A first switch provided corresponding to each of the capacitors and selectively connecting each of the capacitors to a predetermined node;
And a reset transistor that resets the node in response to a reset signal and is back-biased when the reset signal is not supplied. 2. The voltage control circuit according to claim 1, wherein each of the first switches includes a transistor to which a potential obtained by boosting an external potential is supplied to a gate. The voltage control circuit according to claim 2, wherein a potential obtained by boosting an external potential is supplied to the gate of the reset transistor. Controlling a plurality of first switches respectively provided on a plurality of capacitors and selectively connecting the plurality of capacitors to a predetermined node;
Back biasing a reset transistor that resets the predetermined node in response to a reset signal when there is no reset signal. 5. The method according to claim 1, further comprising: setting a gate of a transistor included in each of the plurality of first and second switches to a potential obtained by boosting an external voltage. 6. .

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