JP6744893B2 - Nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a word line driving method for a nonvolatile semiconductor memory device such as a flash memory.

A NAND type or NOR type flash memory or the like requires a high voltage during data read, program and erase operations. Normally, in a flash memory, a low power supply voltage is supplied from the outside, the supplied voltage is boosted by a charge pump, and the boosted voltage is used to generate a program voltage and an erase voltage. If the word line decoder includes a charge pump, the word line decoder becomes large due to the area occupied by the capacitors. Therefore, Patent Document 1 discloses a word line decoder in which the charge pump is omitted and the layout area is reduced. The word line decoder suppresses the driving voltage of the word line from dropping by self-boosting the word line enable signal for enabling the word line.

JP-A-2002-197882

Reading and programming in the flash memory is usually performed in page units. The word line selection circuit selects a block from the memory cell array by decoding the row address, and selects a word line in the selected block. FIG. 1 shows a block selection operation of the word line selection circuit. The voltage Vpp boosted by the charge pump circuit 10 is supplied to the level shifter 20, and the level shifter 20 outputs the output signal BDRV in response to the block selection signal BLKSEL which is the decoding result of the row address. The output signal BDRV of the level shifter 20 is commonly connected to the gate of the block selection transistor 30, and the block selection transistor 30 responds to the output signal BDRV by changing the voltage supplied from the voltage supply unit 40 to each word of the selection block 50. Supply to lines WL0 to WL31 and select gate lines SGD and SGS.

For example, when a program operation is performed, the voltage supply unit 40 supplies an intermediate voltage (eg, 10V) to each word line of the selected block, and then supplies a program voltage (eg, 25V) to the selected word line. An intermediate voltage (for example, 10V) is supplied to the selected word line, a drive voltage (for example, Vcc voltage or 5V) is supplied to the selected gate line SGD, and 0V is supplied to the selected gate line SGS. Further, the page buffer sense circuit supplies the potential corresponding to the data “0” or “1” to the bit line GBL. On the other hand, the level shifter 20 takes into consideration the voltage drop corresponding to the threshold value of the block selection transistor 30 and the back gate bias effect from the source when the block selection transistor 30 is turned on, so as to prevent the program voltage from decreasing. It is necessary to supply the output signal BDRV having a voltage higher than the program voltage (for example, 31 V) as the voltage of BDRV. Therefore, the charge pump circuit 10 must generate the boosted voltage Vpp of at least 31V.

In order to generate a high voltage (for example, 31V) by the charge pump circuit 10, it is necessary to increase the number of stages of the charge pump. In particular, if the external power supplied to the memory chip has a low voltage, the number of stages increases accordingly. However, when the number of stages of the charge pump circuit 10 is increased, the boosting efficiency is lowered, so that there are problems that the power consumption increases and the area occupied by the charge pump circuit 10 increases.

The present invention solves such a conventional problem, and an object of the present invention is to provide a nonvolatile semiconductor memory device that saves space and power.

A non-volatile semiconductor memory device according to the present invention includes a memory cell array including a plurality of blocks, and block selecting means for selecting a block of the memory cell array based on row address information. A plurality of select transistors connected to the line; a first circuit that charges a connection node connected to each gate of the plurality of selection transistors; and a first circuit that is connected to the first circuit and boosts the voltage of the connection node. A second circuit; and a supply means for supplying an operating voltage to one terminal of the plurality of selection transistors, wherein the connection node is subjected to the first boost by the operating voltage supplied by the supplying means. Then, the second boost is performed by the second circuit.

Preferably, the second circuit includes a capacitor connected to the connection node, and the second circuit supplies the voltage output from the first circuit to the capacitor. Preferably, the second circuit includes a first transistor connected between the first circuit and the first circuit, and when the first transistor is made conductive, the voltage output from the first circuit is the first voltage. Is supplied to the capacitor through the transistor. Preferably, the second circuit includes a second transistor connected between the second circuit and the first circuit, and when the second transistor is made conductive, the voltage output from the first circuit is the second voltage. Is charged to the connection node via the transistor. Preferably, the first circuit includes a level shifter that outputs the first voltage based on the high voltage supplied from the charge pump circuit. Preferably, the memory cell array includes blocks of m rows×n columns (m and n are integers of 2 or more), and the first circuit is common to blocks of one row. Preferably, each of the plurality of blocks includes a second circuit. Preferably, the operating voltage when the first boost is applied is an intermediate voltage for enabling the NAND string. Preferably, the supply means supplies the program voltage to the selected word line after the supply of the intermediate voltage, and the program voltage is supplied to the selected word line via the second boosted selection transistor.

A method of driving a word line in a nonvolatile semiconductor memory device according to the present invention charges a gate of each of a plurality of block selection transistors for selecting a block of a memory cell array with a first voltage in response to row address information. By supplying an operating voltage required for each word line to one terminal of the plurality of block selection transistors, the first voltage of each gate is boosted to a second voltage and connected to each gate. The step of boosting the second voltage to the third voltage through the capacitor by supplying the voltage to the capacitor is included.

Preferably, the voltage supplied to the capacitor is the first voltage. Preferably, the operating voltage is an intermediate voltage for making the NAND string conductive. Preferably, the first voltage is charged by the level shifter supplied with a high voltage from the charge pump circuit, and the boosting from the second voltage to the third voltage is performed by the booster circuit using the voltage output from the level shifter. Done.

According to the present invention, since the gate voltage of the select transistor connected to the word line is boosted in two steps, the voltage for charging the gate of the select transistor can be lowered. As a result, the high voltage generated by the booster circuit such as a charge pump can be made smaller than in the conventional case, and the exclusive area and power consumption of the booster circuit can be reduced.

It is a figure explaining operation|movement of the conventional word line selection circuit. It is a figure which shows the structure of the flash memory which concerns on the 1st Example of this invention. FIG. 3 is a circuit diagram showing a configuration of a NAND string of the memory cell array according to the first embodiment of the present invention. It is a figure which shows the structure of the word line selection circuit which concerns on the 1st Example of this invention. FIG. 3 is a waveform diagram illustrating the operation of the word line selection circuit according to the first embodiment of the present invention. FIG. 3 is a layout diagram showing a relationship between blocks and a block selection unit of the memory cell array according to the first exemplary embodiment of the present invention. FIG. 9 is a layout diagram showing the relationship between blocks and level shifters of the memory cell array according to the second embodiment of the present invention. It is a figure explaining the drive method of the word line of the selected block which concerns on the 2nd Example of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the preferred form, the invention is implemented in flash memory.

The configuration of the flash memory according to the first embodiment of the present invention is shown in FIG. As shown in the figure, the flash memory 100 includes a memory array 110 in which a plurality of memory cells are arranged in a matrix, an input/output buffer 120 connected to an external input/output terminal I/O and holding input/output data, and an input/output buffer 120. An address register 130 for receiving address data from the output buffer 120, a command unit 140 for receiving command data and an external control signal from the input/output buffer 120, and a row address information Ax from the address register 130 and a control unit 140 for controlling each unit. , A word line selection circuit 150 for selecting a block and a word line based on the decoding result of the row address information Ax, and holding or selecting data read from a page selected by the word line selection circuit 150. The page buffer/sense circuit 160 which holds the write data to the written page and the column address information Ay from the address register 130, and the selection of the data in the page buffer/sense circuit 160 based on the decoding result of the column address information Ay, etc. And a column selection circuit 170 for performing an internal voltage generation circuit for generating various voltages (write voltage Vpgm, pass voltage Vpass, read pass voltage Vread, erase voltage Vers, etc.) necessary for data read, program, erase, etc. And 180.

The memory array 110 has m memory blocks BLK(0), BLK(1),..., BLK(m−1) arranged in the column direction. A page buffer/sense circuit 160 is arranged near the block BLK(0). For example, as shown in FIG. 3, a plurality of NAND string units NU in which a plurality of memory cells are connected in series are formed in one memory block, and n+1 string units NU are arranged in a row direction in one memory block. It is arranged. The cell unit NU includes a plurality of memory cells MCi (i=0, 1,..., 31) connected in series and a bit line side selection connected to the drain side of the memory cell MC31 which is one end. It includes a transistor TD and a source line side selection transistor TS connected to the source side of the memory cell MC0 at the other end, and the drain of the bit line side selection transistor TD is connected to the corresponding one bit line GBL. The source of the selection transistor TS is connected to the common source line SL. Although FIG. 3 shows a typical cell unit, the cell unit may include one or more dummy cells in the NAND string, or may have a three-dimensional configuration.

A memory cell is typically formed of a source/drain which is an N type diffusion region formed in a P well, a tunnel oxide film formed on a channel between the source/drain, and a tunnel oxide film. And a floating gate (charge storage layer) and a control gate formed on the floating gate via a dielectric film. The memory cell may be an SLC type that stores 1 bit (binary data) or an MLC type that stores multiple bits.

The control gate of the memory cell MCi is connected to the word line WLi, and the gates of the selection transistors TD and TS are connected to the selection gate lines SGD and SGS parallel to the word line WL. When selecting a block based on the row address Ax, the word line selection circuit 150 selectively selects the selection transistors TD and TS via the selection gate signals SGS and SGD of the block according to a read operation, a program operation, an erase operation, and the like. And selectively drive the selected word line and the non-selected word line via the word lines WL0 to WL31.

In the read operation of the flash memory 100, a certain positive voltage is applied to the bit line, a certain voltage (for example, 0V) is applied to the selected word line, and a pass voltage Vpass (for example, 4.5V) is applied to the non-selected word line. Then, a positive voltage (for example, 4.5 V) is applied to the selection gate lines SGD and SGS, the bit line side selection transistor TD and the source line side selection transistor TS are turned on, and 0 V is applied to the common source line. In the program (write) operation, a high voltage program voltage Vpgm (15 to 25V) is applied to the selected word line, an intermediate potential (for example, 10V) is applied to the non-selected word line, and the bit line side selection transistor TD is turned on. , The source line side selection transistor TS is turned off, and the potential according to the data of “0” or “1” is supplied to the bit line GBL. In the erase operation, 0 V is applied to the selected word line in the block, a high voltage (for example, 20 V) is applied to the P well, and electrons in the floating gate are extracted to the substrate, thereby erasing data in block units.

Next, details of the word line selection circuit 150 of this embodiment will be described with reference to FIG. The word line selection circuit 150 includes a block selection unit 200 that selects a block of the memory cell array 110. The block selection unit 200 selects a block based on the decoding result of the row address Ax and drives the word line of the selected block. In the first embodiment, one block selection unit 200 is prepared for one block. For example, when the memory cell array 110 has 1028 blocks in the column direction, 1028 block selecting units 200 are prepared.

The block selection unit 200 includes a level shifter 210. The level shifter 210 inputs the high voltage Vpp boosted by the charge pump circuit and outputs the voltage PSV to the node N1 according to the block selection signal BLKSEL. That is, the level shifter 210 outputs the voltage PSV when the block selection signal BLKSEL is at the H level and outputs the voltage PSV when the block selection signal BLKSEL is at the L level in response to the block selection signal BLKSEL that is the result of decoding the row address. Do not output. The level shifter 210 is supplied with a high voltage Vpp from a charge pump circuit (not shown). However, preferably, the charge pump circuit of the present embodiment supplies a high voltage Vpp of 25 V to the level shifter 210, for example. The voltage Vpp is smaller than the high voltage Vpp (for example, 31 V) of the conventional charge pump circuit 10 shown in FIG.

The block selection unit 200 further includes a booster circuit 220 for boosting the voltage PASSVOLT of the node N2 connected to the gate of the block selection transistor 230. The booster circuit 220 includes four high breakdown voltage NMOS transistors Q1, Q2, Q3, and Q4, and a boosting capacitor Cb. The transistor Q1 is connected between the node N1 and the node N2 connected to the level shifter 210, and the gate thereof is supplied with the local clamp signal XT. The transistor Q2 is connected between the node N2 and GND, and its gate is supplied with a signal (/XT) which is the inverted local clamp signal XT. When the transistor Q1 turns on and the transistor Q2 turns off, the node N2 is charged with the high voltage PSV of the node N1 via the transistor Q1. On the other hand, when the transistor Q1 is turned off and the transistor Q2 is turned on, the electric charge of the node N2 is discharged to GND via the transistor Q2.

The transistor Q3 is connected between the node N1 and the node bst, and its gate is supplied with the local boost signal XB. The transistor Q4 is connected between the node bst and GND, and its gate is supplied with a signal (/XB) obtained by inverting the local boost signal XB. When the transistor Q3 turns on and the transistor Q4 turns off, the high voltage PSV of the node N1 is applied to the node bst. On the other hand, when the transistor Q3 turns off and the transistor Q4 turns on, the electric charge of the node bst is discharged to GND via the transistor Q4. The capacitor Cb is connected between the node bst and the node N2, and capacitively couples the node bst and the node N2. The size of the capacitor Cb is appropriately selected according to the load of the block selection transistor driven by the node N2, the required voltage, and the like.

The booster circuit 220 is preferably operated when a high voltage is required to drive the selected word line. For example, during the program operation, the local clamp signals XT and /XT and the local boost signals XB and /XB are selectively driven, the voltage PASSVOLT of the node N2 is boosted using the capacitor Cb, and the block selection transistor 230 selects the selected word. Ensure that the operating voltage supplied to the line does not drop. Preferably, when local clamp signals XT, /XT and local boost signals XB, /XB are driven to the H level, their voltage levels may be the same level as voltage PSV.

The node N2 of the booster circuit 220 is connected to the gate of the block selection transistor 230. Although only one block selection transistor 230 is illustrated in FIG. 4, in reality, as shown in FIG. 1, one terminal (source electrode) of the block selection transistor is in the block via the node N3. Are connected to the word lines WL0 to WL31 of the NAND string and the select gate lines SGD and SGS, respectively. Further, the other terminal (drain electrode) of the block selection transistor 230 is connected via a node N4 to a voltage supply unit that supplies an operating voltage for programming, reading, erasing, etc. (see FIG. 1). These block selection transistors 230 are composed of high breakdown voltage NMOS transistors.

Next, the operation of the block selection unit 200 of this embodiment will be described with reference to FIG. At time t1, the local clamp signal XT is at L level, /XT is at H level, the transistor Q1 is off, the transistor Q2 is on, and the node N2 is electrically connected to GND through the transistor Q2. Is in a state. Further, the local boost signal XB is at the L level and /XB is at the H level, the transistor Q3 is in the off state, the transistor Q4 is in the on state, and the node bst is electrically connected to the GND level.

At time t2, the block selection unit 200 drives the local clamp signal XT to the H level and /XT to the L level. As a result, the transistor Q1 is turned on, the transistor Q2 is turned off, and the node N2 is cut off from the GND.

At time t3, the block selection signal BLKSEL transitions to H level. In response to this, the level shifter 210 outputs the voltage PSV (for example, 25V) to the node N1 based on the high voltage Vpp from the charge pump circuit. Since the transistor Q1 is in the ON state, the node N2 is charged by the voltage PSV, and the voltage PASSVOLT becomes PSV-Vth level (Vth is the threshold value of the transistor Q1). In this way, the voltage PASSVOLT is supplied to each gate of the block selection transistor 230, the block selection transistor 230 is turned on, and the block is selected. The operation at time t3 may precede the operation at time t2.

At time t4, the voltage supply unit supplies the intermediate voltage (for example, 10 V) to all the word lines of the selected block to the block selection transistor 230 via the node N4. At this time, in all the block selection transistors 230 supplied with the intermediate voltage, the voltage PASSVOLT is self-boosted by the capacitive coupling C1 between the gate and drain. Further, when the block selection transistor 230 is turned on, the voltage PASSVOLT is further self-boosted by the gate-source capacitive coupling C2. By self-boosting all the block selection transistors 230, the intermediate voltage with suppressed voltage drop is supplied to all the word lines of the selected block.

At time t5, the block selection unit 200 drives the local boost signal XB to H level and /XB to L level. As a result, the transistor Q3 turns on, the transistor Q4 turns off, and the voltage PSV of the node N1 is applied to the node bst via the transistor Q3. The node bst rises from the GND level to the PSV-Vth level (Vth is the threshold value of the transistor Q3). Since the voltage of the node bst which is one electrode of the capacitor Cb rises, the voltage PASSVOLT of the node N2 which is the other electrode of the capacitor Cb is boosted by the capacitive coupling of the capacitor Cb. Therefore, the gate voltage PASSVOLT of the self-boosted block selection transistor 230 is further boosted (for example, 31V).

Next, at time t6, the voltage supply unit supplies the program voltage (for example, 25 V) to the selected word line. At this time, since the gate voltage PASSVOLT of the block selection transistor 230 is boosted higher than the program voltage, the program voltage is applied to the selected word line without being dropped by the block selection transistor 230.

Next, at time t7, the supply of the program voltage (selected word line) and the intermediate voltage (non-selected word line) from the voltage supply unit is stopped, the potential of the voltage PASSVOLT gradually drops, and at time t8, the block selection signal BLKSEL, local clamp signal XT, and local boost signal XB are driven to L level.

As described above, according to this embodiment, the voltage PASSVOLT applied to the gate of the block selection transistor 230 is boosted in two steps. Therefore, the target voltage PASSVOLT (selection It is possible to generate word line voltage+Vt of block selection transistor+back gate bias<PASSVOLT. Therefore, the number of stages can be reduced as compared with the conventional charge pump circuit, and the layout area and current consumption can be reduced.

Further, in the present embodiment, the transistor Q1 is interposed between the node N1 and the node N2, so that the source of the transistor Q1 has the voltage PSV, the gate has XT (XT=PSV), and the source and the gate have the same potential. Therefore, even if the transistor Q1 is cut off and the voltage PASSVOLT is further boosted, the voltage is clamped without leaking through the transistor Q1.

In the above embodiment, the voltage PASSVOLT is boosted by charging the node bst with the voltage PSV once, but the invention is not limited to this, and the voltage PASSVOLT may be boosted intermittently by charging a plurality of times. In this case, by supplying a plurality of pulses by the local boost signals XB and /XB, the transistors Q3 and Q4 are switched a plurality of times, and charging/discharging (GND, PSV-Vth, GND, PSV-Vth) of the node bst is repeated. it is, it is possible to repeat several times the step-up voltage PASSVOUT, length boosted voltage due to the leakage of the capacitor Cb during the operation of the time to charge again be lowered.

Further, the voltage PASSVOLT may be monitored, the voltage PASSVOLT may be compared with a desired target voltage, and the local boost signals XB and /XB may be applied to the transistors Q3 and Q4 to boost the voltage based on the comparison result. That is, if the voltage PASSVOLT is less than the target voltage, boosting may be performed by the local boost signals XB and /XB, and if it is equal to or higher than the target voltage, boosting may not be performed.

Further, the capacitor Cb connected to the node N2 can be preferably formed by a MOS capacitor. If the parasitic capacitance of the booster circuit 220 increases due to the capacitor Cb, it may hinder high-speed operation. Therefore, for example, a diode or transistor (turned on when boosting) is connected between the capacitor Cb and the node N2, and the node N2 is connected. The capacitance of the capacitor Cb may be hidden from the side.

Further, in the above-mentioned embodiment, the source of the transistor Q4 is connected to GND. However, if the source is at the GND level, the leakage of the transistor Q4 becomes large. Therefore, an inverter is connected between the transistor Q4 and GND, The local boost signal /XB may be supplied to the input of, or the source of the transistor Q4 may be connected to a voltage such as Vcc or the local boost signal XB. In this case, the latter (the direct boost signal XB is directly connected) can obtain a larger effect. The same applies to the transistor Q2. An inverter is connected between the transistor Q2 and GND to supply the local clamp signal /XT to the input of the inverter, or the source of the transistor Q2 is supplied with a voltage such as Vcc or It may be connected to the local clamp signal XT.

Next, a second embodiment of the present invention will be described. The block selection unit 200 shown in FIG. 4 can be arranged in each block of the memory cell array. For example, as shown in FIG. 6, when 1024 blocks_0 to block_1023 are arranged in the column direction, 1024 block selection units 200_0 to 200_1023 are arranged in the column direction. In the case of such a layout, the block selection unit 200 includes the level shifter 210 as shown in FIG. 4, so that 1024 level shifters 210 are arranged.

Since the level shifter 210 outputs the high voltage Vpp output from the charge pump circuit according to the block selection signal BLKSEL of the Vcc voltage level, it has a high withstand voltage low threshold depletion to mitigate the potential difference between the two. Type of NMOS transistor is used. This depletion transistor requires a large area because it requires a long channel length. As shown in FIG. 6, when 1024 level shifters are arranged, the occupied area increases, which may hinder the miniaturization of the memory chip. Therefore, in the second embodiment, the block selection unit can be shared by several blocks.

FIG. 7 is a diagram showing an arrangement example of the block selection unit according to the second embodiment of the present invention. As shown in the figure, when there are 1024 blocks, the blocks are arranged in the horizontal direction 8×vertical direction 128, and one level shifter is shared by the eight horizontal blocks. That is, the voltage PSV is supplied to the selected eight blocks in the horizontal direction by any one of the level shifters 210_0 to 210_127. In addition, to select any of the eight blocks in the horizontal direction, eight local clamp signals XT0 to XT7 (/XT0 to /XT7) and eight local burst signals XB0 to XB7 (/XB0 to /XB7) are selected. It is done by decoding. For example, if the local clamp signal XT0 and the local burst signal XB0 are selected, the block 0 is selected, and if the local clamp signal XT5 and the local burst signal XB5 are selected, the block 5 of eight blocks in the horizontal direction is selected. To be done.

FIG. 8 shows details of the block selection unit for selecting eight blocks arranged in the horizontal direction. One level shifter 210 shared by eight blocks responds to the H-level block selection signal BLKSEL to boost the voltage PSV of each block when the eight horizontal blocks are selected based on the row address. To 220_1 in common. As described above, the booster circuits 220_7 to 220_0 are selectively operated by the corresponding local clamp signal XT and local boost signal XB. The output voltage PASSVOLT of the booster circuits 220_7 to 220_0 is output to the corresponding block selection transistors 230_7 to 230_0, respectively. The voltage supply unit 300 individually outputs the global signal lines G_SGD, G_WL31 to G_WL0, and G_SGS to the block selection transistors 230_7 to 230_0. That is, it should be noted that the voltage supply unit 300 outputs global signal lines (8×G_SGD, 8×G_WL31 to 8×G_WL0, 8×G_SGS) according to the number of eight blocks.

For example, it is assumed that the level shifter 210_1 is selected and the block_0 in the horizontal direction is programmed. The local clamp signal XT0 is transited to the H level, the booster circuit 220_0 is turned on, and the level shifter 210 outputs the voltage PSV to the booster circuits 220_7 to 220_0 in response to the block selection signal BLKSEL. Since the transistor Q1 of the booster circuit 220_0 is on, the voltage PSV is taken into the booster circuit 220_0, and the voltage PASSVOUT is precharged to PSV-Vth by the voltage PSV. On the other hand, since the transistor Q1 of the booster circuits 220_7 to 220_1 is off, the voltage PSV is not taken into the booster circuit.

Next, the voltage supply unit 300 supplies the required operating voltage to the global word line G_WL. That is, the voltage supply unit 300 supplies the program voltage to the selected word line and the intermediate voltage to the non-selected word line. At this time, the voltage PASSVOLT of the node N2 of the booster circuit 220_0 is charged to PSV-Vth, and the gate of the block selection transistor 230_0 is self-boosted due to the supply of the program voltage. The block selection transistor 230_0 is turned on. On the other hand, since the voltage PASSVOLT of the booster circuits 220_7 to 220_1 is 0V, those block selection transistors 230_7 to 230_1 are off.

After that, when the local boost signal XB0 is asserted, the node bst of the booster circuit 220_0 rises from the GND level to the PSV-Vth level, and the node N2 is boosted via the capacitor Cb. That is, the voltage PASSVOLT is boosted to the operating voltage+Vth+back bias or more after the boosting in two steps.

As described above, in this embodiment, even if the depletion type level shifter having a large area is used, a small number of devices (4 transistors Q1, Q2, Q3, Q4, and capacitor Cb) are provided in each of the horizontal blocks. It is possible to share the level shifter among a plurality of horizontal blocks and reduce the area occupied by the level shifter simply by arranging. The configuration of FIG. 6 requires level shifter×1024 to decode 1024 horizontal blocks. When 8 horizontal blocks are shared as in the present embodiment, level shifter×128 (unit block selection)+16 (XT/XB decoder)=144 is required to decode 1024 horizontal blocks. This makes it possible to significantly reduce the area occupied by the X decoder.

In the present embodiment, the increase in the number of booster circuits sharing the PSV voltage from the level shifter suppresses charge sharing between the nodes N1 and N2 in the selected horizontal block when the local clamp signal XT is asserted. To work. Further, the source voltage of the transistor Q4 to which the local boost signal /XB is applied may be replaced with Vss by the local boost signal XB to suppress the leak from the node bst. The non-selected transistors Q2 and Q4 can use Vcc for the gate voltage, and can be easily manufactured from the XT and XB decoders. The highest PASSVOLT voltage is clamped by the junction BV, automatically protecting the BVox.

In the above embodiment, an example in which one block selection unit is shared by eight horizontal blocks is shown, but this is an example, and one block selection unit may be shared by a plurality of horizontal blocks. You can

As described above, the preferred embodiments of the present invention have been described in detail, but the present invention is not limited to the specific embodiments, and within the scope of the gist of the present invention described in the claims, Various modifications and changes are possible.

100: flash memory 110: memory cell array 120: input/output buffer 130: address register 140: control unit 150: word line selection circuit 160: page buffer/sense circuit 170: column selection circuit 180: internal voltage generation circuit 200: block selection unit 210: Level shifter 220: Boost circuit 230: Block selection transistor

Claims (12)

a memory cell array including a plurality of blocks of m rows×n columns,
Block selecting means for selecting a block of the memory cell array based on row address information,
The block selection means is a plurality of selection transistors connected to each word line of the block,
A first circuit for charging a connection node connected to each gate of the plurality of selection transistors;
Connected to said connection node, a second circuit voltage of the connection node to boost the connection node after being self boosting,
A supply means for supplying an operating voltage to one terminal of the plurality of selection transistors,
The connection node, after the self-boosting is performed by the operation voltage supplied by the supply means, is boosted by the second circuit is performed,
Said first circuit includes a level shifter for outputting a first voltage based on the high voltage, the first circuit is provided m times in each row, one of the first circuit of each row, the row direction n A first voltage is output to the n blocks of the selected row that are shared by the plurality of blocks to charge the connection nodes connected to the gates of the plurality of selection transistors, and m×n each block comprises the second circuit,
It said block selection means further includes a row block selection means for selecting a row of blocks on the basis of the row address, to one of the blocks in the n blocks of the row selected by the row block selection means A non-volatile semiconductor memory device including an operating means for selectively operating the second circuit. It said second circuit includes one capacitor electrode is connected to the connection node, a second circuit, the other with a voltage output from the first circuit is supplied to the other electrode of the capacitor The nonvolatile semiconductor memory device according to claim 1, wherein the connection node is boosted by increasing the voltage of the electrode of . Said second circuit includes a first transistor connected between said first circuit, when the first transistor is in a conductive state, the voltage output from the first circuit is a The nonvolatile semiconductor memory device according to claim 2, wherein the non-volatile semiconductor memory device is supplied to the other electrode of the capacitor through one transistor. The second circuit further includes a second transistor connected between the other electrode of the capacitor and a reference potential, the second transistor turning off or on when the first transistor turns on or off. By switching the first transistor and the second transistor on/off a plurality of times to repeat the charging/discharging of the other electrode of the capacitor a plurality of times, thereby performing the above-mentioned connection. 4. The nonvolatile semiconductor memory device according to claim 3, wherein boosting of the node is performed a plurality of times. The second circuit includes a third transistor connected between said first circuit, when the third transistor is conducting, the voltage output from the first circuit is a through the third transistor is charged to the connection node, a non-volatile semiconductor memory device according to 4 any one claims 1. 6. The nonvolatile semiconductor memory device according to claim 1, wherein the first circuit includes a level shifter that outputs a first voltage based on a high voltage supplied from a charge pump circuit. 7. The non-volatile semiconductor memory device according to claim 1, wherein the operating voltage when the self- boost is performed is an intermediate voltage for making a NAND string conductive. 8. The supply means according to claim 7, wherein the supply means supplies a program voltage to the selected word line after supplying the intermediate voltage, and the program voltage is supplied to the selected word line via the second boosted selection transistor. Nonvolatile semiconductor memory device. A memory cell array including a plurality of blocks of m rows×n columns, a plurality of m level shifters provided for each row, and a gate of a block selection transistor for boosting the gate after the gate is boosted by self boost. A booster circuit, the booster circuit is included in each of m×n blocks, and a level shifter for each row that supplies a first voltage based on a high voltage is shared by n blocks in the row direction. A method of driving a word line in a nonvolatile semiconductor memory device, comprising:
Select n blocks in the row direction based on the row address information,
For one block selected from among the selected said n blocks, the first voltage to each gate of the plurality of block selection transistors for selecting a block of the memory cell array to charge from said level shifter ,
Wherein the plurality of blocks one of the first voltage of the gates by supplying an operating voltage required for each word line to a terminal of the selection transistor is boosted by the self boosting in the second voltage,
Select the booster circuit of the one block selected from among the selected said n blocks, the voltage of the other electrode of the by the selected step-up circuit capacitor having one electrode to each gate of which is connected The method of driving a word line, comprising the step of increasing the second voltage of each gate to a third voltage via the capacitor by increasing the voltage. The method for driving a word line according to claim 9, wherein the voltage supplied to the other electrode of the capacitor is the first voltage. 11. The word line driving method according to claim 9, wherein the operating voltage is an intermediate voltage for enabling the NAND string to be conductive. The first voltage is charged by the level shifter which is supplied with high voltage from the charge pump circuit,
Wherein the second voltage step-up to the third voltage is performed by the booster circuit utilizing a voltage output from the level shifter, the driving method of the word line according to claim 9.

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