JP2007012694A - Semiconductor integrated circuit device of standard cell system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively remove noise on power wiring without increasing a chip size of a semiconductor chip. <P>SOLUTION: A semiconductor integrated circuit device is provided with circuit regions 12 which are formed in a synthesis part of the semiconductor chip and in which active elements are arranged, power wiring regions 13 where power wiring supplying power voltage to the circuit regions 12 is formed and capacitive elements 14 which are formed in the power wiring regions and remove noise on power wiring. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a standard cell type semiconductor integrated circuit device in which a capacitor element for power supply decoupling is formed in a semiconductor chip.

  In recent years, the circuit scale of a semiconductor integrated circuit (LSI) device has increased rapidly, and the current flowing through the semiconductor chip has increased. In addition, the power supply voltage is decreasing, and in high-performance semiconductor integrated circuit devices, countermeasures against noise on the power supply are important in order to prevent circuit malfunction and performance degradation.

  As countermeasures against such power supply noise, conventionally, a capacitor element is externally attached to a package of a semiconductor chip, a capacitor element using a metal wiring as an upper electrode is formed in a semiconductor chip, and a MOS is formed in a gap between circuit blocks. For example, a capacitor element using a transistor is formed.

  However, in order to prevent circuit malfunction and performance degradation, it is necessary to dispose a capacitive element in the vicinity of the MOS transistor for removing noise on the power supply.

  Furthermore, in the case of a so-called eDRAM (embedded DRAM) circuit in which a DRAM (Dynamic Random Access Memory) circuit and a logic circuit are mixedly mounted, conventionally, a DT (Deep Trench) used as a capacitor element is also formed according to the design rule of the DRAM circuit. Has been. Generally, a DRAM circuit is designed to operate with a power supply voltage higher than that used in a logic circuit. For this reason, the DT as a capacitive element and the logic circuit cannot be placed close to each other. When DT is used as a capacitive element for power supply decoupling of a logic circuit, the DT and the logic circuit need to be arranged close to each other. However, the capacity characteristics for power supply decoupling are deteriorated, the layout of the semiconductor chip is increased, and the chip size is increased.

Patent Document 1 describes a semiconductor integrated circuit device in which a capacitive element is formed under both power supply voltage wiring and ground voltage wiring.
JP 2000-101022 A

  The present invention has been made in consideration of the above-described circumstances, and the object thereof is a standard cell type semiconductor that can effectively remove noise on power supply wiring without increasing the chip size of the semiconductor chip. An integrated circuit device is provided.

  A standard cell type semiconductor integrated circuit device according to the present invention includes a semiconductor chip having a synthesis part and a custom part, a circuit area formed in the synthesis part of the semiconductor chip and provided with active elements, and at least a periphery of the circuit area A power supply wiring region provided with a power supply wiring for supplying a power supply voltage to the circuit region, and a capacitor element formed in the power supply wiring region for removing noise riding on the power supply wiring. .

  According to the standard cell type semiconductor integrated circuit device of the present invention, it is possible to effectively remove noise on the power supply wiring without increasing the chip size of the semiconductor chip.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a pattern plan view of a standard cell type semiconductor integrated circuit device according to the first embodiment of the present invention. In a standard cell type semiconductor integrated circuit device, a synthesis part and a custom part are formed on a semiconductor chip. The synthesizing part is a part where a circuit pattern is automatically generated using a CAD tool for automatic placement, and the custom part is a part where a circuit pattern is manually generated. Compared to the fact that the synthesis unit generated using the CAD tool is likely to be wasted in terms of area, the custom unit generated manually is not wasted. FIG. 1 shows only the portion of the semiconductor chip synthesis portion extracted.

  A circuit region 12 in which a plurality of standard cell arrays 11 are formed is disposed in the central portion of the semiconductor chip. In this example, a plurality of standard cell arrays 11 are formed in this circuit region 12 for two columns. As will be described later, for example, a plurality of MOS transistors are formed as active elements in each standard cell array 11. Further, between the standard cell arrays 11 that surround the circuit region 12 and are arranged in two columns, a power source having a high potential (Vdd) voltage and a ground voltage (Gnd) is supplied to each of the plurality of standard cell arrays 11. A power supply wiring region 13 in which a pair of power supply wirings for supplying a voltage is provided is formed.

  Further, a plurality of capacitor elements 14 for power supply decoupling for removing noise on the pair of power supply wirings are formed below the power supply wiring region 13. As shown in the equivalent circuit diagram of FIG. 2, the plurality of capacitive elements 14 are connected in parallel between a power supply wiring 21 for high potential (Vdd) and a power supply wiring 22 for ground voltage (Gnd). Wired to In FIG. 2, reference numeral 23 denotes a circuit configured using a plurality of standard cell arrays 11 arranged in the circuit region 12, and this circuit 23 operates with a voltage between the pair of power supply wires 21 and 22. .

  In the semiconductor integrated circuit device according to the first embodiment, a power supply decoupling capacitor element 14 for removing noise on a pair of power supply wirings is formed below the power supply wiring region 13. For this reason, the capacitive element 14 can be disposed in the vicinity of an active element, for example, a MOS transistor, thereby effectively removing noise on the pair of power supply wires 21 and 22.

  In addition, since the capacitive element 14 is formed below the power supply wiring region 13 of the combining portion, no extra space on the chip for forming the capacitive element 14 is necessary, and the chip size of the semiconductor chip is reduced. Capacitance element 14 can be formed without an increase.

  FIG. 3 is a pattern plan view showing a specific configuration of the standard cells in the standard cell array 11 in FIG. 1 together with a pair of power supply wirings.

  The standard cell 30 has an N well region (N-Well) 31 and a P well region (P-Well) 32 provided adjacent to each other. In the N-well region 31, a plurality of N-type diffusion regions 33 are formed that serve as the source and drain of the PMOS transistor. Further, in the P well region 32, a plurality of P type diffusion regions 34 serving as the source and drain of the NMOS transistor are formed. A gate electrode 35 of the MOS transistor is formed so as to be continuous between the pair of N-type diffusion regions 33 and between the pair of P-type diffusion regions 34.

  Further, an N-type diffusion region 36 for electrically connecting the N well region 31 to the power supply wire 21 is formed below the power supply wire 21 for high potential (Vdd). 36 is connected to the power supply wiring 21 through a plurality of contact portions 37. Similarly, a P-type diffusion region 38 for electrically connecting the P well region 32 to the power supply wiring 22 is formed below the power supply wiring 22 for ground potential (Gnd). The region 38 is connected to the power supply wiring 22 through a plurality of contact portions 39.

  The capacitive element 14 in FIG. 1 is formed at a location where the N-type diffusion region 36 or the P-type diffusion region 38 below the power supply wirings 21 and 22 is not formed. As the capacitive element 14, a plurality of small-sized capacitive elements may be formed and connected in parallel.

  4 shows an example of the capacitive element 14 formed below the power supply wirings 21 and 22, FIG. 4 (a) is a pattern plan view, and FIG. 4 (b) is a sectional view. This capacitive element uses a MOS transistor 45 provided with a source 41, a drain 42, a gate insulating film 43 and a gate electrode 44, and the source 41 and the drain 42 are short-circuited. A capacitance generated parasitically between the source / drain common connection node A and the gate electrode node B is used as the capacitive element 14. When a plurality of capacitive elements are formed and connected in parallel as described above, a plurality of MOS transistors having the configuration shown in FIG. 4 are formed.

  FIGS. 5A and 5B show another example of the capacitive element 14 formed below the power supply wirings 21 and 22. FIG. 5A is a pattern plan view and FIG. 5B is a cross-sectional view. This capacitive element is a DT capacitor in which a conductive layer 53 is formed on the inner peripheral surface of a DT (Deep Trench) 51 formed on a substrate via a capacitor insulating film 52. A capacitance generated between the node B of the deep well 54 formed inside the substrate is used as the capacitive element 14. When a plurality of capacitive elements are formed and connected in parallel as described above, a plurality of DT capacitors having the structure shown in FIG. 5 are formed.

  As the plurality of capacitive elements 14 in FIG. 1, only one of the capacitive element made of the MOS transistor shown in FIG. 4 or the capacitive element made of DT shown in FIG. May be used.

  FIG. 6 is a plan view of a pattern when the standard cell type semiconductor integrated circuit device according to the second embodiment of the present invention is implemented in an eDRAM semiconductor integrated circuit device. Also in this case, the synthesis part and the custom part are formed on the semiconductor chip, and FIG. 6 shows only the synthesis part part of the semiconductor chip.

  A circuit region 12 in which a DRAM circuit 71 and a logic circuit 72 are formed is disposed at the center of the semiconductor chip. For example, a plurality of MOS transistors are formed as active elements in the DRAM circuit 71 and the logic circuit 72, respectively. This MOS transistor has a source, a drain, a gate insulating film, and a gate electrode, for example, as shown in FIG. However, the wirings for the source, drain and gate electrodes are appropriately changed in order to achieve a desired circuit function.

  A power supply voltage including a high potential (Vdd) voltage and a ground voltage (Gnd) with respect to the DRAM circuit 71 and the logic circuit 72 and surrounding the circuit region 12 and between the DRAM circuit 71 and the logic circuit 72. A power supply wiring region 13 in which a pair of power supply wirings for supplying the power supply is provided is formed.

  Furthermore, a plurality of capacitor elements 14 for power supply decoupling for removing noise on the pair of power supply wirings are formed below the power supply wiring region 13. As shown in the equivalent circuit diagram of FIG. 2, the plurality of capacitive elements 14 are connected in parallel between a power supply wiring 21 for high potential (Vdd) and a power supply wiring 22 for ground voltage (Gnd). Wired to In this case, the circuit 23 in FIG. 2 corresponds to a mixed circuit including both the DRAM circuit 71 and the logic circuit 72, and the circuit 23 operates with the voltage between the pair of power supply wires 21 and 22.

  Also in the semiconductor integrated circuit device according to the second embodiment, the capacitor element 14 for power supply decoupling that removes noise on the pair of power supply wirings is formed below the power supply wiring region 13 in the synthesis region. The element 14 can be disposed in the vicinity of an active element, for example, a MOS transistor, thereby effectively removing noise on the pair of power supply lines.

  Further, when a capacitive element made of DT is used as the capacitive element 14 as shown in FIG. 5, this DT is formed in the power supply wiring region 13 different from the formation region of the DRAM circuit 71. Therefore, the capacitive element 14 made of DT formed around the logic circuit 72 can be formed in accordance with the design rule of the logic circuit 72.

  Also in this case, since the capacitor element 14 is formed below the power supply wiring region 13 in the combined region, an extra space on the chip for forming these capacitor elements 14 is unnecessary, and the semiconductor chip The capacitive element 14 can be formed without increasing the chip size.

  Also in the case of the second embodiment, as the capacitive element 14, only one of the capacitive element made of the MOS transistor shown in FIG. 4 or the capacitive element made of DT shown in FIG. 5 may be used. Or you may use both together.

  In the second embodiment, as the MOS transistor formed in the logic circuit 72, a MOS transistor having a thin gate insulating film is used. When a MOS transistor having a thin gate insulating film is used, the leakage current increases. Therefore, when a capacitive element made of a MOS transistor as shown in FIG. 4 is used as the capacitive element 14, a MOS transistor having a thicker gate insulating film than the MOS transistor formed in the logic circuit 72 is used. By using it, the leakage current between the pair of power supply wirings can be reduced.

1 is a pattern plan view of a standard cell type semiconductor integrated circuit device according to a first embodiment of the present invention; FIG. 2 is an equivalent circuit diagram of the semiconductor integrated circuit device of FIG. 1. The pattern top view which shows the specific structure of the standard cell in FIG. 1 with a pair of power supply wiring. The pattern top view and sectional drawing which show an example of the capacitive element in FIG. The pattern top view and sectional drawing which show the other example of the capacitive element in FIG. The pattern top view of the semiconductor integrated circuit device for eDRAMs concerning the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Standard cell array, 12 ... Circuit area | region, 13 ... Power supply wiring area | region, 14 ... Capacitor element, 21 ... Power supply wiring for high potentials, 22 ... Power supply wiring for ground voltage, 23 ... Circuit, 71 ... DRAM circuit, 72 ... Logic circuit.

Claims (5)

A semiconductor chip having a synthesis part and a custom part;
A circuit region formed in a composite portion of the semiconductor chip and provided with an active element;
A power supply wiring region formed at least in the periphery of the circuit region, and provided with a power supply wiring for supplying a power supply voltage to the circuit region;
A standard cell type semiconductor integrated circuit device comprising: a capacitor element that is formed in the power supply wiring region and removes noise on the power supply wiring.   2. The standard cell type semiconductor integrated circuit device according to claim 1, wherein a plurality of standard cells are formed in the circuit region.   2. The standard cell type semiconductor integrated circuit device according to claim 1, wherein an embedded circuit including a DRAM circuit and a logic circuit is formed in the circuit region.   2. The standard cell type semiconductor integrated circuit device according to claim 1, wherein the capacitive element is formed of a MOS transistor.   2. The standard cell type semiconductor integrated circuit device according to claim 1, wherein the capacitive element is a deep trench type capacitive element.

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