JP2006261148A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device in which an SRAM having a reduced SRAM cell size and a DRAM are mixedly mounted by configuring the SRAM by using the same manufacturing process as that of the DRAM provided with a cylinder type capacitance. <P>SOLUTION: In this semiconductor device, the DRAM provided with the DRAM cell of a cylinder type capacitance and the SRAM provided with resistive load type SRAM cell using an electrode of cylinder type capacitance as a load resistance are formed on the same silicon substrate. The SRAM cell consists of a word line WL401a, paired bit lines BL411a and BL412a, access transistors TR431 and TR432, drive transistors TR433 and TR434, and load resistors R441 and R442. A second inverter circuit is configured using a connection point between the load resistor R442 and the drive transistor TR 434 as an output. As described above, by designing the SRAM similarly to the configuration of a DRAM standard process and configuration, an SRAM of a small cell size can be obtained. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a dynamic random access memory (hereinafter abbreviated as DRAM) and a static random access memory (hereinafter abbreviated as SRAM) are mounted on the same substrate.

  Semiconductor devices are used in systems in various fields. In addition, as a key device of the system, the semiconductor device has been scaled up by incorporating various functions in order to ensure the competitiveness of the system. Therefore, a semiconductor device is required to have a CPU, a DRAM as a large-capacity memory, and an SRAM as a cache memory. It is necessary to form DRAM and SRAM on the same silicon substrate and mount them together.

  In that case, it is most efficient if the SRAM can be configured by a DRAM process that requires a large storage capacity. However, unlike a process that is optimal for DRAM and a process that is optimal for SRAM, there is no inherent process in the DRAM process for designing a small memory cell of SRAM. For this reason, the SRAM cell becomes large. Conversely, when a DRAM is configured by an SRAM process, the DRAM cell becomes large. Further, when the processes of DRAM manufacturing and SRAM manufacturing are mixed, the process becomes complicated and the manufacturing cost increases. In any of these options, there is a problem that there is no optimal means, and manufacturing cannot be performed with the same manufacturing apparatus or process as in the past.

  A conventional DRAM will be described with reference to FIGS. The DRAM here is composed of a cell having a cylinder type capacity. 1 is a pattern arrangement diagram, FIG. 2 is a circuit diagram thereof, and FIG. 3 is a sectional view taken along dotted lines 1A-1B and 1C-1D in FIG. Since the DRAM has a large storage capacity, the reduction of the memory cell is the highest priority item in the process, and the design rules of elements other than the memory cell are relaxed. This is because the DRA cell has a DRAM-specific cell capacity (MC241 and MC242 in FIG. 2) formed in a cylinder shape above the transistor. Since a cylinder-type capacitor is formed in the memory cell, the height of the memory cell is increased, and there are differences in cross-sectional structure, step difference, and the like between the memory cell and the element region other than the memory cell. If the optimization of the memory cell is prioritized, the design rule of the element region other than the memory cell is inevitably relaxed.

  The transistors TR231 and TR232 in the circuit diagram of FIG. 2 are formed with the regions where the active regions ND121, ND122 and ND123 and the word lines WL101 to WL106 of FIG. 1 overlap as gates and the active regions on both sides as diffusion layers. The active region is a region where a diffusion layer surrounded by an insulating oxide film in an insulating isolation region and a gate region are formed. The capacitors MC241 and MC242 in FIG. 2 are formed in the cylinder of FIG. 1 and are formed between the lower electrodes 141 and 142 connected to the diffusion layer and the capacitor plates PL251 and PL252 sandwiching the capacitor insulating film. Capacitance plates PL251 and PL252 are connected to the same potential. These capacitor plates PL251 and PL252 are not shown in FIG. 1, but correspond to the capacitor plate PL351 covering the DRAM cell portion shown in FIG.

  In the cross-sectional view of FIG. 3, portions 1A to 1B are parallel to the word lines, and portions 1C to 1D are cross-sectional views parallel to the bit lines. A cross-sectional view along lines 1A-1B shows the cylinder capacity. A cylinder type capacitor is formed between a lower electrode 341 connected by a contact plug 331 from a diffusion layer in an active region separated by an insulating isolation region 321 and a capacitor plate PL 351 as an upper electrode. In the cross-sectional views along the lines 1C to 1D, two transistors corresponding to two bits of the DRAM cell and two capacitors are shown.

  The word lines WL304 and WL306 wired in the direction perpendicular to the paper surface serve as gate electrodes and constitute transistors having the diffusion layers on both sides as sources and drains. The drain is connected to a bit line (not shown), the source diffusion layer is connected to the lower electrode 344 of the capacitor via the contact plug 334, and forms a cell capacitance with the capacitor plate 351, respectively. The word line WL305 is wired in the insulating isolation region.

  Here, the word lines WL304, WL305, and WL306 correspond to the word lines WL104, WL105, and WL106 in FIG. 1, and the bit lines BL311, BL312, and BL313 correspond to the bit lines BL111, BL112, and BL113 in FIG. In the following reference numerals, different reference numerals are used for the cross-sectional view and the plan view, but the last two digits of the reference numerals are made to correspond to each other. In addition, the plan views in the drawings and the embodiments may be expressed regardless of the position in the height direction for easy viewing.

  In the DRAM process described above, when an SRAM cell (FIG. 5) is to be manufactured, the placement location is an element region other than the memory cell, and a resistive load type composed of four transistors and two resistance elements according to a loose design rule. An SRAM cell or a 6-transistor full CMOS SRAM cell in which two resistance elements are replaced by P-type transistors must be designed. In these SRAM cell configurations, there is a problem that the SRAM cell becomes a large size because a process unique to DRAM cannot be utilized.

  There are several patent documents regarding mixed mounting of DRAM and SRAM, or mixed mounting of DRAM and logic. Japanese Patent Application Laid-Open No. 2004-228561 describes a technique for sharing a wiring layer of a DRAM and a wiring layer of a logic circuit. In Patent Document 2, a salicide structure is employed for the logic circuit, and a self-aligned contact structure is employed for the memory element. However, these patent documents do not describe a technique for efficiently mounting DRAM and SRAM, and the problem in mounting DRAM and SRAM remains.

JP 2000-101035 A Japanese Patent Laid-Open No. 2000-232076

  As described above, when the DRAM and the SRAM are mixedly mounted on the same substrate, there are problems that the chip size is increased, the manufacturing process is complicated and the process becomes longer, and the manufacturing cost is increased.

  In view of the above problems, an object of the present application is to provide a semiconductor device in which an SRAM and a DRAM having a reduced SRAM cell size are combined by configuring the SRAM by the same process as that of a DRAM having a cylinder type capacity. That is.

  The semiconductor device according to the present invention is characterized in that a DRAM having a cylinder type capacity DRAM cell and an SRAM having a resistance load type SRAM cell having the electrode of the cylinder type capacity as a load resistance are formed on the same silicon substrate. And

  In the semiconductor device of the present application, the load resistor is formed by a lower electrode of the cylinder-type capacitor.

  In the semiconductor device of the present application, the load resistor is formed by an upper electrode of the cylinder type capacitor.

  In the semiconductor device of the present application, each word line in the DRAM cell and the SRAM cell is formed of the same layer having the same structure.

  In the semiconductor device of the present application, the word line in the DRAM cell and the gate layer of the flip-flop in the SRAM cell are formed in the same layer having the same structure.

  In the semiconductor device of the present application, the active regions in the DRAM cell and the SRAM cell are arranged with the same width and interval, respectively.

  In the semiconductor device of the present application, one bit of the SRAM cell is formed in an area of 8 bits of the DRAM cell.

  The semiconductor device of the present application is characterized in that the cylinder type capacitor in the DRAM cell and the resistor formed in the cylinder in the SRAM cell are arranged at the same position in the diffusion layer.

  In the semiconductor device of the present invention, a DRAM including a cylinder capacitor DRAM cell and an SRAM including a resistance load SRAM cell having a cylinder capacitor electrode as a load resistance are formed on the same silicon substrate. By designing the SRAM cell to be similar to the DRAM standard process and configuration, an SRAM having a small cell size can be obtained, and there is an effect that an optimum semiconductor device in which DRAM and SRAM are mixedly mounted can be obtained.

  The present invention will be described in detail below with reference to the drawings.

  The first embodiment will be described with reference to FIGS. 4 to 6 and FIG. 4A shows an SRAM cell pattern layout with gate wiring emphasized, FIG. 4B shows an SRAM cell pattern layout with metal wiring emphasized, and FIG. 9 shows a DRAM cell pattern layout for comparison. Show. FIG. 5 is a circuit diagram of a resistive load type SRAM cell, and FIG. 6 is a sectional view taken along line 4B-4C in FIG.

  The resistance load type SRAM cell shown in FIG. 5 includes a word line WL401a, bit line pairs BL411a and BL412a, access transistors TR431 and TR432, drive transistors TR433 and TR434, and load resistors R441 and R442. The load resistor R441 and the drive transistor TR433 are connected between the power supply and the ground potential, and constitute a first inverter circuit that outputs a connection point between the load resistor R441 and the drive transistor TR433. The load resistor R442 and the drive transistor TR434 are connected between the power supply and the ground potential, and constitute a second inverter circuit that outputs a connection point between the load resistor R442 and the drive transistor TR434.

  The output of the second inverter circuit is input to the gate of the drive transistor TR433 of the first inverter circuit, and the output of the first inverter circuit is input to the gate of the drive transistor TR434 of the second inverter circuit. And the FF circuit is constituted by the second inverter circuit, and the stored data is stably held. The access transistors TR431 and TR432 are connected between the bit lines BL411a and BL412a and the outputs of the first and second inverter circuits, and the data between the bit lines and the memory cells is transferred by the word line WL401a input to the gate. Interact.

  4A and 4B, the bit line BL411a wired by the metal wiring is connected to the diffusion layer of the transistor TR431 by the contact 432. The other diffusion layer of the transistor TR431 formed in the active region ND431 is connected to the drain diffusion layer of the transistor TR433 by a metal wiring and further to the gate wiring of the transistor TR434 through a through hole 451. The transistor TR433 is formed in the active region ND433, and a load resistor R441 is formed in its drain diffusion layer. A cylinder type capacity is used for the load resistor R441. The source diffusion layer is connected to the GND potential.

  Bit line BL412a wired by metal wiring is connected to the diffusion layer of transistor TR432 by contact 431. The other diffusion layer of the transistor TR432 formed in the active region ND432 is connected to the drain diffusion layer of the transistor TR434 through a metal wiring and further to the gate wiring of the transistor TR433 through a through hole 452. The transistor TR434 is formed in the active region ND434, and a load resistor R442 is formed in its drain diffusion layer. A cylinder type capacity is used for the load resistor R441. The source diffusion layer is connected to the GND potential. The gates of access transistors TR431 and TR432 are connected to word line WL401a.

  FIG. 6 shows a cross-sectional view along the dotted line 4B-4C. Here, the cylinder type capacitor electrode of the DRAM process is used as the load resistance of the SRAM cell. The lower electrode 641 of the cell capacity connected from the drain diffusion layer via the contact plug 631 is connected to the capacity plate PL651 at the connection location 601 on the upper side of the cylinder. The capacitor plate PL651 serving as the upper electrode is connected to the first metal wiring 671 by a via 661 and further to the second metal wiring 672 by a via 662. Therefore, the load resistance is mainly composed of the lower electrode 641. The load resistor is formed simultaneously with the capacity forming step of the DRAM process, and is different from the DRAM process only in that the lower electrode 641 and the capacitor plate PL651 as the upper electrode are connected.

  One bit of these SRAM cells is configured in an area surrounded by a dotted line 4A in FIGS. 4 (A) and 4 (B). The region of dotted line 4A includes active regions ND431, ND432, ND433, and ND434. Here, it will be compared with the DRAM cell of FIG. The active regions ND431, ND432, ND433, and ND434 in FIGS. 4A and 4B are the same as the active regions ND431, ND432, ND433, and ND434 in FIG. That is, the SRAM cell of the present invention is configured in the 8-bit area of the DRAM cell. The SRAM cell of the present invention can be reduced in size by making the process and pattern configuration substantially the same as a DRAM cell.

  The first feature of the present invention is that the lower electrodes 641 forming the cylinder type capacitor of FIG. 6 are replaced with the load resistors R441 and R442 of FIG. As a result, the process structure of the DRAM cell can be used as it is for the SRAM cell. However, in order to use this cylinder-type capacitor as a load resistor, a connection portion 601 between the lower electrode 641 of the normal DRAM process and the capacitor plate PL651 is also required, so only this point needs to be changed from the normal DRAM process. is there. This can be formed by using conventional techniques such as a contact process and an etching process that are often used in the past.

  After being connected to the capacitor plate PL651, the first metal wiring or the second metal wiring is formed by the via 661 connecting the first metal wiring and the capacitor plate or the via 662 connecting the second metal wiring and the first metal wiring. Since connection is possible, potential supply is performed from here. The next feature is that the SRAM cell is constructed while making the structure and shape of the diffusion layer and electrode of the DRAM cell similar. By making the SRAM cell the same process and arrangement as the DRAM cell, the shape and step are the same as the DRAM cell, and the design rule of the SRAM cell can be made the same as the DRAM cell. By designing an SRAM cell with a design rule equivalent to that of a DRAM cell, it is possible to design with a size one third to one fifth smaller than with a design rule other than a DRAM cell. Become.

  The semiconductor device of this embodiment is composed of a DRAM having a cylinder type capacity and an SRAM having an electrode wiring serving as a lower electrode of the cylinder type capacity of the DRAM cell as a load resistance. The SRAM cell is designed to be similar to the DRAM standard process and configuration. Since the SRAM cell has the same shape and step as the DRAM cell, and the same design rule as the DRAM cell can be used for the SRAM cell, an SRAM having a small cell size can be obtained. A semiconductor device in which an optimum DRAM and SRAM are mixedly mounted can be obtained by an SRAM having a small cell size.

  A second embodiment will be described with reference to FIG. FIG. 7 shows a sectional view of the load resistance in this embodiment. The pattern arrangement of the SRAM cell in the second embodiment is the same as that in FIGS. 4A and 4B, and is different from the first embodiment in that a capacitor plate PL651 that is an upper electrode of a cylinder-type capacitor is used as a load resistance. The description of other configurations that are the same as those of the first embodiment is omitted.

  Since the pattern layout of the SRAM cell of Example 2 has the same configuration as that shown in FIGS. 4A and 4B, only the load resistance will be described. A contact plug 731 from the diffusion layer is connected to a capacitor plate 751 which is an upper electrode at a cylinder bottom 701 forming a capacitor of the DRAM. The capacitor plate PL751 is the same as that shown in FIG. 6, and is connected to the metal wiring by a via (not shown). In the first embodiment, the lower electrode 741 of the cylinder type capacitor is used as the load resistance. However, in this embodiment, the load resistor is configured by the capacitor plate 651 that is the upper electrode of the cylinder type capacitor, and the capacitance is formed at the cylinder bottom 701. It is connected to the plate 751.

  When the capacity plate 751 is arranged in a pattern on the entire surface of the memory cell array block, only the capacity plate portion in the cylinder becomes a load resistance. When the capacitor plate 751 is appropriately patterned to form a common wiring portion and a cell-dedicated wiring portion, the capacity plate in the cylinder and the patterned dedicated wiring portion function as a load resistance. This embodiment is an embodiment in which the load resistance of the SRAM cell is configured by a capacitor plate. The cell size is the same as that of a DRAM cell having a cylinder capacity, and the SRAM cell can be made small.

  The semiconductor device of this embodiment is composed of a DRAM having a cylinder type capacitor and an SRAM having a load resistance of an electrode wiring of a capacitor plate which is an upper electrode of the cylinder type capacitor of the DRAM cell. By designing the SRAM cell to be similar to the DRAM standard process and configuration, an SRAM having a small cell size can be obtained, and an optimum semiconductor device in which DRAM and SRAM are mixedly mounted can be obtained.

  A third embodiment will be described with reference to FIG. FIG. 8 shows a pattern layout in this embodiment. This embodiment is a configuration example in which the gate lengths of the access transistors TR431a and TR432a in the SRAM cell of the first embodiment are changed.

  In FIG. 8, the word line WL401b serving as the gate electrode of the access transistors TR431a and TR432a has a larger width in the transistor gate region, and is larger than the gate length of the drive transistors TR433a and TR434a. Other pattern arrangements and connections are the same as those shown in FIGS. 4A and 4B, and the description of the configuration and connection is omitted.

  The SRAM cell of the present invention has a process and pattern arrangement similar to those of a DRAM cell that is embedded. In the DRAM cell shown in FIG. 1, two transistors are formed by two word lines in one active region. However, in the pattern arrangement of the SRAM cell of the present invention shown in FIG. 4, each of the transistors TR431 to TR434 may be formed in one active region. That is, by forming one transistor, the gate length of the transistor can be easily changed. Therefore, the gate lengths of the transistors TR431a and TR432a are increased. In this way, the current driving capability of the transistor in the SRAM cell can be optimized within the minimum cell size. The transistor drive capability can be optimized in time according to the circuit requirements. Conversely, if necessary in the circuit, the transistors TR433a and TR434a can be similarly changed. In this embodiment, the transistor driving capability can be optimized.

  The semiconductor device of this embodiment is composed of a DRAM having a cylinder capacity and an SRAM having a load resistance of an electrode wiring of an electrode forming portion of the cylinder capacity of the DRAM cell. Furthermore, the driving capability of transistors constituting the SRAM cell is optimized, and an optimum SRAM cell can be constructed. By designing the SRAM cell to be similar to the DRAM standard process and configuration, an SRAM cell and an SRAM having a small cell size and an optimum transistor capability can be obtained, and a semiconductor device in which the optimum DRAM and SRAM are mixedly mounted can be obtained.

  Although the present invention has been specifically described above based on the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof.

FIG. 2 is a pattern layout diagram of a DRAM cell in the present invention. It is a circuit diagram of a DRAM cell in the present invention. It is sectional drawing of the DRAM cell in FIG. FIG. 4A is a pattern layout diagram of memory cells, FIG. 4A is a pattern layout diagram of SRAM cells in which word lines are emphasized, and FIG. It is a circuit diagram of the SRAM cell in this invention. It is sectional drawing of the SRAM cell in this invention. 6 is a cross-sectional view of an SRAM cell in Example 2. FIG. 6 is a sectional view of an SRAM cell in Example 3. FIG. FIG. 2 is a pattern layout diagram of a DRAM cell in the present invention.

Explanation of symbols

131, 331, 431, 631, 731 Contact plug 141, 341, 641, 741 Cylinder lower electrode 321, 621, 721 Insulation isolation region 451, 452 Through hole (between gate wiring and metal wiring)
WL101, WL201, WL202, WL304, WL401a, WL401b Word lines BL111, BL211, BL212, BL311, BL411a, BL412a Bit lines ND121, ND122, ND431, ND432, ND433, ND434 Active regions TR231, TR232, TR431, TR432, TR434 Transistors MC241 and MC242 Capacitances PL251, PL252, PL351, PL651, PL751 Capacitance plates R441, R442 Load resistance

Claims (8)

  In a semiconductor device, a DRAM having a DRAM cell of a cylinder type capacity and an SRAM having a resistance load type SRAM cell having a load resistance of an electrode of the cylinder type capacity are formed on the same silicon substrate. Semiconductor device.   The semiconductor device according to claim 1, wherein the load resistance is formed by a lower electrode of the cylinder-type capacitor.   The semiconductor device according to claim 1, wherein the load resistance is formed by an upper electrode of the cylinder-type capacitor.   4. The semiconductor device according to claim 1, wherein each word line in the DRAM cell and the SRAM cell is formed in the same layer having the same structure.   4. The semiconductor device according to claim 1, wherein a word line in the DRAM cell and a gate layer of a flip-flop in the SRAM cell are formed in the same layer having the same structure.   4. The semiconductor device according to claim 1, wherein the active regions in the DRAM cell and the SRAM cell are arranged with the same width and interval.   7. The semiconductor device according to claim 6, wherein 1 bit of the SRAM cell is formed in an area of 8 bits of the DRAM cell. 8. The semiconductor according to claim 1, wherein a cylinder type capacitor in the DRAM cell and a resistor formed in the cylinder in the SRAM cell are arranged at the same position in the diffusion layer. apparatus.

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