JP2006073696A - Semiconductor integrated circuit using standard cell and design method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which has an effect of power-supply noise suppression, and can be stabilized in power supply, in semiconductor integrated circuit designing using standard cells. <P>SOLUTION: In the semiconductor integrated circuit wherein a first standard cell and a second standard cell are provided adjacently, power supply noise can be restrained by arranging a transistor forming a power supply capacity so as to stride a face where the first and the second standard cells contact with each other. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit created by automatic placement and wiring using standard cells and a design method thereof.

  When designing a semiconductor integrated circuit in a semiconductor device, the entire semiconductor integrated circuit is not constructed at once, but a plurality of functional blocks called standard cells are combined based on a predetermined rule. In many cases, a construction method is used. Such a method of combining a plurality of standard cells is called cell-based design.

  In cell-based design, in addition to basic gate circuits such as inverter circuits, AND circuits, and NAND circuits, various circuits such as complex circuits such as flip-flop circuits and relatively large block circuits such as adders are used. Types of circuits are prepared as standard cells and used as needed.

  As a rule of cell base design, standard cell height, power line thickness, input / output pin position, etc. are unified so that standard cells can be arranged as close as possible.

  A block layout diagram using a conventional standard cell will be described with reference to FIG. The block 200 is composed of a cell 1A and a cell 2A. Each of the cell 1A and the cell 2A has a predetermined function (for example, the cell 1A is an AND circuit, and the cell 2A is an inverter circuit). In the drawing, P-type diffusion regions 114, 115, and 116 are arranged on the upper side, and N-type diffusion regions 117, 118, and 119 are arranged on the lower side.

  The P-type diffusion region 114 and the P-type diffusion region 115 are opposed to each other across the 113 that is the boundary between the cell 1A and the cell 2A. Therefore, the dummy gate electrode 111 is disposed on the upper side of the cell boundary 113 in order to eliminate variations in the gate length and the shape of the diffusion region.

  Further, the N-type diffusion region 117 and the N-type diffusion region 118 are opposed to each other across the 113 that is the boundary between the cell 1A and the cell 2A. Accordingly, the dummy gate electrode 112 is disposed on the lower side in order to eliminate variations in the gate length and the shape of the diffusion region.

  Next, a design method in the conventional cell-based design will be described with reference to FIG. FIG. 12 shows a design flow used when a block layout as shown in FIG. 11 is configured. In step 1, a standard cell layout is designed. In addition to basic gate circuits such as inverter circuits, AND circuits, and NAND circuits, standard cells are designed for various types of circuits such as complex circuits such as flip-flop circuits and relatively large block circuits such as adders. The The designed standard cell is stored in the library.

  In step 2, the standard cells are automatically placed and wired using the library storing the standard cells created in step 1. Specifically, the standard cells in the library are arranged according to the circuit function to be realized, and wiring is performed between the arranged standard cells. The automatic placement / wiring described above is performed in consideration of area, clock skew, and the like.

  As a prior art related to the present invention, the gate electrode that contributes to the operation of the transistor and the gate electrode that does not contribute to the operation of the transistor have the same length, and are arranged at the same gate interval along the same length. A method has been proposed in which the end portions of the electrodes are provided longer than the longest diffusion region, thereby eliminating variations in the finished shape of the gate and diffusion region, and realizing a semiconductor device with high speed operation and low power consumption (see Patent Document 1). .

  In addition, there has been proposed a method for realizing a semiconductor device in which a power source noise suppressing effect can be obtained by disposing a transistor constituting a power source capacitor in a standard cell (see Patent Document 2).

In addition, a design method for suppressing power supply noise by providing a capacity cell as a standard cell and automatically arranging it has been proposed (see Patent Document 3).
JP 2002-26125 A JP 2002-110798 A JP 2000-277618 A

  In recent years, with the miniaturization of the process, the voltage drop due to the product of the wiring resistance and current generated on the power supply wiring is increasing. When the voltage drop increases, the power supply voltage of the block decreases, and it is easily affected by power supply noise. In the worst case, a malfunction may occur.

  In order to solve this, Patent Document 2 configures a capacity in a standard cell, and Patent Document 3 provides a capacity cell as a standard cell. However, in Patent Document 2, the area of the standard cell increases because a capacity is intentionally provided in the standard cell. Further, in Patent Document 3, no capacity is provided in each cell, but the capacity cell itself is disposed, so that the area of the semiconductor integrated circuit increases as a result.

  In addition, in the conventional configuration described above, the gate electrode is disposed where the transistor is not adjacent, thereby suppressing variations in the gate length of the transistor and the shape of the diffusion region. However, the dummy gate electrode has other functions. However, there was a problem that the area was wasted.

  In order to solve the above-mentioned problems, the present invention provides a semiconductor integrated circuit design using standard cells, which effectively suppresses power supply noise so as not to increase the area while effectively using dummy gate electrodes, and stabilizes power supply. An object is to provide a semiconductor integrated circuit that can be realized.

  In order to solve the above problems, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit including a first standard cell and a second standard cell, each of which realizes a predetermined logic, and the first standard cell. 1 or a plurality of gate electrodes are arranged at the boundary between the first standard cell and the second standard cell, and at least one of the one or more gate electrodes is used to form a transistor serving as a power source capacity. It is characterized by.

  Also, the semiconductor integrated circuit design method of the present invention uses a plurality of standard cells including the first standard cell and the third standard cell which realize the same logic and have one or more dummy gate electrodes on the end face. A method of designing a semiconductor integrated circuit, wherein at least one dummy gate electrode among the dummy gate electrodes of the first standard cell has a potential fixed and a diffusion region having a potential fixed below. In addition, none of the dummy gate electrodes of the third standard cell is fixed in potential, a step of arranging a plurality of standard cells including the third standard cell, and the plurality of standard cells are arranged. As a result, among the one or more dummy gate electrodes that the third standard cell has on the end face, (1) both Is a diffusion region with a fixed potential, (2) one of both sides is a diffusion region with a fixed potential and the other is an empty region, and (3) there is an empty region on both sides A power supply capacity is formed by replacing the third standard cell with the first standard cell when any one of (1) to (3) is detected. Steps to do.

  According to the semiconductor integrated circuit based on the present invention, in the cell-based design, it is possible to suppress power supply noise without increasing the area by arranging the transistors constituting the power supply capacity across the contact surface of the standard cell.

  In addition, according to the semiconductor integrated circuit design method based on the present invention, it is possible to easily design by replacing the cells, and to arrange the transistors constituting the power source capacity without increasing the area, and to suppress the power source noise.

(Embodiment 1)
Hereinafter, a semiconductor integrated circuit according to a first embodiment of the present invention will be described with reference to the drawings. In the following drawings, black squares indicate contacts.

  FIG. 1 is a diagram showing a configuration of a standard cell 1A used in Embodiment 1 of the present invention, and corresponds to an AND circuit. In FIG. 1, gate electrodes 1 and 2 correspond to input terminals in1 and in2, respectively. That is, the standard cell 1A in FIG. 1 is a circuit that outputs H when in1 and in2 are both H.

  Gate electrodes 1 to 3 and P-type diffusion regions 10 and 12 constitute Pch transistors 14, 15 and 16, and gate electrodes 1 to 3 and N-type diffusion regions 11 and 13 constitute Nch transistors 17, 18 and 19. Has been. The cell frame 20 is indicated by a dotted line to indicate the standard cell area.

  Since there is no transistor between the Pch transistors 15 and 16, the distance between the gate electrode 2 and the gate electrode 3 is longer than the distance between the gate electrode 1 and the gate electrode 2. Accordingly, the dummy gate electrode 8 is disposed in order to eliminate variations in gate length and diffusion region shape. Similarly, a dummy gate electrode 9 is disposed between the Nch transistors 18 and 19.

  Further, the source region of the Pch transistor 14, the source region of the Pch transistor 16, the source region of the Nch transistor 17, and the source region of the Nch transistor 19 are the ends of the standard cell. For this reason, when the standard cell 1A is disposed, the adjacent standard cell and the diffusion region face each other. Therefore, dummy gate electrodes 4, 5, 6, and 7 are arranged in order to eliminate variations in gate length and shape of the diffusion region.

  FIG. 2 is a diagram showing a configuration of another standard cell 2A used in Embodiment 1 of the present invention, and corresponds to an inverter circuit. In FIG. 2, the gate electrode 23 and the P-type diffusion region 21 constitute a Pch transistor, and the gate electrode 23 and the N-type diffusion region 22 constitute an Nch transistor. Here, when the standard cell 2A is arranged, the P-type diffusion region 21 and the N-type diffusion region 22 face the diffusion region of the standard cell arranged adjacent to the right side of the drawing. Therefore, dummy gate electrodes 24 and 25 are provided so that the shape of the diffusion region does not vary. A dummy gate electrode is similarly provided on the left side. Note that the cell frame 26 is indicated by a dotted line to indicate the standard cell region.

  In this embodiment, in addition to the standard cells 1A and 2A, the standard cells of FIGS. 3 and 4 are also provided in the library. FIG. 3 shows a standard cell 1B that realizes the same logic (AND circuit) as the standard cell 1A. Most of the configuration is the same as that of the standard cell 1A, but the standard cell 1A is a dummy gate electrode. It differs from the standard cell 1A in that a transistor 28 serving as a power source capacity is formed by using a gate electrode 27 arranged at the cell boundary. Specifically, it differs from the standard cell 1A in that the potential of the electrode 27 arranged at the boundary is fixed to VDD. As a result, when the potential of the diffusion region facing the diffusion region 11 in the cell adjacent to the left side is fixed, a transistor 28 is formed with the source and drain fixed at VSS and the gate fixed at VDD. Can be used.

  FIG. 4 shows a standard cell 2B that realizes the same logic (inverter circuit) as the standard cell 2A. Most of the configurations are the same as those of the standard cell 2A, but the gate electrode 29 arranged at the cell boundary is shown in FIG. Is different from the standard cell 2A in that the transistor 30 serving as the power source capacity is formed by using. Specifically, it differs from the standard cell 2A in that the potential of the gate electrode 29 arranged at the boundary is fixed at VSS. As a result, when the potential of the diffusion region facing the diffusion region 21 in the cell adjacent to the right side is fixed, a transistor 30 is formed with the source and drain fixed at VSS and the gate fixed at VDD. Can be used.

  FIG. 5 is a diagram showing a block layout of the present invention designed using the standard cells 1A, 2A, 1B, and 2B. The block 100 shown in FIG. 5 has a function corresponding to the block 200 of the conventional example shown in FIG. The components described in FIGS. 1 to 4 are denoted by the same reference numerals and description thereof is omitted.

  As described above, in the semiconductor integrated circuit having the conventional configuration as shown in FIG. 11, the dummy gate electrodes 111 and 112 are provided across the surface 113 where the cell 1A and the cell 2A are in contact with each other. Absent. Therefore, in the block created in the first embodiment, as shown in FIG. 5, the P-type diffusion regions 21 and 10 on both upper sides of the surface 31 where the cell 1B and the cell 2B are in contact with each other are fixed in potential. Since the N-type diffusion regions 22 and 11 are fixed in potential, the gate electrodes 27 and 29 arranged at the boundary are used to form the transistors 28 and 30 in which the potential is fixed. Specifically, the potential of the gate electrode 27 disposed at the cell boundary and having the diffusion regions on both sides fixed to VSS is fixed to VDD. Further, the gate electrode 29 arranged at the cell boundary and having the diffusion regions on both sides fixed to VDD is fixed to VSS. This block layout is a block layout in which standard cells 1B and standard cells 2B are arranged.

  Here, the block layout in which the standard cells 1A and 2A shown in FIG. 11 are arranged and the block layout in which the standard cells 1B and 2B shown in FIG. 5 are arranged have the same area and logic, and become the power supply capacity. The only difference is that the transistors are configured. Therefore, power supply noise can be suppressed without increasing the block area.

  Next, a layout design method for designing a block as shown in FIG. 5 using the standard cells 1A, 2A, 1B, and 2B will be described with reference to the drawings. FIG. 6 shows a block layout design flow in the present embodiment.

  Step 1 is a design process for the standard cell itself. In step 1, in addition to the standard cells having the same layout as the conventional cells such as the standard cells 1A and 2A, the gate electrode arranged at the boundary, as represented by the standard cells 1B and 2B, is fixed in potential and becomes the power source capacity. We also design standard cells that make up transistors. In the present embodiment, block layout is performed using both of these two types of standard cells.

  In step 2, standard cells are arranged using standard cells having a conventional layout represented by standard cells 1A and 2A. This is because it is not known whether the diffusion regions whose potentials are fixed in two adjacent cells face each other unless layout is performed. As a result, a block layout as shown in FIG. 11 is formed. In this block layout, the dummy gate electrodes 111 and 112 are provided across the surface 113 where the standard cell 1A and the standard cell 2A are in contact with each other, but cannot be effectively used.

  Next, in step 3, it is recognized whether the diffusion regions whose potentials are fixed are opposed to each other on both sides of the surface in contact with the standard cell arranged in step 2. When it is recognized that the diffusion regions whose potentials are fixed are opposed to each other, in step 4, the gate electrodes arranged at the cell boundaries shown in the standard cells 1B and 2B are fixed in potential to form a power source capacity. Replaced with standard cells. As a result of the replacement, the block layout as shown in FIG. 5 is completed.

  In this way, it is recognized that the diffusion regions whose potentials are fixed on both sides of the dummy gate electrode across the contact surface of the standard cell are facing each other, and the standard of the same logic in which the gate electrode arranged at the boundary is fixed in potential. By replacing the cells, the block layout design can be easily performed without increasing the block area, and the power supply noise can be suppressed.

  As described above, according to the present embodiment, the potential of the gate electrode across the contact surface of the standard cell can be fixed and effectively used as a transistor constituting the power supply capacity, and power supply noise is suppressed without increasing the block area. be able to. In addition, it is possible to easily design a semiconductor integrated device in which power supply noise is suppressed without increasing the block area.

  In this embodiment, a transistor serving as a power supply capacitor is formed using the gate electrode arranged at the boundary between both the Pch transistor formation region and the Nch transistor formation region. However, only one of the power supply capacitors is used. It is also possible to use a configuration in which a transistor is formed. For example, when the diffusion regions whose potentials are fixed only in one of the P-type diffusion region and the N-type diffusion region are opposed to each other, only the gate electrode arranged on either one of the boundaries is used. To form a transistor.

(Embodiment 2)
Hereinafter, a semiconductor integrated circuit according to a second embodiment of the present invention will be described with reference to the drawings.

  In the second embodiment, a standard cell similar to that of the first embodiment is provided in the library. Details are described in the first embodiment, and thus will be omitted. Furthermore, in the second embodiment, the library cell shown in FIGS. 7 and 8 is provided.

  FIG. 7 shows a standard cell 3A which is an example of a standard cell used in the second embodiment. In the standard cell 3A, the upper side, which is the Pch transistor formation region, of the surface 50 in contact with the right standard cell is an empty region, and the lower N-type diffusion region 51 is fixed at VSS. A dummy gate electrode 53 is provided inside the cell so that the shape of the diffusion region does not vary, a dummy gate electrode 52 is provided above the rightmost cell boundary, and a dummy gate electrode 54 is provided below.

  FIG. 8 shows a standard cell 3C which is an example of a standard cell used in the second embodiment. The standard cell 3C constitutes the same logic as the standard cell 3A, and most of the configuration is the same as that of the standard cell 3A. However, it differs from the standard cell 3A in that the power source capacitance is configured by using the gate electrode 55 arranged at the cell boundary. Specifically, the gate electrode 55 arranged at the cell boundary is fixed at the potential of VSS, and the P-type diffusion region 56 fixed at the potential of VDD is inserted. As a result, when the diffusion region facing the diffusion region 56 inserted in the cell adjacent to the right side is fixed at VDD, the transistor 57 is formed with the source and drain fixed at VDD and the gate fixed at VSS. And can be used as a power source capacity.

  FIG. 9 is a diagram showing a block layout of the present invention designed using standard cells 1A, 1B, 3A, and 3C. The components already described are denoted by the same reference numerals and description thereof is omitted.

  In the block created in the second embodiment, as shown in FIG. 9, the P-type diffusion regions 56 and 10 on both upper sides of the surface where the standard cell 1B and the standard cell 3C are in contact with each other are fixed to VDD. The N-type diffusion regions 51 and 11 on both sides are fixed to VSS, and the potential is fixed using the gate electrodes 55 and 27 arranged at the cell boundary, which is a dummy gate electrode in the standard cell 3A. Transistors 57 and 28 are formed. Specifically, the gate electrode 55 in which the diffusion regions on both sides are fixed to VDD is fixed to VSS. Further, the potential of the gate electrode 27 in which the diffusion regions on both sides are fixed to VSS is fixed to VDD. This block layout is a block layout in which the standard cell 1B shown in FIG. 3 and the standard cell 3C shown in FIG. 8 are arranged.

  Here, comparing FIG. 10 which is a block layout in which the standard cells 1A and 3A are arranged and FIG. 9 which is a block layout in which the standard cells 1B and 3C are arranged, the transistors having the same area and logic and the power source capacity are obtained. Only the points that are configured are different. Therefore, power supply noise can be suppressed without increasing the block area.

  Next, a layout design method for designing a block as shown in FIG. 9 using the standard cells 1A, 1B, 3A, and 3C will be described with reference to the drawings. Here, the flowchart of the layout design method is the same as FIG. 6 which is the flowchart of the first embodiment, and therefore the same drawing is used. However, in the second embodiment, the details of each step are different from those in the first embodiment.

  Step 1 is a design process for the standard cell itself. In step 1, in addition to the standard cells having the same layout as the conventional one represented by the standard cells 1A and 3A, a standard cell in which the potential of the gate electrode arranged at the boundary represented by the standard cells 1B and 3C is fixed is designed. In the present embodiment, block layout is performed using both of these two types of standard cells.

  In step 2, standard cells are arranged using standard cells having a layout represented by standard cells 1A and 3A. If the layout is not performed, whether or not the diffusion region whose potential is fixed in two adjacent cells face each other, or whether the diffusion region whose potential is fixed on one side faces the empty region on the other side Because I don't know. As a result, the block layout shown in FIG. 10 is formed. In this block layout, the dummy gate electrode arranged at the cell boundary is not effectively used.

  Next, in step 3, it is recognized whether the two potential-fixed diffusion regions or the potential-fixed diffusion region and the vacant region are opposed to each other on both sides of the surface in contact with the standard cell arranged in step 2. When it is recognized that the diffusion region whose potential is fixed and the vacant region are opposed to each other, the standard cell 3A having the vacant region is inserted into the diffusion region whose potential is fixed in the vacant region, and the gate disposed at the boundary. The electrode is replaced with a standard cell 3C having a fixed potential. In this example, since the diffusion region whose potential is fixed is opposed to the lower side of the cell boundary, the gate electrode disposed on the boundary of the other standard cell 1A is also connected to the potential using the method of the first embodiment. It is replaced with a fixed standard cell 1B. As a result of the replacement, the block layout as shown in FIG. 9 is completed.

  In this way, when the potential-fixed diffusion region and the vacant region are opposed to each other on both sides of the dummy gate electrode across the contact surface of the standard cell, the potential-fixed diffusion region is inserted into the vacant region and arranged at the boundary. By replacing the formed gate electrode with a standard cell of the same logic whose potential is fixed, the block layout design can be easily performed without increasing the block area, and power supply noise can be suppressed.

  Further, although the second embodiment has been described in a form combined with the first embodiment, the standard is used when the diffusion region facing at one cell boundary of the Pch transistor formation region and the Nch transistor formation region is fixed in potential. It is not always necessary to perform cell replacement.

  In the second embodiment, the case where one is a vacant region and the other is a diffusion region whose potential is fixed is described. However, even when both sides are vacant regions, a transistor serving as a power source capacitor can be formed similarly.

  Needless to say, the present invention is applicable regardless of the logic (inverter circuit, AND circuit, NOR circuit) of the target standard cell.

  The present invention relates to a semiconductor integrated circuit, and is useful for a layout structure of a semiconductor integrated circuit in an LSI design using standard cells and a design method thereof.

Layout diagram of standard cell 1A in the present invention Layout diagram of standard cell 2A in the present invention Layout diagram of standard cell 1B in the present invention Layout diagram of standard cell 2B in the present invention Block layout diagram of the first embodiment of the present invention Design flow diagram of first and second embodiments of the present invention Layout diagram of standard cell 3A in the present invention Layout diagram of standard cell 3C in the present invention Block layout diagram of the second embodiment of the present invention Block layout diagram during design of the second exemplary embodiment of the present invention Conventional block layout diagram Conventional design flow diagram

Explanation of symbols

1, 2, 3, 23 Gate electrode 4, 5, 6, 7, 8, 9, 24, 25, 52, 54 Dummy gate electrode 10, 12, 21, 56 P-type diffusion region 11, 13, 22, 51 N Type diffusion region 14, 15, 16, 30, 57 Pch transistor 17, 18, 19, 28 Nch transistor 20, 26, 31, 50 Cell frame 27, 29, 55 Gate electrode of transistor serving as power source capacity

Claims (8)

A semiconductor integrated circuit comprising a first standard cell and a second standard cell, each of which realizes a predetermined logic,
A transistor in which one or a plurality of gate electrodes are arranged at a boundary between the first standard cell and the second standard cell, and which serves as a power source capacity using at least one of the one or more gate electrodes. A semiconductor integrated circuit, wherein: 2. The transistor as the power source capacitor is a transistor in which the one gate electrode is fixed at a first potential, and a source and a drain are fixed at a second potential different from the first potential. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein a diffusion region having a fixed potential is disposed on both sides of the one gate electrode. The transistor serving as the power supply capacitor has a second potential different from the first potential, with one gate electrode serving as a gate and a first potential, and one of the diffusion-fixed diffusion regions serving as a source and the other serving as a drain. 4. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit is fixed to the transistor. A third standard cell that realizes the same logic as the first standard cell;
2. The semiconductor integrated circuit according to claim 1, wherein the gate electrode arranged at the boundary where the third standard cell is adjacent to another standard cell does not contribute to the formation of a transistor. A method for designing a semiconductor integrated circuit that uses a plurality of standard cells including a first standard cell and a third standard cell that realize the same logic and have one or more dummy gate electrodes on an end face,
Among the dummy gate electrodes of the first standard cell, at least one dummy gate electrode is fixed in potential, and has a diffusion region in which the potential is fixed below, and the dummy gate electrode of the third standard cell has None of these are fixed at potential,
Disposing a plurality of standard cells including the third standard cell;
As a result of the arrangement of the plurality of standard cells, it is detected whether one or a plurality of dummy gate electrodes provided on the end face of the third standard cell has a diffusion region in which both sides are fixed in potential. And steps to
A semiconductor integrated circuit comprising a step of configuring a power supply capacitor by replacing the third standard cell with the first standard cell when it is detected that there is a diffusion region whose potential is fixed. Design method. A method for designing a semiconductor integrated circuit that uses a plurality of standard cells including a first standard cell and a third standard cell that realize the same logic and have one or more dummy gate electrodes on an end face,
Among the dummy gate electrodes of the first standard cell, at least one dummy gate electrode is fixed in potential, and has a diffusion region in which the potential is fixed below, and the dummy gate electrode of the third standard cell has None of these are fixed at potential,
Disposing a plurality of standard cells including the third standard cell;
As a result of the arrangement of the plurality of standard cells, one or both of the dummy gate electrodes of the third standard cell on the end face is a diffusion region in which one side is fixed in potential and the other is a free region. Detecting whether there is something,
A semiconductor integrated circuit comprising a step of configuring a power supply capacitor by replacing the third standard cell with the first standard cell when it is detected that there is a diffusion region whose potential is fixed. Design method. A method for designing a semiconductor integrated circuit that uses a plurality of standard cells including a first standard cell and a third standard cell that realize the same logic and have one or more dummy gate electrodes on an end face,
Among the dummy gate electrodes of the first standard cell, at least one dummy gate electrode is fixed in potential, and has a diffusion region in which the potential is fixed below, and the dummy gate electrode of the third standard cell has None of these are fixed at potential,
Disposing a plurality of standard cells including the third standard cell;
Detecting whether or not one or more dummy gate electrodes provided on the end face of the third standard cell have vacant areas on both sides as a result of the arrangement of the plurality of standard cells;
A semiconductor integrated circuit comprising a step of configuring a power supply capacitor by replacing the third standard cell with the first standard cell when it is detected that there is a diffusion region whose potential is fixed. Design method.

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