KR20160014105A - Methods, structures and designs for self-aligning local interconnects used in integrated circuits - Google Patents

Abstract

Methods, structures, and designs are provided for self-aligned local interconnects. The method includes designing diffusion regions to be within the substrate. Some of the plurality of gates are designed to be active gates, and some of the plurality of gates are designed to be formed over the isolation regions. The method includes designing a plurality of gates in a regular and repeating alignment along the same direction, wherein each of the plurality of gates is designed to have dielectric spacers. The method also includes designing a local interconnect layer between the plurality of gates or adjacent the plurality of gates. The local interconnect layer is conductive and disposed on the substrate to permit electrical contact and interconnection to a portion of the active regions of the active gates or to portions of the active regions of the active regions. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.

Description

[0001] METHODS, STRUCTURES AND DESIGNS FOR SELF-ALIGNING LOCAL INTERCONNECTS [0002] USED IN INTEGRATED CIRCUITS FOR SELF-ALIGNING LOCAL INTERCONNECTORS USED IN INTEGRATED CIRCUITS [0003]

Field of the Invention

The present invention relates generally to integrated circuits, and more particularly, but not exclusively, to the design and manufacture of self-aligned local interconnects for interconnecting semiconductor devices in integrated circuits.

background

As semiconductor technology continues to advance, there is a trend toward very large scale integration with the manufacture of smaller and smaller integrated circuits that contain increasingly more devices on a single semiconductor chip.

Scaling of devices has long been used to increase the density of logic and memory functions. This scaling was possible due to improvements in photolithography and other process steps. However, since optical lithography has reached the end of the cost-effectiveness improvement curve, other approaches are needed to improve density.

The interconnects provide connections between NMOS and PMOS transistors and other components such as resistors and capacitors in the semiconductor chip. Generally, interconnects are fabricated by first depositing and planarizing dielectric layers on semiconductor devices and passive components. Next, feed-thrus are formed in the dielectric layers. Finally, conductors are formed and routed over the dielectric layers to connect the feed-throughs. To complete the circuit node interconnect, a stack is formed with a plurality of layers of dielectrics, feed-throughs, and conductors. This process of manufacturing the interconnects is generally referred to as "metallization ". As the density of devices on the semiconductor chip increases, the complexity of the metallization also increases.

The local interconnects may be a special form of interconnects. In general, local interconnects are used for short distances, such as inside functional cells. Conventional circuits use the same interconnect levels for both local and global connections.

Typically, the contacts of the diffusion regions and Vdd and Vss each require fabricating L-shaped or T-shaped bent diffusion regions extending from the PMOS and NMOS diffusion regions towards the Vdd and Vss lines. Curved regions are undesirable because they require more expensive photolithographic equipment to fabricate. Alternatively, the Vdd and Vss rails may extend over the rectangular diffusion regions, and contacts may be formed in the diffusion regions. However, having power rails on top of diffusion regions is inefficient because the power rails occupy tracks that may be used for signals, and power rails are no longer located at cell boundaries and can not be shared among vertically adjacent cells. to be.

Embodiments of the present invention occur within this context.

Broadly speaking, embodiments of the present invention define fabrication methods, structures, layouts, design methods, and conductive structures for enabling the definition of local interconnections in a circuit. In accordance with embodiments of the present invention, the local interconnects are arranged in the channels or regions between the gate electrodes or in the regions adjacent to the gate electrodes in response to the fabrication process, where the "self-aligned" . The local interconnects are those defined in a self-aligned orientation that can be patterned to leave only the portions required to remove some of the material and complete selected local interconnects.

One of the many beneficial features is that the circuit layout can be done in rectangular or substantially diffusion regions. These rectangular diffusion regions can be fabricated with better accuracy than diffusion regions with bends or elongations. In addition, the self-aligned local interconnects may be used to make power connections (i.e., Vdd and Vss) with the sources and drains of the transistors, without requiring diffusion region extensions. In addition, the self-aligned local interconnects can eliminate the need for specific contacts to the transistor diffusion regions. As will be described in more detail below, the local interconnections make direct and integral contact with the diffusion regions. Thus, the local interconnections may be formed in the first metal tracks, in certain vias, and in some cases, on a second metal track (e.g., for connections between NMOS transistor source / drains and PMOS transistor source / To provide a previously unavailable metal routing on the substrate level, which serves to eliminate the need for a metal layer.

Also, by removing conventional diffusion contacts in the active transistor channels, the strain layer in the diffusion regions is not deformed. This improves the effect of mobility to strengthen the strain layers. Also, allowing the diffusion contacts to be connected with a wider selection of metal-1 tracks provides more flexibility in circuit design, thus enhancing layout and directing to more efficient placement and routing.

In one embodiment, a method for designing local interconnect structures is disclosed. The method includes designing diffusion regions to be within the substrate. Some of the plurality of gates are designed to be active gates, and some of the plurality of gates are designed to be formed over the isolation regions. The method includes designing a plurality of gates in a regular and repeating alignment along the same direction, wherein each of the plurality of gates is designed to have dielectric spacers. The method also includes designing a local interconnect layer between the plurality of gates or adjacent the plurality of gates. The local interconnect layer is conductive and disposed on the substrate to permit electrical contact and interconnection to a portion of the active regions of the active gates or to portions of the active regions of the active regions. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.

The advantages of the present invention are numerous. Most notably, self-aligned local interconnects allow diffusion regions with fewer curvatures, extensions, and the like. In addition, the self-aligned local interconnects reduce the number of contacts required, the use of one metal track, the number of vias required to make contact with the diffusions, and subsequently metal two track usage. Thus, more tracks are opened for routing. In addition, the use of self-aligned local interconnects reduces the use of metal to diffusion contacts, which reduces interference with strain materials on the substrate. Thus, by removing most of the metal into the diffusion regions, the device efficiency is significantly increased. In addition, the self-aligned local interconnects provide more flexibility in metal-1 track assignments for connections within cells or cells, thereby improving density and simplifying subsequent placement and routing.

Another advantage of the self-aligned process for the fabrication of local interconnects compared to the photo aligned process is that the fabrication of the self-aligned local interconnects is dependent on lithography for aligning the sidewall spacers and local interconnects of the gates Is not required. It is known that lithography has a margin of error and therefore, even if the small shift in the local interconnect layer towards the sidewall spacers of the gates in the integrated circuit is "short", the device will result in undesired results.

Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements.
Figure 1 illustrates a generalized stack of layers used to define a dynamic array architecture, in accordance with an embodiment of the invention.
Figure 2a illustrates an exemplary base grid to be projected onto a dynamic array to facilitate definition of a constrained topology, in accordance with an embodiment of the invention.
Figure 2b illustrates individual base gratings projected over individual areas of the die, in accordance with an exemplary embodiment of the present invention.
Figure 3 illustrates an exemplary dynamic array diffusion layer layout, in accordance with one embodiment of the present invention.
Figure 4 illustrates a gate electrode layer and a diffusion layer of Figure 3, according to one embodiment of the present invention.
5A illustrates a circuit representation of a logic inverter using PMOS and NMOS transistors, in accordance with an embodiment of the invention.
5B illustrates a top view of an exemplary logic inverter to illustrate the use of self-aligned local interconnects, in accordance with an embodiment of the present invention.
6A illustrates a top view of an exemplary logic inverter illustrating sidewall spacers surrounding transistor source / drains, electrodes, and gate electrodes, in accordance with an embodiment of the present invention.
Figure 6B is a cross-sectional view of the exemplary logic inverter of Figure 6A, showing the transistor wells, transistor source / drains, gate electrodes, sidewall spacers, and STI regions, along a cut line A-A ' Fig.
Figure 7A illustrates a section of an exemplary logic inverter having a local interconnect layer that covers the underlying elements shown in Figure 6A, in accordance with an embodiment of the invention.
Figure 7b is a cross-sectional view of a section of an exemplary logic inverter having a local interconnect layer covering the underlying elements shown in Figure 6b, in accordance with an embodiment of the invention.
Figure 8A illustrates the formation of a silicide through annealing of a local interconnect layer, in accordance with an embodiment of the present invention.
Figure 8b illustrates depositing a hard mask layer on top of a local interconnect layer on a substrate, in accordance with an embodiment of the invention.
Figure 9A illustrates a polymer layer covering the elements of Figure 8B, in accordance with an embodiment of the present invention.
Figure 9b illustrates a cross-sectional view of a substrate in which a polymer layer is partially removed through plasma etching, in accordance with an embodiment of the present invention.
Figure 9c illustrates a top view of a substrate in which the polymer layer is etched back to approximately the top of the gate electrodes, according to one embodiment of the present invention.
Figure 10a illustrates a top view of an exemplary logic inverter after wet etching to remove polymer from dielectric spacers, in accordance with an embodiment of the present invention.
Figure 10b illustrates a cross-sectional view of an exemplary logic inverter after removal of a polymer covering dielectric spacers, in accordance with an embodiment of the present invention.
11A illustrates a cross-sectional view of an exemplary logic inverter after etching a local interconnect layer and a hard mask layer from gate electrodes and dielectric spacers, in accordance with an embodiment of the invention.
11B illustrates a cross-sectional view of an exemplary logic inverter after selective etching of a residual polymer layer and a hard mask layer, in accordance with an embodiment of the present invention.
Figure 12 illustrates a plan view of an exemplary logic inverter after selective etching of a residual polymer layer and a hard mask layer, in accordance with an embodiment of the present invention.
Figure 13 illustrates a top view of an exemplary logic inverter after masking portions of the local interconnect layer to protect the local interconnect layer at desired locations, in accordance with an embodiment of the present invention.
Figure 14 illustrates a top view of an exemplary logic inverter illustrating residual regions of silicided and non-silicided local interconnects, in accordance with an embodiment of the invention.
Figure 15 illustrates a top view of the exemplary logic inverter of Figure 14, with contacts and metal lines added to the functional interconnections shown, in accordance with an embodiment of the present invention.
16 illustrates a plan view of an exemplary logic inverter illustrating self-aligned local interconnects in a gap of a gate line, in accordance with an embodiment of the present invention.
Figures 17A-17D illustrate cross-sectional views of an exemplary logic inverter using local interconnect metals for making connections to a gate, in accordance with an embodiment of the invention.
18 depicts a self-aligned local interconnect within a gap of a gate line, according to one embodiment of the present invention, and illustrates an exemplary logic inverter that is connected to a gate when "climbing & Fig.

Disclosed are embodiments of the invention for methods and processes for designing, layout-out, fabrication, fabrication, and implementation of "self-aligned local interconnects" in integrated circuits. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. In one embodiment, a process for fabricating self-aligned local interconnects is provided. In other embodiments, a method and layout techniques for using self-aligned local interconnects as an example are disclosed. The advantages and advantages of using these self-aligned local interconnects are also outlined below with particular reference to a particular logic cell. It should be understood, however, that the exemplary logic cell is not limited to the use of self-aligned local interconnections. The use of self-aligned local interconnects may be extended to any circuit layout, logic device, logic cell, logic primitive, interconnect structure, design mask, and the like. Accordingly, in the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.

The self-aligned local interconnects have a number of applications in the manufacture of integrated circuits. Self-alignment of local interconnects in integrated circuits eliminates lithographic error margins and even small misalignment of local interconnects on an integrated circuit can cause electrical shorts and / or disable the device, .

Also, the self-aligned local interconnects may be used for various other purposes. One such purpose is to use self-aligned local interconnects to remove metal contacts from the diffusion regions of the transistors.

In addition, the process of fabricating "self-aligned" local interconnects in integrated circuits is advantageous over other techniques requiring precise alignment through lithographic processes. As is known, as the feature sizes continue to shrink, the ability to precisely align the masks has failed to follow. In addition, interference patterns from neighboring features can create a reinforcement or destructive interference. In the case of constructive interference, unwanted shapes may be generated inadvertently. In the case of destructive interference, desired shapes may be inadvertently removed. In any case, a particular shape is printed in a manner different from that intended, possibly causing device failure. Correction methods such as optical proximity correction (OPC) attempt to predict the effects from neighboring features and to modify the mask so that the printed features are manufactured as desired. However, as described, the quality of light interaction prediction is decreasing as process geometries are reduced and as optical interactions become more complex.

With this overview in mind, the following figures will illustrate exemplary structures, fabrication steps, layout geometries, masks, and interconnect layouts. All of these can be presented in any of the layers of the layout, masks, computer files with mask definitions, and resultant layers on a semiconductor substrate. As a result, it should be understood that the manufacturing processes described below are merely illustrative, and that some steps may be replaced or omitted with other steps as long as the ideas and definitions of "self-aligned" local interconnect lines are maintained .

In one embodiment, the methods and structures of the present invention take advantage of coincident feature orientation that defines a canvas of substantially uniform feature orientations. In the canvas, multiple diffusion regions are defined within the substrate to define active regions for transistor devices. The canvas also includes a plurality of linear gate electrode segments oriented in a common direction on the substrate. Some of the linear gate electrode segments are disposed over the diffusion region. Each of the linear gate electrode segments disposed over the diffusion region includes an essential active portion defined over the diffusion region and a uniformity extension defined to extend over the substrate over the diffusion region. In addition, the linear gate electrode segments are defined to have variable lengths to enable the logic gate function. The canvas further includes a plurality of linear conductor segments disposed in a level above the gate electrode segments such that the common direction of the gate electrode segments is traversed in a substantially perpendicular direction. The plurality of linear conductor segments are defined to minimize the end-to-end spacing between adjacent linear conductor segments in a common line on the substrate.

In describing the drawings and in describing the embodiments, various details of known manufacturing processes have been omitted in order to provide clarity and focus on the described embodiments. Also, a number of terms related to the manufacturing process are not described in detail since they are well known in the art.

I. An overview of the canvas design that implements matching relative feature orientation

1 is a diagram illustrating a generalized stack of layers used to define a dynamic array architecture, in accordance with an embodiment of the invention. It should be appreciated that, as described with respect to FIG. 1, the generalized stack of layers used to define the dynamic array architecture is not intended to express a thorough description of the CMOS fabrication process. However, the dynamic array will be built according to standard CMOS fabrication processes. Generally speaking, the dynamic array architecture includes both definitions of the underlay structure of the dynamic array and techniques for assembling the dynamic array for optimization of area utilization and manufacturability. Thus, the dynamic array is designed to optimize semiconductor fabrication capabilities.

For the definition of the underlying structure of a dynamic array, the dynamic array is constructed in a layered manner on a base substrate (e.g. a semiconductor wafer) 201, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. The diffusion regions 203 are defined in the base substrate 201. Generally, the diffusion regions 203 are separated by isolation regions or by shell low trench isolation (STI) regions. The diffusion regions 203 represent selected regions of the base substrate 201 where impurities are introduced for the purpose of modifying the electrical properties of the base substrate 201. Above the diffusion regions 203, diffusion contacts 205 are defined to enable connection between diffusion regions 203 and conductor lines. For example, diffusion contacts 205 are defined to enable connection between source and drain diffusion regions 203 and their respective conductor nets (net). Gate electrode features 207 are also defined over the diffusion regions 203 to form transistor gates. Gate electrode contacts 209 are defined to enable connection between gate electrode features 207 and conductor lines. For example, gate electrode contacts 209 are defined to enable connection between transistor gates and their respective conductor nets.

Interconnection layers are defined above the diffusion contact layer 205 and the gate electrode contact layer 209. The interconnect layers are formed by depositing a first metal (metal 1) layer 211, a first via (via 1) layer 213, a second metal (metal 2) 217, a third metal (metal 3) layer 219, a third via (via 3) layer 221, and a fourth metal (metal 4) layer 223. The metal and via layers enable the definition of the desired circuit connection. For example, the metal and via layers enable electrical connection of the various diffusion contacts 205 and the gate electrode contacts 209 to realize the logic function of the circuit. It should be appreciated that the dynamic array architecture is not limited to any particular number of interconnect layers, i.e., metal and via layers. In one embodiment, the dynamic array may include additional interconnect layers 225, over a fourth metal (metal 4) layer 223. Alternatively, in other embodiments, the dynamic array may include fewer than four metal layers.

The dynamic array is defined such that the layers (other than the diffusion region layer 203) are constrained to the layout feature shapes that can be defined therein. Specifically, in each layer other than the diffusion region layer 203, substantially linear-shaped layout features are allowed. The linear-shaped layout features in a given layer have a matching vertical cross-sectional shape and are characterized by extending in a single direction on the substrate. However, when some contacts need to be made on some lines, some small vertical projections may be allowed, but these small vertical projections should not constitute a substantial change in direction. Thus, linear-shaped layout features define structures that vary in one-dimensional. Diffusion areas 203 are not required to change to one-dimensional, even if allowed, if necessary. Specifically, the diffusion regions 203 in the substrate can be defined to have any two-dimensionally varying shape with respect to the plane coinciding with the top surface of the substrate. In one embodiment, multiple diffuse curved topologies are defined such that the interaction between a conductive material, such as polysilicon, forming the gate electrode of the transistor, and the bend in diffusion, can be predicted and accurately modeled. The linear-shaped layout features in a given layer are arranged to be parallel to each other. Thus, the linear-shaped layout features within a given layer extend parallel to the substrate in a common direction on the substrate.

In one embodiment, the underlaying layout method of the dynamic array may (but need not necessarily) use the enhanced optical interference of the optical waves in the lithographic process to augment the exposure of neighboring features in a given layer. Thus, the spacing of parallel linear-shaped layout features within a given layer is designed near the reinforced optical interference of standing light waves such that lithographic correction (e.g., OPC / RET) is minimized or eliminated . Thus, in contrast to conventional OPC / RET-based lithographic processes, a dynamic array, as defined herein, can be used for optical interactions between neighboring features, rather than attempting to compensate for optical interactions between neighboring features .

Since the normal optical wave for a given linear-shaped layout feature can be accurately modeled, it is possible to predict how normal optical waves associated with parallelly arranged neighboring linear-shaped layout features within a given layer will interact It is possible. It is therefore possible to predict how a normal light wave used to expose one linear-shaped feature will contribute to the exposure of its neighboring linear-shaped features. Prediction of optical interactions between neighboring linear-shaped features enables identification of the optimal feature-feature spacing such that the light used to render the desired shape reinforces its neighboring features. The feature-feature spacing in a given layer is defined as the feature pitch, where the pitch is the center-center separation distance between adjacent linear-shaped features in a given layer.

In one embodiment, the linear-shaped layout features in a given layer are arranged so that the reinforcement and destructive interference of light from neighboring features provides the best rendering of all neighboring features Quot; < / RTI > The feature-feature spacing within a given layer is proportional to the wavelength of light used to expose the features. The light used to expose each feature within about five light wavelength distances from a given feature will function to a certain extent to enhance the exposure of that feature. The utilization of the constructive interference of the optical waves used to expose the neighboring features allows the fabrication equipment capability to be maximized and not to be limited by considerations regarding optical interactions during the lithography process.

As discussed above, the dynamic array incorporates a constrained topology in which features in each layer (other than diffusion) are required to be substantially linear in shape and oriented in a parallel manner to traverse over the substrate in a common direction. Using the constrained topology of the dynamic array, optical interaction in the photolithographic process can be optimized to achieve accurate transfer of the layout onto the resist.

Figure 2a is a diagram illustrating an exemplary base grid to be projected onto a dynamic array to facilitate definition of a constrained topology, in accordance with an embodiment of the present invention. The base grating can be used to facilitate parallel placement of linear-shaped features within each layer of the dynamic array at appropriately optimized pitches. Although not physically defined as part of the dynamic array, the base lattice can be considered as a projection on each layer of the dynamic array. It should also be appreciated that the base grating is projected in a manner that substantially coincides with the position on each layer of the dynamic array to facilitate accurate feature stacking and alignment.

In the exemplary embodiment of FIG. 2A, the base grating is defined as a rectangular grating, that is, a Cartesian grating, along the first reference direction x and the second reference direction y. The lattice point-lattice point spacing of the first and second reference directions can be defined as needed to enable the definition of features that are linear-shaped with optimized feature-feature spacing. Further, the lattice point spacing in the first reference direction (x) may be different from the lattice point spacing in the second reference direction (y). In one embodiment, a single base grating is projected across the entire die to enable positioning of various linear-shaped features within each layer over the entire die. However, in other embodiments, individual base gratings may be projected over individual areas of the die to support different feature-feature spacing requirements within the individual areas of the die. Figure 2B is a diagram illustrating individual base gratings projected over individual areas of the die, in accordance with an exemplary embodiment of the present invention.

The layout architecture of the dynamic array follows the base grid pattern. Thus, the position at which changes in direction in the diffusion occur, the position at which the gate electrode and metal linear-shaped features are located, the position at which the contacts are located, the location of openings in the linearly shaped gate electrode and metal features, It is possible to use lattice points to do this. The pitch of the lattice points, or lattice point-lattice point spacing, is such that the exposure of neighboring linear-shaped features of a given feature line width at the center of the lattice points of the linear- It should be set for the feature line width. Referring to the dynamic array stack of FIG. 1 and the exemplary base grating of FIG. 2A, in one embodiment, the lattice point spacing of the first reference direction x is set by the required gate electrode pitch. In this same embodiment, the lattice point pitch in the second reference direction y is set by the metal one pitch. For example, in a 90 nm logic process technique, the lattice point pitch in the second reference direction y is about 0.24 microns. In one embodiment, the metal 1 and metal 2 layers will have a common spacing and pitch. Different spacing and pitches over the two metal layers may be used.

The various layers of the dynamic array are defined such that the linear-shaped features in adjacent layers extend in a crosswise manner with respect to each other. For example, the linear-shaped features of adjacent layers may be orthogonal, i.e. extending perpendicular to each other. In addition, the linearly shaped features of one layer may extend across the linearly shaped features of each adjacent layer, such as about 45 degrees. For example, in one embodiment, the linear-shaped features of one layer extend in a first reference direction x, and the linear-shaped features of adjacent layers extend in a first (x) and a second (y) As shown in Fig. In order to route the design in a dynamic array with linear-shaped features arranged in a transverse fashion in adjacent layers, openings can be defined in linear-shaped features and contacts and vias can be defined as needed Should be recognized.

The dynamic array minimizes the use of curvatures (or substantial changes in direction) in the layout shapes to remove unpredictable lithographic interactions. Specifically, prior to OPC or other RET processing, the dynamic array allows for flexures in the diffusion layer to enable control of device sizes, but allows for substantial flexures (or substantial changes in direction) in the layers above the diffusion layer Do not allow it.

An exemplary construction of the dynamic array layers from diffusion to metal 2 is described with reference to FIGS. 3 and 4. FIG. It should be appreciated that the dynamic arrays described with respect to Figures 3 and 4 are provided by way of example only and are not intended to convey limitations of the dynamic array architecture. The dynamic array may be used in accordance with the principles set forth herein to essentially define any integrated circuit design, any logic cell, base cell, architecture, or design layout. The designs can be made on physical chips, wafers, substrates, or can be drawn on paper, film, or stored as files. When stored as files, the files may be stored on any computer readable device. The computer-readable device may be stored on a local computer, a networked computer, and the files may be transferred, shared, or used over the Internet or a local network.

Figure 3 illustrates an exemplary dynamic array diffusion layer layout, in accordance with one embodiment of the present invention. The diffusion layer of FIG. 3 shows a p-diffusion region 401 and an n-diffusion region 403. Although the diffusion regions are defined according to the underlying base grating, the diffusion regions do not experience the linear-shaped feature constraints associated with the layers on the diffusion layer. However, it is noted that the implant layouts are simpler than in prior art designs which may require more profile extensions and flexures. As shown, n + implant regions 412 and p + implant regions 414 are defined as rectangles on the (x), (y) lattice without external jogs and notches . This style allows the use of larger injection areas, reduces the need for OPC / RET, and allows for the use of lower resolution and lower cost lithography systems, such as i-line illumination, for example at 365 nm. .

Figure 4 is a diagram showing a gate electrode layer adjacent to the diffusion layer of Figure 3 on the diffusion layer of Figure 3, in accordance with an embodiment of the invention. As will be appreciated by those skilled in the CMOS art, gate electrode features 501 define transistor gates. The gate electrode features 501 are defined as linear shaped features extending in a parallel relationship across the dynamic array in a second reference direction y. In one embodiment, the gate electrode features 501 are defined to have a common width. However, in other embodiments, one or more of the gate electrode features may be defined to have different widths. The pitch (center-to-center spacing) of the gate electrode features 501 is minimized while ensuring the optimization of lithographic reinforcement, i.e., resonance imaging, provided by the neighboring gate electrode features 501. For purposes of discussion, gate electrode features 501 extending over a dynamic array in a given line are referred to as gate electrode tracks.

The gate electrode features 501 form n-channel and p-channel transistors as they traverse the diffusion regions 403 and 401, respectively. Optimal gate electrode feature 501 printing is accomplished by drawing gate electrode features 501 at all lattice locations, although diffusion regions may not be present at some lattice positions. In addition, the long continuous gate electrode features 501 tend to improve line end shortening effects at the ends of the gate electrode features within the interior of the dynamic array. In addition, gate electrode printing is significantly improved when substantially all of the curvatures are removed from the gate electrode features 501.

Each of the gate electrode tracks may be paused or disconnected at any number of times in a linear traversal across the dynamic array to provide the electrical connection required for the particular logic function to be implemented. When a predetermined gate electrode track is required to be interrupted, the separation between the ends of the gate electrode track segments at the breakpoint is minimized to such an extent that fabrication capability and electrical effects can be taken into account. In one embodiment, optimal fabrication is achieved when common termination-termination spacing is used between features in a particular layer.

II. Logic cell design using self-aligned local interconnects on the canvas

Figure 5A illustrates a circuit representation of an exemplary logic inverter. However, as discussed above, the logic inverter is only shown and described for communicating the process of making self-aligned local interconnects, which may be implemented in any other primitive, cell, logic device, or process method. As shown, PMOS transistor 110 and NMOS transistor 112 are coupled to make a logic inverter. The source of the PMOS transistor 110 is connected to the Vdd 118 and the drain of the PMOS transistor 112 is connected to the drain of the NMOS transistor 112. The source of the NMOS transistor 112 is connected to the ground (Vss) A common input 116 is provided to the transistors and an output 114 is provided at the drain of the PMOS transistor 110 and the drain of the NMOS transistor 112. Again, inverter logic is used as an example to provide an understanding of embodiments of the present invention. However, those skilled in the art will recognize that embodiments may also be employed in the manufacture of any other type of logic cells, devices, and integrated circuits.

5b shows an exemplary logic inverter with self-aligned local interconnects 58/60 for connecting P (64) and N (68) diffusion regions to Vdd 50 and Vss 54, respectively. Fig. In addition, the self-aligned local interconnect 62 is used to connect the drain of the PMOS transistor to the drain of the NMOS transistor. In one embodiment, all self-aligned local interconnects in the integrated circuit are parallel to the gate electrode channels on the substrate. One of the many advantages of placing local interconnects in one direction is that the local interconnect layer replaces one metal layer, which may otherwise need to be made using self-aligned local interconnects. I can do it. The metal first lines 50, 72, 70, and 54 are aligned in one direction perpendicular to the gate electrode line 74. The alignment of the metal lines may be different in other embodiments.

Continuing with FIG. 5B, there are a number of advantages of employing self-aligned local interconnects. In one example, the self-aligned local interconnect 58 connecting the P diffusion region 64 to the Vdd line 50 has the need to fabricate an L shaped diffusion region extending toward the Vdd line 50 Remove. In some designs, the self-aligned local interconnect 58 eliminates the need for a metal strap to connect the diffusion region 64 to the Vdd line 50. Removal of metal straps and associated contacts increases device performance and reduces device size. The performance is increased because the metal strap connecting to the diffusion regions may require one or more contacts that interfere with the beneficial straining of silicon. Thus, reducing the metal contacts to the diffusion regions will increase device performance unless needed for some design configurations.

6A illustrates a partially fabricated integrated circuit showing a P diffusion region 64 and an N diffusion region 68 and a gate electrode line 74 over P diffusion region 64 and N diffusion region 68 Fig. In this exemplary partial view, the other gate electrode lines 74a, 74b lie above the shell row trench isolation (STI) regions. The gate electrodes 74, 74a, 74b include dielectric spacers (or gate sidewall spacers) on either side.

Although not shown for convenience of explanation, the ends of the gate electrodes may also have dielectric spacers. By design, since the gate electrode lines are uniformly arranged on the substrates, some of the gate electrode lines are formed on the STI regions. Thus, the gates formed on the STI are inactive gates. The active gate is formed when the gate electrode is disposed over the diffusion region, and a transistor can be defined. In one embodiment, the partially fabricated integrated circuit is fabricated using a standard CMOS fabrication process.

Figure 6b illustrates a cross-sectional view of the partially fabricated integrated circuit of Figure 6a. It is to be understood that the drawings are not intended to provide an exact representation of the dimensions or exact relative dimensions. On the other hand, the figures should be understood to generally convey the arrangement of features and layers, and an exemplary sequence of processing. It should also be understood that some sequence steps are not illustrated in the figures, as they are not known to the art and are not critical to the process and sequence flows illustrated herein.

With this in mind, a partially fabricated integrated circuit is formed on a silicon wafer and includes isolation between adjacent active devices in the integrated circuit, including well 182 and shell low trench isolation (STI) to provide. Well 182 includes diffusion regions 184 and a gate electrode 74. The gate electrodes include dielectric spacers 230 (also known as sidewall spacers) formed along the sides of the gate electrode lines. As discussed above, to optimize the design, the gate electrodes (or lines) are fabricated in an orientation parallel to each other. Thus, as described herein, "channels" are defined between each gate electrode. Thus, the spacing between two adjacent gate electrode channels is governed by the regular spacing of the gate electrode lines. As will be described in greater detail below, the resulting self-aligned local interconnections will be in channels between adjacent gate electrodes (or next to the gate electrode if no neighboring gate electrode is present). Because the self-aligned local interconnects will most likely remain within the channels, the self-aligned local interconnects will self-align.

7A and 7B, a local interconnect layer 196 is formed over the diffusion regions 184, gate electrodes 74, 74a, 74b, and spacers. By way of example, formation of the local interconnect layer 196 may be accomplished through a metal deposition process. For ease of visualization, the local interconnect layer 196 is shown as a translucent layer in FIG. 7A. The cross-section of Figure 7b shows the local interconnect layer 196 deposited over the features of Figure 6b.

In one embodiment, the local interconnect layer 196 is generally metallic. In a more specific embodiment, the metal may be mostly nickel (Ni). In other embodiments, the metal may be titanium, platinum, or cobalt. In another embodiment, a combination of nickel and platinum may be used. Preferably, the purity of the metal used in the local interconnect layer must conform to industry standard metals. In one embodiment, the local interconnect layer is deposited using physical vapor deposition (PVD) techniques. In other embodiments, the deposition of the local interconnect layer may be done via chemical vapor deposition (CVD) or atomic layer deposition (ALD).

After depositing the interconnect layer 196, the metal of the interconnect layer is reacted with the underlying silicon and, if present in the gate electrode, with the polysilicon. In one example, the reaction is facilitated through a thermal processing step. The reaction may be performed under a number of process conditions, but for example, for a nickel layer, the temperature may range between about 200 and 400 degrees Celsius and may be maintained for a time in the range of about 5 to about 60 seconds ; Higher temperatures may be used for other metals. In another example, the temperature can be set at about 300 degrees Celsius and can be processed for about 30 seconds. The reaction step is generally carried out in a chamber using nitrogen or other inert gases.

As shown in FIG. 8A, as a result of the reaction process, silicide 196 'is formed over the exposed silicon regions. Thus, silicidation (i.e., formation of silicide 196 ') occurs over exposed silicon substrate portions and polysilicon gates that are exposed if present. As is known, the silicide 196 'provides good conduction even when the layer is thin. Portions of the local interconnect layer 196 metal that are not in contact with silicon will, of course, remain as a metal after the reaction process. In the figures, FIG. 8A shaded the silicide 196 ', in contrast to the metal of the local interconnect layer 196 that did not react.

FIG. 8B illustrates the result after the hard mask layer 199 is deposited over the local interconnect layer 196. In one embodiment, the hard mask layer 199 may be an oxide (e.g., SiO _2, etc.). In another embodiment, hardmask layer 199 is a nitride (e.g., silicon nitride, etc.). In yet another embodiment, hardmask layer 199 is amorphous carbon (APF). The hardmask layer 199 can be formed in a number of ways, one such example approach employing one of the CVD, ALD, or PECVD processes. In this embodiment, the hard mask layer 199 is used to protect the local interconnect layer 196 during subsequent removal steps to remove portions of the local interconnect layer 196 where no conductive connection is required .

Figure 9A illustrates a cross-sectional view of Figure 8B after a polymer layer 210 is formed over the hardmask layer 199, in accordance with an embodiment of the present invention. The polymer layer 210 may be applied in a number of known ways. In one example, the polymer layer 210 is preferably spin-coated on the surface of the hard mask layer 199. In another embodiment, the polymer layer 210 may be a positive or negative photoresist material, depending on the desired development process. Other types of photoresist may include, for example, unsensitized photoresists, polymethyl methacrylate resists (PMMA), and the like. If applied, the polymer layer 210 is partially and uniformly removed until the hard mask layer 199 is exposed, as shown in FIG. 9B. The removal is preferably performed using a plasma etch operation. One exemplary etching process may be performed in an oxygen plasma. At this stage, the etch process is preferably substantially anisotropic to achieve a substantially uniform removal profile down to the first exposed hardmask layer 199. Standard termination-point detection techniques may be used to determine when to stop the etching operation illustrated in Figure 9B. FIG. 9C is a plan view showing the exposed hard mask layer 199 and the residual polymer layer 210. FIG. In this stage, gate sidewall spacers (i.e., dielectric spacers) 230 are also still covered by the polymer layer 210.

It should be noted that another advantage of disposing the gate electrode lines at regular regular intervals is that the polymer layer 210 is defined uniformly with substantially equivalent thickness. Without such uniform spacing, the polymer layer 210 may exhibit variations in thickness, which is undesirable. For example, if the thickness of the polymer layer 210 is not substantially uniform over the substrate, some of the gate electrodes covered by the relatively less polymeric material may be exposed first to overetch the hardmask over the specific gates ). ≪ / RTI >

When the hard mask layer 199 on top of the gate electrodes 74, 74a, 74b is exposed, isotropic etching is performed. Isotropic etching is designed to remove side portions 238 of the polymer layer 210, such as the polymer layer 210 on the gate electrode dielectric spacers 230. 10A and 10B, after the isotropic etching is completed, the polymer layer 210 is offset from the gate dielectric spacers 230 and self-aligned with the gate electrodes 74, 74a , 74b) in the form of strips. Thus, the polymer layer 210 will remain everywhere on the substrate except for the gate electrode lines 74, 74a, 74b and the gate dielectric spacers 230.

11A illustrates a cross-section of a substrate after a hard mask layer 199 not covered by the polymer layer 210 has been removed. Depending on the material of the selected hardmask, the removal may be performed using a number of known wet or dry etching processes. In one embodiment, when the exposed hardmask layer 199 is removed, etching may be continued to remove portions of the material of the local interconnect layer 196 over the dielectric spacers 230. The removal of this portion of the local interconnect layer 196 will provide some isolation between the local interconnect layer 196 / silicide 196 'and the dielectric spacers 230. At this point, the residual local interconnect layer 196 material, the silicide 196 'material, and the hard mask layer 199, which are covered by the polymer layer 210, Lt; RTI ID = 0.0 > 230 < / RTI >

11B illustrates another selective etch operation after removal of the polymer layer 210 and hard mask layer 199 from the top of the local interconnect layer 196 (including the silicide portions 196 ' Sectional view of the substrate of FIG. As shown, the local interconnect layer 196 material and silicide portions 196 'will be self-aligned between the dielectric spacers 230. Figure 12 shows a top view of the substrate of Figure 11b. As shown, the local interconnect layer 196 extends in the channels between the gate dielectric spacers 230. As described above, as a result of the etching, the self-aligned local interconnect layer 196 is also spaced a distance 231 from the dielectric spacers 230. 12 also illustrates P (64) and N (68) diffusion regions (both of which are illustrated in cross-sectional views as diffusion regions 184).

13 illustrates a patterning operation to facilitate etching, according to an embodiment of the present invention. In one embodiment, the photoresist is spin coated and then exposed using standard photolithography to define the mask 300. As shown, the mask 300 is defined to cover portions of the local interconnect layer 196 that will remain after the etching operation is performed. The reacted material that forms the silicide 196 'over the exposed silicon or polysilicon, if present, will also remain after etching, even if it is not covered by the mask 300. In one embodiment, the mask 300 can be easily defined without strict layout constraints, since the mask 300 can be defined to be approximately over the gate electrodes 74, 74a, 74b.

It should be appreciated that strict layout constraints are not required because the local interconnect layer 196 material is only within the channels and is already self-aligned between the dielectric spacers 230. Again, however, the silicide 196 'material will remain after etching employed to remove unprotected portions of the local interconnect layer 196. Electrically, the local interconnect layer 196 and the silicide 196 'material will define a conductive link or connection or conductive line similar to a regular interconnect metal line.

14 illustrates a top view of the substrate after etching and subsequent removal of the mask 300. FIG. As shown, the local interconnect layer 196 will remain in the channels where the mask 300 has protected the material, thus forming true self-aligned local interconnect features. Thus, the residual local interconnect layer 196 will functionally complete any desired interconnections within the channel defined between the dielectric spacers 230. [ After the removal of the mask 300, an annealing operation may be performed. For example, annealing may be a rapid thermal annealing (RTA) process operating at approximately 450 degrees Celsius for approximately 30 seconds for nickel.

Referring again to FIG. 5B, as shown in FIG. 15, metal 1 lines may be fabricated perpendicular to the gate electrode lines 74, 74a, 74b. In addition, contacts are formed at desired locations to provide electrical conduction between the various layers, which is necessary to form an exemplary logic circuit.

In one embodiment, metal-1 tracks 702 may be fabricated closer together to each other, which may facilitate easier routing and desired connections. Naturally, the pitch between the lines will depend on the manufacturing capabilities, the particular circuit, the layout, and layout constraints on the type of design and / or circuit. Aligned and localized interconnects 196 are vertically aligned with the metal-1 tracks 702 so that the contact between the self-aligned local interconnects 196 and the selected metal- A greater degree of freedom is available in terms of space in selection. Thus, in addition to the previously discussed advantages of self-aligned local interconnects, self-aligned local interconnects also assist in providing more freedom in routing metal tracks at the above levels, Provides flexibility in design and manufacturing.

Figure 16 illustrates an exemplary inverter logic cell fabricated using the self-aligned local interconnections of the present invention. The circuit is similar to the circuit illustrated in Figure 5A, except that the gate electrode line 74a is divided into two sections to provide a gate electrode gap 703. It may be noted that only one gap is shown for convenience of illustration. In other embodiments, one or more gate electrode lines may have one or more gate electrode gaps. In one embodiment, the gate electrode gap 703 can be used to fabricate self-aligned local interconnects vertically aligned with the gate electrode line 74a. The self-aligned local interconnections in these gate electrode gaps 703 may be used to connect two self-aligned local interconnects or two or more devices parallel to the gate electrode line 74a. In addition, the self-aligned local interconnections in the gate electrode gaps 703 facilitate metal track routing and eliminate the need for some of the metal-1 tracks.

17A-17D illustrate the process operations used to facilitate connection using the local interconnect layer 196 to make contact to the gate electrode 74, in accordance with another embodiment of the present invention. . For ease of understanding, reference is made to cross section 400 also shown in Fig. FIG. 17A represents a stage in processing similar to the processing described up to FIG. 10B. However, a mask 404 is also formed over the region 402 that lies substantially on the sidewalls of the spacers 230 of the gate electrode 74. As long as protection is provided over the material placed along the spacer 230, accurate sizing is not particularly important. This protects the local interconnect material 196 in this area from later etching. The mask 404 may be defined from hard masks or photoresist masks, depending on the selected fabrication process.

FIG. 17B shows the processing after the etching operation is used to remove the exposed hard mask layer 199. FIG. As shown, similar to the process of FIG. 11A, the exposed hardmask layer 199 and the local interconnect layer 196 are removed. The mask 404, the polymer layer 210, and the hard mask 199 are now removed, leaving a local interconnect layer 196, as shown in Figure 17C. 17C also illustrates a mask 300 'used to protect the local interconnect layer 196 at locations where the local interconnect layer 196 is intended to remain. The mask 300 'is shown as protecting over and above the local interconnect layer 196 in the region 402. Thus, because the mask 404 has been used, the local interconnect layer 106 will remain on the sidewalls of the spacers 230, and therefore the local interconnect layers < RTI ID = 0.0 > (196). As a result, in order to make a connection to the gate electrode 74, a connection is made at the level of the substrate, without the need for upper metal levels and contacts.

18 illustrates an exemplary use of a local interconnect layer 196 that clips the dielectric spacers 230 to make a connection to the gate electrode 74 in the region 402. FIG. In this example, the local interconnect layer 196 (going over the spacer 230) makes an electrical connection to the gate electrode 74. It should be understood, however, that the structures and methods used to form the climbing connections over the spacers 230 can be used in a number of different designs, circuits, cells, and logic interconnections.

Methods, designs, layouts, and structures have been disclosed that define ways of using self-aligned local interconnects. It should be noted that the benefits and advantages of using these self-aligned local interconnects are not tied to any particular circuit, cell, or logic. Conversely, the disclosure of these self-aligned local interconnect methods and structures may be extended to any circuit layout, logic device, logic cell, logic primitive, interconnect structure, design mask, and the like. And the layout, design, configuration, or data of the results used to define the self-aligned local interconnects (in any part or area of the chip, larger overall system or implementation) may be stored electronically on the file . The file may be stored on a computer readable medium and the computer readable medium may be shared, transmitted, or communicated over a network, such as the Internet.

Thus, while bearing in mind the above embodiments, it is to be understood that the invention is not limited to the particular embodiments set forth herein, but that the invention may be practiced otherwise than as described in the context of a manufacturing process, a sequence of manufacturing steps, a sequence of manufacturing steps, a chemical used in manufacturing, It should be understood that changes may be employed. While the present invention has been described in terms of several preferred embodiments, it will be apparent to those skilled in the art, upon reading the specification and studying the drawings, that various modifications, additions, substitutions, and equivalents will occur to those skilled in the art. Accordingly, the invention is intended to include all such modifications, additions, substitutions, and equivalents as fall within the true spirit and scope of the present invention.

Claims (22)

At least four linear conductor structures, each of the at least four linear conductor structures being formed to extend in a longitudinal direction in a first direction in a mutually parallel manner, each of the gate electrode portions and the extending portion Wherein each of the gate electrode portions of the at least four linear conductor structures form gate electrodes of different transistors and the extending portions of the at least four linear conductor structures have at least two different extending portion lengths Wherein two of the at least four linear conductor structures form two transistors of a first transistor type each having a shared diffusion region of a first diffusion type and the at least four linear conductors Two of the linear conductor structures in the structures are the second Wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type, The at least four linear conductor structures; And
A plurality of linear conductor structures formed between at least two linear conductor structures of the at least four linear conductor structures so as to be able to extend in the first direction along at least two linear conductor structures of the at least four linear conductor structures. And a local interconnect conductor structure. The method according to claim 1,
Wherein a distance between longitudinally oriented center lines of any of the at least four linear conductor structures measured in a second direction perpendicular to the first direction is an integer multiple of the same pitch, integrated circuit. 3. The method of claim 2,
And at least one non-gate conductor structure formed within the same level as the at least four linear conductor structures without forming a gate electrode of the transistor. The method of claim 3,
Wherein a distance between center lines oriented in the longitudinal direction of adjacently located individual linear conductor structures of the at least four linear conductor structures measured in the second direction perpendicular to the first direction is the same pitch, integrated circuit. The method of claim 3,
Wherein the different transistors comprise collectively positioned first transistor type transistors and collectively positioned second transistor type transistors, wherein the extending portions of the at least four linear conductor structures are connected to the first transistor type < RTI ID = 0.0 > Of the second transistor type and the collective position of the transistors of the second transistor type. The method according to claim 1,
Wherein the first conductivity type is formed in the same level as the at least four linear conductor structures without forming the gate electrode of the transistor and the second conductivity type is formed in the nearest linear conductor structure when measured in a second direction perpendicular to the first direction, non-gate linear conductor structure within the < RTI ID = 0.0 > And
Further comprising a diffusion region formed in a portion of the non-gate linear conductor structure and a portion of the region located between and lying one level below the nearest linear conductor structure. The method according to claim 6,
Wherein the non-gate linear conductor structure and the nearest linear conductor structure have substantially the same size when measured in the second direction perpendicular to the first direction. The method according to claim 1,
Wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type through the local interconnect conductor structure. The method according to claim 1,
Further comprising: a first linear conductor interconnect structure formed to extend in a longitudinal direction in a second direction perpendicular to the first direction. 10. The method of claim 9,
Further comprising a second linear conductor interconnect structure formed to extend longitudinally in the second direction perpendicular to the first direction and spaced laterally of the first linear conductor interconnect structure, . The method according to claim 1,
Further comprising a first linear conductor interconnect structure formed to extend longitudinally in the first direction. 12. The method of claim 11,
Further comprising a second linear conductor interconnect structure formed to extend longitudinally in the first direction and spaced apart next to the first linear conductor interconnect structure. 13. The method of claim 12,
The distance between the longitudinally oriented center lines of any of the at least four linear conductor structures measured in a second direction perpendicular to the first direction is an integer multiple of the same pitch,
Wherein a distance between longitudinally oriented center lines of the first and second linear conductor interconnect structures measured in the second direction perpendicular to the first direction is a rational multiple of the same pitch , An integrated circuit. 14. The method of claim 13,
Wherein the free water ratio is not more than 1 time. 15. The method of claim 14,
Wherein the free water ratio is one time. The method according to claim 1,
A level of interconnects comprising adjacent positioned conductor interconnect structures separated by a first centerline-to-center line distance measured in the first direction, wherein at least one of the extended portions of the at least four linear conductor structures Wherein the extension portion length measured in the first direction is greater than the first centerline-to-centerline distance. 17. The method of claim 16,
Wherein at least one extension of at least one of the extending portions of the at least four linear conductor structures is two times larger than the first centerline-to-center line distance and has an extended portion length measured in the first direction. The method according to claim 1,
Wherein at least one linear conductor structure of the at least four linear conductor structures has an extension length greater than a length of the gate electrode portion. The method according to claim 1,
Wherein the extending portions of the at least four linear conductor structures have at least three different extending portion lengths. The method according to claim 1,
Wherein the different transistors comprise collectively positioned first transistor type transistors and collectively positioned second transistor type transistors, wherein the extending portions of the at least four linear conductor structures are connected to the first transistor type < RTI ID = 0.0 > Of the transistors of the second transistor type and the collective position of the transistors of the second transistor type. To a data storage device comprising a stored program of instructions for a semiconductor device layout,
Wherein the at least four linear conductor structures each extend in a longitudinal direction in a first direction in a manner parallel to each other and each has a gate electrode portion and an extension extending away from the gate electrode portion Each of the gate electrode portions of the at least four linear conductor structures forming gate electrodes of different transistors and the extending portions of the at least four linear conductor structures having at least two different extending portion lengths Wherein the two linear conductor structures of the at least four linear conductor structures each form two transistors of a first transistor type having a shared diffusion region of a first diffusion type and the at least four linear conductor structures The two linear conductor structures of Type shared diffusion region, wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type A layout of the at least four linear conductor structures; And
A plurality of linear conductor structures formed between at least two linear conductor structures of the at least four linear conductor structures so as to be able to extend in the first direction along at least two linear conductor structures of the at least four linear conductor structures. And a layout of the local interconnect conductor structure. As a method of manufacturing an integrated circuit,
Forming at least four linear conductor structures in the gate electrode level of the integrated circuit, wherein the at least four linear conductor structures extend in a longitudinal direction of the first direction in a manner parallel to each other, And an extension extending away from the gate electrode portion, wherein each of the gate electrode portions of the at least four linear conductor structures form gate electrodes of different transistors, and wherein the extension portions of the at least four linear conductor structures The two linear conductor structures of the at least four linear conductor structures each comprise two transistors of the first transistor type having a shared diffusion region of a first diffusion type , Said at least four linear conductor spheres Each of the two linear conductor structures forming two transistors of a second transistor type having a shared diffusion region of a second diffusion type, wherein the shared diffusion region of the first diffusion type forms the second diffusion type Said at least four linear conductor structures being electrically connected to said shared diffusion region of said at least four linear conductor structures; And
At least two of the at least four linear conductor structures are arranged to extend in the first direction along at least two of the linear conductor structures, And forming an interconnect conductor structure. ≪ Desc / Clms Page number 21 >

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