JP2014112745A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an art capable of reducing a layout area of a standard cell included in a digital circuit even in a state where a new layout rule introduced with microfabrication of a MISFET is set.SOLUTION: In a semiconductor device, a projecting line PL1A projects from a power source line L1A at each of corners on both ends of a standard cell CL toward the inside (Y direction) of the standard cell CL, for example, and a bent part BD1A which bends from the projected projecting line PL1A in an X direction is formed. Each bent part BD1A is connected with a p-type semiconductor region PDR by a plug PLG.

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device including a logic circuit using a standard cell (standard cell).

  Japanese Patent Laying-Open No. 2008-110804 (Patent Document 1) describes a layout configuration in which a power supply wiring connected to a diffusion layer is drawn on a boundary line between adjacent standard cells. Specifically, Patent Document 1 describes that a layout configuration is made so that a diffusion layer is made common between adjacent standard cells and wiring is drawn out from a power supply wiring onto a boundary line between adjacent standard cells. . Patent Document 1 describes a configuration in which a wiring drawn on a boundary line between adjacent standard cells and a diffusion layer shared between adjacent standard cells are electrically connected by a plug.

JP 2008-118044 A

  Many integrated circuits are formed in a semiconductor device, and these integrated circuits are constituted by analog circuits or digital circuits. In particular, design techniques using standard cells are widely used as digital circuit layout design techniques. For example, unit circuits such as an inverter circuit, a NAND circuit, an EXOR circuit, and a flip-flop circuit are prepared as standard cells, and the standard cells are arranged in rows. A digital circuit (for example, a logic circuit) having a predetermined function is formed by designing wiring so that an integrated circuit is configured for a plurality of standard cells arranged in a row.

  At this time, each of the plurality of standard cells requires a power source for operation, and therefore the power supply wiring (VDD) and the reference wiring (GND) are arranged so as to sandwich the plurality of standard cells arranged in a row. The power supply voltage and the reference voltage are supplied to each standard cell by the lead wiring drawn from the power wiring (VDD) and the reference wiring (GND). That is, a power supply wiring (VDD) and a reference wiring (GND) extending in parallel in a predetermined direction are formed, and a plurality of standard cells are arranged in a predetermined direction so as to be sandwiched between the power supply wiring (VDD) and the reference wiring (GND). Is arranged. Since each standard cell is composed of a plurality of transistors, a diffusion layer and a gate electrode constituting the transistor are formed in each standard cell.

  Conventionally, there has been no restriction on the layout rule regarding the shape of the diffusion layer and the shape of the gate electrode constituting the standard cell, so that it has been possible to form diffusion layers and gate electrodes of any shape. For this reason, by devising the shape of the diffusion layer and the shape of the gate electrode, the layout of the standard cell could be freely designed so as to reduce the area of the integrated circuit.

  However, in recent years, transistors (MISFET (Metal Insulator Semiconductor Field Effect Transistor)) constituting an integrated circuit have been miniaturized and diffusion layers and gate electrodes constituting the MISFET have been miniaturized. The diffusion layer and the gate electrode are formed using a photolithography technique. However, when the diffusion layer and the gate electrode are miniaturized, the processing accuracy of the photolithography technique becomes a problem. In other words, the shape of the diffusion layer and the shape of the gate electrode were devised so that the layout of the standard cell is minimized, but from the problem of the processing accuracy of the photolithography technology caused by the miniaturization of the diffusion layer and the gate electrode, It has become difficult to form a diffusing layer and a gate electrode having complicated shapes as designed values.

  For example, if the shape of the diffusion layer is a complicated polygon, or if a bent part is formed in the gate electrode, the corner will be rounded due to processing accuracy problems in photolithography technology. Deterioration is likely to occur. In this case, the diffusion layer and the gate electrode have a shape deviating from the design value, resulting in variations in performance of the MISFET.

  Therefore, for example, in the case of forming a MISFET smaller than a 28 nm node, a certain restriction is provided in the layout rule in order to equalize (homogenize) the performance of the formed MISFET. That is, when the MISFET is miniaturized, it becomes difficult to form a complicated shape with high accuracy due to the problem of processing accuracy of the photolithography technique, so the shape of the diffusion layer and the gate electrode constituting the MISFET are simplified. A rule is set to guarantee the performance of the miniaturized MISFET. Specific layout rules include gate electrodes (polysilicon film) arranged at regular intervals and a straight line without bending the gate electrode at all, or a shape of the diffusion layer within 8 vertices Rules such as shapes are provided.

  Under the situation where such a new layout rule is provided, when a standard cell layout is designed, there is a problem that the area of the standard cell increases.

  An object of the present invention is to provide a technique capable of reducing the layout area of a standard cell constituting a digital circuit even in a situation where a new layout rule introduced with miniaturization of a MISFET is provided. There is to do.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a typical embodiment includes a first power supply wiring of a first wiring layer extending on a first side along a first direction, and a second side parallel to the first side at a predetermined interval. And a second power supply wiring of the first wiring layer to which a voltage lower than that of the first power supply wiring is applied. Furthermore, at both ends of the first side, two first protruding wirings that branch out from the first power supply wiring and protrude in the second direction toward the inside of the standard cell, and both ends of the second side 2 and two second protruding wirings that branch out from the second power supply wiring and protrude in the second direction toward the inside of the standard cell. Here, at least one or more of the protruding wirings extracted from the first protruding wiring and the second protruding wiring have a first bent portion whose end is bent in the first direction toward the inside of the standard cell. including.

  A semiconductor device according to a typical embodiment includes a plurality of standard cells arranged adjacent to each other along the first direction of the semiconductor substrate. At this time, each of the plurality of standard cells having a rectangular shape includes (a) a first power supply wiring of a first wiring layer extending on a first side along the first direction, and (b) the first power cell. And a second power supply wiring of the first wiring layer that extends on a second side parallel to the side by a predetermined distance and to which a voltage lower than that of the first power supply wiring is applied. And (c) a first semiconductor region and a second semiconductor arranged in a second direction intersecting the first direction in the semiconductor substrate between the first power supply wiring and the second power supply wiring. The first semiconductor region disposed on the first power supply wiring side and the second semiconductor region disposed on the second power supply wiring side, and (d) extending in the second direction, And a plurality of gate electrodes formed on the semiconductor substrate at equal intervals in the first direction. Further, each of the plurality of standard cells further includes (e) two pieces protruding from the first power supply wiring at both ends of the first side and projecting in the second direction toward the inside of the standard cell. And (f) two second protruding wirings that branch from the second power supply wiring and project in the second direction toward the inside of the standard cell at both ends of the second side. Have Here, at least one or more of the protruding wirings extracted from the first protruding wiring and the second protruding wiring have a first bent portion whose end is bent in the first direction toward the inside of the standard cell. including. When the protruding wiring in which the first bent portion is formed is branched from the first power supply wiring, the protruding wiring is connected to the first bent portion by the first plug. It is electrically connected to the semiconductor region. On the other hand, when the protruding wiring in which the first bent portion is formed is branched from the second power supply wiring, the protruding wiring is connected to the first bent portion by the second plug. It is electrically connected to the semiconductor region.

  A semiconductor device according to a typical embodiment includes a plurality of standard cells arranged adjacent to each other along the first direction of the semiconductor substrate. At this time, each of the plurality of standard cells having a rectangular shape includes (a) a first power supply wiring of a first wiring layer extending on a first side along the first direction, and (b) the first power cell. And a second power supply wiring of the first wiring layer that extends on a second side parallel to the side by a predetermined distance and to which a voltage lower than that of the first power supply wiring is applied. And (c) a first semiconductor region and a second semiconductor arranged in a second direction intersecting the first direction in the semiconductor substrate between the first power supply wiring and the second power supply wiring. The first semiconductor region disposed on the first power supply wiring side and the second semiconductor region disposed on the second power supply wiring side, and (d) extending in the second direction, And a plurality of gate electrodes formed on the semiconductor substrate at equal intervals in the first direction. Further, each of the plurality of standard cells further includes (e) two pieces protruding from the first power supply wiring at both ends of the first side and projecting in the second direction toward the inside of the standard cell. And (f) two second protruding wirings that branch from the second power supply wiring and project in the second direction toward the inside of the standard cell at both ends of the second side. Have One first gate electrode of the plurality of gate electrodes is disposed so as to planarly overlap a first boundary line connecting one end portion of the first side and one end portion of the second side. On the other hand, one second gate electrode of the plurality of gate electrodes is arranged so as to planarly overlap a second boundary line connecting the other end of the first side and the other end of the second side. Yes.

  The effects obtained by the representative embodiments of the invention disclosed in the present application will be briefly described as follows.

  Even in a situation where a new layout rule introduced with the miniaturization of MISFET is provided, the layout area of the standard cells constituting the digital circuit can be reduced.

It is a top view which shows the structure of the semiconductor chip in Embodiment 1 of this invention. FIG. 3 is a diagram showing a layout configuration of standard cells constituting the 4-input NAND circuit in the first embodiment. In Embodiment 1, it is a figure which shows the adjoining standard cell. (A) is a circuit diagram showing two inverter circuits connected in parallel between the input wiring and the output wiring, (b) is a plan view showing a layout configuration example of the inverter circuit shown in (a). . (A)-(d) is a figure which decomposes | disassembles and shows the layout structure of an inverter circuit for every layer. It is sectional drawing cut | disconnected by the AA line of FIG. It is sectional drawing cut | disconnected by the BB line of FIG. It is sectional drawing cut | disconnected by the CC line | wire of FIG. It is sectional drawing cut | disconnected by the DD line | wire of FIG. (A) is a circuit diagram showing the EX-OR circuit connected between the input wiring and the output wiring, (b) is a plan view showing a layout configuration example of the EX-OR circuit shown in (a). is there. (A) And (b) is a figure which decomposes | disassembles and shows the layout structure of an EX-OR circuit in two layers. It is a figure which shows the layout structure which arranged 6 standard cells which comprise an EX-OR circuit in 2 rows 3 columns. It is a figure which shows the layout structure which arranged the standard cell from which several functions differ, (a) is a figure which shows the lower layer which decomposed | disassembled the standard cell into two layers. On the other hand, (b) is a figure which shows the upper layer which decomposed | disassembled the standard cell into two layers. It is a figure which shows the layout structure of the standard cell which formed the flip-flop circuit with a SCAN function. FIG. 10 is a diagram showing a layout configuration of a first wiring layer of a standard cell in which a flip-flop circuit with a SCAN function in a fifth embodiment is formed. FIG. 10 is a diagram showing a second wiring layer of a standard cell in the fifth embodiment. It is a figure which shows the layout structural example of the wiring which connects between standard cells in a 2nd wiring layer. It is a figure which shows the example which applies the technical idea of this invention with respect to 2 input NAND circuit. In a comparative example, it is a figure which shows the layout structural example of the standard cell which comprises a 4-input NAND circuit. It is a figure which shows the comparative example using the conventional design method, and is a figure which shows two adjacent standard cells. In the inverter circuit of the comparative example provided with two inverters, it is a figure which shows the gate electrode and the wiring which comprises a 1st wiring layer. It is a figure which shows the 2nd wiring layer of the standard cell in a comparative example. It is a figure which shows the wiring which connects between standard cells in a comparative example. FIG. 10 is a diagram illustrating an example in which the technique described in Patent Document 1 is applied to a 2-input NAND circuit. FIG. 10 is a diagram illustrating an example in which the technique described in Patent Document 1 is applied to a 2-input NAND circuit.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
FIG. 1 is a plan view showing the configuration of the semiconductor chip CHP in the first embodiment. In FIG. 1, the semiconductor chip CHP in the first embodiment has a communication processor TP, an audio processor SPU, a video processing unit VPU, a three-dimensional image processing processor IP, and a central processing unit CPU.

  The communication processor TP is a processor having a function of communicating with a device connected to the outside of the semiconductor chip, and the audio processor SPU is a processor used when recording and reproducing music. The video processing unit VPU is a processor used for recording and reproducing video (moving images), and the three-dimensional image processor IP is a processor for processing three-dimensional image data. Further, the central processing unit CPU is also called a central processing unit and is the heart of a computer or the like. The central processing unit CPU reads and decodes instructions from the storage device, and performs various operations and controls based on the instructions. These communication processor TP, audio processor SPU, video processing unit VPU, three-dimensional image processing processor IP, and central processing unit CPU are composed of digital circuits (logic circuits). A number of digital circuits are formed in the semiconductor chip CHP as described above. In addition to the above-described components, the peripheral circuit PC of the memory RAM including the memory cell array MCA and the peripheral circuit PC, and the serial interface are provided. Digital circuits are also used for frequency dividers included in (serial I / F), timers, and PLL (Phase Locked Loop) circuits. As such a digital circuit layout design technique, a design technique using standard cells is widely used. For example, unit circuits such as an inverter circuit, a NAND circuit, an EXOR circuit, and a flip-flop circuit are prepared as standard cells, and the standard cells are arranged in rows. Then, by designing the wiring so as to configure an integrated circuit for a plurality of standard cells arranged in a row, a digital circuit (for example, a logic circuit) having a predetermined function is formed. Since each standard cell is composed of a plurality of transistors, a diffusion layer and a gate electrode constituting the transistor are formed in each standard cell.

  Conventionally, there has been no restriction on the layout rule regarding the shape of the diffusion layer and the shape of the gate electrode constituting the standard cell, so that it has been possible to form diffusion layers and gate electrodes of any shape. For this reason, by devising the shape of the diffusion layer and the shape of the gate electrode, the layout of the standard cell could be freely designed so as to reduce the area of the integrated circuit.

  However, in recent years, miniaturization of transistors (MISFETs) constituting integrated circuits has progressed, and miniaturization of diffusion layers and gate electrodes constituting MISFETs has progressed. The diffusion layer and the gate electrode are formed using a photolithography technique. However, when the diffusion layer and the gate electrode are miniaturized, the processing accuracy of the photolithography technique becomes a problem. In other words, the shape of the diffusion layer and the shape of the gate electrode were devised so that the layout of the standard cell is minimized, but from the problem of the processing accuracy of the photolithography technology caused by the miniaturization of the diffusion layer and the gate electrode, It has become difficult to form a diffusing layer and a gate electrode having complicated shapes as designed values.

  For example, if the shape of the diffusion layer is a complicated polygon, or if a bent part is formed in the gate electrode, the corner will be rounded due to processing accuracy problems in photolithography technology. Deterioration is likely to occur. In this case, the diffusion layer and the gate electrode have a shape deviating from the design value, resulting in variations in performance of the MISFET.

  Therefore, for example, in the case of forming a MISFET smaller than a 28 nm node, a certain restriction is provided in the layout rule in order to equalize (homogenize) the performance of the formed MISFET. That is, when the MISFET is miniaturized, it becomes difficult to form a complicated shape with high accuracy due to the problem of processing accuracy of the photolithography technique, so the shape of the diffusion layer and the gate electrode constituting the MISFET are simplified. A rule is set to guarantee the performance of the miniaturized MISFET. Specific layout rules include gate electrodes (polysilicon film) arranged at regular intervals and a straight line without bending the gate electrode at all, or a shape of the diffusion layer within 8 vertices Rules such as shapes are provided.

  If the layout design of the standard cell is designed under such a new layout rule, the area of the standard cell is increased. This will be described below with reference to the drawings.

  FIG. 19 is a diagram illustrating a layout configuration example of the standard cell CL (P) configuring the 4-input NAND circuit. FIG. 19 shows a layout configuration example in the case where a conventional design method is used and a new layout rule is applied. Specifically, as new layout rules, gate electrodes (polysilicon film) are arranged at regular intervals, and the gate electrode is not bent at all, and the shape of the diffusion layer is a figure within 8 vertices. Rules for shape are incorporated.

  As shown in FIG. 19, the power supply wiring L1A and the power supply wiring L1B made of the first wiring layer are arranged so as to extend in the X direction (first direction) across the upper and lower sides of the standard cell CL (P). . The power supply wiring L1A is a wiring for supplying a power supply potential (VDD), and the power supply wiring L1B is a wiring for supplying a reference potential (GND) lower than the power supply potential (VDD). A p-type semiconductor region (p-type diffusion layer) PDR and an n-type semiconductor region (n-type diffusion layer) NDR are formed so as to be sandwiched between the power supply wiring L1A and the power supply wiring L1B. The p-type semiconductor region PDR and the n-type semiconductor region NDR have a quadrangular shape based on a new layout rule that sets the shape of the diffusion layer to a graphic shape within 8 vertices.

  For example, the p-type semiconductor region PDR having a rectangular shape is electrically connected to the protruding wiring PL1A protruding in the Y direction (second direction) from the power supply wiring L1A by the plug PLG, and the power supply potential (VDD) ) Is supplied to the p-type semiconductor region PDR via the protruding wiring PL1A. Similarly, the rectangular n-type semiconductor region NDR is electrically connected to the protruding wiring PL1B protruding in the Y direction (second direction) from the power supply wiring L1B by the plug PLG, and is connected to the reference potential (from the power supply wiring L1B). GND) is supplied to the n-type semiconductor region NDR via the protruding wiring PL1B.

  Here, based on the conventional design method, the power supply wiring L1A and the p-type semiconductor region PDR, and the power supply wiring L1B and the n-type semiconductor region NDR are respectively arranged so as to connect the shortest distances. Connected with PL1B.

  Further, as shown in FIG. 19, each of the regions in the standard cell CL (P) sandwiched between the power supply wiring L1A and the power supply wiring L1B extends in the Y direction (second direction) and is in the X direction. Gate electrodes G1 to G7 are arranged so as to be aligned in the (first direction). Thereby, for example, a p-type MISFET is formed in a region where the gate electrodes G2 to G5 and the p-type semiconductor region PDR overlap each other in a plane, and a region where the gate electrodes G2 to G5 and the n-type semiconductor region NDR overlap each other in a plane. , N-type MISFETs are respectively formed. These gate electrodes G1 to G7 are formed on the basis of a rule in which gate electrodes (polysilicon films) are arranged at equal intervals so that the gate electrodes are not bent at all and are linear.

  The gate electrode G2 is connected to the input wiring A formed from the first wiring layer via the plug PLG, and the gate electrode G3 is connected to the input wiring B formed from the first wiring layer via the plug PLG. Has been. The gate electrode G4 is connected to the input wiring C formed from the first wiring layer via the plug PLG, and the gate electrode G5 is connected to the input wiring D formed from the first wiring layer via the plug PLG. Has been. Further, an output wiring OUT is formed so as not to contact the input wirings A to D, and the output wiring OUT is arranged so as to bypass the gate electrode G6 so as not to contact the input wirings A to D.

  As described above, the standard cell CL (P) constituting the 4-input NAND circuit studied by the present inventors is formed. At this time, although the gate electrode G7 is provided in FIG. 19, it seems that the gate electrode G7 is unnecessary in the standard cell CL (P) constituting the above-described 4-input NAND circuit. However, when the standard cell CL (P) shown in FIG. 19 is composed of six gate electrodes G1 to G6, the following problems occur. That is, in the standard cell CL (P) shown in FIG. 19, since the output wiring OUT detouring to the gate electrode G6 is formed, a plurality of standard cells CL (P) are arranged in the X direction (first direction). In this case, the output wiring OUT is arranged on the boundary line between adjacent standard cells CL (P). As a result, it is conceivable that the output wiring OUT arranged on the gate electrode G6 in one standard cell CL (P) comes into contact with the first wiring layer on the adjacent standard cell CL (P). In order to prevent the first wiring layer from short-circuiting between the adjacent standard cells CL (P) in this way, as shown in FIG. 19, a gate electrode G7 is provided outside the gate electrode G6 to secure a space. doing. Thereby, it is possible to prevent the output wiring OUT formed on the gate electrode G6 from being short-circuited with the first wiring layer formed in the adjacent standard cell CL (P). That is, in the standard cell CL (P) shown in FIG. 19, it is necessary to ensure a certain interval in order to prevent a short circuit failure between the adjacent standard cells CL (P). Accordingly, in the layout configuration of the standard cell CL (P) shown in FIG. 19, it is necessary to secure a useless area as much as space is provided, and there is a problem that the size of the standard cell CL (P) becomes large. I understand.

  This is because a new layout rule is introduced after following the conventional design method. Specifically, as shown in FIG. 19, based on the conventional design method, the power supply wiring L1A and the p-type semiconductor region PDR, or the power supply wiring L1B and the n-type semiconductor region NDR are connected to each other with the shortest distance. They are connected by the protruding wiring PL1A and the protruding wiring PL1B. That is, since the conventional design method of connecting the shortest distance between the power supply wiring L1A and the p-type semiconductor region PDR is used for the protruding wiring PL1A that connects the power supply wiring L1A and the p-type semiconductor region PDR, the input wiring A˜ When D is formed, it is not possible to secure a region for arranging the output wiring OUT, and it becomes necessary to bypass the output wiring OUT on the gate electrode G6. For this reason, the gate electrode G6 cannot be used as the boundary of the standard cell CL (P), and the gate electrode G7 for securing a space is necessary.

  Therefore, the first embodiment proposes a technique that can reduce the size of a standard cell even when a new layout rule is applied by adopting a novel design philosophy changed from the conventional design method. . In the following, a technical idea capable of reducing the size of a standard cell even when a new layout rule is adopted by incorporating this novel design concept will be described.

  FIG. 2 is a diagram showing a layout configuration of the standard cell CL constituting the 4-input NAND circuit according to the first embodiment. The layout configuration of the standard cell CL in the first embodiment incorporates a novel design concept different from the conventional design method and also supports a new layout rule. Specifically, as new layout rules, gate electrodes (polysilicon film) are arranged at regular intervals, and the gate electrode is not bent at all, and the shape of the diffusion layer is a figure within 8 vertices. Rules for shape are incorporated.

  As shown in FIG. 2, a rectangular standard cell (standard power horn (square) cell, power horn (square) cell, power horn cell, square power source standard cell) CL is sandwiched between the upper and lower sides, A power supply line L1A and a power supply line L1B made of the first wiring layer are arranged so as to extend in the X direction (first direction). The power supply wiring L1A is a wiring for supplying a power supply potential (VDD), and the power supply wiring L1B is a wiring for supplying a reference potential (GND, VSS) lower than the power supply potential (VDD). A p-type semiconductor region (p-type diffusion layer) PDR and an n-type semiconductor region (n-type diffusion layer) NDR are formed so as to be sandwiched between the power supply wiring L1A and the power supply wiring L1B. The p-type semiconductor region PDR and the n-type semiconductor region NDR have a quadrangular shape based on a new layout rule that sets the shape of the diffusion layer to a graphic shape within 8 vertices.

  The p-type semiconductor region PDR formed in the standard cell CL has a first boundary line connecting one end of the first side (power supply line L1A) and one end of the second side (power supply line L1B) of the standard cell CL; It arrange | positions so that it may not contact both the 2nd boundary line which ties the other end part of a 1st edge | side (power supply wiring L1A), and the other end part of a 2nd edge | side (power supply wiring L1B). Similarly, the n-type semiconductor region NDR formed in the standard cell CL has a first boundary connecting one end of the first side (power supply line L1A) and one end of the second side (power supply line L1B) of the standard cell CL. The line and the second boundary line connecting the other end of the first side (power supply line L1A) and the other end of the second side (power supply line L1B) are arranged so as not to contact each other. Therefore, considering a plurality of standard cells CL arranged adjacent to each other in the X direction (first direction), the p-type semiconductor regions PDR formed in each standard cell CL are separated from each other and each standard cell CL The n-type semiconductor regions NDR formed in the cell CL are also isolated from each other.

  Subsequently, in the standard cell CL according to the first embodiment, at both ends of the standard cell CL (boundary of the standard cell CL), a branch from the power supply line L1A and a Y direction (second direction) toward the inside of the standard cell CL. Two protruding wirings PL1A that protrude to the right are formed. Similarly, at both ends of the standard cell CL (boundary of the standard cell CL), two protruding wirings (horn (( Square-shaped power supply wiring, horn (square) power supply wiring, horn (square) wiring) PL1B are formed. Then, at least one or more of the protruding wirings extracted from the protruding wiring PL1A and the protruding wiring PL1B includes a bent portion whose end is bent in the X direction (first direction) toward the inside of the standard cell CL. . Specifically, when the protruding wiring formed with the bent portion is branched from the power supply wiring L1A (the protruding wiring PL1A), the protruding wiring PL1A is connected to the bent portion BD1A by the plug PLG. It is electrically connected to the PDR. On the other hand, when the protruding wiring in which the bent portion is formed is branched from the power supply wiring L1B (projecting wiring PL1B), the protruding wiring PL1B is electrically connected to the n-type semiconductor region NDR by the plug PLG connected to the bent portion BD1B. Connected.

  Next, as shown in FIG. 2, each of the regions in the standard cell CL sandwiched between the power supply line L1A and the power supply line L1B extends in the Y direction (second direction) and is in the X direction (first direction). A dummy gate electrode DG1, gate electrodes G1 to G4, and a dummy gate electrode DG2 are arranged so as to be aligned in one direction. Thereby, for example, a p-type MISFET is formed in a region where the gate electrodes G1 to G4 and the p-type semiconductor region PDR overlap in a plane, and a gate electrode G1 to G4 and the n-type semiconductor region NDR are overlapped in a plane. , N-type MISFETs are respectively formed. The gate electrodes G1 to G4 and the dummy gate electrodes DG1 and DG2 are formed based on a rule in which gate electrodes (polysilicon films) are arranged at equal intervals and the gate electrodes are not bent at all and are linear. The dummy gate electrodes DG1 and DG2 here are those that do not overlap the p-type semiconductor region PDR and the n-type semiconductor region NDR in a planar manner and are arranged on the boundary line of the standard cell CL. In other words, the dummy gate electrodes DG1 and DG2 do not function as the gate electrodes of the p-type MISFET and the n-type MISFET, and the potential is in a floating state.

  The gate electrode G1 is connected to the input wiring A formed from the first wiring layer via the plug PLG, and the gate electrode G2 is connected to the input wiring B formed from the first wiring layer via the plug PLG. Has been. The gate electrode G3 is connected to the input wiring C formed from the first wiring layer via the plug PLG, and the gate electrode G4 is connected to the input wiring D formed from the first wiring layer via the plug PLG. Has been. An output wiring OUT is formed so as not to contact the input wirings A to D, and the output wiring OUT is disposed on the gate electrode G4 so as not to contact the input wirings A to D.

  The standard cell CL described above is composed of components formed below the first wiring layer. The standard cell CL is formed of input wirings A to D for inputting input signals to the standard cell CL and the first wiring layer. The output wiring OUT that outputs an output signal from the cell CL is electrically connected to a wiring (second wiring layer) above the first wiring layer. That is, in the first embodiment, the standard cell CL is composed of components below the first wiring layer, and the standard cell CL is connected to the second wiring layer that is higher than the first wiring layer. Logic circuit) is formed.

  An n-type power supply region (semiconductor region) for supplying a power supply potential (VDD) to the n-type well is provided immediately below the power supply wire L1A. The n-type power supply region and the power supply wire L1A are connected by a plug PLG. Has been. Similarly, a p-type power supply region (semiconductor region) for supplying a reference potential (GND) to the p-type well is provided immediately below the power supply wire L1B. The p-type power supply region and the power supply wire L1B are plug PLG. It is connected. That is, an N-type well is formed in the semiconductor substrate on which the standard cell CL is formed, and the power supply wiring L1A and the N-type well are electrically connected by a plurality of plugs PLG (first via plugs). Similarly, a P-type well is formed in the semiconductor substrate in which the standard cell CL is formed, and the power supply wiring L1B and the P-type well are electrically connected by a plurality of plugs (second via plugs). At this time, the plurality of plugs PLG (first via plug and second via plug) are not formed at the four corners of the standard cell CL.

  As described above, the standard cell CL constituting the 4-input NAND circuit in the first embodiment is formed. Here, the feature of the first embodiment is that, for example, as shown in FIG. 2, the protruding wiring PL1A protrudes from the power supply wiring L1A into the inside of the standard cell CL (Y direction) at the corners at both ends of the standard cell CL. In addition, a bent portion BD1A bent in the X direction is formed from the protruding wiring PL1A. The bent portion BD1A and the p-type semiconductor region PDR are connected by a plug PLG. That is, the first embodiment is characterized by a layout configuration that connects the power supply wiring L1A and the p-type semiconductor region PDR.

  For example, as shown in FIG. 19, when the conventional design method is used, the power supply wiring L1A and the p-type semiconductor region PDR, or the power supply wiring L1B and the n-type semiconductor region NDR are respectively protruded wirings so as to connect the shortest distances. They are connected by PL1A and protruding wiring PL1B. In other words, the conventional design method is adopted in which the protruding wiring PL1A connecting the power supply wiring L1A and the p-type semiconductor region PDR is formed so as to connect the shortest distance between the power supply wiring L1A and the p-type semiconductor region PDR. When the input wirings A to D are formed, it is not possible to secure a region for arranging the output wiring OUT, and it becomes necessary to bypass the output wiring OUT on the gate electrode G6. For this reason, the gate electrode G6 cannot be used as the boundary of the standard cell CL (P), and the gate electrode G7 for securing a space is required.

  On the other hand, the first embodiment shown in FIG. 2 uses a novel design technique different from the conventional design technique. Specifically, as shown in FIG. 2, as a method of connecting the power supply wiring L1A and the p-type semiconductor region PDR, the protruding wiring PL1A is arranged so as to connect the power supply wiring L1A and the p-type semiconductor region PDR with the shortest distance. Instead, the protruding wiring PL1A is drawn from the power supply wiring L1A at the corner of the standard cell CL for the time being. Thereafter, by providing a bent portion BD1A to the extracted protruding wiring PL1A, a plug PLG connected to the p-type semiconductor region PDR is formed at the bent portion BD1A. In this case, since the connection between the power supply line L1A and the p-type semiconductor region PDR is not made with the shortest path, the size of the standard cell CL seems to increase at first glance. However, if the protruding wiring PL1A is drawn from the corner of the power supply wiring L1A and then the bent wiring BD1A is provided in the protruding wiring PL1A, the protruding wiring PL1A is formed at the corner of the standard cell CL. The number of protruding wirings PL1A formed inside the cell CL can be reduced. This means that the space provided in the standard cell CL is increased, and the degree of freedom in the layout configuration is improved by effectively using this space.

  Here, the protruding wiring PL1A protruding from the power supply wiring L1A is described, but the same applies to the protruding wiring PL1B protruding from the power supply wiring L1B. That is, as shown in FIG. 2, as a method of connecting the power supply wiring L1B and the n-type semiconductor region NDR, the protruding wiring PL1B is arranged so as to connect the power supply wiring L1B and the n-type semiconductor region NDR with the shortest distance. For the time being, the protruding wiring PL1B is drawn from the power supply wiring L1B at the corner of the standard cell CL. Thereafter, by providing a bent portion BD1B to the extracted protruding wiring PL1B, a plug PLG connected to the n-type semiconductor region NDR is formed at the bent portion BD1B. In this case, since the connection between the power supply line L1B and the n-type semiconductor region NDR is not made with the shortest path, the size of the standard cell CL seems to increase at first glance. However, if the protruding wiring PL1B is drawn from the corner of the power supply wiring L1B and then the bent wiring BD1B is provided in the protruding wiring PL1B, the protruding wiring PL1B is formed at the corner of the standard cell CL. The number of protruding wirings PL1B formed inside the cell CL can be reduced. This means that the space provided in the standard cell CL is increased, and the degree of freedom in the layout configuration is improved by effectively using this space.

  Specifically, as shown in FIG. 2, the protruding wiring PL1A and the protruding wiring PL1B are arranged at the corners (on the boundary line) of the standard cell CL, the bent wiring BD1A is provided in the protruding wiring PL1A, and the protruding wiring The layout configuration is such that a bent portion BD1B is provided in PL1B. Then, the number of protruding wirings PL1A and protruding wirings PL1B formed in the internal region of the standard cell CL can be reduced. As a result, a space can be secured in the internal region of the standard cell CL, and the degree of freedom in layout configuration can be improved. For example, as shown in FIG. 2, the arrangement position of the output wiring OUT can be secured on the gate electrode G4 by devising the arrangement position of the input wiring D based on the improvement in the degree of freedom of the layout configuration. Therefore, the four input wirings A to D and one output wiring OUT of the four-input NAND circuit can be laid out on the four gate electrodes G1 to G4. Therefore, in the standard cell CL of the 4-input NAND circuit in the first embodiment, the standard cell CL can be configured by six electrodes including the dummy gate electrodes DG1 and DG2 and the gate electrodes G1 to G4. That is, in the comparative example shown in FIG. 19, the standard cell CL is configured by seven gate electrodes, whereas in the first embodiment shown in FIG. 2, the standard cell CL is configured by six electrodes. As a result, the size of the standard cell CL can be reduced. That is, in the first embodiment, as shown in FIG. 2, the protruding wiring PL1A and the protruding wiring PL1B are arranged at the corners (on the boundary line) of the standard cell CL, and the protruding wiring PL1A is provided with the bent portion BD1A. In addition, since a novel design method that does not exist in the conventional design method in which the layout configuration is provided so that the bent portion BD1B is provided in the protruding wiring PL1B, a new layout rule introduced along with the miniaturization of the MISFET is provided. Even if it is applied, the remarkable effect that the size of the standard cell CL can be reduced can be obtained.

  In the first embodiment, a four-input NAND circuit is used as an example of the standard cell CL, and the bent portion BD1A is provided in the protruding wiring PL1A formed at both corners of the power supply wiring L1A. On the other hand, protruding wirings PL1B are also formed at both corners of the power supply wiring L1B, but the bent portion BD1B is formed on the protruding wiring PL1B on the left side of FIG. 2, and the protruding wiring on the right side of FIG. The bent portion BD1B is not formed in PL1B. That is, in the four-input NAND circuit according to the first embodiment, among the four protruding wirings (PL1A, PL1B), the three protruding wirings (PL1A, PL1B) are provided with the bent portions (BD1A, BD1B). . However, the technical idea in the first embodiment is not limited to this, and depending on the standard cell CL, two bent wirings (PL1A, PL1B) out of four protruding wirings (PL1A, PL1B) may be bent ( BD1A, BD1B) may be provided, and furthermore, at least one protruding wiring (PL1A, PL1B) may be provided with a bent portion (BD1A, BD1B). That is, the technical idea of the first embodiment is based on the assumption that the protruding wirings (PL1A, PL1B) are provided at the four corners of the standard cell CL, and the four protruding wirings (PL1A, PL1B). Among them, the present invention can be applied to the case where a bent portion (BD1A, BD1B) is provided on at least one protruding wiring (PL1A, PL1B).

  In the first embodiment, each of the plurality of standard cells CL branches from the power supply line L1A at a location other than both ends of one standard cell CL on the first side (power supply line L1A) and is standardized. A protruding wiring PL1A protruding in the Y direction toward the inside of the cell CL may be provided, and the protruding wiring PL1A may be configured to be electrically connected to the p-type semiconductor region PDR via the plug PLG. Similarly, in the first embodiment, each of the plurality of standard cells CL branches from the power supply line L1B at locations other than both ends of one standard cell CL on the second side (power supply line L1B). A protruding wiring PL1B protruding in the Y direction toward the inside of the standard cell CL is provided, and the protruding wiring PL1B is configured to be electrically connected to the n-type semiconductor region NDR through the plug PLG. Good. That is, in the first embodiment, protruding wirings (PL1A, PL1B) protruding in the Y direction from the four corners of the standard cell CL are provided, and bent portions (BD1A, PL1B) bent in the X direction from the protruding wirings (PL1A, PL1B). BD1B) is formed. The bent portion (BD1A, BD1B) is connected to the p-type semiconductor region PDR and the n-type semiconductor region NDR with a plug PLG. However, on the assumption that such a configuration is adopted, There may be a structure in which protruding wirings (PL1A, PL1B) are provided at locations and connected to the n-type semiconductor region NDR or the p-type semiconductor region PDR by a plug PLG. Even in this case, the number of protruding wirings PL1A and protruding wirings PL1B formed in the internal region of the standard cell CL is reduced as compared with the case where all the protruding wirings (PL1A, PL1B) are formed inside the standard cell. be able to. As a result, a space can be secured in the internal region of the standard cell CL, and the degree of freedom in layout configuration can be improved. Therefore, the size of the standard cell CL can be reduced even when the new layout rule introduced with the miniaturization of the MISFET is applied.

  A further feature of the first embodiment is that the minimum line width of the protruding wiring PL1A and the minimum line width of the protruding wiring PL1B are smaller than the line width of the power supply line L1A or the power supply line L1B. For example, the protruding wiring PL1A and the protruding wiring PL1B constitute a wiring for supplying a power supply potential and a reference potential to the p-type semiconductor region PDR and the n-type semiconductor region NDR. It seems that it is desirable that the wiring width is wide because of suppressing the above. Certainly, this is the case when the power supply potential is as high as 5 V, but the semiconductor device targeted in the first embodiment targets, for example, a device miniaturized smaller than a 28 nm node. . In such a miniaturized semiconductor device, the power supply potential is also lowered by the scaling law. For example, the power supply potential is reduced to about 1V. In such a low voltage, the migration of the wiring is not a problem, and therefore it is not necessary to make the wiring width of the protruding wiring PL1A and the protruding wiring PL1B as large as the power wiring L1A and the power wiring L1B. . That is, in the first embodiment, the minimum line width of the protruding wiring PL1A and the minimum line width of the protruding wiring PL1B are smaller than the line width of the power supply wiring L1A or the power supply wiring L1B. As a result, the area occupied by the protruding wirings PL1A and the protruding wirings PL1B formed at the four corners of the standard cell CL can be reduced. As a result, the occupation ratio of the protruding wirings PL1A and the protruding wirings PL1B in the standard cells CL is reduced. be able to. For this reason, in the first embodiment, a space can be secured in the internal region of the standard cell CL, and the degree of freedom of the layout configuration can be improved. Therefore, even when a new layout rule introduced with the miniaturization of the MISFET is applied, the degree of freedom to devise the layout configuration increases, so a layout configuration that can reduce the size of the standard cell CL. It becomes easy to adopt.

  On the other hand, the minimum line widths of the protruding wiring PL1A and the protruding wiring PL1B are larger than the line widths of the gate electrodes G1 to G4 and the dummy gate electrodes DG1 and DG2. In other words, the line widths of the gate electrodes G1 to G4 and the dummy gate electrodes DG1 and DG2 are smaller than the minimum line width of the protruding wiring PL1A and the protruding wiring PL1B. This is because the gate electrodes G1 to G4 (including dummy gate electrodes DG1 and DG2) are most miniaturized among the constituent elements of the standard cell CL, and the protruding wiring PL1A and the protruding wiring PL1B are the gate electrodes G1 to G4. This is because it is formed by processing the first wiring layer whose processing accuracy is relaxed compared to (dummy gate electrodes DG1, DG2).

  As described above, the feature of the first embodiment is that the protruding wirings (PL1A, PL1B) from the power wirings (L1A, L1B) to the inside of the standard cell CL (Y direction) at the corners at both ends of the standard cell CL. It is in the point which forms the bending part (BD1A, BD1B) which bent in the X direction from the protruding wiring (PL1A, PL1B) which protruded and protruded. The bent portions (BD1A, BD1B) and the p-type semiconductor region PDR and the n-type semiconductor region NDR are connected by a plug PLG. Thereby, a space can be secured in the internal region of the standard cell CL, and the degree of freedom of the layout configuration can be improved. Therefore, even when a new layout rule introduced with the miniaturization of the MISFET is applied, the degree of freedom to devise the layout configuration increases, so a layout configuration that can reduce the size of the standard cell CL. It becomes easy to adopt. This characteristic configuration focuses on one standard cell and reduces the size of each standard cell. Furthermore, the above-mentioned characteristic configuration is based on a viewpoint focusing on a plurality of adjacent standard cells. However, the size can be reduced.

  This will be described below. FIG. 20 is a diagram showing a comparative example using a conventional design method. Specifically, FIG. 20 shows two adjacent standard cells CL1 (P) and standard cells CL2 (P). In FIG. 20, in standard cell CL1 (P), protruding wiring PL1B (1) connected to n-type semiconductor region NDR1 is formed at the shortest distance from power supply wiring L1B, and in standard cell CL2 (P), the shortest from power supply wiring L1B is formed. A protruding wiring PL1B (2) that is connected to the n-type semiconductor region NDR2 at a distance is formed. Therefore, it is necessary to form the protruding wiring PL1B (1) and the protruding wiring PL1B (2) in each of the two standard cells CL1 (P) and the standard cell CL2 (P). For this reason, two projecting wirings PL1B (1) and projecting wirings PL1B (2) are required for the two standard cells CL1 (P) and the standard cell CL2 (P).

  On the other hand, FIG. 3 is a diagram showing adjacent standard cell CL1 and standard cell CL2 in the first embodiment. As shown in FIG. 3, in the first embodiment, a protruding wiring PL1B is formed on the boundary line between adjacent standard cells CL1 and CL2, and a bent portion BD1B (1 bent from the protruding wiring PL1B to the right side is formed. ) And a bent portion BD1B (2) bent to the left side. The bent portion BD1B (1) is connected to the n-type semiconductor region NDR1 of the standard cell CL1 via a plug, and the bent portion BD1B (2) is connected to the n-type semiconductor region NDR2 of the standard cell CL2 via a plug. Has been. Therefore, in the first embodiment shown in FIG. 3, the reference potential (GND) is supplied to each standard cell CL1 and standard cell CL2 by one protruding wiring PL1B common to two adjacent standard cells CL1 and CL2. ) Can be supplied.

  That is, in the comparative example shown in FIG. 20, the power supply wiring L1B and the n-type semiconductor regions (NDR1 and NDR2) are each at the shortest distance from two adjacent standard cells CL1 (P) and CL2 (P). Two protruding wirings (BD1B (1) and BD1B (2)) to be connected are required. On the other hand, in the first embodiment shown in FIG. 3, with respect to two adjacent standard cells CL1 and CL2, reference potentials are applied to both standard cells CL1 and CL2 with only one protruding wiring PL1B. (GND) can be supplied. This means that the first embodiment shown in FIG. 3 can reduce the number of protruding wirings drawn from the power supply wiring L1B as compared with the comparative example shown in FIG. Therefore, in the first embodiment shown in FIG. 3, the number of protruding wirings PL1B formed inside the standard cell CL1 or the standard cell CL can be reduced, so that the internal area of the standard cell CL1 or the standard cell CL2 is sufficient. A large space can be secured, and the degree of freedom in layout configuration can be improved. Therefore, even when a new layout rule introduced with the miniaturization of MISFET is applied, the degree of freedom to devise the layout configuration increases, so that the layout of the standard cell CL can be reduced. It becomes easy to adopt the configuration.

(Embodiment 2)
In the first embodiment, a four-input NAND circuit has been described as an example of a standard cell. In the second embodiment, an example in which the technical idea of the present invention is applied to an inverter circuit will be described.

  FIG. 4A is a circuit diagram showing two inverter circuits connected in parallel between the input wiring IN and the output wiring OUT, and FIG. 4B shows a layout configuration example of the inverter circuit shown in FIG. It is a top view. In FIG. 4A, the first inverter includes a p-type MISFET (P1) and an n-type MISFET (N1), and a p-type transistor is provided between the power supply potential (VDD) and the reference potential (GND). The MISFET (P1) and the n-type MISFET (N1) are connected in series. Similarly, the second inverter includes a p-type MISFET (P2) and an n-type MISFET (N2), and a p-type MISFET (P2) between the power supply potential (VDD) and the reference potential (GND). And an n-type MISFET (N2) are connected in series. The input wiring IN is connected to the gate electrodes of both the p-type MISFET (P1) and the n-type MISFET (N1), and is connected to both the gate electrodes of the p-type MISFET (P2) and the n-type MISFET (N2). It is connected. On the other hand, the output wiring OUT is connected to the drain region between the p-type MISFET (P1) and the n-type MISFET (N1), and the drain region between the p-type MISFET (P2) and the n-type MISFET (N2). It is connected. According to the inverter circuit configured as described above, a signal opposite to the signal input to the input wiring IN is output from the output wiring OUT. For example, when the signal “0” is input to the input wiring IN, the signal “1” is output from the output wiring OUT. Conversely, when the signal “1” is input to the input wiring IN, the signal “0” is output from the output wiring OUT.

  Next, FIG. 4B is a plan view showing a layout configuration example of the inverter circuit shown in the circuit diagram of FIG. In FIG. 4B, the layout configuration of the standard cell CL according to the second embodiment incorporates a novel design concept different from the conventional design method and also supports a new layout rule. Specifically, as new layout rules, gate electrodes (polysilicon film) are arranged at regular intervals, and the gate electrode is not bent at all, and the shape of the diffusion layer is a figure within 8 vertices. Rules for shape are incorporated.

  As shown in FIG. 4B, the power supply wiring L1A and the power supply wiring L1B made of the first wiring layer are extended so as to extend in the X direction (first direction) across the rectangular standard cell CL. Is arranged. The power supply wiring L1A is a wiring for supplying a power supply potential (VDD), and the power supply wiring L1B is a wiring for supplying a reference potential (GND) lower than the power supply potential (VDD). A p-type semiconductor region (p-type diffusion layer) PDR and an n-type semiconductor region (n-type diffusion layer) NDR are formed so as to be sandwiched between the power supply wiring L1A and the power supply wiring L1B. The p-type semiconductor region PDR and the n-type semiconductor region NDR have a quadrangular shape based on a new layout rule that sets the shape of the diffusion layer to a graphic shape within 8 vertices.

  The p-type semiconductor region PDR formed in the standard cell CL has a first boundary line connecting one end of the first side (power supply line L1A) and one end of the second side (power supply line L1B) of the standard cell CL; It arrange | positions so that it may not contact both the 2nd boundary line which ties the other end part of a 1st edge | side (power supply wiring L1A), and the other end part of a 2nd edge | side (power supply wiring L1B). Similarly, the n-type semiconductor region NDR formed in the standard cell CL has a first boundary connecting one end of the first side (power supply line L1A) and one end of the second side (power supply line L1B) of the standard cell CL. The line and the second boundary line connecting the other end of the first side (power supply line L1A) and the other end of the second side (power supply line L1B) are arranged so as not to contact each other. Therefore, considering a plurality of standard cells CL arranged adjacent to each other in the X direction (first direction), the p-type semiconductor regions PDR formed in each standard cell CL are separated from each other and each standard cell CL The n-type semiconductor regions NDR formed in the cell CL are also isolated from each other.

  Subsequently, in the standard cell CL according to the second embodiment, at both ends of the standard cell CL (boundary of the standard cell CL), the Y-direction (second direction) branches from the power supply line L1A toward the inside of the standard cell CL. Two protruding wirings PL1A that protrude to the right are formed. Similarly, at both ends of the standard cell CL (boundary of the standard cell CL), two protruding wirings PL1B that branch from the power supply wiring L1B and project in the Y direction (second direction) toward the inside of the standard cell CL are formed. Has been. The two protruding wirings PL1A include a bent portion BD1A whose end is bent in the X direction (first direction) toward the inside of the standard cell CL. The bent portion BD1A is electrically connected to the p-type semiconductor region PDR by a plug PLG. On the other hand, the two protruding wirings PL1B include a bent portion BD1B whose end is bent in the X direction (first direction) toward the inside of the standard cell CL, and the end of the bent portion BD1B is in the Y direction ( A bent portion BD2B bent in the second direction) is provided. The bent portion BD2B is electrically connected to the n-type semiconductor region NDR by the plug PLG.

  As described above, in the second embodiment, the protruding wiring PL1B in which the bent portion BD1B is formed further has a bent portion BD2B bent in the Y direction (second direction) from the end portion of the bent portion BD1B. The bent portion BD2B is electrically connected to the n-type semiconductor region NDR by the plug PLG.

  In the second embodiment, the layout is such that the protruding wiring PL1A has the bent portion BD1A and the protruding wiring PL1B has the bent portion BD1B and the bent portion BD2B, but the bent portion BD1A is formed. The protruding wiring PL1A may further be laid out so as to have a further bent portion bent in the Y direction (second direction) from the end of the bent portion BD1A. In this case, the protruding wiring PL1A in which the bent portion BD1A and the further bent portion are formed is electrically connected to the p-type semiconductor region PDR by the plug PLG connected to the further bent portion.

  Next, as shown in FIG. 4B, each of the regions in the standard cell CL sandwiched between the power supply wiring L1A and the power supply wiring L1B extends in the Y direction (second direction), and X The dummy gate electrode DG1, the gate electrodes G1 to G2, and the dummy gate electrode DG2 are arranged so as to be aligned in the direction (first direction). Thereby, for example, the p-type MISFET (P1) and the p-type MISFET (P2) are respectively formed in regions where the gate electrodes G1 to G2 and the p-type semiconductor region PDR overlap in a plane, and the gate electrodes G1 to G2 and the n-type are formed. An n-type MISFET (N1) and an n-type MISFET (N2) are formed in regions where the semiconductor region NDR overlaps in plan view. The gate electrodes G1 to G2 and the dummy gate electrodes DG1 and DG2 are formed based on a rule in which gate electrodes (polysilicon films) are arranged at equal intervals and the gate electrodes are not bent at all and are linear. The dummy gate electrodes DG1 and DG2 here are those that do not overlap the p-type semiconductor region PDR and the n-type semiconductor region NDR in a planar manner and are arranged on the boundary line of the standard cell CL. In other words, the dummy gate electrodes DG1 and DG2 do not function as the gate electrodes of the p-type MISFETs (P1 and P2) and the n-type MISFETs (N1 and N2), and the potentials are in a floating state.

  In addition, dummy gate electrodes DG1 and DG2 are arranged at both ends of the standard cell CL, and the gate electrodes DG1 and DG2 are evenly arranged inside the dummy cell so that the dummy gate electrode and the gate are arranged on the chip in which the standard cells are continuously arranged. The electrodes are arranged at regular intervals (substantially equidistant), thereby ensuring flatness when polishing by CMP (Chemical Mechanical Polishing). That is, an interlayer insulating film is formed on the upper layer covering the dummy gate electrode and the gate electrode. After this interlayer insulating film is formed, CMP polishing is performed on the surface of the interlayer insulating film in order to planarize the surface of the interlayer insulating film. At this time, when the dummy gate electrodes DG1 and DG2 are not arranged at both ends of the standard cell CL, the gate electrodes are not arranged at equal intervals below the interlayer insulating film. When CMP polishing is performed, there is a risk that flatness may be reduced based on the non-uniformity of the base. However, in the second embodiment, the dummy gate electrodes DG1 and DG2 are formed, whereby the dummy gate electrodes DG1 and DG2 and the gate electrode are arranged at equal intervals. As a result, when the interlayer insulating film formed on the upper layer is polished by CMP, the flatness of the interlayer insulating film can be sufficiently ensured, and a highly reliable wiring layer can be formed.

  The gate electrode G1 is connected to the input wiring IN formed from the first wiring layer via the plug PLG. An output wiring OUT is formed so as not to contact the input wiring IN, and the output wiring OUT is disposed on the gate electrode G2 so as not to contact the input wiring IN.

  The standard cell CL described above is composed of components formed below the first wiring layer. The standard cell CL is formed of the input wiring IN for inputting an input signal to the standard cell CL and the first wiring layer. The output wiring OUT that outputs an output signal from is electrically connected to a wiring (second wiring layer) above the first wiring layer. That is, in the second embodiment, the standard cell CL is composed of components below the first wiring layer, and the standard cell CL is connected to the second wiring layer above the first wiring layer, thereby providing a digital circuit ( Logic circuit) is formed.

  An n-type power supply region (semiconductor region) for supplying a power supply potential (VDD) to the n-type well is provided immediately below the power supply wire L1A. The n-type power supply region and the power supply wire L1A are connected by a plug PLG. Has been. Similarly, a p-type power supply region (semiconductor region) for supplying a reference potential (GND) to the p-type well is provided immediately below the power supply wire L1B. The p-type power supply region and the power supply wire L1B are plug PLG. It is connected. That is, an N-type well is formed in the semiconductor substrate on which the standard cell CL is formed, and the power supply wiring L1A and the N-type well are electrically connected by a plurality of plugs PLG (first via plugs). Similarly, a P-type well is formed in the semiconductor substrate in which the standard cell CL is formed, and the power supply wiring L1B and the P-type well are electrically connected by a plurality of plugs (second via plugs). At this time, the plurality of plugs PLG (first via plug and second via plug) are not formed at the four corners of the standard cell CL.

  Subsequently, when the layout configuration of the inverter circuit shown in FIG. 4B is disassembled for each layer, it is as shown in FIGS. 5A to 5D. FIG. 5A is a diagram showing the lowermost semiconductor substrate. As shown in FIG. 5A, an n-type power supply region DR1, a p-type semiconductor region PDR, an n-type semiconductor region NDR, and a p-type power supply region DR2 are formed on the semiconductor substrate so as to be aligned in the Y direction. ing. All the regions shown in FIG. 5A are formed from semiconductor regions.

  Next, FIG.5 (b) is a figure which shows the structure currently formed in the upper layer of Fig.5 (a). As shown in FIG. 5B, the dummy gate electrode DG1, the gate electrodes G1 to G2, and the dummy gate electrode DG2 are formed so as to extend in the Y direction and to be aligned in the X direction. These dummy gate electrodes DG1 and DG2 and gate electrodes G1 to G2 are formed by processing a polysilicon film.

  FIG. 5C shows the plug PLG formed in the upper layer of FIGS. 5A and 5B. Further, FIG. 5D is a diagram showing the first wiring layer formed in the upper layer of FIGS. 5A to 5C. Specifically, the power wiring L1A, the power wiring L1B, the protruding wiring PL1A, the protruding wiring PL1B, the bent portion BD1A, the bent portion BD1B, the bent portion BD2B, the wiring L1C, the input wiring IN, and the output wiring OUT are formed as the first wiring layer. Has been.

  As described above, in the second embodiment, the protruding wirings (PL1A, PL1B) protrude from the power supply wirings (L1A, L1B) into the standard cell CL (Y direction) at the corners at both ends of the standard cell CL. Further, bent portions (BD1A, BD1B) bent in the X direction are formed from the protruding wirings (PL1A, PL1B) protruding, and further, a bent portion BD2B bent in the Y direction from the bent portion BD1B is formed. The bent portions (BD1A, BD2B) and the p-type semiconductor region PDR and the n-type semiconductor region NDR are connected by a plug PLG. Thereby, a space can be secured in the internal region of the standard cell CL, and the degree of freedom of the layout configuration can be improved. Therefore, even when a new layout rule introduced with the miniaturization of the MISFET is applied, the degree of freedom to devise the layout configuration increases, so a layout configuration that can reduce the size of the standard cell CL. It becomes easy to adopt.

  Here, further advantages in the second embodiment will be described. In the second embodiment, for example, as shown in FIG. 4B, the gate electrode G1 and the gate electrode G2 are electrically connected by a wiring L1C composed of the first wiring layer. This is because a new layout rule is adopted in which the gate electrodes (polysilicon films) are arranged at equal intervals and the gate electrodes are not bent at all and are linear. That is, if there is no new layout rule as described above, the gate electrode G1 and the gate electrode G2 are formed by forming a bent portion by processing the polysilicon film in the gate electrode G1 and the gate electrode G2 formed from the polysilicon film. Can be connected to each other. However, when the above-described new layout rule is set, it becomes impossible to process the gate electrode G1 and the gate electrode G2 themselves so as to provide a bent portion. Therefore, under the new layout rule, the gate electrode G1 and the gate electrode G2 formed of a polysilicon film are formed in a linear shape, and the gate electrode G1 and the gate are formed using the wiring L1C which is the first wiring layer. The electrode G2 must be connected. Thus, under the new layout rule, the wiring L1C of the first wiring layer that electrically connects the gate electrode G1 and the gate electrode G2 is required.

  Under this circumstance, when the conventional design method of forming the projecting wiring PL1B connecting the power supply wiring L1B and the n-type semiconductor region NDR so as to connect the shortest distance between the power supply wiring L1B and the n-type semiconductor region NDR is employed. Further, the margin between the protruding wiring PL1B and the wiring L1C is reduced, and a short circuit defect is likely to occur between the protruding wiring PL1B and the wiring L1C.

  This will be described with reference to FIG. 21 showing a comparative example. FIG. 21 is a diagram showing gate electrodes G1 to G4 and wirings constituting the first wiring layer in an inverter circuit including two inverters. In FIG. 21, since the gate electrode (polysilicon film) is arranged at equal intervals and a new layout rule is adopted in which the gate electrode is linearly formed without bending at all, the gate electrode G2 and the gate electrode G3 They are connected by a wiring L1C made of the first wiring layer. In this state, when the protruding wiring PL1B protruding from the power supply wiring L1B is designed by the conventional design method, as shown in FIG. 21, there is almost no margin between the protruding wiring PL1B and the wiring L1C, and the protruding wiring PL1B and the wiring L1C. It can be seen that short-circuit defects are likely to occur between the two.

  On the other hand, in the present second embodiment, as shown in FIG. 4B, the protruding wiring PL1B protrudes from the corners of both ends of the standard cell CL. Therefore, compared with the case shown in FIG. 21, a sufficient margin can be secured between the wiring L1C formed from the first wiring layer and the protruding wiring PL1B. That is, in the second embodiment, since the protruding wiring PL1B is drawn out from both ends of the standard cell CL, a sufficient space between the wiring L1C and the protruding wiring PL1B can be secured. For this reason, the second embodiment has an advantage that the short-circuit defect between the wiring L1C and the protruding wiring PL1B can be suppressed, and as a result, the reliability of the semiconductor device can be improved. become.

  As described above, in the second embodiment, the two gates extend in the X direction in the separation region between the power supply line L1B extending in the X direction and the bent portion BD1B bent in the X direction. The layout configuration is such that the wiring L1C of the first wiring layer that connects the electrode G1 and the gate electrode G2 is formed. This technical idea can be further expanded. For example, at least one or more wirings of the first wiring layer extending in the X direction are formed in a separation region between the power supply wiring L1B extending in the X direction and the bent portion BD1B bent in the X direction. In addition, it can be said that the protruding wiring PL1B has a layout configuration. In particular, it is effective when the wiring of the first wiring layer formed in the separated region is a wiring that electrically connects two or more gate electrodes included in a plurality of gate electrodes.

  As a modification of the second embodiment, in the separation region between the power supply line L1A extending in the X direction and the bent portion BD1A bent in the X direction, two wires extending in the X direction are provided. The layout may be formed so that the wiring of the first wiring layer that connects the gate electrode G1 and the gate electrode G2 is formed. Also in this case, the technical idea can be easily extended. For example, at least one or more wirings of the first wiring layer extending in the X direction are formed in a separation region between the power supply wiring L1A extending in the X direction and the bent portion BD1A bent in the X direction. In addition, it can be said that the protruding wiring PL1A has a layout configuration. In particular, it is effective when the wiring of the first wiring layer formed in the separated region is a wiring that electrically connects two or more gate electrodes included in a plurality of gate electrodes.

  Next, the device structure of the inverter circuit in the second embodiment will be described. 6 is a cross-sectional view taken along line AA in FIG. 6, in the semiconductor device according to the second embodiment, an element isolation region STI is formed on the main surface of the semiconductor substrate 1S, and a region partitioned by the element isolation region STI is an active region. An n-type well NWL and a p-type well PWL are formed in the semiconductor substrate 1S. The n-type well NWL is a semiconductor region in which an n-type impurity (donor) such as phosphorus or arsenic is introduced into the semiconductor substrate 1S, and the p-type well PWL is a semiconductor in which a p-type impurity (acceptor) such as boron is introduced into the semiconductor substrate 1S. It is an area. An n-type power supply region NR1 for supplying power to the n-type well NWL is formed in a partial surface region of the n-type well NWL. On the other hand, a p-type power supply region PR1 for supplying power to the p-type well PWL is formed in a partial surface region of the p-type well PWL.

  Next, a gate insulating film GOX made of, for example, a silicon oxide film is formed on the semiconductor substrate 1S on which the element isolation region STI, the n-type well NWL, and the p-type well PWL are formed. In addition, for example, a gate electrode G1 made of a polysilicon film is formed.

Note that the gate insulating film GOX is formed of, for example, an insulating film such as a silicon oxide film, and can be formed using, for example, a thermal oxidation method. However, the gate insulating film GOX is not limited to the silicon oxide film and can be variously changed. For example, the gate insulating film GOX may be a silicon oxynitride film (SiON). That is, a structure in which nitrogen is segregated at the interface between the gate insulating film GOX and the semiconductor substrate 1S may be employed. The silicon oxynitride film has a higher effect of suppressing generation of interface states in the film and reducing electron traps than the silicon oxide film. Therefore, the hot carrier resistance of the gate insulating film GOX can be improved, and the insulation resistance can be improved. In addition, the silicon oxynitride film is less likely to penetrate impurities than the silicon oxide film. For this reason, by using a silicon oxynitride film for the gate insulating film GOX, it is possible to suppress fluctuations in the threshold voltage caused by diffusion of impurities in the gate electrode toward the semiconductor substrate. For example, the silicon oxynitride film may be formed by heat-treating the semiconductor substrate 1S in an atmosphere containing nitrogen such as NO, NO _2, or NH ₃ . In addition, after forming a gate insulating film made of a silicon oxide film on the surface of the semiconductor substrate 1S, the semiconductor substrate 1S is heat-treated in an atmosphere containing nitrogen, and nitrogen is segregated at the interface between the gate insulating film GOX and the semiconductor substrate 1S. The same effect can be obtained.

  Further, the gate insulating film GOX may be formed of, for example, a high dielectric constant film having a dielectric constant higher than that of the silicon oxide film. Conventionally, a silicon oxide film has been used as a gate insulating film from the viewpoint of high insulation resistance and excellent electrical and physical stability at the silicon-silicon oxide interface. At this time, in the second embodiment, since the transistor after the 28 nm node is miniaturized, the thickness of the gate insulating film GOX is reduced by the scaling law. When such a thin silicon oxide film is used as the gate insulating film GOX, a so-called tunnel current is generated in which electrons flowing through the channel of the transistor tunnel through the barrier formed by the silicon oxide film and flow to the gate electrode.

  Therefore, by using a material having a dielectric constant higher than that of the silicon oxide film, a high dielectric constant film capable of increasing the physical film thickness even when the capacitance is the same has been used. According to the high dielectric constant film, since the physical film thickness can be increased even if the capacitance is the same, the leakage current can be reduced. In particular, the silicon nitride film is also a film having a higher dielectric constant than the silicon oxide film, but in the second embodiment, it is desirable to use a high dielectric constant film having a higher dielectric constant than the silicon nitride film.

For example, a hafnium oxide film (HfO ₂ film), which is one of hafnium oxides, is used as a high dielectric constant film having a dielectric constant higher than that of a silicon nitride film, but instead of the hafnium oxide film, an HfAlO film (hafnium film) is used. Other hafnium-based insulating films such as aluminate films), HfON films (hafnium oxynitride films), HfSiO films (hafnium silicate films), and HfSiON films (hafnium silicon oxynitride films) can also be used. Further, a hafnium-based insulating film in which an oxide such as tantalum oxide, niobium oxide, titanium oxide, zirconium oxide, lanthanum oxide, or yttrium oxide is introduced into these hafnium-based insulating films can also be used. Since the hafnium-based insulating film has a dielectric constant higher than that of the silicon oxide film or the silicon oxynitride film, like the hafnium oxide film, the same effect as that obtained when the hafnium oxide film is used can be obtained. When the gate insulating film GOX is thus thinned, a high dielectric constant film can be used as the gate insulating film GOX in addition to the silicon oxide film.

  Subsequently, a contact interlayer insulating film CIL is formed on the semiconductor substrate 1S on which the gate electrode G1 is formed. The contact interlayer insulating film CIL is formed of, for example, a silicon oxide film using TEOS as a raw material. The contact interlayer insulating film CIL is formed with a plug PLG that penetrates the contact interlayer insulating film CIL and is electrically connected to the gate electrode G1. The plug PLG is formed, for example, by forming a barrier conductor film made of a titanium / titanium nitride film in a contact hole formed in the contact interlayer insulating film CIL and embedding a tungsten film in the contact hole through the barrier conductor film. ing.

  Further, an interlayer insulating film IL1 is formed on the contact interlayer insulating film CIL on which the plug PLG is formed. The interlayer insulating film IL1 is formed of, for example, a silicon oxide film or a low dielectric constant film having a lower dielectric constant than a silicon oxide film such as a SiOC film. A wiring groove is formed in the interlayer insulating film IL1, a barrier conductor film is formed on the inner wall of the wiring groove, and a copper film is embedded in the wiring groove via the barrier conductor film. Thereby, the wiring L1 made of a copper wiring is formed. The barrier conductor film is formed of a laminated film of tantalum and tantalum nitride films, for example. As described above, the device structure when cut along the line AA in FIG. 4 is described.

  Next, FIG. 7 is a cross-sectional view taken along line BB in FIG. 7, in the semiconductor device according to the second embodiment, an element isolation region STI is formed on the main surface of a semiconductor substrate 1S, and a region partitioned by the element isolation region STI is an active region. An n-type well NWL and a p-type well PWL are formed in the semiconductor substrate 1S. The n-type well NWL is a semiconductor region in which an n-type impurity (donor) such as phosphorus or arsenic is introduced into the semiconductor substrate 1S, and the p-type well PWL is a semiconductor in which a p-type impurity (acceptor) such as boron is introduced into the semiconductor substrate 1S. It is an area. An n-type power supply region NR1 for supplying power to the n-type well NWL is formed in a partial surface region of the n-type well NWL. On the other hand, a p-type power supply region PR1 for supplying power to the p-type well PWL is formed in a partial surface region of the p-type well PWL. Further, in the active region partitioned by the element isolation region STI, a deep p-type impurity diffusion region PR2 serving as a source region and a drain region is formed on the surface of the n-type well NWL, and the source region and the drain are formed on the surface of the p-type well PWL. A deep n-type impurity diffusion region NR2 to be a region is formed. The deep p-type impurity diffusion region PR2 is a semiconductor region into which a p-type impurity such as boron is introduced, and the deep n-type impurity diffusion region NR2 is a semiconductor region into which an n-type impurity such as phosphorus or arsenic is introduced.

  Subsequently, a contact interlayer insulating film CIL is formed on the semiconductor substrate 1S. The contact interlayer insulating film CIL is formed of, for example, a silicon oxide film using TEOS as a raw material. The contact interlayer insulating film CIL includes an n-type power supply region NR1, a deep p-type impurity diffusion region PR2, a deep n-type impurity diffusion region NR2, and a p-type power supply region PR1 through the contact interlayer insulating film CIL. An electrically connected plug PLG is formed. The plug PLG is formed, for example, by forming a barrier conductor film made of a titanium / titanium nitride film in a contact hole formed in the contact interlayer insulating film CIL and embedding a tungsten film in the contact hole through the barrier conductor film. ing.

  Further, an interlayer insulating film IL1 is formed on the contact interlayer insulating film CIL on which the plug PLG is formed. The interlayer insulating film IL1 is formed of, for example, a silicon oxide film or a low dielectric constant film having a lower dielectric constant than a silicon oxide film such as a SiOC film. A wiring groove is formed in the interlayer insulating film IL1, a barrier conductor film is formed on the inner wall of the wiring groove, and a copper film is embedded in the wiring groove via the barrier conductor film. Thereby, the wiring L1 made of a copper wiring is formed. The barrier conductor film is formed of a laminated film of tantalum and tantalum nitride films, for example. As described above, the device structure when cut along the line BB in FIG. 4 is described.

  Next, FIG. 8 is a cross-sectional view taken along the line CC of FIG. 8, in the semiconductor device according to the second embodiment, an element isolation region STI is formed on the main surface of the semiconductor substrate 1S, and a region partitioned by the element isolation region STI is an active region. An n-type well NWL and a p-type well PWL are formed in the semiconductor substrate 1S. The n-type well NWL is a semiconductor region in which an n-type impurity (donor) such as phosphorus or arsenic is introduced into the semiconductor substrate 1S, and the p-type well PWL is a semiconductor in which a p-type impurity (acceptor) such as boron is introduced into the semiconductor substrate 1S. It is an area. An n-type power supply region NR1 for supplying power to the n-type well NWL is formed in a partial surface region of the n-type well NWL. On the other hand, a p-type power supply region PR1 for supplying power to the p-type well PWL is formed in a partial surface region of the p-type well PWL.

  A dummy gate electrode DG1 is formed on the element isolation region STI. The dummy gate electrode DG1 is an electrode that does not function as the gate electrode of the MISFET, and is normally in a floating state.

  Subsequently, a contact interlayer insulating film CIL is formed on the semiconductor substrate 1S on which the dummy gate electrode DG1 is formed. The contact interlayer insulating film CIL is formed of, for example, a silicon oxide film using TEOS as a raw material.

  Further, an interlayer insulating film IL1 is formed on the contact interlayer insulating film CIL. The interlayer insulating film IL1 is formed of, for example, a silicon oxide film or a low dielectric constant film having a lower dielectric constant than a silicon oxide film such as a SiOC film. A wiring groove is formed in the interlayer insulating film IL1, a barrier conductor film is formed on the inner wall of the wiring groove, and a copper film is embedded in the wiring groove via the barrier conductor film. Thereby, the wiring L1 made of a copper wiring is formed. The barrier conductor film is formed of a laminated film of tantalum and tantalum nitride films, for example. As described above, the device structure when cut along the line CC in FIG. 4 is described.

  Next, FIG. 9 is a cross-sectional view taken along line DD of FIG. 9, in the semiconductor device according to the second embodiment, the element isolation region STI is formed on the main surface of the semiconductor substrate 1S, and the region partitioned by the element isolation region STI is an active region. An n-type well NWL is formed in the semiconductor substrate 1S. The n-type well NWL is a semiconductor region in which an n-type impurity (donor) such as phosphorus or arsenic is introduced into the semiconductor substrate 1S.

  A dummy gate electrode DG1, a gate electrode G1, a gate electrode G2, and a dummy gate electrode DG2 are formed on the semiconductor substrate 1S in which the n-type well NWL and the element isolation region STI are formed. A wall SW is formed. A gate insulating film GOX is formed between the gate electrode G1 and the n-type well NWL, and a shallow p-type impurity diffusion region EX is formed in the n-type well NWL aligned with the gate electrode G1. A deep p-type impurity diffusion region PR2 is formed outside the shallow p-type impurity diffusion region EX. A source region and a drain region are formed by the shallow p-type impurity diffusion region EX and the deep p-type impurity diffusion region PR2.

  Similarly, a gate insulating film GOX is formed between the gate electrode G2 and the n-type well NWL, and a shallow p-type impurity diffusion region EX is formed in the n-type well NWL aligned with the gate electrode G2. The deep p-type impurity diffusion region PR2 is formed outside the shallow p-type impurity diffusion region EX. A source region and a drain region are formed by the shallow p-type impurity diffusion region EX and the deep p-type impurity diffusion region PR2.

  A silicide film may be formed on the surface of the gate electrode G1, the surface of the gate electrode G2, and the surface of the deep p-type impurity diffusion region PR2 in order to reduce resistance.

  A contact interlayer insulating film CIL is formed on the semiconductor substrate 1S on which the dummy gate electrode DG1, the gate electrode G1, the gate electrode G2, and the dummy gate electrode DG2 are formed. The contact interlayer insulating film CIL is formed of, for example, a silicon oxide film using TEOS as a raw material. The contact interlayer insulating film CIL is formed with a plug PLG that penetrates the contact interlayer insulating film CIL and is electrically connected to the deep p-type impurity diffusion region PR2. The plug PLG is formed, for example, by forming a barrier conductor film made of a titanium / titanium nitride film in a contact hole formed in the contact interlayer insulating film CIL and embedding a tungsten film in the contact hole through the barrier conductor film. ing.

  Further, an interlayer insulating film IL1 is formed on the contact interlayer insulating film CIL on which the plug PLG is formed. The interlayer insulating film IL1 is formed of, for example, a silicon oxide film or a low dielectric constant film having a lower dielectric constant than a silicon oxide film such as a SiOC film. A wiring groove is formed in the interlayer insulating film IL1, a barrier conductor film is formed on the inner wall of the wiring groove, and a copper film is embedded in the wiring groove via the barrier conductor film. Thereby, the wiring L1 made of a copper wiring is formed. The barrier conductor film is formed of a laminated film of tantalum and tantalum nitride films, for example. As described above, the device structure when cut along the line DD in FIG. 4 is described.

(Embodiment 3)
FIG. 10A is a circuit diagram showing an exclusive OR (EX-OR) circuit connected between the input wiring IN1 and the input wiring IN2 and the output wiring OUT, and FIG. 10B is an EX shown in FIG. It is a top view which shows the example of a layout structure of -OR circuit. In FIG. 10A, the EX-OR circuit is formed by five p-type MISFETs (P1 to P5) and five n-type MISFETs (N1 to N5). The input wiring IN1 is electrically connected to the gate electrode of the p-type MISFET (P1), the gate electrode of the n-type MISFET (N2), the gate electrode of the p-type MISFET (P5), and the gate electrode of the n-type MISFET (N5). Connected. The input wiring IN2 is electrically connected to the gate electrode of the n-type MISFET (N1), the gate electrode of the p-type MISFET (P2), the gate electrode of the n-type MISFET (N4), and the gate electrode of the p-type MISFET (P4). Connected. Furthermore, the output wiring OUT is electrically connected to the drain region of the p-type MISFET (P5) and the drain region of the p-type MISFET (P4).

  According to the EX-OR circuit configured as described above, when the signals input to the input wiring IN1 and the input wiring IN2 are opposite to each other, the signal “1” is output from the output wiring OUT. For example, when the signal “0” is input to the input wiring IN1 and the signal “0” is input to the input wiring IN2, the signal “0” is output from the output wiring OUT. On the other hand, when the signal “1” is input to the input wiring IN1 and the signal “0” is input to the input wiring IN2, the signal “1” is output from the output wiring OUT. Similarly, when the signal “0” is input to the input wiring IN1 and the signal “1” is input to the input wiring IN2, the signal “1” is output from the output wiring OUT. On the other hand, when the signal “1” is input to the input wiring IN1 and the signal “1” is input to the input wiring IN2, the signal “0” is output from the output wiring OUT.

  Next, FIG. 10B is a plan view showing a layout configuration example of the EX-OR circuit shown in the circuit diagram of FIG. In FIG. 10B, the layout configuration of the standard cell CL according to the third embodiment incorporates a novel design concept different from the conventional design method and also supports a new layout rule. Specifically, as new layout rules, gate electrodes (polysilicon film) are arranged at regular intervals, and the gate electrode is not bent at all, and the shape of the diffusion layer is a figure within 8 vertices. Rules for shape are incorporated.

  As shown in FIG. 10 (b), the power supply wiring L1A and the power supply wiring L1B made of the first wiring layer extend in the X direction (first direction) across the upper and lower sides of the rectangular standard cell CL. Has been placed. The power supply wiring L1A is a wiring for supplying a power supply potential (VDD), and the power supply wiring L1B is a wiring for supplying a reference potential (GND) lower than the power supply potential (VDD). A p-type semiconductor region (p-type diffusion layer) PDR and an n-type semiconductor region (n-type diffusion layer) NDR are formed so as to be sandwiched between the power supply wiring L1A and the power supply wiring L1B. The p-type semiconductor region PDR and the n-type semiconductor region NDR have a quadrangular shape based on a new layout rule that sets the shape of the diffusion layer to a graphic shape within 8 vertices.

  The p-type semiconductor region PDR formed in the standard cell CL has a first boundary line connecting one end of the first side (power supply line L1A) and one end of the second side (power supply line L1B) of the standard cell CL; It arrange | positions so that it may not contact both the 2nd boundary line which ties the other end part of a 1st edge | side (power supply wiring L1A), and the other end part of a 2nd edge | side (power supply wiring L1B). Similarly, the n-type semiconductor region NDR formed in the standard cell CL has a first boundary connecting one end of the first side (power supply line L1A) and one end of the second side (power supply line L1B) of the standard cell CL. The line and the second boundary line connecting the other end of the first side (power supply line L1A) and the other end of the second side (power supply line L1B) are arranged so as not to contact each other. Therefore, considering a plurality of standard cells CL arranged adjacent to each other in the X direction (first direction), the p-type semiconductor regions PDR formed in each standard cell CL are separated from each other and each standard cell CL The n-type semiconductor regions NDR formed in the cell CL are also isolated from each other.

  Subsequently, in the standard cell CL according to the third embodiment, the Y direction (second direction) branches from the power supply line L1A toward the inside of the standard cell CL at both ends of the standard cell CL (boundary of the standard cell CL). Two protruding wirings PL1A that protrude to the right are formed. Similarly, at both ends of the standard cell CL (boundary of the standard cell CL), two protruding wirings PL1B that branch from the power supply wiring L1B and project in the Y direction (second direction) toward the inside of the standard cell CL are formed. Has been. Of the two protruding wirings PL1A, the left protruding wiring PL1A includes a bent portion BD1A whose end is bent in the X direction (first direction) toward the inside of the standard cell CL, and further from the bent portion BD1A. A bent portion BD2A bent in the Y direction is included, and a bent portion BD3A further bent in the X direction from the bent portion BD2A is included. The bent portion BD3A is electrically connected to the p-type semiconductor region PDR by a plug PLG. On the other hand, of the two protruding wirings PL1A, the right protruding wiring PL1A has no bent portion.

  On the other hand, the two protruding wirings PL1B include a bent part BD1B whose end is bent in the X direction (first direction) toward the inside of the standard cell CL, and the end of the bent part BD1B is Y. A bent portion BD2B bent in the direction (second direction) is provided. The bent portion BD2B is electrically connected to the n-type semiconductor region NDR by the plug PLG.

  As described above, in the third embodiment, the protruding wiring PL1A in which the bent portion BD1A, the bent portion BD2A, and the bent portion BD3A are formed has the bent portion BD3A electrically connected to the p-type semiconductor region PDR by the plug PLG. Yes. On the other hand, the protruding wiring PL1B in which the bent portion BD1B is formed further has a bent portion BD2B bent in the Y direction (second direction) from the end portion of the bent portion BD1B. It is electrically connected to the n-type semiconductor region NDR by PLG.

  Next, as shown in FIG. 10B, each of the regions in the standard cell CL sandwiched between the power supply wiring L1A and the power supply wiring L1B extends in the Y direction (second direction), and X The dummy gate electrode DG1, the gate electrodes G1 to G5, and the dummy gate electrode DG2 are arranged so as to be aligned in the direction (first direction). Thereby, for example, p-type MISFET (P1) to p-type MISFET (P5) are formed in regions where the gate electrodes G1 to G5 and the p-type semiconductor region PDR overlap in a plane, respectively, and the gate electrodes G1 to G5 and the n-type are formed. The n-type MISFET (N1) to the n-type MISFET (N5) are formed in regions where the semiconductor region NDR overlaps in plan view. The gate electrodes G1 to G5 and the dummy gate electrodes DG1 and DG2 are formed based on a rule in which gate electrodes (polysilicon films) are arranged at equal intervals and the gate electrodes are not bent at all and are linear. The dummy gate electrodes DG1 and DG2 here are those that do not overlap the p-type semiconductor region PDR and the n-type semiconductor region NDR in a planar manner and are arranged on the boundary line of the standard cell CL. In other words, the dummy gate electrodes DG1 and DG2 do not function as the gate electrodes of the p-type MISFETs (P1 to P5) and the n-type MISFETs (N1 to N5) and have a potential in a floating state.

  The gate electrode G1 is connected to the input wiring IN formed from the first wiring layer via the plug PLG. An output wiring OUT is formed so as not to contact the input wiring IN, and the output wiring OUT is disposed on the gate electrode G2 so as not to contact the input wiring IN.

  The standard cell CL described above is composed of components formed below the first wiring layer, and is formed of an input wiring IN1, an input wiring IN2 for inputting an input signal to the standard cell CL, and a first wiring layer. The output wiring OUT that outputs an output signal from the standard cell CL is electrically connected to a wiring (second wiring layer) above the first wiring layer. That is, in the third embodiment, the standard cell CL is composed of the components below the first wiring layer, and the standard cell CL is connected to the second wiring layer above the first wiring layer, so that any digital A circuit (logic circuit) is formed.

  An n-type power supply region (semiconductor region) for supplying a power supply potential (VDD) to the n-type well is provided immediately below the power supply wire L1A. The n-type power supply region and the power supply wire L1A are connected by a plug PLG. Has been. Similarly, a p-type power supply region (semiconductor region) for supplying a reference potential (GND) to the p-type well is provided immediately below the power supply wire L1B. The p-type power supply region and the power supply wire L1B are plug PLG. It is connected. That is, an N-type well is formed in the semiconductor substrate on which the standard cell CL is formed, and the power supply wiring L1A and the N-type well are electrically connected by a plurality of plugs PLG (first via plugs). Similarly, a P-type well is formed in the semiconductor substrate in which the standard cell CL is formed, and the power supply wiring L1B and the P-type well are electrically connected by a plurality of plugs (second via plugs). At this time, the plurality of plugs PLG (first via plug and second via plug) are not formed at the four corners of the standard cell CL.

  Further, in the third embodiment, the two gate electrodes extend in the X direction in the separation region between the power supply wiring L1B extending in the X direction and the bent portion BD1B bent in the X direction. The layout configuration is such that the input wiring IN2 of the first wiring layer that connects G1 and the gate electrode G4 is formed. This technical idea can be further expanded. For example, at least one or more wirings of the first wiring layer extending in the X direction are formed in a separation region between the power supply wiring L1B extending in the X direction and the bent portion BD1B bent in the X direction. In addition, it can be said that the protruding wiring PL1B has a layout configuration. In particular, it is effective when the wiring of the first wiring layer formed in the separated region is a wiring that electrically connects two or more gate electrodes included in a plurality of gate electrodes.

  Further, in the third embodiment, the two gate electrodes extend in the X direction in a separation region between the power supply wiring L1A extending in the X direction and the bent portion BD1A bent in the X direction. The layout configuration is such that the input wiring IN1 of the first wiring layer that connects G2 and the gate electrode G5 is formed. Also in this case, the technical idea can be easily extended. For example, at least one or more wirings of the first wiring layer extending in the X direction are formed in a separation region between the power supply wiring L1A extending in the X direction and the bent portion BD1A bent in the X direction. In addition, it can be said that the protruding wiring PL1A has a layout configuration. In particular, it is effective when the wiring of the first wiring layer formed in the separated region is a wiring that electrically connects two or more gate electrodes included in a plurality of gate electrodes.

  Subsequently, when the layout configuration of the EX-OR circuit shown in FIG. 10B is decomposed into two layers, it is as shown in FIGS. 11A to 11B. FIG. 11A shows the layout configuration of the first layer. As shown in FIG. 11A, an n-type power supply region DR1, a p-type semiconductor region PDR, an n-type semiconductor region NDR, and a p-type power supply region DR2 are formed on the semiconductor substrate so as to be aligned in the Y direction. ing. These regions are all formed from a semiconductor region.

  Next, as shown in FIG. 11A, the dummy gate electrode DG1, the gate electrodes G1 to G5, and the dummy gate electrode DG2 are formed so that each extends in the Y direction and is aligned in the X direction. Yes. These dummy gate electrodes DG1, DG2 and gate electrodes G1-G5 are formed by processing a polysilicon film.

  FIG. 11B is a diagram showing a layout configuration of the second layer. Specifically, in FIG. 11B, as the first wiring layer, the power wiring L1A, the power wiring L1B, the protruding wiring PL1A, the protruding wiring PL1B, the bent portion BD1A, the bent portion BD2A, the bent portion BD3A, the bent portion BD1B, A portion BD2B, an input wiring IN1, an input wiring IN2, and an output wiring OUT are formed.

  As described above, in the third embodiment, the protruding wirings (PL1A, PL1B) protrude from the power supply wirings (L1A, L1B) into the standard cell CL (Y direction) at the corners at both ends of the standard cell CL. In addition, bent portions (BD1A, BD1B) bent in the X direction from the protruding wirings (PL1A, PL1B) protruding are formed. Further, a bent portion BD2A bent from the bent portion BD1A in the Y direction and a bent portion BD3A bent from the bent portion BD2A in the X direction are formed. Further, a bent portion BD2B bent in the Y direction from the bent portion BD1B is formed. The bent portions (BD3A, BD2B) and the p-type semiconductor region PDR and the n-type semiconductor region NDR are connected by a plug PLG. Thereby, a space can be secured in the internal region of the standard cell CL, and the degree of freedom of the layout configuration can be improved. Therefore, even when a new layout rule introduced with the miniaturization of the MISFET is applied, the degree of freedom to devise the layout configuration increases, so a layout configuration that can reduce the size of the standard cell CL. It becomes easy to adopt.

(Embodiment 4)
In the fourth embodiment, an example in which a plurality of standard cells incorporating the technical idea of the present invention is actually arranged will be described. FIG. 12 is a diagram showing a layout configuration in which six standard cells CL1 to CL6 constituting the EX-OR circuit are arranged in two rows and three columns. In FIG. 12, protruding wirings PL1A and protruding wirings PL1B are drawn out from corners at both ends of each standard cell CL1 to CL6. Specifically, a protruding wiring PL1A protrudes from the power supply wiring L1A, and a bent portion BD1A and a bent portion BD2A are provided on the protruding wire PL1A. Similarly, a protruding wiring PL1B protrudes from the power supply wiring L1B, and a bent portion BD1B and a bent portion BD2B are provided on the protruding wire PL1B.

  Here, in the standard cells CL1 to CL6, there are a protruding wiring having a bent portion and a protruding wiring having no bent portion. In this case, the length of the protruding wiring having the bent portion is slightly different from the length of the protruding wiring having no bent portion. This is to secure a margin between the protruding wiring and the neighboring wiring. That is, the protruding wiring having the bent portion and the protruding wiring not having the bent portion are both formed by processing with the photolithography technique. At this time, due to the problem of processing accuracy of the photolithography technology, it is necessary to secure a margin between the protruding wiring having no bent portion and the neighboring wiring, rather than the margin between the protruding wiring having the bent portion and the neighboring wiring. It is. In other words, due to the processing accuracy of the photolithography technology, the margin for preventing short-circuit defects from each other is greater than the distance between the protruding wiring having the bent portion and the neighboring wiring, and the margin between the protruding wiring having no bent portion and the neighboring wiring. Severe between the wiring. Therefore, for example, as shown in FIG. 12, the margin between the protruding wiring having the bent portion and the neighboring wiring is, for example, 0.05 μm, whereas the protruding wiring not having the bent portion is adjacent to the neighboring wiring. The margin between the wiring is, for example, 0.07 μm.

  In addition, the protruding wirings of adjacent standard cells have substantially the same length. This is to determine the length of the protruding wiring after securing the margin in the standard cell based on the relationship between the processing accuracy of the photolithography technique and the adjacent wiring. This is because the length of the protruding wiring may be slightly different. Therefore, the length of the protruding wiring PL1A of the prior art is various when connecting the shortest distance between the power supply wiring L1A and the p-type semiconductor region PDR. Compared with that, the protruding wiring when this embodiment is applied is The length is almost the same in the standard cell and between the different standard cells.

  As shown in FIG. 12, in the fourth embodiment, the protruding wirings (PL1A, PL1B) from the power wirings (L1A, L1B) to the inside of the standard cell CL (Y direction) at the corners at both ends of the standard cell CL. Bending portions (BD1A, BD1B) that protrude and project in the X direction from the protruding wirings (PL1A, PL1B) are formed. Further, a bent portion BD2A bent from the bent portion BD1A in the Y direction and a bent portion BD3A bent from the bent portion BD2A in the X direction are formed. Further, a bent portion BD2B bent in the Y direction from the bent portion BD1B is formed. The bent portions (BD3A, BD2B) and the p-type semiconductor region and the n-type semiconductor region are connected by plugs.

  Further, in the fourth embodiment shown in FIG. 12, since the protruding wirings (PL1A, PL1B) are formed at the corners of both ends of the standard cells CL1 to CL6, the protruding wirings (PL1A, PL1B) between adjacent standard cells. ) Can be made common. Thus, the number of protruding wirings (PL1A, PL1B) formed inside the standard cells CL1 to CL6 can be reduced.

  As described above, in the fourth embodiment, the size reduction effect of the standard cells CL1 to CL6 by forming protruding wirings having bent portions at the corners at both ends of the individual standard cells CL1 to CL6, and the adjacent standard cells Due to the synergistic effect of the size reduction effect of the standard cells CL1 to CL6 by sharing the protruding wiring between the cells, sufficient space can be secured in the internal area of the standard cells CL1 to CL6, and the flexibility of the layout configuration is improved. Can be made. Therefore, even when a new layout rule introduced with the miniaturization of MISFET is applied, the degree of freedom to devise the layout configuration increases, so that the layout of the standard cell CL can be reduced. It becomes easy to adopt the configuration.

  In FIG. 12, the example in which the standard cells CL1 to CL6 including the same EX-OR circuit are arranged has been described. However, the technical idea of the present invention is also applicable to the case where the standard cells CL1 to CL6 having different functions are arranged. Can do. This example will be described below.

  FIG. 13 is a diagram showing a layout configuration in which standard cells CL1 to CL6 having a plurality of different functions are arranged. FIG. 13A is a diagram showing a lower layer obtained by disassembling the standard cells CL1 to CL6 into two layers. On the other hand, FIG.13 (b) is a figure which shows the upper layer which decomposed | disassembled standard cell CL1-CL6 into two layers.

  As shown in FIG. 13A, an n-type power supply region DR1, a p-type semiconductor region PDR, an n-type semiconductor region NDR, and a p-type power supply region DR2 are formed on the semiconductor substrate so as to be aligned in the Y direction. ing. These regions are all formed from a semiconductor region.

  Next, as shown in FIG. 13A, the dummy gate electrode DG and the gate electrode G are formed so as to extend in the Y direction and to be aligned in the X direction. These dummy gate electrode DG and gate electrode G are formed by processing a polysilicon film.

  FIG. 13B is a diagram showing a layout configuration of the second layer. Specifically, in FIG. 13B, as the first wiring layer, the power supply wiring L1A, the power supply wiring L1B, the protruding wiring PL1A, the protruding wiring PL1B, the bent portion BD1A, the bent portion BD2A, the bent portion BD1B, the bent portion BD2B, and the like. Is formed.

  At this time, the standard cell CL1 is a 3-input NAND circuit, and the standard cell CL2 is a 4-input NAND circuit. The standard cell CL3 is a complex circuit (selector), and the standard cell CL4 is an EX-OR circuit. Further, the standard cell CL5 is a complex circuit (selector), and the standard cell CL6 is a 2-input NOR circuit.

  As described above, also in FIG. 13, at the corners of both ends of the standard cells CL1 to CL6, the protruding wirings (PL1A, PL1B) protrude from the power supply wirings (L1A, L1B) into the standard cell CL (Y direction), and Bending portions (BD1A, BD1B) bent in the X direction from the protruding wirings (PL1A, PL1B) protruding are formed. Further, a bent portion BD2A bent in the Y direction from the bent portion BD1A is formed. Further, a bent portion BD2B bent in the Y direction from the bent portion BD1B is formed. The bent portions (BD2A, BD2B) and the p-type semiconductor region and the n-type semiconductor region are connected by plugs.

  Further, even in the case shown in FIG. 13, the protruding wirings (PL1A, PL1B) are formed at the corners of both ends of the standard cells CL1 to CL6, so that the protruding wirings (PL1A, PL1B) are made common between the adjacent standard cells. can do. Thus, the number of protruding wirings (PL1A, PL1B) formed inside the standard cells CL1 to CL6 can be reduced.

  As described above, even when the standard cells CL1 to CL6 having different functions are arranged, the standard cells CL1 to CL6 are formed by forming protruding wirings having bent portions at the corners at both ends of each standard cell CL1 to CL6. A synergistic effect of the size reduction effect and the size reduction effect of the standard cells CL1 to CL6 due to the fact that the protruding wiring can be shared between the adjacent standard cells can be obtained. As a result, a sufficient space can be secured in the internal regions of the standard cells CL1 to CL6, and the degree of freedom in layout configuration can be improved. Therefore, even when a new layout rule introduced with the miniaturization of MISFET is applied, the degree of freedom to devise the layout configuration increases, so that the layout of the standard cell CL can be reduced. It becomes easy to adopt the configuration.

(Embodiment 5)
In the fifth embodiment, a layout configuration example of a standard cell in which a flip-flop circuit with a SCAN function is formed will be described. FIG. 14 is a diagram showing a layout configuration of a standard cell CL in which a flip-flop circuit with a SCAN function is formed. Also in FIG. 14, as a new layout rule, the gate electrode (polysilicon film) is arranged at equal intervals, and the gate electrode is not bent at all, and the shape of the diffusion layer is within 8 vertices. Rules for graphic shapes are incorporated. Even in a situation where such a new layout rule is adopted, by using the technical idea of the present invention, the standard cell CL in the fifth embodiment is more than the first wiring layer and the first wiring layer. It is characterized in that a standard cell CL in which a flip-flop circuit with a SCAN function is formed can be formed only with lower layer components.

  FIG. 15 is a diagram showing a layout configuration of the first wiring layer of the standard cell CL in which the flip-flop circuit with the SCAN function according to the fifth embodiment is formed. As shown in FIG. 15, protruding wirings PL1A and protruding wirings PL1B protrude from the corners of the four corners of the standard cell CL. Specifically, at the corners at both ends of the standard cell CL, the protruding wiring PL1A protrudes from the power supply wiring L1A into the standard cell CL (Y direction). In particular, a bent portion BD1A bent in the X direction is drawn out from the protruding wiring PL1A formed at the right corner. A bent portion BD2A bent in the Y direction is drawn from the bent portion BD1A. On the other hand, at the corners at both ends of the standard cell CL, the protruding wiring PL1B protrudes from the power supply wiring L1B into the standard cell CL (Y direction). A bent portion BD1B bent in the X direction is drawn out from the protruding wiring PL1B formed at the corners at both ends, and a bent portion BD2B bent in the Y direction is drawn out from the bent portion BD1B.

  As described above, also in the fifth embodiment, the protruding wirings (PL1A, PL1B) are drawn out from the corners of the standard cell CL, and the bent portions (BD1A, BD2A, BD1B, BD2B) are formed in the protruding wirings (PL1A, PL1B). The power supply potential (VDD) and the reference potential (GND) are supplied to the standard cell CL. For this reason, the number of protruding wirings formed inside the standard cell CL can be reduced. This means that the space provided in the standard cell CL increases. Therefore, a sufficient space can be secured in the internal region of the standard cell CL in which the flip-flop circuit with the SCAN function in the fifth embodiment is formed, and the degree of freedom of the layout configuration can be improved. Therefore, even when a new layout rule introduced along with the miniaturization of the MISFET is applied, the degree of freedom to devise the layout configuration increases, so that the size of the standard cell CL can be reduced.

  In the fifth embodiment, since a sufficient space can be secured in the internal region of the standard cell CL, only the first wiring layer and the components below the first wiring layer have the SCAN function. A flip-flop circuit can be formed. For example, FIG. 16 is a diagram showing the second wiring layer of the standard cell CL in the fifth embodiment, but the second layer (second wiring layer) above the first layer (first wiring layer) is shown. It can be seen that the wiring for forming the flip-flop circuit is not formed. That is, the standard cell CL in which the flip-flop circuit with the SCAN function in the fifth embodiment is formed by only the first wiring layer and the components below the first wiring layer. Therefore, according to the standard cell CL in the fifth embodiment, the second wiring layer can be freely used as a wiring for connecting the standard cells CL, not a wiring constituting the standard cell CL itself. . For example, FIG. 17 is a diagram illustrating a layout configuration example of the wiring L2 that connects the standard cells CL in the second wiring layer. As shown in FIG. 17, in the fifth embodiment, since the second wiring layer is not used in the standard cell CL itself, the wiring L2 connecting the standard cells CL can be freely laid out. This means that the second wiring layer can be effectively used and the wiring density of the second wiring layer can be improved. As a result, the wiring L2 can be efficiently laid out. The size can be reduced.

  For example, when non-adjacent standard cells are connected, if the wiring for configuring the standard cell is laid out in the second wiring layer, the wiring is bent or arranged around the third wiring layer. It is necessary to do. However, in the fifth embodiment, since the wiring for configuring the standard cell is not arranged in the second wiring layer, the second wiring layer of the standard cell sandwiched between the standard cells connected to each other is used. Therefore, it is possible to wire in a straight line, and an efficient layout can be realized.

  For example, FIG. 22 is a diagram illustrating a second wiring layer of the standard cell CL (P) in the comparative example. As shown in FIG. 22, in the standard cell CL (P) in the comparative example, the wiring L2A of the second wiring layer is used to configure the standard cell CL (P). In the comparative example, since a part of the second wiring layer is used as the wiring of the standard cell CL itself, there are many restrictions when the second wiring layer is used as a wiring for connecting the standard cells CL. FIG. 23 is a diagram illustrating a wiring L2B that connects the standard cells CL in the comparative example. Since the wiring L2B must be arranged so as to avoid the wiring L2A shown in FIG. 22, it is understood that there are many restrictions on the layout and the layout cannot be performed efficiently.

  On the other hand, in the fifth embodiment, even when a new layout rule is adopted, a sufficient space is secured inside the standard cell CL by using the technical idea of the present invention. Therefore, even in a complicated standard cell CL such as a flip-flop circuit with a SCAN function, the standard cell CL can be configured only by the first wiring layer and the components below the first wiring layer. . Therefore, it is not necessary to use the second wiring layer above the first wiring layer as the wiring of the standard cell CL itself, and the second wiring layer can be freely used for connection between the standard cells CL. As a result, the degree of freedom of the wiring layout is improved and the wiring can be efficiently laid out, so that the entire semiconductor device can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  A large number of standard cells of the first to fifth embodiments are arranged on the chip. Since the height of the protruding wiring is almost the same in any standard cell, the dummy gate electrode and the dummy gate electrode can be arranged without any useless space regardless of the function of the cell and the length in the X direction. A standard cell can be arranged with the protruding wiring as a cell boundary. Thereby, the layout efficiency can be increased.

  Finally, main differences between Patent Document 1 described in the background art and the present invention will be described. The first difference between Patent Document 1 and the present invention is that, in the present invention, the gate electrode (polysilicon film) is arranged at equal intervals, and the gate electrode is not bent at all and has a straight line shape. A new layout rule is adopted in which the shape is a figure shape with 8 or less vertices, whereas Patent Document 1 is different in that the technology does not assume such a layout rule.

  Patent Document 1 describes a layout configuration in which a power supply wiring connected to a diffusion layer is drawn on a boundary line between adjacent standard cells. Therefore, even in Patent Document 1, it can be said that the protruding wiring is drawn out from the corner of the standard cell. However, Patent Document 1 is different from the technical idea of the present invention in that a bent portion is not provided in the protruding wiring drawn out from the corner of the standard cell. In Patent Document 1, since the diffusion layers in the standard cell are connected by the adjacent standard cells, it is formed so as to straddle the boundary line of the standard cell only by pulling out the linear protruding wiring from the corner of the standard cell. It is possible to supply power to the diffusion layer. In contrast, in the present invention, the diffusion layer is separated for each standard cell, and the diffusion layer is not formed on the boundary line of the standard cell. For this reason, it is not possible to supply power to the diffusion layer with only the protruding wiring drawn out on the boundary line of the standard cell, and it is necessary to provide power to the diffusion layer by providing a bent portion that bends from the protruding wiring to the inside of the standard cell. is there. Thus, it can be seen that there is a large second difference between Patent Document 1 and the present invention.

  Further, in Patent Document 1, an inverter circuit is merely exemplified as a standard cell. That is, only the case where adjacent standard cells are inverter circuits is shown. Therefore, for example, considering the case where the adjacent standard cells are an inverter circuit and a NOR circuit, the following inconvenience occurs. In the case of inverter circuits, a diffusion layer serving as a source region can be connected between adjacent standard cells, but when the inverter circuit and the NOR circuit are adjacent, the source region of the inverter circuit and the drain region of the NOR circuit are connected. The diffusion layer cannot be connected. That is, the technique of Patent Document 1 cannot be applied to a case where the inverter circuit and the NOR circuit are adjacent to each other, and can be said to be a technique having poor versatility.

  Consider a case where the adjacent standard cell is a two-input NAND circuit. FIG. 24 is a diagram illustrating an example in which the technique described in Patent Document 1 is applied to a 2-input NAND circuit. As shown in FIG. 24, the input wiring A1, the input wiring B1, and the output wiring OUT1 are formed in the standard cell CL1, and the input wiring A2, the input wiring B2, and the output wiring OUT2 are formed in the standard cell CL2. ing. If the standard cell CL1 and the standard cell CL2 are arranged adjacent to each other based on the technique described in Patent Document 1, the input wiring A1 of the standard cell CL1 and the input wiring A2 of the standard cell CL2 are in contact with each other. Therefore, as shown in FIG. 25, when the adjacent standard cell CL1 and standard cell CL2 are two-input NAND circuits, there is a gap between the standard cell CL1 and the standard cell CL2 so that the input wiring A1 and the input wiring A2 do not contact each other. Need to be separated. As a result, the size of the entire semiconductor device increases.

  On the other hand, FIG. 18 is a diagram showing an example in which the technical idea of the present invention is applied to a 2-input NAND circuit. As shown in FIG. 18, in the present invention, the bent portion BD1A is formed in the protruding wiring PL1A, and the bent portion BD1B and the bent portion BD2B are formed in the protruding wiring PL1B, so that the input wiring A1 and the input wiring A2 are in contact with each other. It can be seen that this can be prevented. As described above, it can be seen that the technical idea of the present invention is completely different from the technique of Patent Document 1.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

1S Semiconductor substrate A Input wiring A1 Input wiring B Input wiring B1 Input wiring BD1A Bending portion BD1B Bending portion BD1B (1) Bending portion BD1B (2) Bending portion BD2A Bending portion BD2B Bending portion BD3A Bending portion C Input wiring CHP Contact Interlayer insulation film CL Standard cell CL1 Standard cell CL2 Standard cell CL3 Standard cell CL4 Standard cell CL5 Standard cell CL6 Standard cell CL (P) Standard cell CL1 (P) Standard cell CL2 (P) Standard cell CPU Central processing unit D Input wiring DG dummy gate electrode DG1 dummy gate electrode DG2 dummy gate electrode DR1 n-type power supply region DR2 p-type power supply region EX shallow p-type impurity diffusion region G gate electrode GOX gate insulating film G1 gate electrode G2 gate electrode G3 gate electrode G4 gate G5 gate electrode G6 gate electrode G7 gate electrode IL1 interlayer insulation film IN input wiring IN1 input wiring IN2 input wiring IP 3D image processor L1 wiring L1A power wiring L1B power wiring L1C wiring L2 wiring L2A wiring L2B wiring MCA memory cell array NDR n-type semiconductor region NDR1 n-type semiconductor region NDR2 n-type semiconductor region NR1 n-type power supply region NR2 deep n-type impurity diffusion region NWL n-type well N1 n-type MISFET
N2 n-type MISFET
N3 n-type MISFET
N4 n-type MISFET
N5 n-type MISFET
OUT output wiring OUT1 output wiring OUT2 output wiring PC peripheral circuit PDR p-type semiconductor region PLG plug PL1A protruding wiring PL1B protruding wiring PL1B (1) protruding wiring PL1B (2) protruding wiring PR1 p-type power supply region PR2 deep p-type impurity diffusion region PWL p-type well P1 p-type MISFET
P2 p-type MISFET
P3 p-type MISFET
P4 p-type MISFET
P5 p-type MISFET
RAM memory SPU audio processor STI element isolation region SW sidewall TP communication processor VPU video processing unit

Claims (7)

A plurality of standard cells arranged adjacent to each other along the first direction of the semiconductor substrate;
Each of the plurality of standard cells having a rectangular shape is
(A) a first power supply wiring of a first wiring layer extending on a first side along the first direction;
(B) a second power supply wiring of the first wiring layer that extends on a second side parallel to the first side by a predetermined distance and to which a voltage lower than that of the first power supply wiring is applied;
(C) a first semiconductor region and a second semiconductor region arranged in a second direction intersecting the first direction in the semiconductor substrate between the first power supply wiring and the second power supply wiring; The first semiconductor region disposed on the first power supply wiring side and the second semiconductor region disposed on the second power supply wiring side;
(D) a semiconductor device having a plurality of gate electrodes extending in the second direction and formed on the semiconductor substrate at equal intervals in the first direction,
Each of the plurality of standard cells further includes
(E) Two first protruding wirings that branch from the first power supply wiring and protrude in the second direction toward the inside of the standard cell at both ends of the first side;
(F) Two second protruding wirings that branch from the second power supply wiring and project in the second direction toward the inside of the standard cell at both ends of the second side,
One of the plurality of gate electrodes is disposed so as to planarly overlap a first boundary line connecting one end of the first side and one end of the second side;
One second gate electrode among the plurality of gate electrodes is disposed so as to overlap in plan with a second boundary line connecting the other end of the first side and the other end of the second side,
When the surface of the semiconductor substrate is viewed in plan, one of the first protruding wirings and one of the second protruding wirings are disposed so as to overlap the first gate electrode, and the other of the first protruding wirings and the first protruding wirings 2. The semiconductor device according to claim 2, wherein the other of the two protruding wirings is disposed so as to overlap with the second gate electrode. The semiconductor device according to claim 1,
The semiconductor device, wherein the first gate electrode and the second gate electrode are dummy gate electrodes in a floating state. The semiconductor device according to claim 1,
The line width of the first gate electrode is smaller than the minimum line width of the first protruding wiring, and the line width of the second gate electrode is smaller than the minimum line width of the second protruding wiring. A semiconductor device. The semiconductor device according to claim 1,
The standard cell is formed of only the wiring of the first wiring layer and the components formed below the first wiring layer. The semiconductor device according to claim 4,
The standard cell is formed of the first wiring layer, and has an input wiring for inputting an input signal to the standard cell, and an output wiring formed of the first wiring layer for outputting an output signal from the standard cell. The input wiring and the output wiring are electrically connected to wiring higher than the first wiring layer. The semiconductor device according to claim 1,
The semiconductor device, wherein the first semiconductor region and the second semiconductor region have a rectangular shape with four vertices. The semiconductor device according to claim 1,
The standard cell is used in a digital circuit.

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