JPH11214649A - Hybrid semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a hybrid semiconductor integrated circuit device, wherein capacitance elements used in logic circuits can be easily realized and the level of integration can be improved by reducing the space factor by the capacitance elements. SOLUTION: In a hybrid semiconductor integrated circuit device having DRAM circuit 4 and logic circuits mixed on the same semiconductor substrate 10, capacitance elements constituted in the same structure as information storing capacitance elements of memory cells of the DRAM circuit 4 are disposed in the logic circuits. The capacitance element is constituted of a trench 12, an electrode formed of a p-type well region 11, a dielectric film 13 and an electrode 14 and a trench capacitance structure is adopted and is used as capacitance element, etc., incorporated in a smoothing capacitor and logic circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mixed semiconductor integrated circuit device, and more particularly to a mixed semiconductor integrated circuit device in which a dynamic random access memory (DRAM) circuit and a logic circuit are mixed on the same semiconductor substrate. It relates to a circuit device.

[0002]

2. Description of the Related Art Application-specific semiconductor integrated circuit devices (ASI)
Recently, the demand for this type of ASIC is increasing because C: Application Specific Integrated Circuits can shorten the design and development period. The ASIC regularly arranges a plurality of basic cells (Basic-cells) as the minimum unit of a circuit, and the CAD (Compu
A logic circuit can be constructed by connecting between transistors in the basic cell and between the basic cells based on information designed by ter Aided Design).

[0003] The basic cell is a complementary MOSFET (Metal Oxide Semiconductor Fiscal) for the purpose of high integration and low power consumption.
In many cases, it is formed by an eld effect transistor) or mainly using the complementary MOSFET. Usually, one or a plurality of sets of complementary MOSFETs are arranged in one basic cell, and a layout in which a logic circuit such as an inverter circuit or a NAND gate circuit is easily constructed is adopted.

The connection is made by a plurality of layers of wiring. For example, in an ASIC adopting a two-layer wiring structure, connection between transistors in a basic cell and connection in a row direction between the basic cells are performed by the first-layer wiring. The connection in the column direction between the basic cells is performed by the second layer wiring. As the wiring formed in each wiring layer, a wiring mainly composed of an aluminum alloy film is used for the purpose of increasing the signal transmission speed.

[0005]

In the above-mentioned ASIC, no consideration is given to the following points. In order to reduce power supply noise and ensure the stability of circuit operation, and to form capacitors used in logic circuits, ASICs use capacitors of unused basic cells to form capacitors. . For example, the source region and the drain region of the n-channel MOSFET of the basic cell are connected to the circuit reference power supply, the gate electrode is connected to the circuit operation power supply, and the space between the gate electrode and the source region, The generated mirror capacitance forms a smoothing capacitor. Further, by incorporating the capacitance element formed by the Miller capacitance into a logic circuit, a capacitance element used in the logic circuit is formed.

However, in the above-mentioned ASIC, in order to form a large capacity like a smoothing capacitor, it is necessary to increase the transistor size of a basic cell or to use transistors of a large number of basic cells as capacitive elements. Therefore, there is a problem that the number of mounted logic circuits is reduced and the degree of integration is reduced. Furthermore, a capacitor formed by a transistor of a basic cell has a wasteful area of a source region and a drain region that do not contribute to formation of a capacitor, and there is a problem that the formation of the capacitor itself lowers the degree of integration.

The present invention has been made to solve the above problems, and has been made by focusing on a mixed semiconductor integrated circuit device in which a DRAM circuit and a logic circuit are mixed on the same semiconductor substrate. Accordingly, an object of the present invention is to provide a mixed-type semiconductor integrated circuit device capable of easily realizing a capacitance element used in a logic circuit, reducing the area occupied by the capacitance element, and improving the degree of integration. It is.

[0008]

In order to solve the above-mentioned problems, the present invention provides a DRAM circuit having a memory cell composed of a series circuit of a switching transistor and an information storage capacitor, and a logic circuit identical to the DRAM circuit. In a mixed-type semiconductor integrated circuit device mixed with a semiconductor substrate, the logic circuit has substantially the same structure as the information storage capacitor element inside the logic circuit or outside the logic circuit and is used in the logic circuit. A capacitor is provided. Preferably, the information storage capacitor element is constructed by a trench formed in the depth direction from the main surface of the semiconductor substrate, and a lower electrode, a dielectric film, and an upper electrode formed along the inner wall of the trench. The capacitance element used in the logic circuit is formed with a trench capacitor structure having the same structure as the information storage capacitance element. The capacitive element thus configured is a smoothing capacitor,
Alternatively, it is used as a capacitor for constructing a logic circuit. Further, the mixed semiconductor integrated circuit device is preferably an ASIC.

In the hybrid semiconductor integrated circuit device thus configured, the capacitance used in the logic circuit is the same as that of the information storage capacitor formed with the optimum structure for maximizing the charge storage amount. Since the element is constructed, the capacitance element can be easily formed, and the area occupied by the capacitance element can be reduced. In addition, by adopting the trench capacitor structure for the capacitance element, the charge storage amount can be secured in the depth direction of the semiconductor substrate, and the area occupied by the capacitance element itself can be reduced as much as possible. Therefore, the degree of integration of the mixed semiconductor integrated circuit device can be improved.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below. FIG. 4 shows the first embodiment of the present invention.
FIG. 5 is a layout diagram of a mixed-type semiconductor integrated circuit device according to an embodiment. Mixed semiconductor integrated circuit device 1 shown in FIG.
Is an ASIC, which is configured by a semiconductor chip having a square planar shape. A plurality of external connection terminals 2 are arranged in a peripheral portion along each side of the mixed semiconductor integrated circuit device 1. The external connection terminal 2 includes an external connection terminal for an input signal, an external connection terminal for an output signal or an external connection terminal for an input / output signal, an external connection terminal for a circuit reference power supply, and an external connection terminal for a circuit operation power supply. included. Inside the external connection terminals 2, a plurality of interface circuits (buffer circuits) 3 are arranged along the arrangement of the external connection terminals 2. The interface circuit 3 includes an input interface circuit, an output interface circuit, and an input / output interface circuit.

[0011] Inside the interface circuit 3,
A DRAM circuit 4 is provided at the center of the mixed type semiconductor integrated circuit device 1.
The DRAM circuit 4 and the logic circuit 5 are mixed on one chip. The DRAM circuit 4 can write information, store information, and read information at any time. The logic circuit 5 performs processing on, for example, an input command and outputs the processing result.

FIG. 1 is a sectional structural view of a memory cell of a DRAM circuit 4 and a basic cell for constructing logic of a logic circuit 5, and FIG.
Is a plan view of a memory cell, and FIG. 3 is a plan view of a basic cell. As shown in FIG. 1, the mixed semiconductor integrated circuit device 1 includes a semiconductor substrate 10 made of an n-type single crystal silicon substrate. In the DRAM circuit 4, a p-type well region 11 is formed in a main surface portion of a semiconductor substrate 10, and the p-type well region 1 is formed.
1 is supplied with a circuit reference power supply Vss, for example, 0V. In the logic circuit 5, the main surface of the semiconductor substrate 10 is provided with a DRAM.
A p-type well region 15 formed independently and optimally is formed in a manufacturing process different from the p-type well region 11 formed in the circuit 4, and an n-type well is further formed on a main surface portion of the p-type well region 15. Region 16 is formed. p-type well region 15
Is supplied with a circuit reference power supply Vss, for example, 0 V, and the n-type well region 16 is supplied with a circuit operation power supply Vcc, for example, 3.3 V. That is, the logic circuit 5 is formed in a double well structure. This logic circuit 5 has a complementary MISFET (Meta
l Insulator Semiconductor Field Effect Transisto
The basic cells formed in r) are arranged.

In FIG. 1, as shown on the left and in FIG.
In the circuit 4, a plurality of memory cells formed of a series circuit of a switching transistor and an information storage capacitor are arranged in a matrix. A memory cell that stores 1-bit information is arranged at the intersection of word line 21WL and data line 31DL, and is electrically connected to each of word line 21WL and data line 31DL.

The information storage capacitance element of the memory cell includes a trench 12 formed in the p-type well region 11, an electrode (lower electrode) formed in the p-type well region 11, and a dielectric film 13.
And an electrode (upper electrode) 14. That is, a trench capacitor structure is adopted as the information storage capacitor. The trench 12 is a pore formed by being dug down in the depth direction from the main surface of the p-type well region 11. The semiconductor substrate 10 has a minimum occupied area due to the minimum processing dimension, and
Anisotropic etching using RIE is used to form the trench 12 in order to secure a sufficient charge accumulation amount in the depth direction of the trench. The dielectric film 13 is formed on the surface of the p-type well region 11 along the trench 12. As the dielectric film 13, for example, a single-layer film of a silicon oxide film or a composite film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are overlapped is used. The electrode 14 is buried inside the trench 12 via the dielectric film 13. As the electrode 14, for example, a polycrystalline silicon film doped with an n-type impurity for ensuring conductivity is used.

The switching transistor has an n-channel in a region surrounded by an insulating film 17 for element isolation.
It is composed of MISFET. The inter-element isolation insulating film 17 is formed by a shallow groove and an insulating film buried in the groove, and the inter-element isolation insulating film 17 has an STI (Shallow Trench Isolation).
n) The structure is adopted.

The n-channel MISFET has a p-type well region 11
, A gate insulating film 20, a gate electrode 21, and a pair of n-type semiconductor regions 22 used as a source region and a drain region. Gate insulating film 20 is formed of, for example, a silicon oxide film formed on the surface of p-type well region 11. The gate electrode 21 is formed on the surface of the gate insulating film 20.
For example, a single-layer film of a polycrystalline silicon film doped with an impurity for ensuring conductivity is used. Also, the gate electrode 21
In order to reduce the resistance value and increase the signal transmission speed, a composite film (polycide film) formed of a polycrystalline silicon film and a silicide film laminated on the surface thereof is used. The gate electrode 21 is integrally formed with the gate electrode 21 of the switching transistor of another memory cell adjacent in the gate width direction (formed in the same manufacturing process),
These gate electrodes 21 form word lines 21WL extending in the gate width direction. The pair of n-type semiconductor regions 22 are formed on the main surface of the p-type well region 11 by self-alignment with the gate electrode 21. The pair of n-type semiconductor regions 22 have a low impurity concentration on the channel formation region side, for example.
The n-channel MISFET has an LDD (Lightly Doped Drain) structure.

One n-type semiconductor region 22 of the n-channel MISFET is electrically connected to an electrode 14 of an information storage capacitor through a memory cell wiring (suffacestrap) 23.
The wiring 23 in the memory cell is formed of, for example, a polycrystalline silicon film doped with an impurity for ensuring conductivity. n channel
The other n-type semiconductor region 22 of the MISFET is a data line 31DL.
Is electrically connected to The mixed-type semiconductor integrated circuit device 1 according to the present embodiment employs a three-layer wiring structure.
The data line 31DL is formed in the first wiring layer. The data line 31DL is formed mainly of, for example, an aluminum alloy film. This data line 31DL is connected to the interlayer insulating film 30
And is connected to the n-type semiconductor region 22 through a connection hole formed in the interlayer insulating film 30.

The DRAM circuit 4 composed of such memory cells is designed in advance as a DRAM macro cell and stored as fixed macro cell information (circuit components) in a CAD database. When designing a logic circuit using CAD, the macro cell information stored in the database is read out to create logic circuit information in which each of the DRAM circuit 4 and the logic circuit 5 is laid out. Created. Then, using the manufacturing mask, the mixed semiconductor integrated circuit device 1 shown in FIG. 4 described above is manufactured.

On the other hand, the basic cell of the logic circuit 5 is shown in FIG.
As shown in the middle and right sides and the right side in FIG.
It consists of. The n-channel MISFET of the complementary MISFET has a p-channel MISFET in a region surrounded by an insulating film 17 for element isolation.
It is formed in the mold well region 15. n-channel MISFET is p
A channel formation region formed by the mold well region 15, a gate insulating film 20, a gate electrode 21, and a pair of n-type semiconductor regions 22 used as a source region and a drain region. This n-channel MISFET has basically the same structure as that of the n-channel MISFET which is the switching transistor of the memory cell described above, and is formed in the same manufacturing process.

Similarly, the p-channel MISFET of the complementary MISFET is formed in the n-type well region 16 in a region surrounded by the element isolation insulating film 17. p-channel MISFET
Comprises a channel forming region formed by the n-type well region 16, a gate insulating film 20, a gate electrode 21, and a pair of p-type semiconductor regions 24 used as a source region and a drain region. This p-channel MISFET has basically the same structure as the n-channel MISFET, although the manufacturing process for forming the p-type semiconductor region 24 is different.

In the logic circuit 5, a three-layer wiring 3
1, 34 and 37 are used and the connections are made. Wiring 3
Numeral 1 is formed on the surface of the interlayer insulating film 30 and is used as a first layer wiring. This wiring 31 is basically used for connection between transistors in the basic cell, and
Is electrically connected to the transistor directly through the connection hole formed in the transistor. The wiring 34 is formed on the surface of the interlayer insulating film 32 and is used as a second-layer wiring. This wiring 34
Basically extend in the row direction (vertical direction in FIG. 3) and connect the basic cells. Electrical connection between the wiring 34 and the wiring 31 thereunder is made through a stud electrode 33 buried in an interlayer insulating film 32. As the stud electrode 33, for example, a tungsten electrode is used. Wiring 3
Reference numeral 7 is formed on the surface of the interlayer insulating film 35 and is used as a third-layer wiring. The wiring 37 basically extends in the column direction (horizontal direction in FIG. 3) and connects the basic cells.
The electrical connection between the wiring 37 and the wiring 34 thereunder is made through a stud electrode 36 embedded in an interlayer insulating film 35. As the stud electrode 33, for example, a tungsten electrode is used. The wirings 31, 34, and 37 are all formed of wiring mainly composed of an aluminum alloy film. A final passivation film 38 is formed on the wiring 37 formed on the uppermost layer.

At a position close to the n-channel MISFET in the basic cell, a p-type semiconductor region 24p for supplying a circuit reference power supply Vss to the p-type well region 15 is formed. A circuit reference power supply Vss is supplied to the p-type semiconductor region 24p through the wiring 31 and the like. Similarly, at a position close to the p-channel MISFET, n for supplying the circuit operation power supply Vcc to the n-type well region 16 is used.
The type semiconductor region 22n is configured. n-type semiconductor region 22
A circuit operation power supply Vcc is supplied to n through a wiring 31 or the like.

In the mixed type semiconductor integrated circuit device 1 thus configured, as shown in the central part in FIG. 1 and on the left side in FIG.
A capacitor element cell (C-cell) is arranged around
The capacitance element cell forms a capacitance element used in the logic circuit 5. Capacitive elements composed of capacitive element cells are DRAM
It is formed with a trench capacitor structure having substantially the same structure as the information storage capacitance element constituting the memory cell of the circuit 4. That is, the capacitance element cell itself is in the p-type well region 11.
The capacitor is formed by a trench 12 formed in the p-type well region 11, an electrode formed by the p-type well region 11, a dielectric film 13 and an electrode 14. This capacitive element has a small occupied area and can secure a charge accumulation amount in the depth direction of the semiconductor substrate 10. As will be described later, the manufacturing process of the mixed-type semiconductor integrated circuit device 1 incorporates the manufacturing process of the information storage capacitor element by mixing the DRAM circuits 4. Is formed. That is, the respective manufacturing steps of the capacitive element and the information storage capacitive element are the same manufacturing steps. And
Three-layer wirings 31, 34 and 37 used in the logic circuit 5 are used for the connection of the capacitance element, that is, the connection in the capacitance element cell and the connection between the capacitance element cell and other basic cells.

A p-type semiconductor region 24p for supplying a circuit reference power supply Vss to the p-type well region 11 is formed at a position close to the capacitance element in the capacitance element cell. A circuit reference power supply Vss is supplied to the p-type semiconductor region 24p through the wiring 31 and the like.

As shown in FIGS. 1 and 3, the p-type well region 11 of the capacitive element cell and the p-type well region 15 of the basic cell are provided.
Between the p-type semiconductor region 24p and the wirings 31, 34, 37
Are electrically connected (connected) through each of them, and the electrode 14 of the capacitance element of the capacitance element cell is electrically connected to the circuit operating power supply Vcc, whereby the capacitance element of the capacitance element cell functions as a smoothing capacitor. Noise can be reduced.

The capacitance element cells are designed in advance as one macro cell and stored as fixed macro cell information in a CAD database, similarly to the aforementioned DRAM macro cell.
When designing a logic circuit using CAD, the capacitor cell information stored in the database is read, and the capacitor cell is laid out together with the DRAM circuit 4 and the logic circuit 5.

Next, the above-mentioned mixed type semiconductor integrated circuit device 1
Will be described with reference to FIGS. 5 to 8. 5 to 8 are cross-sectional structural views of the mixed semiconductor integrated circuit device 1 shown for each manufacturing process for explaining the manufacturing method.

(1) First, in the semiconductor substrate 10, the DR
A p-type well region 11 is formed in each of the formation region of the AM circuit 4 and the formation region of the logic circuit 5 in the capacitor element cell formation region. Further, a p-type well region 15 and an n-type well region 16 are formed in the basic cell formation region in the formation region of the logic circuit 5. Next, as shown in FIG. 5, a capacitor for information storage is formed in the p-type well region 11 in the formation region of the DRAM circuit 4 and is formed in the p-type well region 11 in the formation region of the logic circuit 5 by the same manufacturing process. A capacitor is formed. Each of the information storage capacitor element and the capacitor element is formed by forming a trench 12, forming a dielectric film 13 along the inner wall of the trench 12, and thereafter embedding an electrode 14 inside the trench 12. .

(2) Next, an insulating film 17 for element isolation is formed. Thereafter, as shown in FIG. 6, an n-channel MISFET as a switching transistor is formed in a region where the DRAM circuit 4 is formed, and an n-channel MISFET and a p-channel MISFET are formed in a region where the logic circuit 5 is formed.

(3) Next, after each of the interlayer insulating film 30 and the connection hole is formed, as shown in FIG. 7, a data line 31 is formed in a formation region of the DRAM circuit 4 and a logic circuit 5 is formed. A wiring 31 serving as a first-layer wiring is formed in the region. When the formation of the data line 31DL is completed, the DRAM circuit 4 is almost completed. In the formation region of the logic circuit 5, the wiring 31 is basically used for connection in a basic cell and connection in a capacitor element cell.

(4) Next, as shown in FIG. 8, the interlayer insulating film 32, the connection hole, the stud electrode 33, the wiring 34 serving as the second layer wiring, the interlayer insulating film 35, the connection hole, the stud electrode 3
6. Each of the wirings 37 to be the third layer wiring is sequentially formed. The wirings 34 and 37 are used for connection between basic cells, connection between capacitive element cells, connection between capacitive element cells and basic cells, and the like.

Then, as shown in FIG. 1 described above, by forming the final passivation film 38, the mixed type semiconductor integrated circuit device 1 according to the present embodiment is completed.

As described above, in the mixed-type semiconductor integrated circuit device 1 according to the present embodiment, the information storage capacitance element of the DRAM circuit 4 formed with the optimum structure for maximizing the charge storage amount. Since the capacitance element used in the logic circuit 5 is constructed by the same structure as that described above, the capacitance element can be easily formed and the area occupied by the capacitance element can be reduced. In addition, by adopting the trench capacitor structure for the capacitance element, the charge storage amount can be secured in the depth direction of the semiconductor substrate 10, and the area occupied by the capacitance element itself can be reduced as much as possible. Therefore, the degree of integration of the mixed semiconductor integrated circuit device 1 can be improved.

(Second Embodiment) In the present embodiment, a case where a large-capacity capacitive element is constructed in the mixed semiconductor integrated circuit device 1 will be described. FIG. 9 shows the second embodiment of the present invention.
FIG. 5 is a plan view of a main part of the mixed-type semiconductor integrated circuit device according to the embodiment and showing a capacitive element cell. As shown in FIG. 9, when a large capacity is required, a capacitor element cell (C-cell) in which a plurality of capacitors are electrically connected in parallel is constructed in the mixed semiconductor integrated circuit device 1. One capacitive element of the capacitive element cell has basically the same structure as a memory cell of the DRAM circuit 4 which can store 1-bit information. That is, as shown in FIG. 1 described above, the capacitive element is formed by one trench 12, an electrode formed by the p-type well region 11, the dielectric film 13, and the electrode 14 buried in the trench 12. The capacitive elements are regularly arranged in a matrix.

One switching transistor is electrically connected in series to one capacitance element. This switching transistor is formed by an n-channel MISFET. n
The gate electrode 21 of the channel MISFET is shared wirings 31 and 34
Are connected to the circuit operating power supply Vcc, and the n-channel MISFET is always maintained in a conductive state. n channel
The other n-type semiconductor region 22 (see FIG. 1) of the MISFET is connected to the circuit operation power supply Vcc or the logic circuit 5 through each of the shared wirings 31 and 34. Since the n-channel MISFET is always kept conductive, the electrode 14
Is connected to the circuit operating power supply Vcc or the logic circuit 5. As shown on the left side in FIG. 9, the p-type well region 11, that is, the other electrode of the capacitive element is connected to the circuit reference power supply Vs.
Since s is supplied, when the circuit operating power supply Vcc is connected to the electrode 14, the capacitive element is used as a smoothing capacitor as described in the first embodiment to reduce power supply noise. it can. When the logic circuit 5 is connected to the electrode 14, the capacitance element functions as a capacitance element incorporated in the logic circuit of the logic circuit 5. As a logic circuit incorporating a relatively large-capacity capacitive element, for example, there is a PLL (Phase Locked Loop) circuit.

FIG. 10 is a plan view showing an arrangement of basic cells for constructing a PLL circuit and an arrangement of capacitive element cells incorporated in the PLL circuit. The circuit configuration of a PLL circuit is generally known, and the circuit configuration changes according to the purpose of use. Therefore, a detailed description of the circuit configuration is omitted, but basically a plurality of basic cells (Basic-cell ). A plurality of basic cells are regularly arranged in the row direction in the logic circuit 5 to form a basic cell row, and a wiring area is secured between this basic cell row and another adjacent basic cell row. As described above, the wiring 34 formed in the second wiring layer and the wiring 37 formed in the third wiring layer are arranged in the wiring region.

As shown in FIG. 10, the capacitance element cells shown in FIG. 9 are arranged in place of a predetermined basic cell in the vicinity where a PLL circuit is constructed. Although it differs depending on the PLL circuit to be constructed, in this embodiment, the capacitance element is 500p
It is set to the capacitance value of F-1.5nF and builds a low-pass filter.

FIG. 11 is a plan view showing another example of an arrangement of basic cells for constructing a PLL circuit and an arrangement of capacitive element cells incorporated in the PLL circuit. The capacitive element cells can be arranged in the wiring area between the basic cell rows instead of replacing the basic cells. The wiring region is originally used for connection between the basic cells. However, since the main surface of the semiconductor substrate 10 is under the wiring layer of the wiring region and is an unused region where no element is formed, the wiring region is not used. If a capacitor element cell is arranged, the semiconductor substrate 1
0 can be effectively used, and the arrangement of the capacitor element cells can be relatively freely performed.

As described above, in the hybrid semiconductor integrated circuit device 1 according to the present embodiment, the same effects as those obtained in the hybrid semiconductor integrated circuit device 1 according to the first embodiment described above. Is obtained. Further, by disposing the capacitor element cells in the wiring region, the semiconductor substrate 10 can be effectively used, and the integration degree of the mixed semiconductor integrated circuit device 1 can be further improved.

(Third Embodiment) In the present embodiment, in the mixed semiconductor integrated circuit device 1 according to the above-described second embodiment, a large-capacity capacitive element is constructed in an empty area of the semiconductor substrate 10. The following describes the case. FIGS. 12 to 14 are plan views of a main part of a mixed type semiconductor integrated circuit device according to a third embodiment of the present invention, which is a capacitive element cell.

A mixed type semiconductor integrated circuit device 1 shown in FIG.
Is to dispose the capacitor cell shown in FIG. 9 just below the external connection terminal 2. The external connection terminal 2 is usually formed in the final wiring layer, that is, the third wiring layer in this embodiment (formed by the wiring 37), and immediately below the external connection terminal 2 is an empty area where no element is formed. Therefore, the capacitor element cells are arranged by utilizing the empty area. External connection terminal 2
Is usually formed with a large area of, for example, 150-250 μm on one side in consideration of a bonding area and a bonding deviation between a bonding wire and a bump electrode, and is disposed immediately below the external connection terminal 2. A large capacitance value can be secured for the capacitor.

A mixed semiconductor integrated circuit device 1 shown in FIG.
Places the capacitive element cell shown in FIG. 9 in the unused interface circuit 3. The circuit operation power supply wiring (Vcc) is provided on the interface circuit 3 by a final wiring layer, that is, a wiring 37 formed in a third wiring layer in the present embodiment.
Since the wiring) and the circuit reference power supply wiring (Vss wiring) are arranged, connection between each of the circuit operation power supply wiring and the circuit reference power supply wiring and the capacitance element of the capacitance element cell can be easily performed. That is, a smoothing capacitor can be easily realized.

A mixed semiconductor integrated circuit device 1 shown in FIG.
In the figure, the capacitor element cell shown in FIG. 9 is arranged in a dead space between the interface circuits 3 at a corner portion of a semiconductor chip (corner portion of a semiconductor chip). As in the hybrid semiconductor integrated circuit device 1 shown in FIG. 13, a smoothing capacitor can be easily realized.

As described above, in the mixed semiconductor integrated circuit device 1 according to the present embodiment, the same effects as those obtained by the mixed semiconductor integrated circuit device 1 according to the first embodiment described above. Is obtained. Further, by arranging the capacitor element cell directly under the external connection terminal 2, in the unused interface circuit 3, or in the dead space, the semiconductor substrate 10 can be effectively used, and the integration of the mixed type semiconductor integrated circuit device 1 can be achieved. The degree can be further improved. further,
Since the capacitor element cell can be easily connected to the power supply wiring,
For example, a smoothing capacitor can be easily realized.

The present invention is not limited to the above embodiment. For example, when the memory cell of the DRAM circuit 4 includes a capacitor for storing information having a stacked capacitor structure, the logic circuit 5 includes a capacitor having a stacked capacitor structure.

The present invention also relates to an ASIC employing a standard cell system and an AS employing an embedded array system.
Applicable to any of ICs.

[0047]

According to the present invention, it is possible to provide a mixed type semiconductor integrated circuit device which can easily realize a capacitance element used in a logic circuit, reduce the area occupied by the capacitance element, and improve the degree of integration. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a mixed-type semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the DRAM circuit.

FIG. 3 is a plan view of a logic circuit.

FIG. 4 is a layout diagram of a mixed type semiconductor integrated circuit device.

FIG. 5 is a sectional structural view in a first manufacturing step for explaining the method for manufacturing a mixed semiconductor integrated circuit device.

FIG. 6 is a sectional structural view in a second manufacturing step.

FIG. 7 is a sectional structural view in a third manufacturing step.

FIG. 8 is a sectional structural view in a fourth manufacturing step.

FIG. 9 is a plan view of a main part of a mixed-type semiconductor integrated circuit device according to a second embodiment of the present invention, which is a capacitive element cell.

FIG. 10 is a plan view showing an arrangement of basic cells forming a PLL circuit and an arrangement of capacitive element cells incorporated in the PLL circuit.

FIG. 11 is a plan view showing another example of an arrangement of basic cells for constructing a PLL circuit and an arrangement of capacitive element cells incorporated in the PLL circuit.

FIG. 12 is a plan view of a main part of a mixed-type semiconductor integrated circuit device according to a third embodiment of the present invention, showing a capacitive element cell;

FIG. 13 is a plan view of a capacitor cell showing another example.

FIG. 14 is a plan view of a capacitor cell showing another example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Mixed-type semiconductor integrated circuit device 4 DRAM circuit 5 Logic circuit 10 Semiconductor substrate 11, 15, 16 Well area 12 Trench 13 Dielectric film 14 Electrode 20 Gate insulating film 21 Gate electrode 21WL Word line 22, 22n, 24, 24p Semiconductor area 31, 34, 37 Wiring 31DL Word line

Claims (5)

[Claims] 1. A hybrid semiconductor integrated circuit device in which a logic circuit and a dynamic random access memory circuit having a memory cell formed of a series circuit of a switching transistor and an information storage capacitor are mixed on the same semiconductor substrate. A memory element having substantially the same structure as that of the information storage capacitor of the memory cell and used in the logic circuit, inside or outside the logic circuit. Mixed type semiconductor integrated circuit device. 2. The information storage capacitive element of the memory cell includes a trench formed in a depth direction from a main surface of the semiconductor substrate, a lower electrode formed along an inner wall of the trench, a dielectric film, 2. A capacitor formed of a trench capacitor structure formed with an upper layer electrode, and the capacitor element used in the logic circuit is formed by a trench capacitor structure having the same structure as the information storage capacitor element. 6. A mixed semiconductor integrated circuit device according to claim 1. 3. The capacitance element is used as a smoothing capacitor having one electrode connected to a circuit reference power supply and the other electrode connected to a circuit operation power supply.
Or a mixed type semiconductor integrated circuit device according to claim 2. 4. The mixed-type semiconductor integrated circuit device according to claim 1, wherein said capacitance element is used as a capacitance element for constructing a circuit of said logic circuit. 5. The mixed semiconductor integrated circuit device according to claim 1, wherein said mixed semiconductor integrated circuit device is a semiconductor integrated circuit device for specific use.