CN110739299A - Semiconductor package - Google Patents

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Publication number
CN110739299A
CN110739299A CN201910376198.6A CN201910376198A CN110739299A CN 110739299 A CN110739299 A CN 110739299A CN 201910376198 A CN201910376198 A CN 201910376198A CN 110739299 A CN110739299 A CN 110739299A
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China
Prior art keywords
integrated circuit
circuit chip
semiconductor package
cells
disposed
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Granted
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CN201910376198.6A
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Chinese (zh)
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CN110739299B (en
Inventor
金容勳
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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  • General Physics & Mathematics (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides semiconductor package, the semiconductor package including a connection member having a surface and a second surface opposite to each other and including a redistribution layer, an integrated circuit chip disposed on the surface of the connection member and including a plurality of cells, at least capacitors on the surface of the connection member and proximate to the integrated circuit chip, an encapsulant on the surface of the connection member and encapsulating the integrated circuit chip and the at least capacitors, wherein the plurality of cells include core power cells selected from the group consisting of a central processing unit, a graphics processing unit, and an artificial intelligence unit, at least of the core power cells are disposed proximate to an edge of the integrated circuit chip, and the at least capacitors are disposed proximate to the edge of the integrated circuit chip.

Description

Semiconductor package
This application claims the benefit of priority of korean patent application No. 10-2018-0084572, filed on 20.7.2018, to the korean intellectual property office, the disclosure of which is incorporated herein by reference in its entirety.
Technical Field
The present application relates to semiconductor packages.
Background
The main focus of technological development of semiconductor chips has been on reducing the size of components, and with the increase in demand for small semiconductor chips and the like, there has been a demand in the field of packaging for semiconductor packages that are smaller in size while being capable of having multiple pins.
Such semiconductor packages include packages that include large-scale integrated circuit (LSI) chips, also referred to as microcontroller units (MCUs), microprocessor units (MPUs), or systems on a chip (SOCs). such semiconductor packages may be used generally for portable electronic devices such as netbook PCs, tablet PCs, smart phones, and portable video game machines .
Disclosure of Invention
The aspect of the present disclosure may provide a semiconductor package with improved Power Integrity (PI) by optimizing the internal design of the semiconductor chip and the location of the capacitors.
According to aspect of the present disclosure, a semiconductor package includes a connection member having a surface and a second surface opposite to each other and including a redistribution layer, an integrated circuit chip disposed on the surface of the connection member, having connection electrodes connected to the redistribution layer, and being configured by a plurality of cells, at least capacitors disposed on the surface of the connection member in proximity to the integrated circuit chip, an encapsulant disposed on the surface of the connection member and encapsulating the integrated circuit chip and the at least capacitors, wherein the plurality of cells includes core power cells selected from the group consisting of a Central Processing Unit (CPU), a Graphic Processing Unit (GPU), and an artificial intelligence unit (AI), at least of the core power cells being disposed adjacent to an edge of the integrated circuit chip, and the at least capacitors being disposed adjacent to the edge of the integrated circuit chip.
According to another aspect of the present disclosure, a kind of semiconductor package includes a connection member having a 0 th surface and a second surface opposite to each other and including a redistribution layer, an integrated circuit chip disposed on the th surface of the connection member, having a connection electrode connected to the redistribution layer, and being configured by a plurality of cells, a plurality of capacitors disposed on the th surface of the connection member to be adjacent to the integrated circuit chip, an encapsulant disposed on the th surface of the connection member and encapsulating the integrated circuit chip and the plurality of capacitors, wherein the plurality of cells include a th cell having a th power consumption and a second cell having a second power consumption lower than the th power consumption, the th cell is disposed adjacent to an edge of the integrated circuit chip, the second cell is disposed on the integrated circuit chip more inward than the th cell, and the plurality of capacitors is disposed adjacent to the edge of the integrated circuit chip.
According to another aspect of the present disclosure, a semiconductor package includes an integrated circuit chip including a th core power cell and a th other cell disposed adjacent to a 0 th edge of the integrated circuit chip, the integrated circuit chip being disposed on a th surface of a connection member, a capacitor disposed on the th surface of the connection member and disposed adjacent to the th edge of the integrated circuit chip, and an encapsulant disposed on the th surface of the connection member and encapsulating at least portion of each of the integrated circuit chip and the capacitor, wherein the connection member includes a wiring layer directly connecting the th core power cell and the capacitor.
Drawings
The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
fig. 1 is a schematic block diagram illustrating an example of an electronic device system;
fig. 2 is a schematic perspective view showing an example of an electronic device;
fig. 3A and 3B are schematic sectional views showing states of a fan-in type semiconductor package before and after packaging;
fig. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in type semiconductor package;
fig. 5 is a schematic sectional view showing a case where a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device;
fig. 6 is a schematic cross-sectional view showing a case where a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device;
fig. 7 is a schematic sectional view showing a fan-out type semiconductor package;
fig. 8 is a schematic sectional view showing a case where a fan-out type semiconductor package is mounted on a main board of an electronic device;
fig. 9 is a schematic cross-sectional view of a semiconductor package according to an exemplary embodiment in the present disclosure;
fig. 10 is a plan view showing the semiconductor package taken along line I-I' in fig. 9;
fig. 11 is an enlarged sectional view showing a portion a of the semiconductor package shown in fig. 9;
FIGS. 12A and 12B are block diagrams depicting layout variations of various cells of an integrated circuit chip;
fig. 13 is a schematic cross-sectional view illustrating a semiconductor package according to exemplary embodiments in the present disclosure, and
fig. 14 is a plan view of the semiconductor package taken along line II-II' in fig. 13.
Detailed Description
Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the drawings, the shape, size, and the like of components may be exaggerated or reduced for clarity.
Here, the lower side, the lower portion, the lower surface, and the like are used to indicate a direction toward the mounting surface of the fan-out type semiconductor package with respect to the cross section of the drawing, and the upper side, the upper portion, the upper surface, and the like are used to indicate a direction opposite to the direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above.
It will be understood that when an element is referred to as being "" and "second," the element is not limited thereto, the terms "," "second," and the like, may be used merely for the purpose of distinguishing the element from other elements, and may not limit the order or importance of the elements.
For example, unless an opposite or contradictory description is provided herein, elements described in a particular exemplary embodiment may be understood as descriptions relating to another exemplary embodiment even if not described in another exemplary embodiment.
The terminology used herein is for the purpose of describing example embodiments only and is not intended to be limiting of the disclosure. In this case, the singular form includes the plural form unless the context indicates otherwise.
Electronic deviceDevice for measuring the position of a moving object
Fig. 1 is a schematic block diagram illustrating an example of an electronic device system.
Referring to fig. 1, a main board 1010 may be accommodated in the electronic device 1000. Motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc. physically and/or electrically connected thereto. These components may be connected to other components, which will be described below, by various signal lines 1090.
The chip related component 1020 may include: a memory chip such as a volatile memory (e.g., a Dynamic Random Access Memory (DRAM)), a nonvolatile memory (e.g., a Read Only Memory (ROM)), a flash memory, or the like; an application processor chip such as a central processing unit (e.g., Central Processing Unit (CPU)), a graphics processor (e.g., Graphics Processing Unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and logic chips such as analog-to-digital converters (ADCs), Application Specific Integrated Circuits (ASICs), and the like. However, the chip-related component 1020 is not limited thereto, but may also include other types of chip-related components. Further, the chip related components 1020 may be combined with each other.
Network-related components 1030 may include components designated to operate in accordance with protocols such as wireless fidelity (Wi-Fi) (institute of electrical and electronics engineers (IEEE)802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), evolution data optimized (Ev-DO), high speed packet access + (HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), Enhanced Data GSM Environment (EDGE), global system for mobile communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless and wired protocols designated after the above-mentioned protocols, however, network-related components 1030 are not limited thereto, but may also include components designated to operate in accordance with various other wireless standards or wired protocols, or wired standards or protocols, in addition, network-related components 1030 may be combined with one another of the above-mentioned chip-related components 1020 .
Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. however, other components 1040 are not so limited and may also include passive components for various other purposes, etc. furthermore, other components 1040 may be combined with one another with the above-described chip-related component 1020 or network-related component 1030 .
Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and/or electrically connected to the motherboard 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a Compact Disc (CD) drive (not shown), a Digital Versatile Disc (DVD) drive (not shown), and so forth. However, these other components are not limited thereto, but may also include other components for various purposes according to the type of the electronic device 1000 and the like.
The electronic device 1000 may be a smart phone, a Personal Digital Assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game, a smart watch, an automotive component, and so forth. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.
Fig. 2 is a schematic perspective view showing an example of the electronic device.
Referring to fig. 2, a semiconductor package may be used for various purposes in various electronic devices as described above, for example, a motherboard 1110 may be accommodated in a main body 1101 of a smart phone 1100, and various electronic components 1120 may be physically or electrically connected to the motherboard 1110, in addition, other components (such as a camera 1130) that may or may not be physically and/or electrically connected to the motherboard 1110 may be accommodated in the main body 1101, of the electronic components 1120 may be chip-related components, and the semiconductor package 100 may be, for example, an application processor in the chip-related components, but is not limited thereto.
Semiconductor package
Typically, a large number of microelectronic circuits are integrated in a semiconductor chip. However, the semiconductor chip itself may not be used as a finished semiconductor product, and may be damaged by external physical or chemical impact. Therefore, the semiconductor chip cannot be used in an exposed state, but is packaged and used in an electronic device or the like in a packaged state.
The reasons why the semiconductor package is required are: with respect to the electrical connection, there is a difference in circuit width between the semiconductor chip and the main board of the electronic device. In detail, in the case of a semiconductor chip, the size of the connection pads and the pitch between the connection pads are very fine, whereas in the case of using a main board in an electronic device, the size of the component mounting pads and the pitch between the component mounting pads are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the main board, and a packaging technique for alleviating the difference in circuit width between the semiconductor chip and the main board is required.
Semiconductor packages manufactured by such a packaging technique may be classified into fan-in type semiconductor packages and fan-out type semiconductor packages according to their structures and intended purposes.
Hereinafter, a fan-in type semiconductor package and a fan-out type semiconductor package will be described in more detail with reference to the accompanying drawings.
Fan-in type semiconductor package
Fig. 3A and 3B are schematic sectional views showing states of a fan-in type semiconductor package before and after being packaged, and fig. 4 is a schematic sectional view showing a packaging process of the fan-in type semiconductor package.
Referring to fig. 3A, 3B, and 4, the semiconductor chip 2220 may be, for example, an Integrated Circuit (IC) in a bare state, and includes a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads 2222 formed on surfaces of the body 2221 and including a conductive material such as aluminum (Al), or the like, and a passivation layer 2223, which is an oxide film, a nitride film, or the like, formed on surfaces of the body 2221 and covering at least portions of the connection pads 2222.
Accordingly, the connection members 2240 may be formed on the semiconductor chip 2220 to redistribute the connection pads 2222 according to the size of the semiconductor chip 2220, the connection members 2240 may be formed by forming an insulation layer 2241 on the semiconductor chip 2220 using an insulation material such as a photo dielectric (PID) resin, then forming via holes 2243h to open the connection pads 2222, and then forming wiring patterns 2242 and vias 2243, then, a passivation layer 2250 to protect the connection members 2240 may be formed, openings 2251 may be formed, then an under bump metal layer 2260 may be formed, and the like, and as a result, a fan-in type semiconductor package 2200 including, for example, the semiconductor chip 2220, the connection members 2240, the passivation layer 2250, and the under bump metal layer 2260 may be manufactured through the series processes as described above.
As described above, the fan-in type semiconductor package may be in the form of a package in which all connection pads (e.g., input/output (I/O) terminals) of the semiconductor chip are disposed inside the semiconductor chip. In addition, the fan-in type semiconductor package may have satisfactory electrical characteristics and may be manufactured inexpensively. Accordingly, many components mounted in the smart phone have been manufactured in a fan-in type semiconductor package form, and in particular, many components mounted in the smart phone have been developed to achieve rapid signal transmission while having a compact size.
However, the fan-in type semiconductor package has a significant spatial limitation since it requires all I/O terminals to be disposed inside the semiconductor chip. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a small size. In addition, due to the above disadvantages, it may not be possible to directly mount and use the fan-in type semiconductor package on the main board of the electronic device, because: even when the size of the I/O terminals of the semiconductor chip and the pitch between the I/O terminals of the semiconductor chip are increased by the redistribution process, the size of the I/O terminals of the semiconductor chip and the pitch between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in type semiconductor package on the main board of the electronic device.
Fig. 5 is a schematic cross-sectional view showing a case where a fan-in type semiconductor package is mounted on an interposer substrate and is finally mounted on a main board of an electronic device, and fig. 6 is a schematic cross-sectional view showing a case where a fan-in type semiconductor package is embedded in an interposer substrate and is finally mounted on a main board of an electronic device.
Referring to fig. 5, in the fan-in type semiconductor package 2200, the connection pads 2222 (i.e., I/O terminals) of the semiconductor chip 2220 may be redistributed again through the interposer 2301, and then, the fan-in type semiconductor package 2200 may be finally mounted on the main board 2500 of the electronic device while being mounted on the interposer 2301. In this case, the low melting point metal or alloy balls 2270 or the like may be fixed by the underfill resin 2280 or the like, and the outside of the fan-in type semiconductor package 2200 may be covered with the encapsulant 2290 or the like. Alternatively, referring to fig. 6, the fan-in type semiconductor package 2200 may be embedded in a separate interposer substrate 2302, connection pads 2222 (which are I/O terminals) of the semiconductor chip 2220 may be redistributed again through the interposer substrate 2302 while the fan-in type semiconductor package 2200 is embedded in the interposer substrate 2302, and the fan-in type semiconductor package 2200 may be finally mounted on the main board 2500 of the electronic device.
As described above, it may be difficult to directly mount and use the fan-in type semiconductor package on the main board of the electronic device. Accordingly, the fan-in type semiconductor package may be used by being first mounted on a separate interposer and then mounted on a main board of an electronic device through a packaging process. Alternatively, the fan-in type semiconductor package may be used by being mounted on a main board of an electronic device while being embedded in an interposer substrate.
Fan-out type semiconductor package
Fig. 7 is a schematic sectional view showing a fan-out type semiconductor package.
Referring to fig. 7, in the fan-out type semiconductor package 2100, for example, the outside of the semiconductor chip 2120 may be protected by an encapsulant 2130, and connection pads 2122 of the semiconductor chip 2120 may be redistributed to the outside of the semiconductor chip 2120 by connection members 2140. In this case, the passivation layer 2150 may also be formed on the connection member 2140, and the under bump metal layer 2160 may also be formed in the opening of the passivation layer 2150. A low melting point metal or alloy ball 2170 may also be formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an Integrated Circuit (IC) including a body 2121, a connection pad 2122, a passivation film (not shown), and the like. The connecting member 2140 may include: an insulating layer 2141; a redistribution layer 2142 formed on the insulating layer 2141; and a via 2143 electrically connecting the connection pad 2122, the redistribution layer 2142, and the like to each other.
In the present manufacturing process, the connection member 2140 may be formed after the encapsulant 2130 is formed outside the semiconductor chip 2120. In this case, a process for connecting the members 2140 is performed after the semiconductor chip 2120 is encapsulated, and thus, the vias 2143 connected to the redistribution layer may be formed to have a width that becomes smaller as they approach the semiconductor chip 2120 (see an enlarged region).
, the fan-in type semiconductor package has a form in which all of the I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip, and thus the semiconductor chip is reduced in size, and balls are also reduced in size and pitch, so that the standardized ball layout is not applicable to the fan-in type semiconductor package.
Fig. 8 is a schematic sectional view showing a case where the fan-out type semiconductor package is mounted on a main board of an electronic device.
Referring to fig. 8, the fan-out type semiconductor package 2100 may be mounted on the main board 2500 of the electronic device by low melting point metal or alloy balls 2170 or the like. More specifically, as described above, since the fan-out type semiconductor package 2100 may include the connection members 2140, the connection members 2140 being formed on the semiconductor chip 2120 and enabling the connection pads 2122 to be redistributed even to the fan-out region located outside of the specific size of the semiconductor chip 2120, the fan-out type semiconductor package 2100 may allow the standardized ball layout to be used as it is, and as a result, the fan-out type semiconductor package 2100 may be mounted on the main board 2500 of the electronic device without using a separate interposer substrate or the like.
As described above, since the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate interposer, the fan-out type semiconductor package can be implemented in a thickness smaller than that of the fan-in type semiconductor package using the interposer. Therefore, the fan-out type semiconductor package can be miniaturized and slimmed. In addition, the fan-out type semiconductor package has excellent thermal and electrical characteristics, making it particularly suitable for mobile products. Further, the fan-out type semiconductor package can be realized in a more compact form than that of a general Package On Package (POP) type package using a Printed Circuit Board (PCB), and a problem due to warpage can be solved.
As described above, the fan-out type semiconductor package refers to a packaging technique for mounting a semiconductor chip on a main board or the like of an electronic device and protecting the semiconductor chip from external impact. Likewise, the fan-out type semiconductor package is based on a concept different from that of a Printed Circuit Board (PCB) such as an interposer (having a specification, a use, and the like different from those of the fan-out type semiconductor package, and having a fan-in type semiconductor package embedded therein).
Fig. 9 is a schematic cross-sectional view illustrating a semiconductor package according to an exemplary embodiment. Fig. 10 is a plan view illustrating the semiconductor package taken along line I-I' in fig. 9.
Referring to fig. 9 and 10, the semiconductor package 100 according to the present exemplary embodiment may include a connection member 140 having th and second surfaces 140A and 140B opposite to each other and including a redistribution layer 145, an integrated circuit chip 120 disposed on the th surface 140A of the connection member 140 and having a connection electrode 122 connected to the redistribution layer, a plurality of capacitors 180 disposed adjacent to the integrated circuit chip 120 on the th surface 140A of the connection member 140, and an encapsulant 130 disposed on the th surface 140A of the connection member 140 and encapsulating the integrated circuit chip 120 and the plurality of capacitors 180.
In the present exemplary embodiment, the semiconductor package 100 may include a support member 110 disposed on the th surface of the connection member and having a cavity 110H the integrated circuit chip 120 and the plurality of capacitors 180 may be accommodated in the cavity 110H.
Further, the semiconductor package 100 may further include: a passivation layer 150 disposed on the second surface 140B of the connection member 140; an Under Bump Metallurgy (UBM) layer 160 disposed on the passivation layer 150 and connected to the redistribution layer through the opening (O) of the passivation layer 150; and an electrical connection structure 170 disposed on the UBM layer 160.
The integrated circuit chip 120 used in the present exemplary embodiment may be a semiconductor chip constituted by a plurality of cells, and may include a large scale integrated circuit (LSI) chip including various logic circuits and memory circuits. Such an integrated circuit chip 120 may be referred to as a microcontroller unit (MCU), a microprocessor unit (MPU), or a system on a chip (SOC). For example, the integrated circuit chip 120 may be formed on a single semiconductor substrate, such as silicon, using previously disclosed semiconductor fabrication techniques.
As shown in FIG. 10, the plurality of units may include central processing units CPU1 and CPU2, graphics processing unit GPU, artificial intelligence unit AI, input output units IO1-IO4, interface units GPIO1 and GPIO2, and memory unit MEMU 1-4.
The central processing units CPU1 and CPU2 may control the semiconductor devices, and the graphics processing unit GPU may perform image processing. The input/output cells IO1 and IO2 may be interfaces for performing data input and output between the integrated circuit chip 120 and an external device. The memory units MEMU1 to 4 may be memories such as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), a flash memory, a phase change memory (PRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FeRAM), or a Magnetoresistive Random Access Memory (MRAM).
Further, the integrated circuit chip 120 may further include an interrupt controller (INTC), a communication unit (CMU), a Direct Memory Access Controller (DMAC), an analog-to-digital converter (ADC), and a clock generator (CPG) according to its use.
The above-described elements of integrated circuit chip 120 may be classified according to their power consumption. In this disclosure, a unit having relatively large power consumption may be referred to as a "core power unit", and a unit having relatively low power consumption may be referred to as a "low power unit".
In the present exemplary embodiment, the central processing units CPU1 and CPU2, the graphic processing unit GPU and/or the artificial intelligence unit AI may correspond to a core power unit, and the input and output units IO1 to IO4, the interface units GPIO1 and GPIO2 or the memory unit may correspond to a low power unit.
In accordance with such power consumption, the layout of the cells constituting the integrated circuit chip can be modified. Fig. 12A and 12B are block diagrams depicting layout variations of various cells on an integrated circuit chip. In particular, the layout shown in fig. 12A may be understood as an exemplary embodiment before being modified, and the layout shown in fig. 12B may be understood as an exemplary embodiment after being modified.
Referring to fig. 12A, in a conventional integrated circuit chip 120, core power cells having large power consumption are generally disposed inside a chip area because they occupy a relatively large area, and low power cells such as input and output cells IO1-IO4, interface cells GPIO1, and GPIO2, which tend to occupy a relatively small area, are generally disposed adjacent to an edge of the chip in order to facilitate input and output with external devices.
In another aspect, in the integrated circuit chip used in the present exemplary embodiment, at least of the core power cells may be disposed adjacent to an edge of the integrated circuit chip 120. for example, as shown in fig. 12B, processing devices (such as CPUs 1 and GPUs) occupying relatively large areas may be disposed along respective opposite edges of the integrated circuit chip 120. according to this layout, at least other core power cells may be spaced from the edge of the integrated circuit chip, with other cells interposed between the at least other core power cells and the edge of the integrated circuit chip, and with the at least other core power cells having a lower power consumption than the at least core power cells, hi addition, according to this layout, at least 5966 of the plurality of low power cells may be disposed spaced from the edge of the integrated circuit chip 120, with 355 cells interposed between the at least low power cells and the edge of the integrated circuit chip 120. for example, memory cells 377 2 and may be disposed between the input and output cells and the edge of the integrated circuit chip 120, and the integrated circuit chip 594624 and the integrated circuit chip with the integrated circuit chip 120, with the integrated circuit chip 59 and the integrated circuit 4624.
As shown in fig. 10, an integrated circuit chip 120 having such a layout may allow cells having relatively large power consumption to be disposed closer to the decoupling capacitor 180. Multiple capacitors 180 may be disposed along the edge of integrated circuit chip 120 adjacent to CPU1 and the GPU.
For example, the CPU1 and the GPU with large power consumption may be disposed in two opposing corners of the integrated circuit chip 120, and the plurality of capacitors 180 may be arranged along two edges adjacent at each corner. In this way, core power cells disposed in corners of integrated circuit chip 120 may allow for a greater number of capacitors or capacitors with greater capacitance to be disposed adjacent to the core power cells by utilizing two adjacent edges.
As described above, when the plurality of cells constituting the integrated circuit chip 120 include the th cell having th power consumption and the second cell having the second power consumption lower than th power consumption, within the integrated circuit chip, the th cell (e.g., CPU1 or GPU) may be disposed adjacent to edges of the integrated circuit chip 120, the second cell (e.g., MEMU2 or IO2) may be disposed on the integrated circuit chip 120 further inward than the th cell, and the plurality of capacitors 180 may be disposed adjacent to the edges of the integrated circuit chip 120.
Connection member 140 may include redistribution layer 145 connected to connection electrodes 122 of integrated circuit chip 120. The connection electrodes 122 of the integrated circuit chip 120 may each be bonded to each of the cells and may be connected to different regions of the redistribution layer 145. As shown in fig. 9 and 11, the redistribution layer 145 may include wiring patterns 142 and vias 143 connecting the wiring patterns 142 to each other.
As shown in fig. 11, redistribution layer 145 may include wiring 145', wiring 145' directly connecting connection electrode 122, which is joined with a GPU, which is of a core power cell, to capacitor 180 disposed adjacent to the GPU.
In particular, in the semiconductor package 100 according to the present exemplary embodiment, the GPU disposed adjacent to the edge of the integrated circuit chip 120 and the capacitor adjacent to the edge may be connected to each other by a short wiring, thereby reducing the equivalent series inductance. As a result, the input impedance in the high frequency region can be improved. In addition, in the present exemplary embodiment, the CPU1 and the GPU may be disposed in the corners of the integrated circuit chip 120, and thus a sufficient number of capacitors 180 may be disposed along the adjacent two edges corresponding to each corner, the total capacitance of the capacitors connected by the wiring 145' may be increased, and as a result, the input impedance in the low frequency region may be improved.
The semiconductor package 100 according to the present exemplary embodiment may include an electrical connection structure 170 (such as a conductive bump) when mounted on a main board. Such electrical connection structures 170 may be connected to redistribution layer 145.
Since the semiconductor package 100 requires uninterrupted power supply, a decoupling capacitor (not shown) may be additionally disposed adjacent to the electrical connection structure 170 disposed on the second surface of the connection member. However, a given space may be limited, and it may be difficult to provide a sufficient number of such decoupling capacitors. Furthermore, the deployment of such additional decoupling capacitors makes the electrical connection path between the decoupling capacitor and the integrated circuit chip large, resulting in an increase in the equivalent series inductance.
In the present exemplary embodiment, the capacitor 180 may be disposed adjacent to the integrated circuit chip 120 on the th surface 140A of the connection member 140, and core power cells having relatively large power consumption may be disposed along an edge adjacent to the capacitor 180.
Hereinafter, the main components of the semiconductor package 100 according to the present exemplary embodiment will be described in more detail.
The integrated circuit chip 120 may be formed based on an active wafer, in which case, a base material of the body 121 of the integrated circuit chip 120 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. various circuits may be formed on the body 121 through a semiconductor process, the connection electrode 122 may be formed to electrically connect the integrated circuit chip 120 to other components, and the connection electrode 122 may be formed using a conductive material such as aluminum (Al), etc., but is not limited thereto.
The support member 110 may include an insulating layer 111 and -and 112 b-th and 112 a-second wiring patterns 112a and 112b, the support member 110 may be formed on upper and lower surfaces of the insulating layer 111 and then may be connected to each other through a via 113 penetrating the insulating layer 111 to achieve a desired wiring structure.
In addition, the support member 110 may be formed to have a thickness corresponding to that of the integrated circuit chip 120, and the second wiring pattern 112b of the support member 110 may be aligned with a position between the active surface and the inactive surface of the integrated circuit chip 120. The active surface of the integrated circuit chip 120 refers to the surface of the integrated circuit chip 120 on which the connection electrodes 122 are provided, and the inactive surface of the integrated circuit chip 120 refers to the surface of the integrated circuit chip 120 opposite to the active surface.
Since the support member 110 is not particularly limited in its thickness and may be formed to correspond to the thickness of the integrated circuit chip 120, the support member 110 may be formed through a conventional wafer process, and the redistribution layer 145 of the connection member 140 may be formed to have a smaller thickness by a micro-patterning technique using photolithography, and thus, the thickness of the wiring patterns 112a and the second wiring patterns 112b of the support member 110 may be greater than the thickness of the redistribution layer 145 of the connection member 140.
The insulating material of the support member 110 may include a resin containing a reinforcement such as an inorganic filler, and a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, wherein the inorganic filler may be silicon dioxide, aluminum oxide, etc., for example, the insulating material of the support member 110 may include, in particular, ABF (Ajinomoto build-up film), FR-4 resin, Bismaleimide Triazine (BT) resin, photo dielectric (PID) resin, etc., and in addition, a material in which the thermosetting resin or the thermoplastic resin is impregnated together with the inorganic filler in a core material such as glass fiber, glass cloth, etc., such as a prepreg, may be used, if necessary.
The th and second wiring patterns 112a and 112b of the support member 110 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof the via 113 of the support member 110 penetrating the insulating layer 111 may be formed using a conductive material and may be integrated with the portion of the th and second wiring patterns 112a and 112 b.
Although not shown in the drawings, a metal layer may be additionally provided on the sidewall of the cavity 110H, if necessary. The metal layer may be used to effectively release heat generated by the integrated circuit chip 120 and/or block electromagnetic waves. In particular, there may be a plurality of cavities 110H, and in each of the plurality of cavities 110H, an integrated circuit chip 120 and/or passive components such as capacitors may be provided, although other structures known in the art may also be used herein.
Encapsulant 130 may be formed to protect integrated circuit chip 120, capacitor 180, and support member 110. the encapsulation scheme is not particularly limited as long as it encapsulates integrated circuit chip 120, capacitor 180, and at least portions of support member 110. for example, encapsulant 130 may cover the inactive surface of integrated circuit chip 120 and the upper surface of support member 110, and may fill the space between integrated circuit chip 120 and support member 110. in an embodiment, encapsulant 130 may fill at least portions of the space between connection member 140 and passivation film 123 of integrated circuit chip 120. in another embodiment, encapsulant 130 may act as an adhesive, depending on the material of encapsulant 130, while reducing buckling by filling cavities 110H.
For example, the material of the encapsulant 130 is not limited to any particular material, and for example, an insulating material may be used, such insulating materials may be thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, and resins containing inorganic fillers in thermosetting or thermoplastic resins such as ABF (Ajinomoto build-up film), FR-4 resins, Bismaleimide Triazine (BT) resins, photo dielectric (PID) resins, and the like.
The connection members 140 may redistribute the connection electrodes 122 on the integrated circuit chip 120. Tens to hundreds of connection electrodes 122 having various functions may be redistributed by the connection member 140 and may be physically and/or electrically connected to an external device through the electrical connection structure 170 according to their functions. Connection member 140 may include redistribution layer 145 connected to connection electrodes 122 of integrated circuit chip 120 and extending to a lower surface of support member 110.
The redistribution layer 145 of the connection member 140 may be connected to the connection electrode 122 of the integrated circuit chip 120 and the th wiring pattern 112a of the support member 110 to electrically connect the redistribution structures of the integrated circuit chip 120 and the support member 110.
The redistribution layer 145 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof in a manner similar to that described for the th and second wiring patterns 112a and 112b, the redistribution layer 145 may perform various functions according to the design of its respective layer.
The passivation layer 150 may include tens to thousands of openings (O) to expose at least portions of the redistribution layer 145 of the connection member 140, the passivation layer 150 may use a photosensitive insulating material such as a photosensitive insulating resin or a solder resist material, but is not limited thereto, for example, the passivation layer 150 may use an insulating resin mixed with an inorganic filler such as ABF (Ajinomoto build-up film), etc., and when it uses an insulating resin mixed with an inorganic filler, the insulating layer 141 of the connection member 140 may also include an insulating resin mixed with an inorganic filler.
The electrical connection structure 170 may serve as a connection terminal for physically and/or electrically connecting the semiconductor package 100 to an external device (e.g., a motherboard). The electrical connection structure 170 may use a conductive material, for example, a low melting point alloy (such as Sn-Al-Cu). The electrical connection structures 170 may be pads, balls, pins, etc. The electrical connection structure 170 may be formed of multiple layers or a single layer.
The number, interval, arrangement form, etc. of the electrical connection structures 170 are not particularly limited and may be sufficiently modified by those skilled in the art according to design details. For example, the number of the electrical connection structures 170 may be from tens to thousands, or may be more or less than tens to thousands, depending on the number of the connection electrodes 122 of the integrated circuit chip 120.
In addition, the fan-out package may be mounted in an electronic device without using a separate substrate, as compared to a Ball Grid Array (BGA) package, a grid array (LGA) package, or the like, and thus may be manufactured to have a reduced thickness and to be more price competitive.
The capacitor 180 employed in the present exemplary embodiment may be a multilayer ceramic capacitor (MLCC), and more particularly, may be a multilayer ceramic capacitor (MLCC) that can provide sufficient capacitance, which is currently used as an embedded type in the related art. Capacitor 180 may be used to achieve low equivalent series inductance (ESL) and provide the base capacitance.
Fig. 13 is a schematic cross-sectional view illustrating semiconductor packages according to exemplary embodiments of the present disclosure, and fig. 14 is a plan view of the semiconductor packages taken along line II-II' in fig. 13.
Referring to fig. 13 and 14, it may be understood that the semiconductor package 100A according to the present exemplary embodiment has a structure similar to that shown in fig. 9 and 10, except that the semiconductor package 100A has a different substrate structure, does not include a support member, and has a different integrated circuit chip layout and a different capacitor arrangement. Components according to the present exemplary embodiment may be understood with reference to the description of the same or similar components of the semiconductor package 100 shown in fig. 9 and 10, unless explicitly described to the contrary.
The semiconductor package 100A according to the present exemplary embodiment may include an interposer 240 instead of the connection member, the interposer 240 may include a substrate 241, a wiring circuit (not shown) formed on the substrate 241, and a plurality of pads 242 and second pads 243 disposed on upper and lower surfaces of the substrate 241, respectively, and connected through the wiring circuit, the wiring circuit may include a wiring 245 directly connecting the capacitor 180 and the core power cell disposed along an edge of the integrated circuit chip 120.
The substrate 241 of the interposer 240 may be a silicon substrate, however, the substrate 241 of the interposer 240 is not limited thereto, and may be a Printed Circuit Board (PCB) in another example, for example, the substrate 241 may be formed using a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, or may be a photosensitive insulating layer, external terminals 270 may be disposed on the plurality of second pads 243 located on the lower surface of the interposer 240, the external terminals 270 may include at least metals selected from tin (Sn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), and bismuth (Bi), or may include alloys thereof.
The integrated circuit chip 120 may be flip-chip bonded such that the active surface on which the connection electrode 122 is disposed faces the upper surface of the interposer 240, the th pad 242 of the interposer 240 and the connection electrode 122 may be bonded to the connection terminal 116.
For example, as shown in FIG. 14, the CPUs 1, the CPUs 2, the AIs, and the GPUs may each be disposed along an edge of the integrated circuit chip 120 or in a corner of the integrated circuit chip 120, while a portion of of the plurality of low power cells (e.g., IO2) may be spaced apart from the edge of the integrated circuit chip 120, and another cell is interposed between a portion of of the plurality of low power cells and the edge of the integrated circuit chip 120.
The integrated circuit chip 120 having the above-described layout may allow cells having relatively large power consumption to be disposed closer to the decoupling capacitor 180. A plurality of such capacitors 180 may be disposed along an edge of the integrated circuit chip 120 adjacent to the CPU1, the CPU2, the AI, and the GPU unlike the previous exemplary embodiment, the plurality of capacitors 180 may have a rectangular structure and may be arranged such that only terminals of each of the plurality of capacitors 180 are disposed adjacent to the edge, so that more capacitors may be disposed, thereby ensuring sufficient capacitance.
In particular, the CPU1 and the GPU, which consume a large amount of power, may be disposed in two corners of the integrated circuit chip 120, and the plurality of capacitors 180 may be arranged along two adjacent edges corresponding to each corner. In this way, core power cells disposed in corners of integrated circuit chip 120 may allow for a greater number of capacitors or capacitors with greater capacitance to be disposed adjacent to the core power cells by utilizing two adjacent edges.
As described above, according to exemplary embodiments of the present disclosure, in an integrated circuit chip including a plurality of cells, a cell having large power consumption may be disposed adjacent to an edge of the chip, and a capacitor may be disposed adjacent to the edge to significantly improve Power Integrity (PI) of a semiconductor package.
While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the invention defined by the appended claims.

Claims (23)

  1. A semiconductor package of the kind , comprising:
    a connecting member having th and second surfaces opposite to each other and including a redistribution layer;
    an integrated circuit chip disposed on the th surface of the connection member, having connection electrodes connected to the redistribution layer, and including a plurality of cells;
    at least capacitors disposed on the th surface of the connecting member and disposed adjacent to the integrated circuit chip, and
    an encapsulant disposed on the th surface of the connection member and encapsulating the integrated circuit chip and the at least capacitors,
    wherein the plurality of cells includes core power cells, at least of the core power cells being disposed adjacent to a th edge of the integrated circuit chip,
    the at least capacitors are disposed adjacent to the th edge of the integrated circuit chip.
  2. 2. The semiconductor package of claim 1, wherein the redistribution layer comprises wiring directly connecting the at least core power cells and the at least capacitors.
  3. 3. The semiconductor package of claim 1, wherein the at least capacitors comprise a plurality of capacitors arranged along the edge of the integrated circuit chip.
  4. 4. The semiconductor package of claim 1, wherein at least of the at least core power cells are disposed in a corner of the integrated circuit chip so as to be adjacent to two intersecting edges of the integrated circuit chip.
  5. 5. The semiconductor package of claim 4, wherein a plurality of capacitors are disposed along the two intersecting edges.
  6. 6. The semiconductor package of claim 1, wherein the plurality of cells further comprises at least other core power cells spaced apart from an edge of the integrated circuit chip with other cells interposed between the at least other core power cells and the edge of the integrated circuit chip, and the power consumption of the at least other core power cells is lower than the power consumption of the at least core power cells.
  7. 7. The semiconductor package of claim 1, wherein the plurality of cells further comprises a plurality of low power cells, a power consumption of each of the plurality of low power cells is lower than a power consumption of each of the core power cells, and at least of the plurality of low power cells are spaced apart from an edge of the integrated circuit chip with other cells interposed between the at least of the plurality of low power cells and the edge of the integrated circuit chip.
  8. 8. The semiconductor package of claim 7, wherein the plurality of low power units comprises units selected from the group consisting of interface units, memory units, and input-output units.
  9. 9. The semiconductor package of claim 1, further comprising a support member disposed on the -th surface of the connection member and having a cavity that houses the integrated circuit chip and the at least capacitors.
  10. 10. The semiconductor package of claim 9, wherein the support member comprises: a wiring structure connecting upper and lower surfaces of the support member and connected to the redistribution layer.
  11. 11. The semiconductor package of claim 1, wherein the core power unit comprises a unit selected from the group consisting of a central processing unit, a graphics processing unit, and an artificial intelligence unit.
  12. A semiconductor package of the type 12, , comprising:
    a connecting member having th and second surfaces opposite to each other and including a redistribution layer;
    an integrated circuit chip disposed on the th surface of the connection member, having connection electrodes connected to the redistribution layer, and including a plurality of cells;
    a plurality of capacitors disposed on the th surface of the connecting member and adjacent to the integrated circuit chip, and
    an encapsulant disposed on the th surface of the connection member and encapsulating the integrated circuit chip and the plurality of capacitors,
    wherein the plurality of cells include an th cell having a th power consumption and disposed adjacent to an edge of the integrated circuit chip, and a second cell having a second power consumption lower than the th power consumption and disposed more inward than the th cell with respect to the edge, and
    the plurality of capacitors is disposed adjacent to the edge of the integrated circuit chip.
  13. 13. The semiconductor package of claim 12, wherein the th cell comprises at least cells selected from the group consisting of a central processing unit, a graphics processing unit, and an artificial intelligence unit.
  14. 14. The semiconductor package according to claim 12, wherein a plurality of said th cells are included, and
    the plurality of th cells are disposed adjacent to edges of the integrated circuit chip or in a corner of the integrated circuit chip.
  15. 15. The semiconductor package of claim 12, wherein the second cells comprise at least cells selected from an interface cell, a memory cell, and an input-output cell.
  16. 16. The semiconductor package of claim 12, wherein the redistribution layer comprises routing directly connecting the cells and the plurality of capacitors.
  17. A semiconductor package of the kind 17, , comprising:
    an integrated circuit chip including a core power cell and a other cell disposed adjacent to an th edge of the integrated circuit chip, the integrated circuit chip disposed on a th surface of a connection member;
    a capacitor disposed on the th surface of the connecting member and disposed adjacent to the th edge of the integrated circuit chip, and
    an encapsulant disposed on the th surface of the connection member and encapsulating at least portions of each of the integrated circuit chip and the capacitor,
    wherein the connection member includes a wiring layer directly connecting the th core power cell and the capacitor.
  18. 18. The semiconductor package of claim 17, wherein the connection member further comprises a redistribution layer connected to connection electrodes of the integrated circuit chip.
  19. 19. The semiconductor package of claim 17, wherein the integrated circuit chip further comprises a second core power cell having a lower power consumption than the th core power cell, the second core power cell disposed away from the th edge relative to the th core power cell with other cells interposed between the second core power cell and the th edge.
  20. 20. The semiconductor package of claim 17, wherein the th other cell has a lower power consumption than the th core power cell.
  21. 21. The semiconductor package of claim 17, wherein the th core power unit is selected from the group consisting of a central processing unit, a graphics processing unit, and an artificial intelligence unit.
  22. 22. The semiconductor package of claim 17, wherein the th other unit is selected from the group consisting of an interface unit, a memory unit, and an input-output unit.
  23. 23. The semiconductor package of claim 17, wherein only terminals of the capacitor are disposed adjacent to the edge.
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