CN110739299A - 半导体封装件 - Google Patents
半导体封装件 Download PDFInfo
- Publication number
- CN110739299A CN110739299A CN201910376198.6A CN201910376198A CN110739299A CN 110739299 A CN110739299 A CN 110739299A CN 201910376198 A CN201910376198 A CN 201910376198A CN 110739299 A CN110739299 A CN 110739299A
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- integrated circuit
- circuit chip
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Abstract
本发明提供一种半导体封装件。所述半导体封装件包括:连接构件,具有彼此相对的第一表面和第二表面,并包括重新分布层;集成电路芯片,设置在所述连接构件的所述第一表面上,并且包括多个单元;至少一个电容器,位于所述连接构件的所述第一表面上并接近所述集成电路芯片;包封剂,位于所述连接构件的所述第一表面上并包封所述集成电路芯片和所述至少一个电容器,其中,所述多个单元包括从由中央处理单元、图形处理单元和人工智能单元组成的组中选择的核心功率单元,所述核心功率单元中的至少一个核心功率单元设置为邻近于所述集成电路芯片的边缘,并且所述至少一个电容器设置为邻近于所述集成电路芯片的所述边缘。
Description
本申请要求于2018年7月20日提交到韩国知识产权局的第10-2018-0084572号韩国专利申请的优先权的权益,所述韩国专利申请的公开内容通过引用全部包含于此。
技术领域
本申请涉及一种半导体封装件。
背景技术
半导体芯片的技术发展的主要焦点已经放在减小组件的尺寸上,并且随着对小型半导体芯片等的需求的增长,封装领域中需求尺寸更小、同时能够具有多个引脚的半导体封装件。已经提出的满足这种需求的一种封装技术是扇出型半导体封装件。
这种半导体封装件包括这样的封装件,该封装件包括也被称为微控制器单元(MCU)、微处理器单元(MPU)或片上系统(SOC)的大规模集成电路(LSI)芯片。这种半导体封装件可广泛用于便携式电子装置,诸如上网本PC、平板PC、智能电话和便携式视频游戏机。此外,即使在诸如上面列出的高速便携式电子装置中的典型高速切换环境中,这种半导体封装件也会需要不间断的电力供应。
发明内容
本公开的一方面可以通过优化半导体芯片的内部设计和电容器的位置来提供具有改善的电源完整性(PI)的半导体封装件。
根据本公开的一方面,一种半导体封装件包括:连接构件,具有彼此相对的第一表面和第二表面,并且包括重新分布层;集成电路芯片,设置在所述连接构件的所述第一表面上,具有连接到所述重新分布层的连接电极,并且通过多个单元构成;至少一个电容器,设置为在所述连接构件的所述第一表面上接近所述集成电路芯片;包封剂,设置在所述连接构件的所述第一表面上,并包封所述集成电路芯片和所述至少一个电容器,其中,所述多个单元包括从由中央处理单元(CPU)、图形处理单元(GPU)和人工智能单元(AI)组成的组中选择的核心功率单元,所述核心功率单元中的至少一个核心功率单元设置为邻近于所述集成电路芯片的边缘,并且所述至少一个电容器设置为邻近于所述集成电路芯片的所述边缘。
根据本公开的另一方面,一种半导体封装件包括:连接构件,具有彼此相对的第一表面和第二表面,并且包括重新分布层;集成电路芯片,设置在所述连接构件的所述第一表面上,具有连接到所述重新分布层的连接电极,并且通过多个单元构成;多个电容器,在所述连接构件的所述第一表面上设置为接近所述集成电路芯片;包封剂,设置在所述连接构件的所述第一表面上,并包封所述集成电路芯片和所述多个电容器,其中,所述多个单元包括具有第一功耗的第一单元和具有低于所述第一功耗的第二功耗的第二单元,所述第一单元设置为邻近于所述集成电路芯片的边缘,所述第二单元比所述第一单元更向内地设置在所述集成电路芯片上,并且所述多个电容器设置为邻近于所述集成电路芯片的所述边缘。
根据本公开的另一方面,一种半导体封装件包括:集成电路芯片,包括设置为邻近于所述集成电路芯片的第一边缘的第一核心功率单元和第一其它单元,所述集成电路芯片设置在连接构件的第一表面上;电容器,设置在所述连接构件的所述第一表面上并设置为邻近于所述集成电路芯片的所述第一边缘;和包封剂,设置在所述连接构件的所述第一表面上并包封所述集成电路芯片和所述电容器中的每个的至少一部分,其中,所述连接构件包括直接连接所述第一核心功率单元和所述电容器的布线层。
附图说明
通过以下结合附图的详细描述,将更清楚地理解本公开的上述和其它方面、特征和优点,在附图中:
图1是示出电子装置系统的示例的示意性框图;
图2是示出电子装置的示例的示意性透视图;
图3A和图3B是示出封装之前和之后的扇入型半导体封装件的状态的示意性截面图;
图4是示出扇入型半导体封装件的封装工艺的示意性截面图;
图5是示出扇入型半导体封装件安装在中介基板上并最终安装在电子装置的主板上的情况的示意性截面图;
图6是示出将扇入型半导体封装件嵌入到中介基板内并最终安装在电子装置的主板上的情况的示意性截面图;
图7是示出扇出型半导体封装件的示意性截面图;
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图;
图9是根据本公开中的示例性实施例的半导体封装件的示意性截面图;
图10是示出沿图9中的线I-I'截取的半导体封装件的平面图;
图11是示出图9中所示的半导体封装件的部分A的放大截面图;
图12A和图12B是用于描述集成电路芯片的各种单元的布局变化的框图;
图13是示出根据本公开中的一个示例性实施例的半导体封装件的示意性截面图;和
图14是沿图13中的线II-II'截取的半导体封装件的平面图。
具体实施方式
在下文中,将参照附图描述本公开中的示例性实施例。在附图中,为了清楚起见,可夸大或缩小组件的形状、尺寸等。
在此,下侧、下部、下表面等用于表示相对于附图的截面朝向扇出型半导体封装件的安装表面的方向,而上侧、上部、上表面等用于表示与该方向相反的方向。然而,这些方向是为了便于解释而定义的,并且权利要求不受如上所述定义的方向的特别限制。
在说明书中将组件“连接”到另一组件的含义包括通过粘合剂层等的间接连接以及两个组件之间的直接连接。另外,“电连接”意味着包括物理连接和物理断开的概念。可以理解,当元件用“第一”和“第二”表示时,该元件不限于此。术语“第一”、“第二”等可以仅用于将该元件与其它元件区分开的目的,并且可以不限制所述元件的顺序或重要性。在一些情况下,在不脱离在此阐述的权利要求的范围的情况下,第一元件可以被称为第二元件。类似地,第二元件也可以称为第一元件。
在此使用的术语“示例性实施例”不是指相同的示例性实施例,并且被提供用于强调与另一示例性实施例的特定特征或特性不同的特定特征或特性。然而,在此提供的示例性实施例被认为能够通过整体或部分地彼此组合来实现。例如,除非在此提供相反或矛盾的描述,否则在特定示例性实施例中描述的一个元件即使未在另一示例性实施例中描述,也可以被理解为与另一示例性实施例相关的描述。
在此使用的术语仅用于描述示例性实施例而不是限制本公开。在这种情况下,除非在上下文中另有说明,否则单数形式包括复数形式。
电子装置
图1是示出电子装置系统的示例的示意性框图。
参照图1,电子装置1000中可以容纳主板1010。主板1010可以包括与其物理和/或电连接的芯片相关组件1020、网络相关组件1030、其它组件1040等。这些组件可以通过各种信号线1090连接到将在下面描述的其它组件。
芯片相关组件1020可包括:存储器芯片,诸如易失性存储器(例如,动态随机存取存储器(DRAM))、非易失性存储器(例如,只读存储器(ROM))、闪存等;应用处理器芯片,诸如中央处理器(例如,中央处理单元(CPU))、图形处理器(例如,图形处理单元(GPU))、数字信号处理器、密码处理器、微处理器、微控制器等;以及逻辑芯片,诸如模拟数字转换器(ADC)、专用集成电路(ASIC)等。然而,芯片相关组件1020不限于此,而是还可包括其它类型的芯片相关组件。此外,芯片相关组件1020可彼此组合。
网络相关组件1030可包括被指定为根据诸如以下的协议操作的组件:无线保真(Wi-Fi)(电工电子工程师协会(IEEE)802.11族等)、全球微波接入互操作性(WiMAX)(IEEE802.16族等)、IEEE 802.20、长期演进技术(LTE)、演进数据最优化(Ev-DO)、高速分组接入+(HSPA+)、高速下行链路分组接入+(HSDPA+)、高速上行链路分组接入+(HSUPA+)、增强型数据GSM环境(EDGE)、全球移动通信系统(GSM)、全球定位系统(GPS)、通用分组无线业务(GPRS)、码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳电信(DECT)、蓝牙、3G协议、4G协议和5G协议以及在上述协议之后指定的任意其它无线协议和有线协议。然而,网络相关组件1030不限于此,而是还可包括被指定为根据各种其它无线标准或协议或者有线标准或协议操作的组件。此外,网络相关组件1030可与上述芯片相关组件1020一起彼此组合。
其它组件1040可包括高频电感器、铁氧体电感器、功率电感器、铁氧体磁珠、低温共烧陶瓷(LTCC)、电磁干扰(EMI)滤波器、多层陶瓷电容器(MLCC)等。然而,其它组件1040不限于此,并且还可包括用于各种其它目的的无源组件等。此外,其它组件1040可与上述芯片相关组件1020或网络相关组件1030一起彼此组合。
根据电子装置1000的类型,电子装置1000可包括可物理连接和/或电连接到主板1010或者可不物理连接和/或电连接到主板1010的其它组件。这些其它组件可包括例如相机1050、天线1060、显示器1070、电池1080、音频编解码器(未示出)、视频编解码器(未示出)、功率放大器(未示出)、指南针(未示出)、加速计(未示出)、陀螺仪(未示出)、扬声器(未示出)、大容量存储单元(例如,硬盘驱动器)(未示出)、光盘(CD)驱动器(未示出)、数字通用光盘(DVD)驱动器(未示出)等。然而,这些其它组件不限于此,而是还可根据电子装置1000的类型等而包括用于各种目的的其它组件。
电子装置1000可以是智能电话、个人数字助理(PDA)、数字摄像机、数码相机、网络系统、计算机、监视器、平板PC、膝上型PC、上网本PC、电视机、视频游戏机、智能手表、汽车组件等。然而,电子装置1000不限于此,而可以是处理数据的任意其它电子装置。
图2是示出电子装置的示例的示意性透视图。
参照图2,半导体封装件可在如上所述的各种电子装置中用于各种目的。例如,母板1110可容纳在智能电话1100的主体1101中,并且各种电子组件1120可物理连接或者电连接到母板1110。另外,可物理连接和/或电连接到母板1110或者可不物理连接和/或电连接到母板1110的其它组件(诸如,相机1130)可容纳在主体1101中。电子组件1120中的一些可以是芯片相关组件,并且半导体封装件100可以是例如芯片相关组件中的应用处理器,但不限于此。电子装置不必然地限于智能电话1100,而可以是如上所述的其它电子装置。
半导体封装件
通常,半导体芯片中集成了大量的微电子电路。然而,半导体芯片本身可能无法用作成品的半导体产品,并且可能会由于外部的物理冲击或者化学冲击而损坏。因此,半导体芯片不能在暴露状态下使用,而是被封装并且在封装状态下在电子装置等中使用。
需要半导体封装的原因是:就电连接而言,半导体芯片和电子装置的主板之间的电路宽度存在差异。详细地,在半导体芯片的情况下,连接焊盘的尺寸和连接焊盘之间的间距非常细小,而在电子装置中使用主板的情况下,组件安装焊盘的尺寸和组件安装焊盘之间的间距显著大于半导体芯片的连接焊盘的尺寸和连接焊盘之间的间距。因此,会难以将半导体芯片直接安装在主板上,并且需要用于缓解半导体芯片和主板之间的电路宽度的差异的封装技术。
通过这种封装技术制造的半导体封装件可根据其结构和预期目的而分为扇入型半导体封装件和扇出型半导体封装件。
在下文中,将参照附图更详细地描述扇入型半导体封装件和扇出型半导体封装件。
扇入型半导体封装件
图3A和图3B是示出扇入型半导体封装件在被封装之前和封装之后的状态的示意性截面图,图4是示出扇入型半导体封装件的封装工艺的示意性截面图。
参照图3A、图3B以及图4,半导体芯片2220可以是例如处于裸态的集成电路(IC),并且包括:主体2221,包括硅(Si)、锗(Ge)、砷化镓(GaAs)等;连接焊盘2222,形成在主体2221的一个表面上,并且包括诸如铝(Al)等的导电材料;以及钝化层2223,为氧化物膜、氮化物膜等,形成在主体2221的一个表面上并且覆盖连接焊盘2222的至少一部分。
因此,根据半导体芯片2220的尺寸,可在半导体芯片2220上形成连接构件2240,以使连接焊盘2222重新分布。连接构件2240可通过如下步骤形成:使用诸如感光电介质(PID)树脂的绝缘材料在半导体芯片2220上形成绝缘层2241,之后形成使连接焊盘2222敞开的通路孔2243h,然后形成布线图案2242和过孔2243。然后,可形成保护连接构件2240的钝化层2250,可形成开口2251,然后可形成凸块下金属层2260等。结果,可通过如上所述一系列工艺制造包括例如半导体芯片2220、连接构件2240、钝化层2250和凸块下金属层2260的扇入型半导体封装件2200。
如上所述,扇入型半导体封装件可以是半导体芯片的所有的连接焊盘(例如,输入/输出(I/O)端子)设置在半导体芯片的内部的封装件形式。另外,扇入型半导体封装件可具有令人满意的电特性,并且可以廉价地制造。因此,安装在智能电话中的许多元件已经按照扇入型半导体封装件形式来制造,并且具体地,安装在智能电话中的许多元件已经被开发为在具有紧凑的尺寸的同时实现快速的信号传输。
然而,由于扇入型半导体封装件要求所有的I/O端子都设置在半导体芯片的内部,因此扇入型半导体封装件具有显著的空间局限性。因此,难以将此结构应用于具有大量的I/O端子的半导体芯片或者具有小尺寸的半导体芯片。另外,由于上述缺点,可能无法在电子装置的主板上直接安装和使用扇入型半导体封装件,这是原因:即使当半导体芯片的I/O端子的尺寸和半导体芯片的I/O端子之间的间距通过重新分布工艺被增大时,半导体芯片的I/O端子的尺寸和半导体芯片的I/O端子之间的间距可能仍不足以将扇入型半导体封装件直接安装在电子装置的主板上。
图5是示出扇入型半导体封装件安装在中介基板上并且最终安装在电子装置的主板上的情况的示意性截面图,图6是示出扇入型半导体封装件嵌入在中介基板内并且最终安装在电子装置的主板上的情况的示意性截面图。
参照图5,在扇入型半导体封装件2200中,半导体芯片2220的连接焊盘2222(即,I/O端子)可通过中介基板2301再次重新分布,并且然后,扇入型半导体封装件2200在安装在中介基板2301上的同时可最终安装在电子装置的主板2500上。在这种情况下,低熔点金属或合金球2270等可通过底部填充树脂2280等固定,并且扇入型半导体封装件2200的外侧可利用包封剂2290等覆盖。可选地,参照图6,扇入型半导体封装件2200可嵌入在单独的中介基板2302内,在扇入型半导体封装件2200嵌入在中介基板2302内的同时,半导体芯片2220的连接焊盘2222(为I/O端子)可通过中介基板2302再次重新分布,并且扇入型半导体封装件2200可最终安装在电子装置的主板2500上。
如上所述,会难以在电子装置的主板上直接安装和使用扇入型半导体封装件。因此,扇入型半导体封装件可通过首先安装在单独的中介基板上然后通过封装工艺安装在电子装置的主板上而使用。可选地,扇入型半导体封装件可通过在嵌入在中介基板内的同时安装在电子装置的主板上而使用。
扇出型半导体封装件
图7是示出扇出型半导体封装件的示意性截面图。
参照图7,在扇出型半导体封装件2100中,例如,半导体芯片2120的外侧可通过包封剂2130保护,并且半导体芯片2120的连接焊盘2122可通过连接构件2140重新分布到半导体芯片2120的外部。在这种情况下,钝化层2150还可形成在连接构件2140上,并且凸块下金属层2160还可形成在钝化层2150的开口中。低熔点金属或合金球2170还可形成在凸块下金属层2160上。半导体芯片2120可以是包括主体2121、连接焊盘2122、钝化膜(未示出)等的集成电路(IC)。连接构件2140可包括:绝缘层2141;重新分布层2142,形成在绝缘层2141上;及过孔2143,使连接焊盘2122、重新分布层2142等彼此电连接。
在本制造工艺中,可以在包封剂2130形成在半导体芯片2120外部之后形成连接构件2140。在这种情况下,在包封半导体芯片2120之后执行用于连接构件2140的工艺,并且因此,连接到重新分布层的过孔2143可以形成为具有随着它们接近半导体芯片2120而变小的宽度(请参照放大区域)。
如上所述,扇出型半导体封装件具有半导体芯片的I/O端子通过形成在半导体芯片上的连接构件重新分布并且设置在半导体芯片的外部的形式。一方面,扇入型半导体封装件具有半导体芯片的所有的I/O端子需要设置在半导体芯片的内部的形式,因此半导体芯片的尺寸减小,球的尺寸和节距也需要减小,致使标准化的球布局不适用扇入型半导体封装件。另一方面,如上所述,扇出型半导体封装件具有半导体芯片的I/O端子通过形成在半导体芯片上的连接构件重新分布并且设置在半导体芯片的外部的形式,因此,即使半导体芯片的尺寸减小,在扇出型半导体封装件中仍可按照原样使用标准化的球布局。结果,扇出型半导体封装件可在不使用单独的中介基板的情况下安装在电子装置的主板上,如下所述。
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图。
参照图8,扇出型半导体封装件2100可通过低熔点金属或合金球2170等安装在电子装置的主板2500上。更具体地,如上所述,由于扇出型半导体封装件2100可包括连接构件2140,连接构件2140形成在半导体芯片2120上并且能够使连接焊盘2122甚至重新分布到位于半导体芯片2120的具体尺寸的外部的扇出区域,因此扇出型半导体封装件2100可允许按照原样使用标准化的球布局,结果,扇出型半导体封装件2100可在不使用单独的中介基板等的情况下安装在电子装置的主板2500上。
如上所述,由于扇出型半导体封装件可在不使用单独的中介基板的情况下安装在电子装置的主板上,因此扇出型半导体封装件可按照比使用中介基板的扇入型半导体封装件的厚度小的厚度实现。因此,扇出型半导体封装件可被小型化和纤薄化。另外,扇出型半导体封装件具有优异的热特性和电特性,使得其特别适合于移动产品。此外,扇出型半导体封装件可按照比使用印刷电路板(PCB)的普通的层叠封装(POP)类型封装件的形式更紧凑的形式实现,并且可解决由于翘曲而引起的问题。
如上所述,扇出型半导体封装指的是用于将半导体芯片安装在电子装置的主板等上并且保护半导体芯片免受外部冲击的影响的封装技术。同样地,扇出型半导体封装基于与诸如中介基板的印刷电路板(PCB)(具有与扇出型半导体封装件的规格、用途等不同的规格、用途等,并且具有嵌入其中的扇入型半导体封装件)的概念不同的概念。
图9是示出根据示例性实施例的半导体封装件的示意性截面图。图10是示出沿图9中的线I-I'截取的半导体封装件的平面图。
参照图9和图10,根据本示例性实施例的半导体封装件100可以包括:连接构件140,具有彼此相对的第一表面140A和第二表面140B,并且包括重新分布层145;集成电路芯片120,设置在连接构件140的第一表面140A上,并具有连接到重新分布层的连接电极122;多个电容器180,设置为在连接构件140的第一表面140A上靠近集成电路芯片120;包封剂130,设置在连接构件140的第一表面140A上,并且包封集成电路芯片120和多个电容器180。
在本示例性实施例中,半导体封装件100可以包括:支撑构件110,设置在连接构件的第一表面上并且具有腔110H。集成电路芯片120和多个电容器180可以被容纳在腔110H中。
此外,半导体封装件100还可以包括:钝化层150,设置在连接构件140的第二表面140B上;凸块下金属(UBM)层160,设置在钝化层150上并通过钝化层150的开口(O)连接到重新分布层;电连接结构170,设置在UBM层160上。
在本示例性实施例中使用的集成电路芯片120可以是由多个单元构成的半导体芯片,并且可以包括大规模集成电路(LSI)芯片,大规模集成电路(LSI)芯片包括各种逻辑电路和存储器电路。这种集成电路芯片120可以称为微控制器单元(MCU)、微处理器单元(MPU)或片上系统(SOC)。例如,通过使用先前公开的半导体制造技术,可以在诸如硅的单个半导体基板上形成集成电路芯片120。
如图10所示,多个单元可包括中央处理单元CPU1和CPU2、图形处理单元GPU、人工智能单元AI、输入输出单元IO1-IO4、接口单元GPIO1和GPIO2以及存储器单元MEMU1-4。
中央处理单元CPU1和CPU2可以控制半导体器件,并且图形处理单元GPU可以执行图像处理。输入输出单元IO1和IO2可以是用于在集成电路芯片120和外部装置之间执行数据输入和输出的接口。存储器单元MEMU 1-4可以是诸如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、闪存、相变存储器(PRAM)、电阻随机存取存储器(ReRAM)、铁电随机存取存储器(FeRAM)或磁阻随机存取存储器(MRAM)的存储器。
此外,集成电路芯片120还可以根据其用途包括中断控制器(INTC)、通信单元(CMU)、直接存储器存取控制器(DMAC)、模数转换器(ADC)和时钟脉冲发生器(CPG)。
可以根据它们的功耗对集成电路芯片120的上述单元进行分类。在本公开中,具有相对大的功耗的单元可以被称为“核心功率单元”,并且具有相对低的功耗的单元可以被称为“低功率单元”。
在本示例性实施例中,中央处理单元CPU1和CPU2、图形处理单元GPU和/或人工智能单元AI可以对应于核心功率单元,且输入输出单元IO1-IO4、接口单元GPIO1和GPIO2或存储器单元可以对应于低功率单元。
根据这样的功耗,可以修改构成集成电路芯片的单元的布局。图12A和图12B是描述集成电路芯片上各种单元的布局变化的框图。特别地,图12A中所示的布局可以被理解为在被修改之前的示例性实施例,并且图12B中所示的布局可以被理解为在修改之后的示例性实施例。
参照图12A,在传统的集成电路芯片120中,具有大功耗的核心功率单元因其占据相对较大的面积而通常设置在芯片区域的内部,而倾向于占据相对较小面积的诸如输入输出单元IO1-IO4、接口单元GPIO1和GPIO2的低功率单元通常被设置为邻近于芯片的边缘,以便于与外部装置进行输入和输出。
另一方面,在本示例性实施例中使用的集成电路芯片中,所述核心功率单元中的至少一个可以被设置为邻近于集成电路芯片120的边缘。例如,如图12B所示,可以沿着集成电路芯片120的相应的相对边缘来设置占据相对较大面积的处理器件(诸如CPU1和GPU)。根据这种布局,至少一个其它核心功率单元可以与集成电路芯片的边缘间隔开,且其它单元介于所述至少一个其它核心功率单元与集成电路芯片的边缘之间,并且所述至少一个其它核心功率单元的功耗低于所述至少一个核心功率单元的功耗。另外,根据这种布局,多个低功率单元中的至少一个低功率单元可以被设置为与集成电路芯片120的边缘间隔开,且另一单元介于所述至少一个低功率单元与集成电路芯片120的边缘之间。例如,一个存储器单元MEMU2和一个输入输出单元IO2可以分别与集成电路芯片120的一个边缘间隔开,且另一存储器单元MEMU1介于存储器单元MEMU2和集成电路芯片120的一个边缘之间,另一输入输出单元IO1介于输入输出单元IO2和集成电路芯片120的一个边缘之间。
如图10所示,具有这种布局的集成电路芯片120可以允许具有相对大的功耗的单元被设置为更靠近去耦电容器180。可以沿着集成电路芯片120的与CPU1和GPU邻近的边缘设置多个电容器180。
例如,具有大功耗的CPU1和GPU可以设置在集成电路芯片120的两个相对的拐角中,并且多个电容器180可以沿着在每个拐角处相邻的两个边缘布置。这样,设置在集成电路芯片120的拐角中的核心功率单元可以允许通过利用两个相邻边缘将更多数量的电容器或具有更大电容的电容器设置为邻近于核心功率单元。
如上所述,当构成集成电路芯片120的多个单元包括具有第一功耗的第一单元和具有低于第一功耗的第二功耗的第二单元时,在集成电路芯片内,第一单元(例如,CPU1或GPU)可以设置为邻近于集成电路芯片120的一个边缘,第二单元(例如,MEMU2或IO2)可以比第一单元更靠内侧设置在集成电路芯片120上,并且多个电容器180可以设置为邻近于集成电路芯片120的所述一个边缘。
连接构件140可以包括连接到集成电路芯片120的连接电极122的重新分布层145。集成电路芯片120的连接电极122可以各自与单元中的每个接合,并且可以连接到重新分布层145的不同区域。如图9和图11所示,重新分布层145可以包括布线图案142以及将布线图案142彼此连接的过孔143。
如图11中所示,重新分布层145可以包括布线145',布线145'将与作为核心功率单元之一的GPU接合的连接电极122直接连接到与GPU相邻设置的电容器180。布线145'可以是电源布线。
特别地,在根据本示例性实施例的半导体封装件100中,邻近于集成电路芯片120的边缘设置的GPU和邻近于所述边缘的电容器可以通过短布线彼此连接,从而减小等效串联电感。结果,可以改善高频区域中的输入阻抗。另外,在本示例性实施例中,CPU1和GPU可以设置在集成电路芯片120的拐角中,并且因此可以使足够数量的电容器180沿着与每个拐角对应的相邻的两个边缘设置,由布线145'连接的电容器的总电容可以增加,结果,可以改善低频区域中的输入阻抗。
根据本示例性实施例的半导体封装件100在安装在主板上时可以包括电连接结构170(诸如导电凸块)。这种电连接结构170可以连接到重新分布层145。
由于半导体封装件100需要不间断的电力供应,所以可以邻近于设置在连接构件的第二表面上的电连接结构170另外地部署去耦电容器(未示出)。然而,给定的空间可能受限,并且可能难以设置足够数量的这种去耦电容器。此外,这种额外的去耦电容器的部署使得去耦电容器和集成电路芯片之间的电连接路径变大,从而导致等效串联电感增加。
在本示例性实施例中,电容器180可以设置为连接构件140的第一表面140A上邻近于集成电路芯片120,并且具有相对大的功耗的核心功率单元可以沿着邻近于电容器180的边缘设置。这可以用于缩短连接路径,并且同时可以允许设置具有足够电容的去耦电容器或者设置足够数量的去耦电容器以明显改善阻抗特性。
在下文中,将更详细地描述根据本示例性实施例的半导体封装件100的主要组件。
可以基于有源晶片形成集成电路芯片120。在这种情况下,集成电路芯片120的主体121的基体材料可以是硅(Si)、锗(Ge)、砷化镓(GaAs)等。可以通过半导体工艺在主体121上形成各种电路。连接电极122可以形成为将集成电路芯片120电连接到其它组件,并且连接电极122可以利用诸如铝(Al)等的导电材料形成,但不限于此。暴露连接电极122的钝化膜123可以形成在主体121上,并且钝化膜123可以包括氧化硅膜和/或氮化硅膜。连接电极122的下表面可以通过钝化膜123相对于包封剂130的下表面具有台阶。因此,可以在一定程度上防止包封剂130渗入到连接电极122的下表面中。
可以在支撑构件110上形成布线结构,以进一步简化连接构件140的重新分布层145。这允许对在形成连接构件140的复杂的重新分布层的工艺期间可能发生的缺陷引起的产量降低进行抑制,并且还允许制造具有较小厚度的封装件。支撑构件110可以包括绝缘层111以及第一布线图案112a和第二布线图案112b。第一布线图案112a和第二布线图案112b可以形成在绝缘层111的上表面和下表面上,然后可以通过贯穿绝缘层111的过孔113彼此连接,以实现期望的布线结构。
另外,支撑构件110可以形成为具有与集成电路芯片120的厚度对应的厚度,并且支撑构件110的第二布线图案112b可以与集成电路芯片120的有效表面和无效表面之间的位置对齐。集成电路芯片120的有效表面指的是集成电路芯片120的其上设置有连接电极122的表面,集成电路芯片120的无效表面指的是集成电路芯片120的与有效表面背对的表面。
由于支撑构件110在其厚度方面没有特别限制并且可以形成为对应于集成电路芯片120的厚度,因此支撑构件110可以通过传统的晶片工艺形成,而连接构件140的重新分布层145可以通过使用光刻的微图案形成技术形成,以具有更小的厚度。因此,支撑构件110的第一布线图案112a和第二布线图案112b的厚度可以大于连接构件140的重新分布层145的厚度。
支撑构件110的绝缘材料可以使用与无机填料混合的绝缘树脂。例如,支撑构件110的绝缘材料可以包括含有诸如无机填料的增强物的树脂以及诸如环氧树脂的热固性树脂或诸如聚酰亚胺的热塑性树脂,其中无机填料可以是二氧化硅、氧化铝等。特别地,支撑构件110的绝缘材料可包括ABF(Ajinomoto build-up film)、FR-4树脂、双马来酰亚胺三嗪(BT)树脂、感光电介质(PID)树脂等。另外,如果需要,可以使用其中将热固性树脂或热塑性树脂与无机填料一起浸渍在诸如玻璃纤维、玻璃布、玻璃织物等芯材中的材料,例如半固化片。
支撑构件110的第一布线图案112a和第二布线图案112b可以包括导电材料,诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。支撑构件110的贯穿绝缘层111的过孔113可以利用导电材料形成,并且可以与第一布线图案112a和第二布线图案112b的一部分一体化。
尽管未在附图中示出,但是如果需要,可以在腔110H的侧壁上另外设置金属层。金属层可用于有效地释放由集成电路芯片120产生的热和/或阻挡电磁波。特别地,可以存在多个腔110H,并且在多个腔110H中的每个腔中,可以设置集成电路芯片120和/或诸如电容器的无源组件,但是此处也可以使用现有技术中公知的其它结构。
包封剂130可以形成为保护集成电路芯片120、电容器180和支撑构件110。包封方案不受特别限制,只要其包封集成电路芯片120、电容器180和支撑构件110的至少一部分即可。例如,包封剂130可以覆盖集成电路芯片120的无效表面和支撑构件110的上表面,并且可以填充集成电路芯片120与支撑构件110之间的空间。在实施例中,包封剂130可以填充连接构件140和集成电路芯片120的钝化膜123之间的空间的至少一部分。在另一实施例中,根据包封剂130的材料,包封剂130可以用作粘合剂,同时通过填充腔110H而减小屈曲。
例如,包封剂130的材料不限于任何特定材料,例如,可以使用绝缘材料。这种绝缘材料可以是诸如环氧树脂的热固性树脂、诸如聚酰亚胺的热塑性树脂以及在热固性或热塑性树脂中含有无机填料的树脂,诸如ABF(Ajinomoto build-up film)、FR-4树脂、双马来酰亚胺三嗪(BT)树脂、感光电介质(PID)树脂等。另外,包封剂130可以使用先前在现有技术中公开的模制材料(诸如环氧模塑化合物(EMC)等),并且如果需要,还可以使用将热固性树脂或热塑性树脂与无机填料一起浸渍在诸如玻璃纤维等芯材中的树脂。
连接构件140可以将集成电路芯片120上的连接电极122重新分布。具有各种功能的数十到数百个连接电极122可以通过连接构件140重新分布,并且根据它们的功能可以通过电连接结构170物理和/或电气地连接到外部装置。连接构件140可以包括连接到集成电路芯片120的连接电极122并延伸至支撑构件110的下表面的重新分布层145。
连接构件140的重新分布层145可以连接到集成电路芯片120的连接电极122和支撑构件110的第一布线图案112a,以将集成电路芯片120和支撑构件110的重新分布结构进行电连接。
重新分布层145可以包括铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。以类似于针对第一布线图案112a和第二布线图案112b描述的方式,重新分布层145可以根据其相应层的设计执行各种功能。例如,重新分布层145可以包括接地(GND)图案、电源(PWR)图案、信号(S)图案等。
钝化层150被配置为保护连接构件140免受外部物理或化学损坏。钝化层150可以包括数十至数千个开口(O),以暴露连接构件140的重新分布层145的至少一部分。钝化层150可以使用感光绝缘材料,诸如感光绝缘树脂或阻焊材料,但不限于此。例如,钝化层150可以使用与无机填料混合的绝缘树脂,诸如ABF(Ajinomoto build-up film)等,并且当它使用与无机填料混合的绝缘树脂时,连接构件140的绝缘层141也可以包括与无机填料混合的绝缘树脂。
电连接结构170可以用作将半导体封装件100物理和/或电气地连接到外部装置(例如,主板)的连接端子。电连接结构170可以使用导电材料,例如低熔点合金(诸如Sn-Al-Cu)。电连接结构170可以是焊盘、球、引脚等。电连接结构170可以由多个层或单个层形成。
电连接结构170的数量、间隔、布置形式等不受特别限制,并且根据设计细节,可以被本领域技术人员充分地修改。例如,根据集成电路芯片120的连接电极122的数量,电连接结构170的数量可以从数十到数千,或者可以多于或少于数十到数千。
电连接结构170中的至少一个可以设置在扇出区域中。扇出区域指的是设置集成电路芯片120的区域之外的区域。与扇入型封装件相比,这种扇出型封装件可以具有提高的可靠性,可以实现多个输入/输出(I/O)端子,并且可以促进3D互连。另外,与球栅阵列(BGA)封装件、栅格阵列(LGA)封装件等相比,扇出型封装件可以在不使用单独的基板的情况下安装在电子装置中,因此可以被制造为具有减小的厚度以及更具价格竞争力。
在本示例性实施例中采用的电容器180可以是多层陶瓷电容器(MLCC),更具体地,可以是当前在现有技术中用作嵌入型的可以提供足够电容的多层陶瓷电容器(MLCC)。电容器180可用于实现低等效串联电感(ESL)并提供基础电容。
根据本公开的示例性实施例可以通过各种修改来实现。图13是示出根据本公开的一个示例性实施例的半导体封装件的示意性截面图,并且图14是沿图13中的线II-II'截取的半导体封装件的平面图。
参照图13和图14,可以理解,除了半导体封装件100A具有不同的基板结构、不包括支撑构件并且具有不同的集成电路芯片布局和不同的电容器布置,根据本示例性实施例的半导体封装件100A具有与图9和图10中所示的结构类似的结构。除非明确地相反描述,否则可以参照图9和图10中所示的半导体封装件100的相同或相似组件的描述来理解根据本示例性实施例的组件。
根据本示例性实施例的半导体封装件100A可以包括中介件240来代替连接构件。中介件240可以包括基板241、形成在基板241上的布线电路(未示出)以及分别设置在基板241的上表面和下表面上且通过布线电路连接的多个第一焊盘242和第二焊盘243。布线电路可以包括将电容器180和沿着集成电路芯片120的边缘设置的核心功率单元进行直接连接的布线245。
中介件240的基板241可以是硅基板。然而,中介件240的基板241不限于此,并且在另一示例中可以是印刷电路板(PCB)。例如,基板241可以利用诸如环氧树脂的热固性树脂或诸如聚酰亚胺的热塑性树脂形成,或者可以是感光绝缘层。外部端子270可以设置在位于中介件240的下表面上的多个第二焊盘243上。外部端子270可以包括选自锡(Sn)、镍(Ni)、金(Au)、银(Ag)、铜(Cu)和铋(Bi)中的至少一种金属,或可包括它们的合金。
集成电路芯片120可以倒装结合,使得其上设置有连接电极122的有效表面面对中介件240的上表面。中介件240的第一焊盘242和连接电极122可以结合到连接端子116。
在本示例性实施例中采用的集成电路芯片120中,核心功率单元可以设置为邻近于集成电路芯片120的一个边缘。例如,如图14所示,CPU1、CPU2、AI和GPU可以各自沿着集成电路芯片120的边缘设置或设置在集成电路芯片120的拐角中,而多个低功率单元的一部分(例如,IO2)可以与集成电路芯片120的边缘间隔开,且另一单元介于所述多个低功率单元的一部分与集成电路芯片120的边缘之间。
具有上述布局的集成电路芯片120可以允许具有相对大的功耗的单元被设置为更靠近去耦电容器180。可以沿着集成电路芯片120的与CPU1、CPU2、AI和GPU邻近的边缘设置多个这样的电容器180。与前面的示例性实施例不同,多个电容器180可以具有矩形结构,并且可以布置为使得多个电容器180中的每个电容器仅有一个端子邻近于所述边缘设置,从而可以布置更多的电容器,由此确保足够的电容。
特别地,消耗大量功率的CPU1和GPU可以设置在集成电路芯片120的两个拐角中,并且多个电容器180可以沿着与每个拐角对应的相邻的两个边缘布置。这样,设置在集成电路芯片120的拐角中的核心功率单元可以允许通过利用两个相邻边缘将更多数量的电容器或具有更大电容的电容器设置为邻近于核心功率单元。
如上所述,根据本公开的示例性实施例,在包括多个单元的集成电路芯片中,具有大功耗的单元可以邻近于所述芯片的边缘设置,并且电容器可以邻近于所述边缘设置以显著改善半导体封装件的电源完整性(PI)。
虽然已经在上面示出并描述了示例性实施例,但是对于本领域技术人员来说显而易见的是,在不脱离由所附权利要求限定的本发明的范围的情况下,可以进行修改和变化。
Claims (23)
1.一种半导体封装件,包括:
连接构件,具有彼此相对的第一表面和第二表面,并包括重新分布层;
集成电路芯片,设置在所述连接构件的所述第一表面上,具有连接到所述重新分布层的连接电极,并包括多个单元;
至少一个电容器,设置在所述连接构件的所述第一表面上并设置为邻近于所述集成电路芯片;和
包封剂,设置在所述连接构件的所述第一表面上,并包封所述集成电路芯片和所述至少一个电容器,
其中,所述多个单元包括核心功率单元,至少一个所述核心功率单元设置为邻近于所述集成电路芯片的第一边缘,
所述至少一个电容器设置为邻近于所述集成电路芯片的所述第一边缘。
2.根据权利要求1所述的半导体封装件,其中,所述重新分布层包括直接连接所述至少一个核心功率单元和所述至少一个电容器的布线。
3.根据权利要求1所述的半导体封装件,其中,所述至少一个电容器包括沿着所述集成电路芯片的所述第一边缘布置的多个电容器。
4.根据权利要求1所述的半导体封装件,其中,所述至少一个核心功率单元中的至少一个设置在所述集成电路芯片的拐角中,以便邻近于所述集成电路芯片的两个相交边缘。
5.根据权利要求4所述的半导体封装件,其中,沿着所述两个相交边缘布置有多个电容器。
6.根据权利要求1所述的半导体封装件,其中,所述多个单元还包括与所述集成电路芯片的边缘间隔开的至少一个其它核心功率单元,且其它单元介于所述至少一个其它核心功率单元与所述集成电路芯片的所述边缘之间,并且所述至少一个其它核心功率单元的功耗低于所述至少一个核心功率单元的功耗。
7.根据权利要求1所述的半导体封装件,其中,所述多个单元还包括多个低功率单元,所述多个低功率单元中的每个的功耗低于所述核心功率单元中的每个的功耗,并且所述多个低功率单元中的至少一个与所述集成电路芯片的边缘间隔开,且其它单元介于所述多个低功率单元中的所述至少一个低功率单元与所述集成电路芯片的所述边缘之间。
8.根据权利要求7所述的半导体封装件,其中,所述多个低功率单元包括从由接口单元、存储器单元和输入输出单元组成的组中选择的单元。
9.根据权利要求1所述的半导体封装件,所述半导体封装件还包括:支撑构件,设置在所述连接构件的所述第一表面上,并且具有容纳所述集成电路芯片和所述至少一个电容器的腔。
10.根据权利要求9所述的半导体封装件,其中,所述支撑构件包括:布线结构,连接所述支撑构件的上表面和下表面并连接到所述重新分布层。
11.根据权利要求1所述的半导体封装件,其中,所述核心功率单元包括从由中央处理单元、图形处理单元和人工智能单元组成的组中选择的单元。
12.一种半导体封装件,包括:
连接构件,具有彼此相对的第一表面和第二表面,并包括重新分布层;
集成电路芯片,设置在所述连接构件的所述第一表面上,具有连接到所述重新分布层的连接电极,并包括多个单元;
多个电容器,设置在所述连接构件的所述第一表面上并邻近于所述集成电路芯片;和
包封剂,设置在所述连接构件的所述第一表面上并包封所述集成电路芯片和所述多个电容器,
其中,所述多个单元包括:第一单元,具有第一功耗并且设置为邻近于所述集成电路芯片的边缘;以及第二单元,具有低于所述第一功耗的第二功耗并且相对于所述边缘比所述第一单元更靠内侧设置,并且
所述多个电容器设置为邻近于所述集成电路芯片的所述边缘。
13.根据权利要求12所述的半导体封装件,其中,所述第一单元包括从由中央处理单元、图形处理单元和人工智能单元组成的组中选择的至少一个单元。
14.根据权利要求12所述的半导体封装件,其中,包括多个所述第一单元,并且
所述多个第一单元邻近于所述集成电路芯片的一个边缘设置或设置在所述集成电路芯片的拐角中。
15.根据权利要求12所述的半导体封装件,其中,所述第二单元包括从接口单元、存储器单元和输入输出单元中选择的至少一个单元。
16.根据权利要求12所述的半导体封装件,其中,所述重新分布层包括直接连接所述第一单元和所述多个电容器的布线。
17.一种半导体封装件,包括:
集成电路芯片,包括设置为邻近于所述集成电路芯片的第一边缘的第一核心功率单元和第一其它单元,所述集成电路芯片设置在连接构件的第一表面上;
电容器,设置在所述连接构件的所述第一表面上并设置为邻近于所述集成电路芯片的所述第一边缘;和
包封剂,设置在所述连接构件的所述第一表面上并包封所述集成电路芯片和所述电容器中的每个的至少一部分,
其中,所述连接构件包括直接连接所述第一核心功率单元和所述电容器的布线层。
18.根据权利要求17所述的半导体封装件,其中,所述连接构件还包括连接到所述集成电路芯片的连接电极的重新分布层。
19.根据权利要求17所述的半导体封装件,其中,所述集成电路芯片还包括具有比所述第一核心功率单元的功耗低的功耗的第二核心功率单元,所述第二核心功率单元设置为相对于所述第一核心功率单元远离所述第一边缘,且其它单元介于所述第二核心功率单元与所述第一边缘之间。
20.根据权利要求17所述的半导体封装件,其中,所述第一其它单元具有比所述第一核心功率单元的功耗低的功耗。
21.根据权利要求17所述的半导体封装件,其中,所述第一核心功率单元选自由中央处理单元、图形处理单元和人工智能单元组成的组。
22.根据权利要求17所述的半导体封装件,其中,所述第一其它单元选自由接口单元、存储器单元和输入输出单元组成的组。
23.根据权利要求17所述的半导体封装件,其中,所述电容器的仅一个端子邻近于所述第一边缘设置。
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