TW202008522A - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
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- TW202008522A TW202008522A TW108106181A TW108106181A TW202008522A TW 202008522 A TW202008522 A TW 202008522A TW 108106181 A TW108106181 A TW 108106181A TW 108106181 A TW108106181 A TW 108106181A TW 202008522 A TW202008522 A TW 202008522A
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Abstract
一種半導體封裝包括:連接構件,具有彼此相對的第一表面及第二表面且包括重佈線層;積體電路晶片,配置於連接構件的第一表面上且包括多個單元;至少一個電容器,位於連接構件的第一表面上且靠近積體電路晶片;以及包封體,位於連接構件的第一表面上且包封積體電路晶片及所述至少一個電容器,其中所述多個單元包括選自由中央處理單元、圖形處理單元及人工智慧單元組成的群組的核心功率單元,核心功率單元中的至少一者鄰近積體電路晶片的一個邊緣配置,且所述至少一個電容器鄰近積體電路晶片的所述一個邊緣配置。
Description
本揭露是有關於一種半導體封裝。
已將對半導體晶片的技術發展的主要關注放在減小組件的尺寸方面,且隨著對小半導體晶片等的需求增加,在封裝領域中亟需在能夠具有多個引腳的同時尺寸更小的半導體封裝。為了滿足此種需求而提出的一種類型的封裝技術是扇出型半導體封裝。
此種半導體封裝包括包含大型積體電路(large-scale integration circuit,LSI)晶片的封裝,所述大型積體電路晶片亦被稱為微控制器單元(microcontroller unit,MCU)、微處理器單元(microprocessor unit,MPU)或系統晶片(system-on-a-chip,SOC)。此種半導體封裝可廣泛用於可攜式電子裝置,例如隨身型易網機個人電腦(netbook PC)、平板個人電腦、智慧型電話及可攜式視訊遊戲機。此外,即使在高速可攜式電子裝置(例如以上列出的裝置)中是典型的高速切換環境中,此種半導體封裝亦可能需要不中斷的電力供應。
本揭露的態樣可提供一種半導體封裝,所述半導體封裝藉由將其中的半導體晶片的內部設計以及電容器的位置最佳化而具有改善的電源完整性(power integrity,PI)。
根據本揭露的態樣,一種半導體封裝包括:連接構件,具有彼此相對的第一表面及第二表面且包括重佈線層;積體電路晶片,配置於所述連接構件的所述第一表面上,具有連接至所述重佈線層的連接電極,且由多個單元構成;至少一個電容器,靠近所述積體電路晶片配置於所述連接構件的所述第一表面上;以及包封體,配置於所述連接構件的所述第一表面上且包封所述積體電路晶片及所述至少一個電容器,其中所述多個單元包括選自由中央處理單元(central processing unit,CPU)、圖形處理單元(graphics processing unit,GPU)及人工智慧單元(artificial intelligence unit,AI)組成的群組的功率核心單元,核心功率單元中的至少一者鄰近所述積體電路晶片的一個邊緣配置,且所述至少一個電容器鄰近所述積體電路晶片的所述一個邊緣配置。
根據本揭露的另一態樣,一種半導體封裝包括:連接構件,具有彼此相對的第一表面及第二表面且包括重佈線層;積體電路晶片,配置於所述連接構件的所述第一表面上,具有連接至所述重佈線層的連接電極,且由多個單元構成;多個電容器,緊密地靠近所述積體電路晶片配置於所述連接構件的所述第一表面上;以及包封體,配置於所述連接構件的所述第一表面上且包封所述積體電路晶片及所述多個電容器,其中所述多個單元包括第一單元及第二單元,所述第一單元具有第一耗電率,所述第二單元具有較所述第一耗電率低的第二耗電率,所述第一單元鄰近所述積體電路晶片的一個邊緣配置,所述第二單元被配置成在所述積體電路晶片上較所述第一單元更向內,且所述多個電容器鄰近所述積體電路晶片的所述一個邊緣配置。
在下文中,將參照所附圖式闡述本揭露中的例示性實施例。在所附圖式中,為清晰起見,可誇大或縮小組件的形狀、尺寸等。
在本文中,下側、下部分、下表面等是用來指相對於圖式的剖面的朝向扇出型半導體封裝之安裝表面的方向,而上側、上部分、上表面等是用來指與所述方向相反的方向。然而,定義該些方向是為了方便闡釋,且本申請專利範圍並不受如上所述所定義的方向特別限制。
在說明中,組件與另一組件的「連接」的意義包括經由黏合層的間接連接以及在兩個組件之間的直接連接。另外,「電性連接」意為包括物理連接及物理斷接的概念。可理解,當以「第一」及「第二」來指稱元件時,所述元件不受其限制。使用用語「第一」、「第二」等可能僅用於將所述元件與其他元件區分開的目的,且可不限制所述元件的順序或重要性。在一些情形中,在不背離本文中所提出的申請專利範圍的範圍的條件下,第一元件可被稱作第二元件。相似地,第二元件亦可被稱作第一元件。
本文中所使用的用語「例示性實施例」並非指稱同一例示性實施例,而是為強調與另一例示性實施例的特定特徵或特性不同的特定特徵或特性而提供。然而,本文中所提供的例示性實施例被視為能夠藉由彼此整體組合或部分組合而實施。舉例而言,即使並未在另一例示性實施例中闡述在特定例示性實施例中闡述的一個元件,除非在另一例示性實施例中提供了相反或矛盾的說明,否則所述元件亦可被理解為與另一例示性實施例相關的說明。
本文中所使用的用語僅為闡述例示性實施例使用,而非限制本揭露。在此種情形中,除非在上下文中另有解釋,否則單數形式包括多數形式。電子裝置
圖1為示出電子裝置系統的實例的方塊示意圖。
參照圖1,電子裝置1000中可容置主板1010。主板1010可包括物理連接及/或電性連接至主板1010的晶片相關組件1020、網路相關組件1030、其他組件1040等。該些組件可連接至以下將闡述的其他組件,以形成各種訊號線1090。
晶片相關組件1020可包括:記憶體晶片,例如揮發性記憶體(例如動態隨機存取記憶體(dynamic random access memory,DRAM))晶片、非揮發性記憶體(例如唯讀記憶體(read only memory,ROM))晶片、快閃記憶體等;應用處理器晶片,例如中央處理器(例如,中央處理單元(CPU))、圖形處理器(例如,圖形處理單元(GPU))、數位訊號處理器、密碼處理器(cryptographic processor)、微處理器、微控制器等;及邏輯晶片,例如類比數位轉換器、應用專用積體電路(application-specific IC,ASIC)等。然而,晶片相關組件1020不限於此,而是亦可包括其他類型的晶片相關組件。另外,晶片相關組件1020可與彼此組合。
網路相關組件1030可包括例如以下協定:無線保真(wireless fidelity,Wi-Fi)(電氣及電子工程師學會(Institute of Electrical And Electronics Engineers,IEEE)802.11家族等)、全球互通微波存取(worldwide interoperability for microwave access,WiMAX)(IEEE 802.16家族等)、IEEE 802.20、長期演進(long term evolution,LTE)、僅支援資料的演進(evolution data only,Ev-DO)、高速封包存取+(high speed packet access +,HSPA+)、高速下行封包存取+(high speed downlink packet access +,HSDPA+)、高速上行封包存取+(high speed uplink packet access +,HSUPA+)、增強型資料GSM環境(enhanced data GSM environment,EDGE)、全球行動通訊系統(global system for mobile communications,GSM)、全球定位系統(global positioning system,GPS)、通用封包無線電服務(general packet radio service,GPRS)、分碼多重存取(code division multiple access,CDMA)、分時多重存取(time division multiple access,TDMA)、數位增強型無線電訊(digital enhanced cordless telecommunications,DECT)、藍芽、3G協定、4G協定及5G協定以及繼上述協定之後指定的任何其他無線協定及有線協定。然而,網路相關組件1030不限於此,而是可包括多種其他無線標準或協定或者有線標準或協定。另外,網路相關組件1030可與上述的晶片相關組件1020一起彼此組合。
其他組件1040可包括高頻電感器、鐵氧體電感器(ferrite inductor)、功率電感器(power inductor)、鐵氧體珠粒(ferrite beads)、低溫共燒陶瓷(low temperature co-fired ceramic,LTCC)、電磁干擾(electromagnetic interference,EMI)濾波器、多層陶瓷電容器(multilayer ceramic capacitor,MLCC)等。然而,其他組件1040並非僅限於此,而是亦可包括用於各種其他目的的被動組件等。另外,其他組件1040可與上文所闡述的晶片相關組件1020及/或網路相關組件1030一起彼此組合。
端視電子裝置1000的類型,電子裝置1000可包括可物理連接至或電性連接至主板1010的其他組件,或可不物理連接至或不電性連接至主板1010的其他組件。該些其他組件可包括例如照相機1050、天線1060、顯示器1070、電池1080、音訊編解碼器(圖中未示出)、視訊編解碼器(圖中未示出)、功率放大器(圖中未示出)、羅盤(圖中未示出)、加速度計(圖中未示出)、陀螺儀(圖中未示出)、揚聲器(圖中未示出)、大容量儲存單元(例如硬碟驅動機)(圖中未示出)、光碟(compact disk,CD)驅動機(圖中未示出)、數位多功能光碟(digital versatile disk,DVD)驅動機(圖中未示出)等。然而,該些其他組件不限於此,而是亦可端視電子裝置1000的類型而包括用於各種目的的其他組件等。
電子裝置1000可為智慧型電話、個人數位助理(personal digital assistant,PDA)、數位攝影機、數位照相機(digital still camera)、網路系統、電腦、監視器、平板個人電腦(tablet PC)、膝上型個人電腦、隨身型易網機個人電腦(netbook PC)、電視、視訊遊戲機(video game machine)、智慧型手錶或汽車組件等。然而,電子裝置1000並非僅限於此,而是亦可為處理資料的任何其他電子裝置。
圖2為示出電子裝置的實例的立體示意圖。
參照圖2,半導體封裝可在各種電子裝置(例如上述電子裝置)中用於各種目的。舉例而言,主板1110可容置於智慧型電話1100的本體1101中,且各種電子組件1120可物理連接至或電性連接至主板1110。另外,可物理連接至及/或電性連接至主板1010或可不物理連接至及/或不電性連接至主板1010的其他組件(例如照相機模組1130)可容置於本體1101中。電子組件1120中的一些電子組件可為晶片相關組件,且半導體封裝100可例如為晶片相關組件之中的應用處理器,但並非僅限於此。所述電子裝置未必限於智慧型電話1100,而是可為如上所述的其他電子裝置。半導體封裝
一般而言,在半導體晶片中整合有許多精密的電路。然而,半導體晶片單靠自身不能充當已完成的半導體產品,且可能處於因外部物理性或化學性影響而受損的風險下。因此,半導體晶片無法在被暴露狀態下使用,而是被封裝並以封裝狀態在電子裝置等中使用。
由於半導體晶片與電子裝置的主板之間存在電性連接方面的電路寬度差異,因而需要半導體封裝。詳言之,在半導體晶片的情形中,連接墊的尺寸及各連接墊之間的間隔極為精密,而在電子裝置中使用的主板的情形中,組件安裝墊的尺寸及各組件安裝墊之間的間隔顯著大於半導體晶片的連接墊的尺寸及間隔。因此,可能難以將半導體晶片直接安裝於主板上,且可能需要用於緩衝半導體晶片與主板之間的電路寬度差異的封裝技術。
端視半導體封裝的結構及預期用途而定,藉由此種封裝技術所製造的半導體封裝可分類為扇入型半導體封裝或扇出型半導體封裝。
在下文中將參照所附圖式更詳細地闡述扇入型半導體封裝及扇出型半導體封裝。扇入型 半導體封裝
圖3A及圖3B為示出扇入型半導體封裝在封裝前及封裝後狀態的剖面示意圖,且圖4為示出扇入型半導體封裝的封裝製程的剖面示意圖。
參照圖3A、圖3B及圖4,半導體晶片2220可例如是處於裸露狀態下的積體電路(integrated circuit,IC),半導體晶片2220包括:本體2221,包含矽(Si)、鍺(Ge)、砷化鎵(GaAs)等;連接墊2222,形成於本體2221的一個表面上且包含例如鋁(Al)等導電材料;以及鈍化層2223,其是氧化物膜或氮化物膜等,且形成於本體2221的一個表面上且覆蓋連接墊2222的至少部分。
因此,根據半導體晶片2220的特定尺寸,可在半導體晶片2220上形成連接構件2240,以對連接墊2222進行重佈線。連接構件2240可藉由以下步驟來形成:利用例如感光成像介電(photoimageable dielectric,PID)樹脂等絕緣材料在半導體晶片2220上形成絕緣層2241,然後形成敞開連接墊2222的通孔孔洞2243h,並接著形成配線圖案2242及通孔2243。隨後,可形成鈍化層2250以保護連接構件2240,且可形成開口2251,並且接著可形成凸塊下金屬層2260等。因此,可如上所述藉由一系列製程來製造包括例如半導體晶片2220、連接構件2240、鈍化層2250及凸塊下金屬層2260的扇入型半導體封裝2200。
如上所述,扇入型半導體封裝可呈其中半導體晶片的所有連接墊(例如,輸入/輸出(input/output,I/O)端子)都配置於半導體晶片內的一種封裝形式。另外,扇入型半導體封裝可具有期望的電性特性且可便宜地製造。因此,安裝在智慧型電話中的許多元件已以扇入型半導體封裝形式製造,且具體而言,已開發出安裝在智慧型電話中的許多元件以進行快速的訊號傳輸並同時具有緊湊的尺寸。
然而,由於扇入型半導體晶片需要將所有輸入/輸出端子均配置於半導體晶片內,因此扇入型半導體封裝具有顯著的空間限制。因此,難以將此結構應用於具有大量輸入/輸出端子的半導體晶片或具有小尺寸的半導體晶片。另外,由於上述此種缺點,扇入型半導體封裝可能無法在電子裝置的主板上直接安裝及使用,此乃因即使當藉由重佈線製程來增大半導體晶片的輸入/輸出端子的尺寸以及各輸入/輸出端子之間的間隔時,半導體晶片的輸入/輸出端子的尺寸以及各輸入/輸出端子之間的間隔可能仍不足以適於容許扇入型半導體封裝直接安裝於電子裝置的主板上。
圖5為示出扇入型半導體封裝安裝於中介基板上且最終安裝於電子裝置的主板上之情形的剖面示意圖。圖6為示出扇入型半導體封裝嵌入中介基板中且最終安裝於電子裝置的主板上之情形的剖面示意圖。
參照圖5及圖6,在扇入型半導體封裝2200中,半導體晶片2220的連接墊2222(其為輸入/輸出端子)可經由中介基板2301再次進行重佈線,且接著扇入型半導體封裝2200在被安裝於中介基板2301上的同時可最終安裝於電子裝置的主板2500上。在此種情形中,可藉由底部填充樹脂2280等來固定低熔點金屬或合金球2270等,且扇入型半導體封裝2200的外側可以包封體2290等覆蓋。或者,扇入型半導體封裝2200可嵌入單獨的中介基板2302中,且半導體晶片2220的作為輸入/輸出端子的連接墊2222可藉由中介基板2302再次進行重佈線,並且接著扇入型半導體在被嵌入中介基板2302中的同時可最終安裝於電子裝置的主板2500上。
如上所述,可能難以在電子裝置的主板上直接安裝並使用扇入型半導體封裝。因此,扇入型半導體封裝可藉由首先安裝於單獨的中介基板上並接著藉由封裝製程安裝於電子裝置的主板上來使用。或者,扇入型半導體封裝可藉由在被嵌入中介基板中的同時安裝於電子裝置的主板上來使用。扇出型 半導體封裝
圖7為示出扇出型半導體封裝的剖面示意圖。
參照圖7,在扇出型半導體封裝2100中,舉例而言,半導體晶片2120的外側可由包封體2130保護,且半導體晶片2120的連接墊2122可藉由連接構件2140而甚至在半導體晶片2120之外進行重佈線。在此種情形中,可在連接構件2140上進一步形成鈍化層2150,且可在鈍化層2150的開口中進一步形成凸塊下金屬層2160。可在凸塊下金屬層2160上進一步形成低熔點金屬或合金球2170。半導體晶片2120可為包括本體2121、連接墊2122、鈍化膜(圖中未示出)等的積體電路(IC)。連接構件2140可包括絕緣層2141;重佈線層2142,形成於絕緣層2141上;及通孔2143,將連接墊2122、重佈線層2142等彼此電性連接。
在本製造製程中,可在半導體晶片2120之外形成包封體2130之後形成連接構件2140。在此種情形中,在包封半導體晶片2120之後執行用於連接構件2140的製程,且因此連接至重佈線層的通孔2143可被形成為具有隨著通孔2143靠近半導體晶片2120而變得更小的寬度(請參照放大區)。
如上所述,扇出型半導體封裝具有其中半導體晶片的輸入/輸出端子藉由形成於半導體晶片上的連接構件甚至在半導體晶片之外進行重佈線並配置的一種形式。在一個方面,扇入型半導體封裝具有其中半導體晶片的所有輸入/輸出端子均需要配置於半導體晶片內的一種形式,只要半導體晶片的尺寸減小,則球的尺寸及間距亦需要減小,因而使得標準化球佈局無法應用於扇入型半導體封裝中。另一方面,如上所述,扇出型半導體封裝具有其中半導體晶片的輸入/輸出端子藉由形成於半導體晶片上的連接構件甚至在半導體晶片之外進行重佈線並配置的一種形式,因此即使當半導體晶片的尺寸減小時,標準化球佈局亦可照樣在扇出型半導體封裝中使用。因此,扇出型半導體封裝無需使用單獨的中介基板即可安裝於電子裝置的主板上,如下文將闡述。
圖8為示出扇出型半導體封裝安裝於電子裝置的主板上之情形的剖面示意圖。
參照圖8,扇出型半導體封裝2100可經由低熔點金屬或合金球2170等安裝於電子裝置的主板2500上。更具體而言,如上所述,由於扇出型半導體封裝2100可包括形成於半導體晶片2120上且能夠甚至將連接墊2122重佈線至半導體晶片2120的特定尺寸之外的扇出區域的連接構件2140,因此扇出型半導體封裝2100可容許照樣使用標準化球佈局,且因此,無需使用單獨的中介基板等即可安裝於電子裝置的主板2500上。
如上所述,由於扇出型半導體封裝無需使用單獨的中介基板即可安裝於電子裝置的主板上,因此扇出型半導體封裝可被達成為具有較使用中介基板的扇入型半導體封裝的厚度小的厚度。因此,扇出型半導體封裝可小型化及薄化。另外,扇出型半導體封裝具有優異的熱特性及電性特性,且因此尤其適合用於行動產品。此外,扇出型半導體封裝可以較使用印刷電路板(printed circuit board,PCB)的一般疊層封裝(package-on-package,POP)型封裝的形式更緊湊的形式來達成,且可解決由翹曲(warpage)引起的問題。
如上所述,扇出型半導體封裝是指能夠將半導體晶片安裝在電子裝置的主板等上,並進一步保護半導體晶片免於外部影響的封裝技術。因此,扇出型半導體封裝是基於與例如中介基板等印刷電路板(PCB)不同的概念,所述印刷電路板中嵌有扇入型半導體封裝,且具有與扇出型半導體封裝不同的規格、不同的用途等。
圖9為示出根據例示性實施例的半導體封裝的剖面示意圖。圖10為示出沿圖9中的I-I'線截取的半導體封裝的平面圖。
參照圖9及圖10,根據本例示性實施例的半導體封裝100可包括:連接構件140,具有彼此相對的第一表面140A及第二表面140B,且包括重佈線層145;積體電路晶片120,配置於連接構件140的第一表面140A上,且具有連接至重佈線層的連接電極122;多個電容器180,緊密地靠近積體電路晶片120而配置於連接構件140的第一表面140A上;以及包封體130,配置於連接構件140的第一表面140A上,且包封積體電路晶片120及所述多個電容器180。
在本例示性實施例中,半導體封裝100可包括支撐構件110,支撐構件110配置於連接構件的第一表面上且具有空腔110H。積體電路晶片120及所述多個電容器180可容置於空腔110H中。
另外,半導體封裝100可更包括:鈍化層150,配置於連接構件140的第二表面140B上;凸塊下金屬(underbump metal,UBM)層160,配置於鈍化層150上且經由鈍化層150的開口(O)連接至重佈線層;以及電性連接結構170,配置於凸塊下金屬層160上。
在本例示性實施例中使用的積體電路晶片120可為由多個單元構成的半導體晶片,且可包括包含各種邏輯電路以及記憶體電路的大型積體電路晶片(LSI)。此種積體電路晶片120可被稱為微控制器單元(MCU)、微處理器單元(MPU)或系統晶片(SOC)。舉例而言,積體電路晶片120可藉由使用先前揭露的半導體製造技術形成於例如矽等單一半導體基板上。
如圖10所示,所述多個單元可包括中央處理單元CPU1及中央處理單元CPU2、圖形處理單元GPU、人工智慧單元AI、輸入輸出單元IO1、輸入輸出單元IO2、輸入輸出單元IO3、輸入輸出單元IO4、輸入輸出單元GPIO1及輸入輸出單元GPIO2以及記憶體單元MEMU1、記憶體單元MEMU2、記憶體單元MEMU3及記憶體單元MEMU4。
中央處理單元CPU1及中央處理單元CPU2可控制半導體裝置,且圖形處理單元GPU可執行影像處理。輸入輸出單元IO1及輸入輸出單元IO2可為用於在積體電路晶片120與外部裝置之間執行資料的輸入及輸出的介面。記憶體單元MEMU1、記憶體單元MEMU2、記憶體單元MEMU3及記憶體單元MEMU4可為以下記憶體:例如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(static random access memory,SRAM)、快閃記憶體、相變化記憶體(phase-change memory,PRAM)、電阻式隨機存取記憶體(resistive random access memory,ReRAM)、鐵電式隨機存取記憶體(ferroelectric random access memory,FeRAM)或磁阻式隨機存取記憶體(magnetoresistive random access memory,MRAM)。
另外,積體電路晶片120可根據其用途而更包括中斷控制器(interrupt controller,INTC)、通訊單元(communication unit,CMU)、直接記憶體存取控制器(direct memory access controller,DMAC)、類比至數位轉換器(analog-to-digital convertor,ADC)以及時鐘脈波產生器(clock pulse generator,CPG)。
積體電路晶片120的上述單元可根據其耗電率來分類。在本揭露中,具有相對大耗電率的單元可被稱為「核心功率單元」,且具有相對低耗電率的單元可被稱為「低功率單元」。
在本例示性實施例中,中央處理單元CPU1及中央處理單元CPU2、圖形處理單元GPU及/或人工智慧單元AI可對應於核心功率單元,且輸入輸出單元IO1至輸入輸出單元IO4、輸入輸出單元GPIO1及輸入輸出單元GPIO2或記憶體單元可對應於低功率單元。
根據此種耗電率,可對構成積體電路晶片的單元的佈局進行修改。圖12A及圖12B為闡述積體電路晶片上的各種單元的佈局變化的方塊圖。具體而言,圖12A所示佈局可被理解為修改之前的例示性實施例,且圖12B所示佈局可被理解為修改之後的例示性實施例。
參照圖12A,在傳統的積體電路晶片120中,具有大耗電率的核心功率單元由於其佔據相對較大的面積,通常配置於晶片區域內,而趨於佔據相對較小面積的低功率單元(例如,輸入輸出單元IO1至輸入輸出單元IO4、輸入輸出單元GPIO1及輸入輸出單元GPIO2)通常鄰近晶片的邊緣配置,以有利於與外部裝置進行的輸入及輸出。
另一方面,在本例示性實施例中使用的積體電路晶片中,核心功率單元中的至少一者可鄰近積體電路晶片120的邊緣配置。舉例而言,如圖12B所示,佔據相對較大面積的處理裝置(例如中央處理單元CPU1及圖形處理單元GPU)可沿著積體電路晶片120的各相對邊緣配置。根據此種佈局,多個低功率單元中的至少一者可被配置成面對積體電路晶片120的邊緣,且其間插置有另一單元。舉例而言,一個記憶體單元MEMU2及一個輸入輸出單元IO2可分別與積體電路晶片120的一個邊緣間隔開,且其間分別插置有另一記憶體單元MEMU1及另一輸入輸出單元IO1。
如圖10所示,具有此種佈局的積體電路晶片120可容許具有相對大耗電率的單元被配置成更靠近去耦電容器180。所述多個電容器180可沿著積體電路晶片120的邊緣配置,且具有鄰近其配置的中央處理單元CPU1及圖形處理單元GPU。
舉例而言,具有大耗電率的中央處理單元CPU1及圖形處理單元GPU可配置於積體電路晶片120的兩個相對的隅角中,且所述多個電容器180可沿著每一隅角處相鄰的兩個邊緣排列。因此,配置於積體電路晶片120的隅角中的核心功率單元可藉由利用所述兩個相鄰的邊緣而容許更大數目的電容器或具有更大電容的電容器鄰近核心功率單元配置。
如上所述,當構成積體電路晶片120的所述多個單元包括具有第一耗電率的第一單元以及具有較第一耗電率低的第二耗電率的第二單元時,在積體電路晶片內,第一單元(例如,中央處理單元CPU1或圖形處理單元GPU)可鄰近積體電路晶片120的一個邊緣配置,第二單元(例如,記憶體單元MEMU2或輸入輸出單元IO2)可被配置成在積體電路晶片120上較第一單元更向內,且所述多個電容器180可鄰近積體電路晶片120的所述一個邊緣配置。
連接構件140可包括連接至積體電路晶片120的連接電極122的重佈線層145。積體電路晶片120的連接電極122可分別與所述單元中的每一者接合,且可連接至重佈線層145的不同區域。
如圖11所示,重佈線層145可包括配線145',配線145'將與作為核心功率單元中的一者的圖形處理單元GPU接合的連接電極122直接連接至鄰近其配置的電容器180。配線145'可為電源配線(power wiring line)。
具體而言,在根據本例示性實施例的半導體封裝100中,鄰近積體電路晶片120的邊緣配置的圖形處理單元GPU與鄰近所述邊緣的電容器可經由短配線P彼此連接,藉此減小等效串聯電感(equivalent series inductance)。因此,可改善高頻區域中的輸入阻抗。另外,在本例示性實施例中,中央處理單元CPU1及圖形處理單元GPU可配置於積體電路晶片120的隅角中,且因此可能夠使足夠數目的電容器180沿著鄰近於每一隅角的兩個邊緣配置,可增加由配線145連接的電容器的總電容,且因此可改善低頻區域中的輸入阻抗。
根據本例示性實施例的半導體封裝100當安裝於主板上時,可包括電性連接結構170,例如導電凸塊。此種電性連接結構170可連接至重佈線層145。
由於半導體封裝100需要不間斷的電力供應,因此可鄰近配置於連接構件的第二表面上的電性連接結構170額外部署去耦電容器(圖中未示出)。然而,給定的空間可能是有限的,且可能難以配置足夠數目的這樣的去耦電容器。此外,額外的去耦電容器的此種部署會導致去耦電容器與積體電路晶片之間的電性連接通路變得更大,因而導致等效串聯電感增加。
在本例示性實施例中,電容器180可鄰近積體電路晶片120配置於連接構件140的第一表面140A上,且具有相對大耗電率的核心功率單元可沿著鄰近電容器180的邊緣配置。此可用於縮短連接通路,且同時可容許提供具有足夠電容的去耦電容器或足夠數目的去耦電容器以顯著改善阻抗特性。
在下文中,將更詳細闡述根據本例示性實施例的半導體封裝100的主要組件。
積體電路晶片120可基於主動晶圓而形成。在此種情形中,積體電路晶片120的本體121的基礎材料(base material)可為矽(Si)、鍺(Ge)、砷化鎵(GaAs)等。可藉由半導體製程在本體121上形成各種電路。連接電極122可被形成以將積體電路晶片120電性連接至其他組件,且可由例如鋁(Al)等導電材料形成,但不限於此。可在本體121上形成暴露出連接電極122的鈍化膜123,且鈍化膜123可包括氧化矽膜及/或氮化矽膜。藉由鈍化膜123,連接電極122的下表面可具有相對於包封體130的下表面的台階。因此,可在一定程度上防止包封體130滲出至連接電極122的下表面中。
可在支撐構件110上形成配線結構,以進一步簡化連接構件140的重佈線層145。此使得能夠抑制由在形成連接構件140的複雜重佈線層的製程期間可能發生的缺陷引起的良率降低,且進一步使得能夠製造具有較小厚度的封裝。可在支撐構件110的上表面及下表面上形成第一配線圖案112a及第二配線圖案112b,且接著可經由晶片貫通孔(圖中未示出)將第一配線圖案112a與第二配線圖案112b彼此連接以達成期望的配線結構。
另外,支撐構件110可被形成為具有與半導體晶片120的厚度對應的厚度,且支撐構件110的第二配線圖案112b可配置於半導體晶片120的主動面與非主動面之間。
由於支撐構件110在其厚度方面不受特別限制且可被形成為與積體電路晶片120的厚度對應,因此支撐構件110可藉由傳統晶圓製程來形成,而連接構件140的重佈線層145可藉由微圖案形成技術使用微影法而被形成為具有甚至更小的厚度。因此,支撐構件110的第一配線圖案112A及第二配線圖案112B的厚度可大於連接構件140的重佈線層145的厚度。
支撐構件110的絕緣材料可使用與無機填料混合的絕緣樹脂。舉例而言,支撐構件110的絕緣材料可包括含有加強材(例如無機填料)的樹脂以及例如環氧樹脂等熱固性樹脂或例如聚醯亞胺等熱塑性樹脂,其中所述無機填料可為二氧化矽、氧化鋁等。具體而言,支撐構件110的絕緣材料可包括味之素構成膜(Ajinomoto build-up film,ABF)、FR-4樹脂、雙馬來醯亞胺三嗪(bismaleimide triazine,BT)樹脂、感光成像介電樹脂(PID)等。另外,若需要,則可使用其中將熱固性樹脂或熱塑性樹脂與無機填料一起浸入例如玻璃纖維、玻璃布、玻璃纖維布等核心材料中的材料,例如預浸體。
支撐構件110的第一配線圖案112A及第二配線圖案112B可包含導電材料,例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)、或其合金。支撐構件110的晶片貫通孔可由導電材料形成,且可與第一配線圖案112A及第二配線圖案112B的部分整合。
儘管圖式中未示出,然而若需要,則可在空腔110H的側壁上另外配置金屬層。所述金屬層可用於有效地釋放由積體電路晶片120產生的熱量及/或阻擋電磁波。具體而言,可存在多個空腔110H,且在所述多個空腔110H中的每一者中,可配置積體電路晶片120或例如電容器等被動組件,但此處亦可使用先前技術中眾所習知的其他結構。
包封體130可被形成以保護積體電路晶片120、電容器180及支撐構件110。包封方案不受特別限制,只要包封方案包封積體電路晶片120、電容器180及支撐構件110的至少部分即可。舉例而言,包封體130可覆蓋積體電路晶片120的非主動面以及支撐構件110的上表面,且可填充積體電路晶片120的非主動面與支撐構件110的上表面之間的空間。在實施例中,包封體130可填充連接構件140與積體電路晶片120的鈍化膜123之間的空間的至少一部分。在另一實施例中,端視包封體130的材料而定,包封體130可在藉由填充空腔110H來減少彎曲的同時用作黏合劑。
舉例而言,包封體130的材料不限於任何特定材料,且例如可使用絕緣材料。此種絕緣材料可為熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺;以及除熱固性樹脂或熱塑性樹脂之外還含有無機填料的樹脂,例如味之素構成膜(ABF)、FR-4樹脂、雙馬來醯亞胺三嗪(BT)樹脂、感光成像介電樹脂(PID)等。另外,包封體139可使用之前在先前技術中揭露的模製材料,例如環氧模製化合物(epoxy molding compound,EMC)等,且若需要,則亦可使用具有熱固性樹脂或熱塑性樹脂與無機填料一起浸入例如玻璃纖維等核心材料中的樹脂。
連接構件140可對積體電路晶片120上的連接電極122進行重佈線。具有各種功能的數十至數百個連接電極122可藉由連接構件140進行重佈線,且可端視其功能而經由電性連接結構170物理連接及/或電性連接至外部裝置。連接構件140可連接至積體電路晶片120的連接電極122,以包括在支撐構件110的下表面上延伸的重佈線層145。
連接構件140的重佈線層145可連接至積體電路晶片120的連接電極122以及支撐構件110的第一配線圖案112a,以電性連接積體電路晶片120與支撐構件110的重佈線結構。
重佈線層145可包含銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)、或其合金。以與針對第一配線圖案112a及第二配線圖案112b所闡述的方式相似的方式,重佈線層145可根據其對應層的設計而執行各種功能。舉例而言,重佈線層145可包括接地(GND)圖案、電源(PWR)圖案、訊號(S)圖案等。
鈍化層150被配置以保護連接構件140免受外部物理或化學損害。鈍化層150可包括暴露出連接構件140的重佈線層145的至少一部分的數十至數千個開口(O)。鈍化層150可使用感光成像絕緣材料,例如感光成像絕緣樹脂或阻焊劑材料,而不限於此。舉例而言,鈍化層150可使用與無機填料混合的絕緣樹脂,例如味之素構成膜(ABF)等,且此時,連接構件140的絕緣層141亦可包含與無機填料混合的絕緣樹脂。
電性連接結構170可用作用於將半導體封裝100物理連接及/或電性連接至外部裝置(例如,主板)的連接端子。電性連接結構170可使用導電材料,例如低熔點合金(例如Sn-Al-Cu)。電性連接結構170可為接腳、球或引腳等。電性連接結構170可由多層或單層形成。
電性連接結構170的數目、間隔、配置形式等不受特別限制,且可由熟習此項技術者端視設計特定細節進行充分地修改。舉例而言,電性連接結構170的數目可根據積體電路晶片120的連接電極122的數目而為數十至數千個,或者可多於或少於數十至數千個。
電性連接結構170中的至少一者可配置於扇出區域中。所述扇出區域是指其中配置有積體電路晶片120的區域之外的區域。此種扇出型封裝相較於扇入型封裝而言可具有提高的可靠性,可實施多個輸入/輸出(I/O)端子,且可有利於三維(3D)內連線。另外,相較於球柵陣列(ball grid array,BGA)封裝、接腳柵陣列(land grid array,LGA)封裝等而言,扇出型封裝無需使用單獨的基板即可安裝於電子裝置中,且因此可被製造成具有減小的厚度且更具價格競爭力。
在本例示性實施例中採用的電容器180可為可提供足夠電容的多層陶瓷電容器(MLCC),且更具體而言,為當前在先前技術中作為嵌入型使用的多層陶瓷電容器(MLCC)。電容器180可用於達成低等效串聯電感(equivalent serial inductance,ESL)且提供基極電容(base capacitance)。
根據本揭露的例示性實施例可以各種修改實施。圖13為示出根據本揭露一個例示性實施例的半導體封裝的剖面示意圖,且圖14為沿圖13中的II-II'線截取的半導體封裝的平面圖。
參照圖13及圖14,可以理解,除了半導體封裝100A具有不同的基板結構、不包括支撐構件、且具有不同的積體電路晶片佈局以及不同的電容器佈置以外,根據本例示性實施例的半導體封裝100A具有與圖9及圖10所示結構相似的結構。除非作出明確相反的闡述,否則根據本例示性實施例的組件可參照對圖9及圖10所示半導體封裝100的相同或相似組件的說明來理解。
根據本例示性實施例的半導體封裝100A可包括中介層240來代替連接構件。中介層240可包括:基板241;配線電路(圖中未示出),形成於基板241上;以及多個第一接墊242及第二接墊243,分別配置於基板241的上表面及下表面上並藉由配線電路連接。配線電路可包括直接連接電容器180與沿著積體電路晶片120的邊緣配置的核心功率單元的配線245。
中介層240的基板241可為矽基板。然而,中介層240的基板241不限於此,且在另一實例中可為印刷電路板(PCB)。舉例而言,基板241可由例如環氧樹脂等熱固性樹脂或例如聚醯亞胺等熱塑性樹脂形成,或者可為感光成像絕緣層。可在位於中介層240的下表面上的多個第二接墊243上設置外部端子270。外部端子270可包含選自錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、銅(Cu)及鉍(Bi)的至少一種金屬,或者可包含其合金。
積體電路晶片120可被覆晶接合成使得上面配置有連接電極122的主動面面對中介層240的上表面。中介層240的第一接墊242以及連接電極122可接合至連接端子116。
在本例示性實施例中所採用的積體電路晶片120中,核心功率單元可鄰近積體電路晶片120的一個邊緣配置。舉例而言,如圖14所示,中央處理單元CPU1、中央處理單元CPU2、人工智慧單元AI以及圖形處理單元GPU可分別沿著積體電路晶片120的邊緣或在積體電路晶片120的隅角中配置,而多個低功率單元的一部分(例如,輸入輸出單元IO2)可與積體電路晶片120的邊緣間隔開,且其間插置有另一單元。
具有上述佈局的積體電路晶片120可容許具有相對大耗電率的單元被配置成甚至更靠近去耦電容器180。可沿著積體電路晶片120的邊緣配置多個此種電容器180,使得中央處理單元CPU1、中央處理單元CPU2、人工智慧單元AI及圖形處理單元GPU鄰近所述多個此種電容器180配置。與前面的例示性實施例不同,所述多個電容器180可具有矩形結構,且可被排列成使得所述多個電容器180中的每一者的僅一個端子鄰近邊緣配置,進而使得可排列更多電容器以由此確保足夠的電容。
具體而言,消耗大量電力的中央處理單元CPU1及圖形處理單元GPU可配置於積體電路晶片120的兩個隅角中,且所述多個電容器180可沿著鄰近於每一隅角的兩個邊緣排列。因此,配置於積體電路晶片120的隅角中的核心功率單元可藉由利用兩個相鄰的邊緣而容許更大數目的電容器或具有更大電容的電容器鄰近核心功率單元配置。
如上所述,根據本揭露的例示性實施例,在包括多個單元的積體電路晶片中,具有大耗電率的多個單元可鄰近晶片的邊緣配置,且電容器可鄰近邊緣配置以顯著改善半導體封裝的電源完整性(PI)。
儘管以上已示出並闡述了例示性實施例,然而對於熟習此項技術者而言將顯而易見的是,在不背離由隨附申請專利範圍所界定的本發明的範圍的條件下,可作出修改及變型。
100、100A‧‧‧半導體封裝110‧‧‧支撐構件110H‧‧‧空腔112a‧‧‧第一配線圖案112b‧‧‧第二配線圖案116‧‧‧連接端子120、120'‧‧‧積體電路晶片121、1101、2121、2221‧‧‧本體122‧‧‧連接電極123‧‧‧鈍化膜130、2130、2290‧‧‧包封體140、2140、2240‧‧‧連接構件140A‧‧‧第一表面140B‧‧‧第二表面141、2141、2241‧‧‧絕緣層145、2142‧‧‧重佈線層145'、245‧‧‧配線150、2150、2223、2250‧‧‧鈍化層160、2160、2260‧‧‧凸塊下金屬(UBM)層170‧‧‧電性連接結構180‧‧‧電容器/去耦電容器240‧‧‧中介層241‧‧‧基板242‧‧‧第一接墊243‧‧‧第二接墊270‧‧‧外部端子1000‧‧‧電子裝置1010、1110、2500‧‧‧主板1020‧‧‧晶片相關組件1030‧‧‧網路相關組件1040‧‧‧其他組件1050‧‧‧照相機1060‧‧‧天線1070‧‧‧顯示器1080‧‧‧電池1090‧‧‧訊號線1100‧‧‧智慧型電話1120‧‧‧電子組件1130‧‧‧照相機模組2100‧‧‧扇出型半導體封裝2120、2220‧‧‧半導體晶片2122、2222‧‧‧連接墊2143、2243‧‧‧通孔2170、2270‧‧‧合金球2200‧‧‧扇入型半導體封裝2242‧‧‧配線圖案2243h‧‧‧通孔孔洞2251、O‧‧‧開口2280‧‧‧底部填充樹脂2301、2302‧‧‧中介基板A‧‧‧部分AI‧‧‧人工智慧單元CPU1、CPU2‧‧‧中央處理單元GPU‧‧‧圖形處理單元I-I'、II-II'‧‧‧線IO1、IO2、IO3、IO4、GPIO1、GPIO2‧‧‧輸入輸出單元MEMU1、MEMU2、MEMU3、MEMU4‧‧‧記憶體單元X、Y、Z‧‧‧方向
藉由結合附圖閱讀以下詳細說明,將更清晰理解本揭露的以上及其他態樣、特徵以及優點,在附圖中: 圖1為示出電子裝置的實例的方塊示意圖。 圖2為示出電子裝置的實例的立體示意圖。 圖3A及圖3B為示出扇入型半導體封裝在封裝前及封裝後狀態的剖面示意圖。 圖4為示出扇入型半導體封裝的封裝製程的剖面示意圖。 圖5為示出扇入型半導體封裝安裝於中介基板上且最終安裝於電子裝置的主板上之情形的剖面示意圖。 圖6為示出扇入型半導體封裝嵌入中介基板中且最終安裝於電子裝置的主板上之情形的剖面示意圖。 圖7為示出扇出型半導體封裝的剖面示意圖。 圖8為示出扇出型半導體封裝安裝於電子裝置的主板上之情形的剖面示意圖。 圖9為根據本揭露中的例示性實施例的半導體封裝的剖面示意圖。 圖10為示出沿圖9中的I-I'線截取的半導體封裝的平面圖。 圖11為示出圖9所示半導體封裝的部分A的放大剖面圖。 圖12A及圖12B為用於闡述積體電路晶片的各種單元的佈局變化的方塊圖。 圖13為示出根據本揭露中的一個例示性實施例的半導體封裝的剖面示意圖。 圖14為示出沿圖13中的II-II'線截取的半導體封裝的平面圖。
100‧‧‧半導體封裝
110‧‧‧支撐構件
110H‧‧‧空腔
112a‧‧‧第一配線圖案
112b‧‧‧第二配線圖案
120‧‧‧積體電路晶片
121‧‧‧本體
122‧‧‧連接電極
123‧‧‧鈍化膜
130‧‧‧包封體
140‧‧‧連接構件
140A‧‧‧第一表面
140B‧‧‧第二表面
141‧‧‧絕緣層
145‧‧‧重佈線層
145'‧‧‧配線
150‧‧‧鈍化層
160‧‧‧凸塊下金屬(UBM)層
170‧‧‧電性連接結構
180‧‧‧電容器/去耦電容器
A‧‧‧部分
I-I'‧‧‧線
O‧‧‧開口
X、Y、Z‧‧‧方向
Claims (22)
- 一種半導體封裝,包括: 連接構件,具有彼此相對的第一表面及第二表面,且包括重佈線層; 積體電路晶片,配置於所述連接構件的所述第一表面上,具有連接至所述重佈線層的連接電極,且包括多個單元; 至少一個電容器,配置於所述連接構件的所述第一表面上,且鄰近所述積體電路晶片配置;以及 包封體,配置於所述連接構件的所述第一表面上,且包封所述積體電路晶片及所述至少一個電容器, 其中核心功率單元中的至少一者鄰近所述積體電路晶片的第一邊緣配置,且 所述至少一個電容器鄰近所述積體電路晶片的所述第一邊緣配置。
- 如申請專利範圍第1項所述的半導體封裝,其中所述重佈線層包括直接連接所述核心功率單元與所述至少一個電容器的配線。
- 如申請專利範圍第1項所述的半導體封裝,其中所述至少一個電容器包括沿著所述積體電路晶片的所述第一邊緣排列的多個電容器。
- 如申請專利範圍第1項所述的半導體封裝,其中所述核心功率單元中的所述至少一者配置於所述積體電路晶片的隅角中以鄰近所述積體電路晶片的兩個相交的邊緣。
- 如申請專利範圍第4項所述的半導體封裝,其中所述至少一個電容器包括沿著所述兩個相交的邊緣排列的多個電容器。
- 如申請專利範圍第1項所述的半導體封裝,其中至少一個另一核心功率單元與所述積體電路晶片的邊緣間隔開且所述至少一個另一核心功率單元與所述積體電路晶片的所述邊緣之間插置有另一單元,並且所述至少一個另一核心功率單元的耗電率低於所述核心功率單元中的所述至少一者的耗電率。
- 如申請專利範圍第1項所述的半導體封裝,其中所述多個單元更包括多個低功率單元,所述多個低功率單元中的每一者的耗電率低於所述核心功率單元中的每一者的耗電率,並且所述多個低功率單元中的至少一者與所述積體電路晶片的邊緣間隔開且所述多個低功率單元中的所述至少一者與所述所述積體電路晶片的所述邊緣之間插置有另一單元。
- 如申請專利範圍第7項所述的半導體封裝,其中所述多個低功率單元包括選自由介面單元、記憶體單元及輸入輸出單元組成的群組的單元。
- 如申請專利範圍第1項所述的半導體封裝,更包括支撐構件,所述支撐構件配置於所述連接構件的所述第一表面上,且具有容置所述積體電路晶片及所述至少一個電容器的空腔。
- 如申請專利範圍第9項所述的半導體封裝,其中所述支撐構件包括配線結構,所述配線結構連接所述支撐構件的上表面與下表面且連接至所述重佈線層。
- 如申請專利範圍第1項所述的半導體封裝,其中所述多個單元包括選自由中央處理單元、圖形處理單元及人工智慧單元組成的群組的核心功率單元。
- 一種半導體封裝,包括: 連接構件,具有彼此相對的第一表面及第二表面,且包括重佈線層; 積體電路晶片,配置於所述連接構件的所述第一表面上,具有連接至所述重佈線層的連接電極,且包括多個單元; 多個電容器,配置於所述連接構件的所述第一表面上,且鄰近所述積體電路晶片;以及 包封體,配置於所述連接構件的所述第一表面上,且包封所述積體電路晶片及所述多個電容器, 其中所述多個單元包括第一單元及第二單元,所述第一單元具有第一耗電率且鄰近所述積體電路晶片的一個邊緣配置,所述第二單元具有較所述第一耗電率低的第二耗電率且被配置成在所述積體電路晶片上較所述第一單元更向內,且 所述多個電容器鄰近所述積體電路晶片的所述一個邊緣配置。
- 如申請專利範圍第11項所述的半導體封裝,其中所述第一單元包括選自由中央處理單元、圖形處理單元及人工智慧單元組成的群組的至少一個單元。
- 如申請專利範圍第12項所述的半導體封裝,其中所述第一單元包括多個第一單元,且 所述多個第一單元沿著所述積體電路晶片的另一邊緣配置或配置於所述積體電路晶片的另一隅角中。
- 如申請專利範圍第11項所述的半導體封裝,其中所述第二單元包括選自介面單元、記憶體單元及輸入輸出單元的至少一個單元。
- 如申請專利範圍第11項所述的半導體封裝,其中所述重佈線層包括直接連接所述第一單元與所述多個電容器的配線。
- 一種半導體封裝,包括: 積體電路晶片,包括鄰近所述積體電路晶片的第一邊緣配置的第一核心功率單元、以及第一其他單元,所述積體電路晶片配置於連接構件的第一表面上; 電容器,配置於所述連接構件的所述第一表面上,且鄰近所述積體電路晶片的所述第一邊緣;以及 包封體,配置於所述連接構件的所述第一表面上,且包封所述積體電路晶片及所述電容器中的每一者的至少一部分, 其中所述連接構件包括直接連接所述第一核心功率單元與所述電容器的配線層。
- 如申請專利範圍第17項所述的半導體封裝,其中所述連接構件更包括連接至所述積體電路晶片的連接電極的重佈線層。
- 如申請專利範圍第17項所述的半導體封裝,其中所述積體電路晶片更包括第二核心功率晶片,所述第二核心功率晶片的耗電率低於所述第一核心功率單元的耗電率,所述第二核心功率單元被配置成遠離所述第一邊緣,且所述第二核心功率單元與所述第一邊緣之間插置有另一單元。
- 如申請專利範圍第17項所述的半導體封裝,其中所述第一其他單元的耗電率低於所述第一核心功率單元的耗電率。
- 如申請專利範圍第17項所述的半導體封裝,其中所述第一核心功率單元選自由中央處理單元、圖形處理單元及人工智慧單元組成的群組。
- 如申請專利範圍第17項所述的半導體封裝,其中所述第一其他單元選自由介面單元、記憶體單元及輸入輸出單元組成的群組。
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