KR20220116922A - 열 통로를 갖는 반도체 패키지 - Google Patents

열 통로를 갖는 반도체 패키지 Download PDF

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KR20220116922A
KR20220116922A KR1020210020382A KR20210020382A KR20220116922A KR 20220116922 A KR20220116922 A KR 20220116922A KR 1020210020382 A KR1020210020382 A KR 1020210020382A KR 20210020382 A KR20210020382 A KR 20210020382A KR 20220116922 A KR20220116922 A KR 20220116922A
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South Korea
Prior art keywords
chip
heat transfer
wiring structure
passive
active
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KR1020210020382A
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English (en)
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김응규
석경림
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삼성전자주식회사
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Priority to KR1020210020382A priority Critical patent/KR20220116922A/ko
Priority to US17/358,149 priority patent/US20220262699A1/en
Publication of KR20220116922A publication Critical patent/KR20220116922A/ko

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    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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Abstract

반도체 패키지는 신호 배선 및 상기 신호 배선과 이격된 열 전달 배선을 갖는 배선 구조체를 포함한다. 상기 배선 구조체 상에 액티브 칩(Active Chip)이 배치된다. 상기 배선 구조체 및 상기 액티브 칩 사이에 신호 단자가 배치된다. 상기 배선 구조체 및 상기 액티브 칩 사이에 배치되고 상기 열 전달 배선에 접속된 제1 열 전달 단자가 제공된다. 상기 배선 구조체 상에 패시브 칩(Passive Chip)이 배치된다. 상기 배선 구조체 및 상기 패시브 칩 사이에 배치되고 상기 열 전달 배선에 접속된 제2 열 전달 단자가 제공된다. 상기 패시브 칩 상에 히트 스프레더(Heat Spreader)가 배치된다.

Description

열 통로를 갖는 반도체 패키지{SEMICONDUCTOR PACKAGE INCLUDING THERMAL PATH}
열 통로를 갖는 반도체 패키지 및 그 형성 방법에 관한 것이다.
전자 시스템의 경박단소화에 따라 다수의 반도체 칩을 탑재할 수 있는 다양한 반도체 패키지들이 연구되고 있다. 상기 다수의 반도체 칩의 각각은 동작 중 주변 환경보다 높은 온도의 열이 발생될 수 있다. 상기 다수의 반도체 칩에서 발생하는 열은 상기 전자 시스템의 오 동작을 유발하고 상기 전자 시스템의 수명에 나쁜 영향을 준다.
본 발명 기술적 사상의 실시예들에 따른 과제는 효율적인 방열 특성을 갖는 반도체 패키지 및 그 형성 방법을 제공하는데 있다.
본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 신호 배선 및 상기 신호 배선과 이격된 열 전달 배선을 갖는 배선 구조체를 포함한다. 상기 배선 구조체 상에 액티브 칩(Active Chip)이 배치된다. 상기 배선 구조체 및 상기 액티브 칩 사이에 신호 단자가 배치된다. 상기 배선 구조체 및 상기 액티브 칩 사이에 배치되고 상기 열 전달 배선에 접속된 제1 열 전달 단자가 제공된다. 상기 배선 구조체 상에 패시브 칩(Passive Chip)이 배치된다. 상기 배선 구조체 및 상기 패시브 칩 사이에 배치되고 상기 열 전달 배선에 접속된 제2 열 전달 단자가 제공된다. 상기 패시브 칩 상에 히트 스프레더(Heat Spreader)가 배치된다.
본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 신호 배선 및 상기 신호 배선과 이격된 열 전달 배선을 갖는 배선 구조체를 포함한다. 상기 배선 구조체 상에 배치되고 상기 신호 배선 및 상기 열 전달 배선에 접속된 액티브 칩이 제공된다. 상기 배선 구조체 상에 배치되고 상기 열 전달 배선에 접속된 패시브 칩이 제공된다. 상기 패시브 칩 상에 히트 스프레더가 배치된다.
본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 신호 배선 및 상기 신호 배선과 이격된 열 전달 배선을 갖는 재-배선층(Re-Distribution Layer; RDL)을 포함한다. 상기 재-배선층 상에 액티브 칩이 배치된다. 상기 재-배선층 및 상기 액티브 칩 사이에 신호 단자가 배치된다. 상기 재-배선층 및 상기 액티브 칩 사이에 배치되고 상기 열 전달 배선에 접속된 제1 열 전달 단자가 제공된다. 상기 재-배선층 상에 패시브 칩이 배치된다. 상기 재-배선층 및 상기 패시브 칩 사이에 배치되고 상기 열 전달 배선에 접속된 제2 열 전달 단자가 제공된다. 상기 패시브 칩 상에 히트 스프레더가 배치된다. 상기 재-배선층의 하면 상에 외부 단자가 배치된다. 상기 재-배선층 상에 배치되고 상기 액티브 칩 및 상기 히트 스프레더 사이에 연장된 봉지재가 제공된다.
본 발명 기술적 사상의 실시예들에 따르면, 배선 구조체 상의 액티브 칩 및 패시브 칩이 제공된다. 상기 패시브 칩 상에 히트 스프레더가 배치된다. 상기 배선 구조체는 신호 배선 및 상기 신호 배선과 이격된 열 전달 배선을 포함할 수 있다. 상기 액티브 칩에서 발생하는 열은 상기 열 전달 배선, 상기 상기 패시브 칩, 및 상기 히트 스프레더를 경유하여 효율적으로 분산될 수 있다. 고집적화에 유리하고 효율적인 방열 특성을 갖는 반도체 패키지를 구현할 수 있다.
도 1 내지 도 7은 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지를 설명하기 위한 단면도들이다.
도 8 내지 도 13은 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지 형성 방법들을 설명하기 위한 단면도들이다.
도 1 내지 도 7은 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지를 설명하기 위한 단면도들이다. 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 FOWLP(Fan-Out Wafer Level Package), FIWLP(Fan-In Wafer Level Package), PLP(Panel Level Package), PoP(Package on Package), SIP(System-In-Package), 또는 이들의 조합을 포함할 수 있다.
도 1을 참조하면, 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 배선 구조체(30), 다수의 신호 단자(41), 제1 열 전달 단자(42), 다수의 제2 열 전달 단자(45), 다수의 외부 단자(49), 다수의 신호 패드(51), 제1 열 전달 패드(52), 다수의 제2 열 전달 패드(55), 제1 액티브 칩(Active Chip; 61), 패시브 칩(Passive Chip; 71), 제1 봉지재(81), 제2 봉지재(85), 열 인터페이스 물질 층(Thermal Interface Material Layer; TIM Layer; 97), 및 히트 스프레더(Heat Spreader; 98)를 포함할 수 있다. 상기 배선 구조체(30)는 절연층(31), 다수의 신호 배선(33), 및 열 전달 배선(34)을 포함할 수 있다.
일 실시예에서, 상기 배선 구조체(30)는 로직 칩(Logic Chip), 버퍼 칩(Buffer Chip), 컨트롤러 칩(Controller Chip), 애플리케이션 프로세서 칩(Application Processor Chip), 인터포저 칩(Interposer Chip), 휘발성 메모리 칩(Volatile Memory Chip), 비-휘발성 메모리 칩(Non-Volatile Memory Chip), 또는 이들의 조합과 같은 반도체 칩을 포함할 수 있다. 상기 배선 구조체(30)는 재-배선층(Re-Distribution Layer; RDL), 인쇄 회로 기판, 인터포저(Interposer) 기판, 상기 반도체 칩, 또는 이들의 조합을 포함할 수 있다.
일 실시예에서, 상기 배선 구조체(30)는 재-배선층(RDL)을 포함할 수 있다. 상기 절연층(31)은 ABF(Ajinomoto Build-up Film)와 같은 폴리머 절연층을 포함할 수 있다. 상기 다수의 신호 배선(33) 및 상기 열 전달 배선(34)은 상기 절연층(31) 내에 배치될 수 있다. 상기 다수의 신호 배선(33)은 다수의 수평 배선, 다수의 수직 배선, 다수의 상부 패드, 다수의 하부 패드, 또는 이들의 조합을 포함할 수 있다. 상기 열 전달 배선(34)은 다수의 수평 열 전달 배선, 다수의 수직 열 전달 배선, 다수의 상부 열 전달 패드, 또는 이들의 조합을 포함할 수 있다. 상기 열 전달 배선(34)은 상기 다수의 신호 배선(33)과 이격될 수 있다. 상기 다수의 신호 배선(33) 및 상기 열 전달 배선(34)은 Cu, W, WN, Ni, Co, Al, Ti, TiN, Ta, TaN, Ag, Pt, Au, Ru, Cr, Sn, 또는 이들의 조합과 같은 도전성 물질(Conductive Material)을 포함할 수 있다.
상기 배선 구조체(30) 상에 상기 제1 액티브 칩(Active Chip; 61) 및 상기 패시브 칩(Passive Chip; 71)이 장착될 수 있다. 상기 배선 구조체(30) 및 상기 제1 액티브 칩(61) 사이와 상기 배선 구조체(30) 및 상기 패시브 칩(71) 사이에 상기 제1 봉지재(81)가 배치될 수 있다. 상기 제1 액티브 칩(61) 및 상기 배선 구조체(30) 사이에 상기 다수의 신호 단자(41) 및 상기 제1 열 전달 단자(42)가 배치될 수 있다. 상기 패시브 칩(71) 및 상기 배선 구조체(30) 사이에 상기 다수의 제2 열 전달 단자(45)가 배치될 수 있다.
상기 제1 액티브 칩(61)은 상기 다수의 신호 패드(51) 및 상기 제1 열 전달 패드(52)를 포함할 수 있다. 상기 제1 열 전달 패드(52)는 상기 다수의 신호 패드(51)와 이격될 수 있다. 상기 다수의 신호 단자(41)는 상기 제1 봉지재(81)를 관통하여 상기 다수의 신호 패드(51) 및 상기 다수의 신호 배선(33)에 접촉될 수 있다. 상기 제1 열 전달 단자(42)는 상기 제1 봉지재(81)를 관통하여 상기 제1 열 전달 패드(52) 및 상기 열 전달 배선(34)에 접촉될 수 있다. 상기 패시브 칩(71)은 상기 다수의 제2 열 전달 패드(55)를 포함할 수 있다. 상기 다수의 제2 열 전달 단자(45)는 상기 제1 봉지재(81)를 관통하여 상기 제2 열 전달 패드(55) 및 상기 열 전달 배선(34)에 접촉될 수 있다.
상기 제1 액티브 칩(61)은 로직 칩(Logic Chip), 버퍼 칩(Buffer Chip), 컨트롤러 칩(Controller Chip), 애플리케이션 프로세서 칩(Application Processor Chip), 인터포저 칩(Interposer Chip), 메모리 칩(Memory Chip), 또는 이들의 조합을 포함할 수 있다. 상기 제1 액티브 칩(61)은 휘발성 메모리 칩(Volatile Memory Chip), 비-휘발성 메모리 칩(Non-Volatile Memory Chip), 또는 이들의 조합과 같은 메모리 칩을 포함할 수 있다. 상기 패시브 칩(71)은 상기 제1 액티브 칩(61)과 유사한 구성을 갖는 더미 칩(Dummy Chip)을 포함할 수 있다. 상기 패시브 칩(71)은 상기 제1 액티브 칩(61)과 유사한 열 팽창 계수를 갖는 물질을 포함할 수 있다. 상기 패시브 칩(71)은 단결정 실리콘 층과 같은 반도체 층을 포함할 수 있다. 상기 패시브 칩(71)은 상기 제1 액티브 칩(61)보다 두꺼울 수 있다.
상기 다수의 신호 단자(41), 상기 제1 열 전달 단자(42), 및 상기 다수의 제2 열 전달 단자(45)의 각각은 솔더 볼, 도전성 범프, UBM(Under Bump Metallurgy), 도전성 필라(Conductive Pillar), 도전성 리드, 도전성 핀, 또는 이들의 조합을 포함할 수 있다. 상기 다수의 신호 패드(51), 상기 제1 열 전달 패드(52), 및 상기 다수의 제2 열 전달 패드(55)의 각각은 Cu, W, WN, Ni, Co, Al, Ti, TiN, Ta, TaN, Ag, Pt, Au, Ru, Cr, Sn, 또는 이들의 조합과 같은 도전성 물질을 포함할 수 있다.
상기 제1 봉지재(81)는 상기 배선 구조체(30) 및 상기 제1 액티브 칩(61) 사이와 상기 배선 구조체(30) 및 상기 패시브 칩(71) 사이를 채우고 상기 제1 액티브 칩(61) 및 상기 패시브 칩(71)의 측면들을 부분적으로 덮을 수 있다. 상기 제1 봉지재(81)는 필러(Filler) 및 레진(Resin)을 갖는 언더필(Under Fill)을 포함할 수 있다. 상기 필러(Filler)는 유동성 확보에 유리한 구상 필러를 포함할 수 있다. 상기 필러(Filler)는 알루미늄 산화물(Al2O3), 알루미늄 질화물(AlN), 붕소 질화물(BN), 실리콘 산화물(SiO2), 또는 이들의 조합을 포함할 수 있다. 일 실시예에서, 상기 제1 봉지재(81)는 에폭시 몰딩 컴파운드(Epoxy Molding Compound)를 포함할 수 있다. 일 실시예에서, 상기 제1 봉지재(81)는 DAF(Die Attach Film)을 포함할 수 있다.
상기 패시브 칩(71)은 상기 제1 액티브 칩(61)보다 두꺼울 수 있다. 상기 패시브 칩(71)의 상면은 상기 제1 액티브 칩(61)의 상면보다 높은 레벨에 배치될 수 있다. 상기 배선 구조체(30) 상에 상기 제1 액티브 칩(61)의 상면 및 측면들을 덮고 상기 패시브 칩(71)의 측면들을 덮는 상기 제2 봉지재(85)가 배치될 수 있다. 상기 제2 봉지재(85)는 상기 제1 봉지재(81)의 상면 및 측면들을 덮을 수 있다. 상기 제2 봉지재(85) 및 상기 패시브 칩(71)의 상면들은 실질적으로 동일한 평면을 이룰 수 있다. 상기 제2 봉지재(85)는 에폭시 몰딩 컴파운드(Epoxy Molding Compound)를 포함할 수 있다.
상기 제2 봉지재(85) 및 상기 패시브 칩(71) 상에 상기 열 인터페이스 물질 층(Thermal Interface Material Layer; TIM Layer; 97)이 배치될 수 있다. 상기 열 인터페이스 물질 층(97)은 갭 필(gap fill) 특성이 우수하고 열 전도성이 우수한 물질을 포함할 수 있다. 상기 열 인터페이스 물질 층(97) 상에 상기 히트 스프레더(Heat Spreader; 98)가 배치될 수 있다.
상기 열 인터페이스 물질 층(97)은 상기 제2 봉지재(85), 상기 패시브 칩(71) 및 상기 히트 스프레더(98)에 직접적으로 접촉될 수 있다. 상기 열 인터페이스 물질 층(97) 및 상기 제1 액티브 칩(61) 사이에 상기 제2 봉지재(85)가 개재될 수 있다. 상기 히트 스프레더(98)는 다양한 형상의 3차원 구조를 포함할 수 있다. 상기 히트 스프레더(98)는 Cu, Al, 또는 이들의 조합과 같은 열 전도성이 우수한 물질을 포함할 수 있다. 상기 패시브 칩(71) 및 상기 히트 스프레더(98) 사이의 간격은 상기 제1 액티브 칩(61) 및 상기 히트 스프레더(98) 사이의 간격보다 작을 수 있다.
상기 배선 구조체(30)의 하면 상에 상기 다수의 외부 단자(49)가 배치될 수 있다. 상기 다수의 외부 단자(49)는 상기 다수의 신호 배선(33)에 접속될 수 있다. 상기 다수의 외부 단자(49)는 솔더 볼, 도전성 범프, UBM(Under Bump Metallurgy), 도전성 필라(Conductive Pillar), 도전성 리드, 도전성 핀, 또는 이들의 조합을 포함할 수 있다. 일 실시예에서, 상기 다수의 외부 단자(49)는 생략될 수 있다.
본 발명 기술적 사상의 실시예들에 따르면, 상기 제1 액티브 칩(61)의 내부 및 주변에서 발생하는 열은 상기 제1 열 전달 패드(52), 상기 제1 열 전달 단자(42), 상기 열 전달 배선(34), 상기 다수의 제2 열 전달 단자(45), 상기 다수의 제2 열 전달 패드(55), 상기 패시브 칩(71), 상기 열 인터페이스 물질 층(97), 및 상기 히트 스프레더(98)를 통하여 효율적으로 분산될 수 있다.
도 2를 참조하면, 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 배선 구조체(30), 다수의 신호 단자(41), 제1 열 전달 단자(42), 다수의 제2 열 전달 단자(45), 다수의 외부 단자(49), 다수의 신호 패드(51), 제1 열 전달 패드(52), 다수의 제2 열 전달 패드(55), 제1 액티브 칩(61), 패시브 칩(71), 제1 봉지재(81), 제2 봉지재(85), 열 인터페이스 물질 층(97), 및 히트 스프레더(98)를 포함할 수 있다.
일 실시예에서, 상기 제1 액티브 칩(61), 상기 패시브 칩(71), 및 상기 제2 봉지재(85)의 상면들은 실질적으로 동일한 평면을 이룰 수 있다. 상기 제2 봉지재(85)는 상기 제1 액티브 칩(61) 및 상기 패시브 칩(71)의 측면들을 덮을 수 있다. 상기 제1 액티브 칩(61), 상기 패시브 칩(71), 및 상기 제2 봉지재(85) 상에 상기 열 인터페이스 물질 층(97)이 배치될 수 있다. 상기 열 인터페이스 물질 층(97)은 상기 제1 액티브 칩(61), 상기 패시브 칩(71), 및 상기 제2 봉지재(85) 의 상면들에 직접적으로 접촉될 수 있다. 상기 열 인터페이스 물질 층(97) 상에 상기 히트 스프레더(98)가 배치될 수 있다.
도 3을 참조하면, 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 배선 구조체(30), 다수의 신호 단자(41), 제1 열 전달 단자(42), 다수의 제2 열 전달 단자(45), 다수의 외부 단자(49), 다수의 신호 패드(51), 제1 열 전달 패드(52), 다수의 제2 열 전달 패드(55), 제1 액티브 칩(61), 패시브 칩(71), 다수의 관통 전극(75), 제1 봉지재(81), 제2 봉지재(85), 열 인터페이스 물질 층(97), 및 히트 스프레더(98)를 포함할 수 있다.
일 실시예에서, 상기 다수의 관통 전극(75)은 상기 패시브 칩(71)을 관통하여 상기 열 인터페이스 물질 층(97) 및 상기 다수의 제2 열 전달 패드(55)에 접속될 수 있다. 상기 다수의 관통 전극(75)은 열 전도성이 우수한 물질을 포함할 수 있다. 상기 다수의 관통 전극(75)은 Cu, W, WN, Ni, Co, Al, Ti, TiN, Ta, TaN, Ag, Pt, Au, Ru, Cr, Sn, 또는 이들의 조합과 같은 도전성 물질을 포함할 수 있다.
도 4를 참조하면, 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 배선 구조체(30), 다수의 외부 단자(49), 다수의 신호 패드(51), 제1 열 전달 패드(52), 다수의 제2 열 전달 패드(55), 제1 액티브 칩(61), 패시브 칩(71), 제2 봉지재(85), 열 인터페이스 물질 층(97), 및 히트 스프레더(98)를 포함할 수 있다.
일 실시예에서, 상기 제2 봉지재(85)는 상기 배선 구조체(30) 및 상기 제1 액티브 칩(61) 사이와 상기 배선 구조체(30) 및 상기 패시브 칩(71) 사이에 연장될 수 있다. 상기 배선 구조체(30)는 절연층(31), 다수의 신호 배선(33), 및 열 전달 배선(34)을 포함할 수 있다. 상기 다수의 신호 배선(33)은 다수의 수평 배선, 다수의 수직 배선(33V), 다수의 하부 패드, 또는 이들의 조합을 포함할 수 있다. 상기 열 전달 배선(34)은 다수의 수평 열 전달 배선, 다수의 수직 열 전달 배선(34V), 또는 이들의 조합을 포함할 수 있다.
상기 다수의 신호 패드(51)는 상기 다수의 수직 배선(33V)에 접속될 수 있다. 상기 제1 열 전달 패드(52) 및 상기 다수의 제2 열 전달 패드(55)는 상기 다수의 수직 열 전달 배선(34V)에 접속될 수 있다. 상기 다수의 수직 배선(33V) 및 상기 다수의 수직 열 전달 배선(34V)의 각각은 하부의 수평 폭이 상부의 수평 폭보다 클 수 있다.
도 5를 참조하면, 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 배선 구조체(30), 다수의 신호 단자(41), 제1 열 전달 단자(42), 다수의 제2 열 전달 단자(45), 다수의 외부 단자(49), 다수의 신호 패드(51), 제1 열 전달 패드(52), 다수의 제2 열 전달 패드(55), 제1 액티브 칩(61), 패시브 칩(71), 제1 봉지재(81), 제2 봉지재(85), 열 인터페이스 물질 층(97), 및 히트 스프레더(98)를 포함할 수 있다.
일 실시예에서, 상기 배선 구조체(30)는 인쇄 회로 기판, 또는 인터포저(Interposer) 기판을 포함할 수 있다.
도 6을 참조하면, 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 배선 구조체(30), 다수의 신호 단자(41), 제1 열 전달 단자(42), 다수의 제2 열 전달 단자(45), 다수의 외부 단자(49), 다수의 신호 패드(51), 제1 열 전달 패드(52), 다수의 제2 열 전달 패드(55), 제1 액티브 칩(61), 제2 액티브 칩(62), 패시브 칩(71), 제1 봉지재(81), 제2 봉지재(85), 열 인터페이스 물질 층(97), 및 히트 스프레더(98)를 포함할 수 있다.
일 실시예에서, 상기 제1 액티브 칩(61) 및 상기 제2 액티브 칩(62)의 각각은 로직 칩(Logic Chip), 버퍼 칩(Buffer Chip), 컨트롤러 칩(Controller Chip), 애플리케이션 프로세서 칩(Application Processor Chip), 인터포저 칩(Interposer Chip), 메모리 칩(Memory Chip), 또는 이들의 조합을 포함할 수 있다. 상기 제1 액티브 칩(61) 및 상기 제2 액티브 칩(62)의 각각은 휘발성 메모리 칩(Volatile Memory Chip), 비-휘발성 메모리 칩(Non-Volatile Memory Chip), 또는 이들의 조합과 같은 메모리 칩을 포함할 수 있다. 예를들면, 상기 제1 액티브 칩(61)은 애플리케이션 프로세서 칩을 포함할 수 있으며, 상기 제2 액티브 칩(62)은 메모리 칩을 포함할 수 있다.
도 7을 참조하면, 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 배선 구조체(30), 다수의 신호 단자(41), 제1 열 전달 단자(42), 다수의 제2 열 전달 단자(45), 다수의 외부 단자(49), 다수의 신호 패드(51), 제1 열 전달 패드(52), 다수의 제2 열 전달 패드(55), 제1 액티브 칩(61), 내부 패키지(69), 패시브 칩(71), 제1 봉지재(81), 제2 봉지재(85), 열 인터페이스 물질 층(97), 및 히트 스프레더(98)를 포함할 수 있다. 상기 내부 패키지(69)는 내부 배선 구조체(63), 제3 액티브 칩(64), 제4 액티브 칩(65), 제5 액티브 칩(66), 제6 액티브 칩(64), 제3 봉지재(82), 및 제4 봉지재(86)를 포함할 수 있다.
일 실시예에서, 상기 내부 배선 구조체(63)는 로직 칩(Logic Chip), 버퍼 칩(Buffer Chip), 컨트롤러 칩(Controller Chip), 애플리케이션 프로세서 칩(Application Processor Chip), 인터포저 칩(Interposer Chip), 휘발성 메모리 칩(Volatile Memory Chip), 비-휘발성 메모리 칩(Non-Volatile Memory Chip), 또는 이들의 조합과 같은 반도체 칩을 포함할 수 있다. 상기 내부 배선 구조체(63)는 재-배선층(Re-Distribution Layer; RDL), 인쇄 회로 기판, 인터포저(Interposer) 기판, 상기 반도체 칩, 또는 이들의 조합을 포함할 수 있다.
상기 제3 액티브 칩(64), 상기 제4 액티브 칩(65), 상기 제5 액티브 칩(66), 및 상기 제6 액티브 칩(64)의 각각은 로직 칩(Logic Chip), 버퍼 칩(Buffer Chip), 컨트롤러 칩(Controller Chip), 애플리케이션 프로세서 칩(Application Processor Chip), 인터포저 칩(Interposer Chip), 메모리 칩(Memory Chip), 또는 이들의 조합을 포함할 수 있다. 상기 제3 액티브 칩(64), 상기 제4 액티브 칩(65), 상기 제5 액티브 칩(66), 및 상기 제6 액티브 칩(64)의 각각은 휘발성 메모리 칩(Volatile Memory Chip), 비-휘발성 메모리 칩(Non-Volatile Memory Chip), 또는 이들의 조합과 같은 메모리 칩을 포함할 수 있다. 예를들면, 상기 제3 액티브 칩(64), 상기 제4 액티브 칩(65), 상기 제5 액티브 칩(66), 및 상기 제6 액티브 칩(64)의 각각은 DRAM(Dynamic Random Access Memory)과 같은 휘발성 메모리 칩(Volatile Memory Chip)을 포함할 수 있다.
상기 제3 액티브 칩(64), 상기 제4 액티브 칩(65), 상기 제5 액티브 칩(66), 및 상기 제6 액티브 칩(64)은 상기 내부 배선 구조체(63) 상에 차례로 적층될 수 있다. 상기 내부 배선 구조체(63), 상기 제3 액티브 칩(64), 상기 제4 액티브 칩(65), 상기 제5 액티브 칩(66), 및 상기 제6 액티브 칩(64) 사이에 다수의 내부 신호 단자(43) 및 다수의 내부 열 전달 단자(44)가 배치될 수 있다. 상기 내부 배선 구조체(63), 상기 제3 액티브 칩(64), 상기 제4 액티브 칩(65), 상기 제5 액티브 칩(66), 및 상기 제6 액티브 칩(64) 사이에 상기 제3 봉지재(82)가 배치될 수 있다.
상기 다수의 내부 열 전달 단자(44)는 상기 다수의 내부 신호 단자(43)와 이격될 수 있다. 상기 다수의 내부 신호 단자(43) 및 상기 다수의 내부 열 전달 단자(44)의 각각은 솔더 볼, 도전성 범프, UBM(Under Bump Metallurgy), 도전성 필라(Conductive Pillar), 도전성 리드, 도전성 핀, 또는 이들의 조합을 포함할 수 있다. 상기 제3 봉지재(82)는 필러(Filler) 및 레진(Resin)을 갖는 언더필(Under Fill)을 포함할 수 있다. 일 실시예에서, 상기 제3 봉지재(82)는 DAF(Die Attach Film)을 포함할 수 있다.
상기 내부 배선 구조체(63), 상기 제3 액티브 칩(64), 상기 제4 액티브 칩(65), 상기 제5 액티브 칩(66), 및 상기 제6 액티브 칩(64)의 각각은 다수의 내부 신호 배선(37) 및 다수의 내부 열 전달 배선(38)을 포함할 수 있다. 상기 다수의 내부 열 전달 배선(38)은 상기 다수의 내부 신호 배선(37)과 이격될 수 있다.
상기 다수의 내부 신호 배선(37)은 다수의 수평 배선, 다수의 수직 배선, 또는 이들의 조합을 포함할 수 있다. 일 실시예에서, 상기 다수의 내부 신호 배선(37)은 관통 전극과 같은 다수의 수직 배선을 포함할 수 있다. 상기 다수의 내부 열 전달 배선(38)은 다수의 수평 열 전달 배선, 다수의 수직 열 전달 배선, 또는 이들의 조합을 포함할 수 있다. 일 실시예에서, 상기 다수의 내부 열 전달 배선(38)은 관통 전극과 같은 다수의 수직 열 전달 배선을 포함할 수 있다.
상기 내부 배선 구조체(63) 상에 상기 제3 액티브 칩(64), 상기 제4 액티브 칩(65), 상기 제5 액티브 칩(66), 및 상기 제6 액티브 칩(64)을 덮는 상기 제4 봉지재(86)가 배치될 수 있다. 상기 제4 봉지재(86)는 에폭시 몰딩 컴파운드(Epoxy Molding Compound)를 포함할 수 있다.
도 8 내지 도 13은 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지 형성 방법들을 설명하기 위한 단면도들이다.
도 8을 참조하면, 캐리어(Carrier; 25) 상에 버퍼 층(26)이 형성될 수 있다. 상기 버퍼 층(26) 상에 배선 구조체(30)가 형성될 수 있다. 일 실시예에서, 상기 캐리어(25)는 실리콘 웨이퍼와 같은 반도체 기판을 포함할 수 있다. 상기 버퍼 층(26)은 접착층을 포함할 수 있다.
상기 배선 구조체(30)는 절연층(31), 다수의 신호 배선(33), 및 열 전달 배선(34)을 포함할 수 있다. 상기 절연층(31)은 ABF(Ajinomoto Build-up Film)와 같은 폴리머 절연층을 포함할 수 있다. 상기 다수의 신호 배선(33) 및 상기 열 전달 배선(34)은 상기 절연층(31) 내에 형성될 수 있다. 상기 다수의 신호 배선(33)은 다수의 수평 배선(33H), 다수의 수직 배선(33V), 다수의 상부 패드(33P), 다수의 하부 패드(33T), 또는 이들의 조합을 포함할 수 있다. 상기 다수의 수평 배선(33H), 상기 다수의 수직 배선(33V), 상기 다수의 상부 패드(33P), 및 상기 다수의 하부 패드(33T)는 서로 연결될 수 있다.
상기 열 전달 배선(34)은 다수의 수평 열 전달 배선(34H), 다수의 수직 열 전달 배선(34V), 다수의 상부 열 전달 패드(34P), 또는 이들의 조합을 포함할 수 있다. 상기 다수의 수평 열 전달 배선(34H), 상기 다수의 수직 열 전달 배선(34V), 및 상기 다수의 상부 열 전달 패드(34P)는 서로 연결될 수 있다. 상기 열 전달 배선(34)은 상기 다수의 신호 배선(33)과 이격될 수 있다.
상기 다수의 수직 배선(33V) 및 상기 다수의 수직 열 전달 배선(34V)의 각각은 하부의 수평 폭이 상부의 수평 폭보다 작을 수 있다. 상기 다수의 수직 배선(33V) 및 상기 다수의 수직 열 전달 배선(34V)의 각각은 비아 플러그(Via Plug)를 포함할 수 있다. 상기 열 전달 배선(34)은 상기 다수의 신호 배선(33) 중 몇몇과 동시에 형성된 동일한 물질을 포함할 수 있다.
도 9를 참조하면, 상기 배선 구조체(30) 상에 제1 액티브 칩(Active Chip; 61) 및 패시브 칩(Passive Chip; 71)이 장착될 수 있다. 일 실시예에서, 상기 패시브 칩(71)은 상기 제1 액티브 칩(61)보다 두꺼울 수 있다. 상기 패시브 칩(71)의 최상단은 상기 제1 액티브 칩(61)보다 높은 레벨에 돌출될 수 있다.
상기 제1 액티브 칩(61)은 다수의 신호 패드(51) 및 제1 열 전달 패드(52)를 포함할 수 있다. 상기 패시브 칩(71)은 다수의 제2 열 전달 패드(55)를 포함할 수 있다. 상기 제1 액티브 칩(61) 및 상기 배선 구조체(30) 사이에 다수의 신호 단자(41) 및 제1 열 전달 단자(42)가 형성될 수 있다. 상기 다수의 신호 단자(41)는 상기 다수의 신호 패드(51) 및 상기 다수의 상부 패드(도 8의 33P)에 접촉될 수 있다. 상기 제1 열 전달 단자(42)는 상기 제1 열 전달 패드(52) 및 상기 다수의 수직 열 전달 배선(도 8의 34V)에 접촉될 수 있다. 상기 패시브 칩(71) 및 상기 배선 구조체(30) 사이에 다수의 제2 열 전달 단자(45)가 형성될 수 있다. 상기 다수의 제2 열 전달 단자(45)는 상기 제2 열 전달 패드(55) 및 상기 다수의 수직 열 전달 배선(도 8의 34V)에 접촉될 수 있다.
상기 다수의 신호 단자(41), 상기 제1 열 전달 단자(42), 및 상기 다수의 제2 열 전달 단자(45)의 각각은 솔더 볼, 도전성 범프, UBM(Under Bump Metallurgy), 도전성 필라(Conductive Pillar), 도전성 리드, 도전성 핀, 또는 이들의 조합을 포함할 수 있다. 상기 제1 열 전달 단자(42) 및 상기 다수의 제2 열 전달 단자(45)는 상기 다수의 신호 단자(41)와 실질적으로 동일한 물질을 포함할 수 있다.
도 10을 참조하면, 상기 배선 구조체(30) 및 상기 제1 액티브 칩(61) 사이와 상기 배선 구조체(30) 및 상기 패시브 칩(71) 사이에 제1 봉지재(81)가 형성될 수 있다. 상기 제1 봉지재(81)는 상기 배선 구조체(30) 및 상기 제1 액티브 칩(61) 사이와 상기 배선 구조체(30) 및 상기 패시브 칩(71) 사이를 채우고 상기 제1 액티브 칩(61) 및 상기 패시브 칩(71)의 측면들을 부분적으로 덮을 수 있다.
상기 제1 봉지재(81)는 필러(Filler) 및 레진(Resin)을 갖는 언더필(Under Fill)을 포함할 수 있다. 상기 필러(Filler)는 유동성 확보에 유리한 구상 필러를 포함할 수 있다. 상기 필러(Filler)는 알루미늄 산화물(Al2O3), 알루미늄 질화물(AlN), 붕소 질화물(BN), 실리콘 산화물(SiO2), 또는 이들의 조합을 포함할 수 있다. 일 실시예에서, 상기 제1 봉지재(81)는 에폭시 몰딩 컴파운드(Epoxy Molding Compound)를 포함할 수 있다. 일 실시예에서, 상기 제1 봉지재(81)는 DAF(Die Attach Film)을 포함할 수 있다.
도 11을 참조하면, 상기 배선 구조체(30) 상에 상기 제1 액티브 칩(61) 및 상기 패시브 칩(71)의 상면 및 측면들을 덮는 제2 봉지재(85)가 형성될 수 있다. 상기 제2 봉지재(85)는 에폭시 몰딩 컴파운드(Epoxy Molding Compound)를 포함할 수 있다. 상기 제2 봉지재(85)는 상기 제1 봉지재(81)의 상면 및 측면들을 덮을 수 있다.
도 12를 참조하면, 상기 제2 봉지재(85)를 부분적으로 제거하여 상기 패시브 칩(71)의 상면이 노출될 수 있다. 상기 제2 봉지재(85)는 상기 제1 액티브 칩(61)의 상면 및 측면들을 덮을 수 있다. 상기 제2 봉지재(85) 및 상기 패시브 칩(71)의 상면들은 실질적으로 동일한 평면을 이룰 수 있다.
도 13을 참조하면, 상기 제2 봉지재(85) 및 상기 패시브 칩(71) 상에 열 인터페이스 물질 층(Thermal Interface Material Layer; TIM Layer; 97)이 형성될 수 있다. 상기 열 인터페이스 물질 층(97) 상에 히트 스프레더(Heat Spreader; 98)가 형성될 수 있다. 상기 캐리어(25) 및 상기 버퍼 층(26)이 제거될 수 있다. 상기 배선 구조체(30)의 하면 상에 다수의 외부 단자(49)가 형성될 수 있다.
상기 다수의 외부 단자(49)는 상기 다수의 하부 패드(도 8의 33T)에 접촉될 수 있다. 상기 다수의 외부 단자(49)는 솔더 볼, 도전성 범프, UBM(Under Bump Metallurgy), 도전성 필라(Conductive Pillar), 도전성 리드, 도전성 핀, 또는 이들의 조합을 포함할 수 있다. 싱귤 레이션(singulation) 공정을 이용하여 다수의 반도체 패키지로 분할될 수 있다.
이상, 첨부된 도면을 참조하여 본 발명의 기술적 사상에 따른 실시예들을 설명하였지만, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자는 본 발명이 그 기술적 사상이나 필수적인 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 이상에서 기술한 실시예는 모든 면에서 예시적인 것이며 한정적이 아닌 것으로 이해하여야 한다.
30: 배선 구조체
31: 절연층
33: 신호 배선
34: 열 전달 배선
41: 신호 단자
42: 제1 열 전달 단자
45: 제2 열 전달 단자
49: 외부 단자
51: 신호 패드
52: 제1 열 전달 패드
55: 제2 열 전달 패드
61: 제1 액티브 칩(Active Chip)
71: 패시브 칩(Passive Chip)
81: 제1 봉지재
85: 제2 봉지재
97: 열 인터페이스 물질 층(Thermal Interface Material Layer)
98: 히트 스프레더(Heat Spreader)

Claims (10)

  1. 신호 배선 및 상기 신호 배선과 이격된 열 전달 배선을 갖는 배선 구조체;
    상기 배선 구조체 상의 액티브 칩(Active Chip);
    상기 배선 구조체 및 상기 액티브 칩 사이의 신호 단자;
    상기 배선 구조체 및 상기 액티브 칩 사이에 배치되고 상기 열 전달 배선에 접속된 제1 열 전달 단자;
    상기 배선 구조체 상의 패시브 칩(Passive Chip);
    상기 배선 구조체 및 상기 패시브 칩 사이에 배치되고 상기 열 전달 배선에 접속된 제2 열 전달 단자; 및
    상기 패시브 칩 상의 히트 스프레더(Heat Spreader)를 포함하는 반도체 패키지.
  2. 제1 항에 있어서,
    상기 패시브 칩은 상기 제1 액티브 칩보다 두꺼운 반도체 패키지.
  3. 제1 항에 있어서,
    상기 패시브 칩 및 상기 히트 스프레더 사이의 간격은 상기 제1 액티브 칩 및 및 상기 히트 스프레더 사이의 간격보다 가까운 반도체 패키지.
  4. 제1 항에 있어서,
    상기 패시브 칩은 더미 칩(Dummy Chip)을 포함하는 반도체 패키지.
  5. 제1 항에 있어서,
    상기 신호 단자, 상기 제1 열 전달 단자, 및 상기 제2 열 전달 단자의 각각은 솔더 볼, 도전성 범프, UBM(Under Bump Metallurgy), 도전성 필라(Conductive Pillar), 도전성 리드, 도전성 핀, 또는 이들의 조합을 포함하는 반도체 패키지.
  6. 제1 항에 있어서,
    상기 배선 구조체 및 상기 액티브 칩 사이와 상기 배선 구조체 및 상기 패시브 칩 사이의 제1 봉지재를 더 포함하되,
    상기 제1 봉지재는 필러(Filler) 및 레진(Resin)을 갖는 언더필(Under Fill)을 포함하는 반도체 패키지.
  7. 제1 항에 있어서,
    상기 배선 구조체 상에 배치되고 상기 패시브 칩의 측면 상의 제2 봉지재를 더 포함하는 반도체 패키지.
  8. 제7 항에 있어서,
    상기 제2 봉지재는 상기 액티브 칩의 측면을 덮는 반도체 패키지.
  9. 신호 배선 및 상기 신호 배선과 이격된 열 전달 배선을 갖는 배선 구조체;
    상기 배선 구조체 상에 배치되고 상기 신호 배선 및 상기 열 전달 배선에 접속된 액티브 칩(Active Chip);
    상기 배선 구조체 상에 배치되고 상기 열 전달 배선에 접속된 패시브 칩(Passive Chip); 및
    상기 패시브 칩 상의 히트 스프레더(Heat Spreader)를 포함하는 반도체 패키지.
  10. 신호 배선 및 상기 신호 배선과 이격된 열 전달 배선을 갖는 재-배선층(Re-Distribution Layer; RDL);
    상기 재-배선층 상의 액티브 칩(Active Chip);
    상기 재-배선층 및 상기 액티브 칩 사이의 신호 단자;
    상기 재-배선층 및 상기 액티브 칩 사이에 배치되고 상기 열 전달 배선에 접속된 제1 열 전달 단자;
    상기 재-배선층 상의 패시브 칩(Passive Chip);
    상기 재-배선층 및 상기 패시브 칩 사이에 배치되고 상기 열 전달 배선에 접속된 제2 열 전달 단자;
    상기 패시브 칩 상의 히트 스프레더(Heat Spreader);
    상기 재-배선층의 하면 상의 외부 단자; 및
    상기 재-배선층 상에 배치되고 상기 액티브 칩 및 상기 히트 스프레더 사이에 연장된 봉지재를 포함하는 반도체 패키지.

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US8957525B2 (en) * 2012-12-06 2015-02-17 Texas Instruments Incorporated 3D semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
US10291397B2 (en) * 2016-12-16 2019-05-14 Intel Corporation Active interposer for localized programmable integrated circuit reconfiguration
KR102527409B1 (ko) * 2016-12-19 2023-05-02 에스케이하이닉스 주식회사 칩들 사이에 열 전달 블록을 배치한 반도체 패키지 및 제조 방법
JP2018107370A (ja) * 2016-12-28 2018-07-05 ルネサスエレクトロニクス株式会社 半導体装置
US10276551B2 (en) * 2017-07-03 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device package and method of forming semiconductor device package
US10431517B2 (en) * 2017-08-25 2019-10-01 Advanced Micro Devices, Inc. Arrangement and thermal management of 3D stacked dies
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