TWI808338B - Semiconductor device - Google Patents

Abstract

Embodiments provide a semiconductor device that suppresses an increase in the area of a semiconductor substrate. The semiconductor device (1) of the embodiment includes: a semiconductor substrate (10), a first semiconductor layer (12), a first conductor (13), a first power line (PW), a second power line (GW), and a circuit (3). The semiconductor substrate (10) has: a first surface, a second surface facing the first surface, and a third surface provided between the first surface and the second surface. The first semiconductor layer (12) is provided along the first surface from the third surface. The first conductor (13) is provided on the first semiconductor layer (12). The first power line (PW) is electrically connected to the first conductor (13). The second power line (GW) is electrically connected to the semiconductor substrate (10). The circuit (3) is provided on the semiconductor substrate (10) and connected to the first power line (PW) and the second power line (GW).

Description

Semiconductor device

Embodiments of the present invention relate to a semiconductor device including a bypass capacitor. [Related application]

This application claims the priority of Japanese Patent Application No. 2019-169564 (filing date: September 18, 2019) and Japanese Patent Application No. 2020-029110 (filing date: February 25, 2020), which are the basic applications. This application incorporates the entire content of the basic application by referring to this basic application.

It is known to provide bypass capacitors on semiconductor substrates in order to suppress fluctuations in power supply voltage.

The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing an increase in the area of a semiconductor substrate.

A semiconductor device according to an embodiment includes a semiconductor substrate, a first semiconductor layer, a first conductor, a first power line, a second power line, and a circuit. The semiconductor substrate has: a first surface, a second surface facing the first surface, and a third surface provided between the first surface and the second surface. The first semiconductor layer is provided along the first surface from the third surface. The first conductor is provided on the first semiconductor layer. The first power line is electrically connected to the first conductor. The second power line is electrically connected to the semiconductor substrate. The circuit is provided on the semiconductor substrate and connected to the first power line and the second power line.

Embodiments are described below with reference to the drawings. Each embodiment is an example of a device or a method that actualizes the technical idea of the invention. The drawings are schematic or conceptual representations, and the dimensions and proportions of the drawings may not necessarily be the same as the actual ones. The technical idea of the present invention is not defined by the shape, structure, arrangement, etc. of the constituent elements.

In addition, in the following description, the same code|symbol is attached|subjected to the component which has substantially the same function and a structure. The numerals following the characters constituting the reference symbols are referred to by the reference symbols including the same characters, and are used when distinguishing elements having the same constitution from each other. When there is no need to distinguish elements indicated by reference symbols containing the same characters, these elements are referred to by reference symbols containing only characters, respectively.

[1] First Embodiment Next, the semiconductor device 1 according to the first embodiment will be described.

[1-1] Configuration of semiconductor device 1 [1-1-1] Overall configuration of semiconductor device 1 FIG. 1 shows a configuration example of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 is, for example, integrated on one semiconductor substrate. As shown in FIG. 1 , the semiconductor device 1 includes power lines PW and GW, pads P1 and P2 , a capacitor unit 2 , and a circuit unit 3 .

The power supply lines PW and GW are used to supply the power supply voltage to each circuit included in the semiconductor device 1 . The pads P1 and P2 are respectively configured to be connectable to devices outside the semiconductor device 1 . The pad P1 is a power pad on the positive side of the semiconductor device 1 and is connected to the power line PW. For example, a power supply voltage VDD is applied to the pad P1. The pad P2 is a power pad on the negative side of the semiconductor device 1 and is connected to the power line GW. The pad P2 is connected to the ground node GND, for example.

The capacitor unit 2 is connected between the power line PW and the power line GW. The capacitor unit 2 is used to suppress fluctuations in the voltage of the power line PW. The circuit unit 3 is connected to the power supply lines PW and GW, respectively. The circuit unit 3 includes a circuit that operates according to a voltage supplied via the power line PW. The circuit included in the circuit unit 3 may be, for example, a peripheral circuit of a NAND flash memory.

FIG. 2 shows an example of the configuration of the capacitor unit 2 included in the semiconductor device 1 according to the first embodiment. As shown in FIG. 2 , the capacitance unit 2 includes, for example, a plurality of capacitors CP. One electrode of each of the plurality of capacitors CP is connected to the power line PW, and the other electrode is connected to the power line GW. That is, a plurality of capacitors CP are connected in parallel between the power lines PW and GW. Each of the plurality of capacitors CP is also called, for example, a bypass capacitor.

[1-1-2] Structure of semiconductor device 1 Hereinafter, an example of the configuration of the capacitor unit 2 in the first embodiment will be described.

Also, in the drawings referred to below, the plane defined by the X direction and the Y direction corresponds to the surface of the semiconductor substrate 10 on which the semiconductor device 1 is formed, and the Z direction corresponds to the vertical direction of the surface of the semiconductor substrate 10 on which the semiconductor device 1 is formed. In the plan view, hatching lines are added appropriately for the convenience of observing the figure. Hatching added to a plan view is not necessarily related to the material or characteristics of the elements to which the hatching is added. In the cross-sectional view, constituent elements such as an insulating layer (interlayer insulating film), wiring, and a contact portion are appropriately omitted for the convenience of viewing the drawing.

In the following description, a region of the semiconductor substrate 10 including the capacitor CP included in the capacitor unit 2 is referred to as a capacitor region CA. In addition, a region of the semiconductor substrate 10 including a transistor included in the circuit portion 3 is referred to as a transistor region TA.

FIG. 3 shows an example of the planar layout in the capacitor region CA of the semiconductor device 1 according to the first embodiment. As shown in FIG. 3 , the capacitor unit 2 includes a plurality of conductors 13 , conductors 17 and 18 , a diffusion region 19 , and a plurality of contact portions CT.

Each conductor 13 corresponds to one side electrode of one capacitor CP. The plurality of conductors 13 are arranged in a matrix of, for example, 4 rows and 3 columns. Each electrical conductor 13 is arranged overlapping with the electrical conductor 17 . The conductor 17 functions as a power line PW. Each electric conductor 13 is electrically connected to the electric conductor 17 via the contact portion CT.

The diffusion region 19 is disposed on the surface of the semiconductor substrate 10 . The diffusion region 19 is, for example, a P-type diffusion region, and is electrically connected to the semiconductor substrate 10 . The conductor 18 is overlapped on the diffusion region 19 . The conductor 18 functions as the power line GW. Diffusion region 19 is electrically connected to conductor 18 via contact portion CT.

In addition, the number and arrangement of capacitors CP are not limited to the example shown in FIG. 3 . In addition, the area of the diffusion region 19 or the positional relationship with the conductor 13 is not limited to the example shown in FIG. 3 .

FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3, showing an example of the cross-sectional structure in the capacitor region CA of the semiconductor device 1 according to the first embodiment. As shown in FIG. 4 , the semiconductor device 1 further includes an insulator layer 11 and a semiconductor layer 12 . The semiconductor substrate 10 includes a plurality of recesses CC.

The insulator layer 11 is respectively provided on the surface of the semiconductor substrate 10 , the side surface and the bottom of the concave portion CC. The insulator layer 11 provided on the surface of the semiconductor substrate 10 and the insulator layer 11 provided in the concave portion CC are continuously provided. The semiconductor layer 12 is provided on the insulator layer 11 in a region corresponding to each capacitor CP. The semiconductor layer 12 has a portion provided along the recesses CC, and is divided, for example, between adjacent recesses CC. The conductor 13 is disposed on the semiconductor layer 12 . Recess CC is filled with conductor 13 . In the region corresponding to each capacitor CP, the side surfaces of the semiconductor layer 12 and the conductor 13 are aligned.

With such a configuration, in each recess CC, the semiconductor layer 12 and the conductor 13 function as one electrode of the capacitor CP, the insulator layer 11 functions as an insulator between electrodes of the capacitor CP, and the semiconductor substrate 10 functions as the other electrode of the capacitor CP. One electrode of the capacitor CP is connected to a conductor 17 that functions as a power supply line PW via a contact portion CT. The semiconductor substrate 10 that functions as the other electrode of the capacitor CP is connected to the conductor 18 that functions as the power line GW via the diffusion region 19 and the contact portion CT.

FIG. 5 shows an example of a cross-sectional structure in the transistor region TA of the semiconductor device 1 according to the first embodiment. Also, the area shown in FIG. 5 includes a part of the capacitor area CA. As shown in FIG. 5 , the transistor area TA includes, for example, a transistor TR. In the transistor region TA, the semiconductor device 1 further includes an insulator 14 , a well region 15 , a diffusion region 16 , and a conductor 30 .

The insulator 14 is formed inside the semiconductor substrate 10 , and its upper end contacts the upper surface of the semiconductor substrate 10 . The insulator 14 is used as an insulating region STI (Shallow Trench Isolation) between adjacent well regions, and divides a part of the semiconductor substrate 10 in the transistor region TA. The well region 15 is formed in a region partitioned by the insulator 14 inside the semiconductor substrate 10 , and its upper end is in contact with the upper surface of the semiconductor substrate 10 . Two diffusion regions 16 are formed inside the well region 15 , and their upper ends are in contact with the upper surface of the semiconductor substrate 10 .

A plurality of conductors 30 are disposed above the well region 15 . The plurality of conductors 30 are wirings corresponding to the drain, source and gate of the transistor TR, respectively. The two diffusion regions 16 function as the drain or the source of the transistor TR respectively. The two diffusion regions 16 are electrically connected to the corresponding conductors 30 via the contacts CT. The semiconductor layer 12 is disposed over the well region 15 and on the insulator layer 11 . The conductor 13 is disposed on the semiconductor layer 12 . The semiconductor layer 12 and the conductor 13 function as a gate electrode of the transistor TR. The set of the semiconductor layer 12 and the conductor 13 is electrically connected to the conductor 30 through the contact portion CT.

[1-2] Manufacturing method Hereinafter, an example of a series of manufacturing steps for forming the capacitor CP and the transistor TR in the first embodiment will be described with appropriate reference to FIG. 6 . FIG. 6 is a flow chart showing an example of the manufacturing process of the semiconductor device 1 according to the first embodiment. 7 to 15 each show an example of a cross-sectional structure including structures corresponding to the capacitor CP and the transistor TR in the manufacturing process of the semiconductor device 1 according to the first embodiment.

First, as shown in FIG. 7 , an insulator layer 21 is formed on the semiconductor substrate 10 (step S101 ). The insulator layer 21 includes, for example, silicon nitride (SiN).

Next, as shown in FIG. 8, the etching part EP is processed (step S102). Specifically, firstly, a mask having an opening in a region corresponding to the etching portion EP is formed by photolithography or the like. Next, the etched portion EP is formed by anisotropic etching using the formed mask. The etching portion EP formed in this process penetrates the insulator layer 21 and stops in the semiconductor substrate 10 . The etched portion EP formed in the transistor region TA has a groove-like shape extending in the Y-axis direction. Compared with the etched part EP provided in the transistor region, the etched part EP formed in the capacitor region CA has a shorter length in the Y-axis direction, for example, a hole shape. Anisotropic etching in this project is, for example, RIE (Reactive Ion Etching).

Next, as shown in FIG. 9 , the insulator 14 is formed (step S103 ). Specifically, first, the insulator 14 is formed to fill the etched portion EP. Next, the insulator 14 formed outside the etched portion EP is removed by, for example, CMP (Chemical Mechanical Polishing). The insulator 14 includes, for example, silicon oxide (SiO ₂ ).

Next, as shown in FIG. 10 , well region 15 is formed (step S104 ). Specifically, in the transistor region TA, the region partitioned by the insulator 14 is doped with, for example, phosphorus to form the well region 15 .

Next, the insulator layer 22 is formed to cover the insulator 14 in the transistor region TA (step S105 ). Specifically, first, the insulator layer 22 is formed on the insulator layer 21 and the insulator 14 . The insulator layer 22 includes, for example, silicon nitride. Next, a mask having an opening in a region corresponding to the capacitor region CA is formed by lithography or the like. Next, the insulator layer 22 formed in the capacitor region CA is removed by anisotropic etching using the formed mask. Anisotropic etching in this project is, for example, RIE.

Next, as shown in FIG. 11, the insulator 14 of the capacitor region CA is removed (step S106). Specifically, for example, the insulator 14 not covered by the insulator layer 22 in the capacitor region CA is removed by wet etching to expose the etched portion EP in the capacitor region CA.

Next, as shown in FIG. 12 , the insulating layers 21 and 22 are removed (step S107 ). Specifically, for example, the insulator layers 21 and 22 are removed by wet etching. Next, the insulator 14 protruding from the semiconductor substrate 10 is removed, for example, by CMP.

Next, as shown in FIG. 13, the insulator layer 11, the semiconductor layer 12, and the conductor 13 are formed (step S108). Specifically, first, the insulator layer 11 is formed on the surface of the semiconductor substrate 10 , the side surfaces and the bottom of the etched portion EP, the surface of the insulator 14 , and the surface of the well region 15 . Next, the semiconductor layer 12 is formed on the surface of the insulator layer 11 . In addition, the conductor 13 is formed on the surface of the semiconductor layer 12 so as to fill the etched portion EP. Insulator layer 11 includes, for example, silicon oxide. The semiconductor layer 12 includes, for example, silicon (Si). Conductor 13 contains, for example, tungsten (W).

Next, the mask 23 is formed and processed (step S109). Specifically, the mask 23 is formed on the conductor 13 by photolithography or the like. The mask 23 covers, for example, a region corresponding to one electrode of the capacitor CP and a region corresponding to the gate electrode of the transistor TR, and has openings in other regions.

Next, as shown in FIG. 14, the semiconductor layer 12 and the conductor 13 are processed (step S110). Specifically, part of the semiconductor layer 12 and the conductor 13 are removed by anisotropic etching using the mask 23 to expose a part of the surface of the insulator layer 11 . The mask 23 is then removed, for example, by wet etching (step S111 ).

Next, as shown in FIG. 15 , the diffusion region 16 is formed (step S112 ). Specifically, the diffusion region 16 is formed by doping, for example, boron in the well region 15 . Thereafter, various wirings including the conductor 17 and the conductor 30 are provided on the semiconductor substrate 10 . Next, the conductor 17 and the capacitor CP are connected through the contact portion CT. The conductor 30 is connected to the transistor TR through the contact portion CT.

The capacitor CP and the transistor TR are respectively formed through the manufacturing process described above. In addition, the manufacturing process described above is only an example, and other processes may be inserted between each manufacturing process.

[1-3] Effects of the first embodiment According to the semiconductor device 1 of the first embodiment described above, the manufacturing cost of the semiconductor device 1 can be suppressed. Hereinafter, detailed effects of the semiconductor device 1 according to the first embodiment will be described.

For example, the consumption current of a circuit may vary according to the operation of the circuit. For example, bypass capacitors are used to suppress fluctuations in the voltage of the power supply line when the consumption current changes. When the current consumption of the circuit increases, the bypass capacitor supplies the charged charge to the circuit, thereby suppressing fluctuations in the voltage of the power line.

However, when a bypass capacitor is provided on a semiconductor substrate, there is a problem that a large area is required for the bypass capacitor in order to obtain a desired capacitance. FIG. 16 shows an example of the planar layout of the capacitor unit 2 included in the comparative example of the semiconductor device 1 according to the first embodiment. FIG. 17 is a cross-sectional view corresponding to line XVII-XVII in FIG. 16 , showing a cross-sectional structure of the capacitor unit 2 included in the comparative example.

As shown in FIG. 16 , the capacitor unit 2 included in the comparative example includes a plate capacitor FC. As shown in FIG. 17, the region where the semiconductor layer 12 and the conductor 13 are provided on the surface of the semiconductor substrate 10 functions as a plate capacitor FC. In the flat panel capacitor FC, the occupied area on the semiconductor substrate 10 is substantially equal to the surface area of one electrode.

In contrast, the semiconductor device 1 according to the first embodiment includes a plurality of capacitors CP, and each capacitor CP has a portion provided along the concave portion CC. The surface area of one electrode of the capacitor CP is larger than the occupied area on the semiconductor substrate 10 . That is, compared with the plate capacitor FC of the comparative example, the capacitor CP of the semiconductor device 1 according to the first embodiment has a larger capacitance per unit area relative to the occupied area on the semiconductor substrate 10 .

Thereby, according to the semiconductor device 1 of the first embodiment, the area occupied by the capacitor can be reduced while maintaining the capacitance of the capacitor. Since the occupied area of the bypass capacitor can be reduced, the size of the semiconductor substrate 10 on which the semiconductor device 1 is provided can be reduced, and the manufacturing cost of the semiconductor device 1 can be suppressed.

In addition, in the semiconductor device 1 of the first embodiment, some steps of the process of forming the transistor TR and the capacitor CP can be integrated. Specifically, as shown in step S102 of FIG. 6 , shapes corresponding to the concave portion CC and the insulating region STI can be simultaneously processed as a plurality of etching portions EP. In addition, the semiconductor layer 12 and the conductor 13 which is one electrode of the capacitor CP, and the gate electrode of the transistor which is the semiconductor layer 12 and the conductor 13 can be formed and processed simultaneously.

Thereby, in the semiconductor device 1 according to the first embodiment, it is possible to suppress an increase in the number of processes accompanying the formation of the capacitor CP. Therefore, the semiconductor device 1 according to the first embodiment can suppress the manufacturing cost.

[2] Second Embodiment The second embodiment is a specific example of the layout of the capacitor CP included in the semiconductor device 1 of the first embodiment. Hereinafter, regarding the semiconductor device 1 of the second embodiment, points different from those of the first embodiment will be described.

[2-1] Composition FIG. 18 shows an example of the circuit configuration of the semiconductor device 1 according to the second embodiment. As shown in FIG. 18 , a semiconductor device 1 according to the second embodiment includes capacitor units CU1 to CU4 as a capacitor unit 2 , includes circuits 3 a and 3 b as a circuit unit 3 , and further includes a signal line SW. In addition, the resistance component of the power supply line PW is represented by resistance RP1 and RP2. In addition, the description related to the pad P2 and the power line GW is omitted, and it shows with a ground symbol.

The signal CLK is input to the circuit 3a. Next, the circuit 3a outputs a signal based on the signal CLK to the circuit 3b via the signal line SW. The circuits 3a and 3b are supplied with a power supply voltage from the power supply line PW. Hereinafter, the connection part of the power line PW and the circuit 3a or 3b is called the power supply terminal of the circuit 3a and the power supply terminal of the circuit 3b. The voltage at the power supply terminal of the circuit 3a is called voltage VDD1, and the current consumed by the circuit 3a is called current I1.

The capacitor units CU1 to CU4 respectively include, for example, a plurality of capacitors CP connected in parallel. One electrode of each of the capacitor units CU1 and CU2 is provided so that the distance from the power supply terminal of the circuit 3a becomes short. One electrode of each of the capacitor units CU3 and CU4 is provided so that the distance from the power supply terminal of the circuit 3b becomes short. In addition, the resistance component of the power supply line PW from the pad P1 to the capacitor units CU1 and CU2 and the circuit 3a is represented by the resistance RP1. The resistance component of the power line PW from the capacitor units CU1 and CU2 and the circuit 3a to the capacitor units CU3 and CU4 and the circuit 3b is represented by a resistance RP2.

FIG. 19 shows an example of the planar layout of the semiconductor device 1 according to the second embodiment. As shown in FIG. 19, the semiconductor device 1 according to the second embodiment further includes contacts CT1 to CT8. As shown in FIG. 19 , the power line PW extends from the pad P1 in the X direction.

The circuits 3a and 3b are arranged along the power line PW. The circuit 3a is arranged closer to the pad P1 than the circuit 3b. The respective power supply terminals of the circuits 3a and 3b are connected to the power supply line PW. The circuit 3a and the circuit 3b are connected via a signal line SW. Capacitor units CU1 and CU2 are arranged in the vicinity of the power supply terminals of the circuit 3a. Capacitor units CU3 and CU4 are arranged in the vicinity of the power supply terminals of the circuit 3b.

The contact portion CT1 connects the power line PW to one electrode of the capacitor unit CU1. The contact portion CT2 connects the power line PW to one electrode of the capacitor unit CU2. The contact portion CT3 connects the power line PW to one electrode of the capacitor unit CU3. The contact portion CT4 connects the power line PW to one electrode of the capacitor unit CU4. The contact portion CT5 connects the power line PW to the power terminal of the circuit 3a. The contact portion CT6 connects the power line PW to the power terminal of the circuit 3b. The contact portion CT7 connects the signal line SW to the signal output portion of the circuit 3a. The contact portion CT8 connects the signal line SW to the signal input portion of the circuit 3b.

In the example shown in FIG. 19 , the resistance component of the power line PW from the pad P1 to the portion where the contacts CT1 , CT2 , and CT5 are connected corresponds to the resistance RP1 . In addition, the resistance component from the part where contact part CT1, CT2 and CT5 are connected to the part where contact part CT3 and CT4 and CT6 are connected among power supply line PW corresponds to resistance RP2. Other configurations of the semiconductor device 1 of the second embodiment are the same as those of the first embodiment.

[2-2] Effects of the second embodiment According to the semiconductor device 1 of the second embodiment described above, the operational reliability of the semiconductor device 1 can be improved. Hereinafter, detailed effects of the semiconductor device 1 according to the second embodiment will be described.

In the design of a semiconductor device, it is preferable to densely arrange components such as a plurality of circuits or capacitors. When elements are densely laid out, the size of the semiconductor substrate can be suppressed, and the manufacturing cost of the semiconductor device can be suppressed. In addition, it is preferable that the resistance component of the wiring provided between the bypass capacitor and the power supply terminal of the circuit is small. When the resistance component of the wiring provided between the bypass capacitor and the power supply terminal of the circuit is small, the bypass capacitor can supply charges to the circuit as soon as possible, and can further suppress fluctuations in the power supply voltage.

However, when a certain element is large in size, for example, a capacitor is large in size, if the circuit and bypass capacitors are densely arranged, the wiring connecting the bypass capacitor and the power supply terminal of the circuit may become longer. FIG. 20 shows an example of a circuit configuration of a semiconductor device 1 as a comparative example of the second embodiment. As shown in FIG. 20, the difference between the semiconductor device 1 of the comparative example and the second embodiment is that the capacitor unit 2 in the comparative example includes plate capacitors FC1 to FC4, and the resistance components of the power line PW are represented by resistors RP3 to RP5.

Plate capacitors FC1 to FC4 are integrated settings. The circuit 3a is arranged not close to the plate capacitors FC1 to FC4 but close to the pad P1. The circuit 3b is disposed farther from the pad P1 than the plate capacitors FC1 to FC4. In addition, the resistance component of the power supply line PW from the pad P1 to the power supply terminal of the circuit 3a is represented by the resistance RP3. The resistance component of the power line PW from the power supply end of the circuit 3a to the plate capacitors FC1-FC4 is represented by a resistance RP4. The resistance component of the power supply line PW from the plate capacitors FC1 to FC4 to the power supply terminal of the circuit 3b is represented by a resistance RP5.

FIG. 21 shows an example of a planar layout of a semiconductor device 1 as a comparative example of the second embodiment. As shown in FIG. 21 , the semiconductor device 1 of the comparative example further includes contact portions CT1 to CT8 . Each of the plate capacitors FC1 to FC4 included in the comparative example and each of the capacitor units CU1 to CU4 included in the semiconductor device 1 of the second embodiment have substantially the same capacitance.

That is, the plate capacitor FC included in the comparative example has a smaller capacitance per unit area on the semiconductor substrate 10 than the capacitor unit CU included in the second embodiment. Therefore, the occupied area on the semiconductor substrate 10 of the plate capacitor FC is larger than that of the capacitor unit CU. The layout of the comparative example is different from the layout of the semiconductor device 1 of the second embodiment in order to densely arrange large plate capacitors FC.

Specifically, in the comparative example, the circuit 3a, the panel capacitors FC1 and FC2, the panel capacitors FC3 and FC4, and the circuit 3b are arranged along the power line PW in order from the pad P1. Plate capacitors FC1 to FC4 are arranged between the circuit 3a and the circuit 3b. The power line PW is arranged to overlap the panel capacitors FC1 and FC3. The signal line SW is arranged to overlap the plate capacitors FC2 and FC4. In the comparative example, the resistance component of the power supply line PW up to the connection portion from the pad P1 to the contact portion CT5 corresponds to the resistance RP3. The resistance component of the power line PW from the connection part of the contact part CT5 to the connection part of the contact part CT1-CT4 corresponds to resistance RP4. The resistance component from the connection part of the contact part CT1-CT4 to the connection part of the contact part CT6 corresponds to resistance RP5.

As described above, in the semiconductor device 1 of the comparative example, the power supply line PW connecting the power supply terminal of the circuit 3a and the panel capacitors FC1 to FC4 is long and includes a resistance component equivalent to the resistance RP4. In addition, the power line PW connecting the circuit 3b and the panel capacitors FC1 to FC4 is long and includes a resistance component equivalent to the resistance RP5.

On the other hand, in the semiconductor device 1 according to the second embodiment, the capacitor unit CU occupying an area on the semiconductor substrate 10 smaller than that of the plate capacitor FC is arranged close to the power supply terminal of the circuit. The power supply line PW of the portion connecting the power supply end of the circuit 3a and the capacitor units CU1 and CU2 is shortened, and the resistance component of the power supply line PW of the connected portion is reduced. In addition, the power supply line PW connecting the power supply terminal of the circuit 3b and the capacitor units CU3 and CU4 is shortened, and the resistance component is small.

Accordingly, in the semiconductor device 1 according to the second embodiment, when the circuits and capacitors are densely arranged, the resistance component of the wiring provided between the bypass capacitor and the power supply terminal of the circuit can be reduced. FIG. 22 shows the relationship between voltage and current and time in the semiconductor device of the second embodiment and its modification. The three graphs shown in FIG. 22 respectively show the relationship between the signal CLK and time, the relationship between the current I1 and time, and the relationship between the voltage VDD1 and time from the top. In the graph of the voltage VDD1, the solid line represents the second embodiment, and the dotted line represents the comparative example.

Signal CLK changes from "H" level to "L" level or from "L" level to "H" level at times t1, t2, t3 and t4, respectively. The circuit 3a operates according to the signal CLK, and the current I1 corresponding to the consumption current of the circuit 3a increases at times t1, t2, t3 and t4 respectively. When the current I1 increases, the bypass capacitor supplies the charge and suppresses the variation of the voltage VDD1. In the comparative example, the resistance component between the circuit 3a and the bypass capacitor is large, so the voltage VDD1 fluctuates greatly. On the other hand, in the semiconductor device 1 of the second embodiment, the resistance component between the circuit 3a and the bypass capacitor is small, so the variation of the voltage VDD1 is suppressed to be small. As described above, the semiconductor device 1 of the second embodiment can suppress fluctuations in the power supply voltage more than those of the comparative example. Therefore, the semiconductor device 1 of the second embodiment can improve the operational reliability more than that of the comparative example.

In addition, fluctuations in power supply voltage may also cause jitter. When the circuit intends to operate at high speed, it is better to suppress the generation of jitter. On the other hand, as described above, the semiconductor device 1 according to the second embodiment can suppress fluctuations in the power supply voltage, thereby suppressing occurrence of jitter.

In addition, it is better that the parasitic resistance and parasitic capacitance of the signal wiring are small. When the parasitic resistance and parasitic capacitance of the signal wiring are small, high-speed signals can be stably transmitted.

In the semiconductor device 1 of the comparative example, the circuit 3 a and the circuit 3 b are provided apart from each other and connected by a long signal line SW. When the length of the signal line SW becomes longer, the parasitic resistance may become larger. In addition, the signal line SW is provided to overlap the plate capacitors FC2 and FC4. When the signal line SW is overlapped with other elements such as capacitors, the parasitic capacitance may increase.

On the other hand, in the semiconductor device 1 according to the second embodiment, the circuit 3a and the circuit 3b are provided close to each other and connected by a short signal line SW. In addition, the signal line SW is not overlapped with elements other than the circuit 3a and the circuit 3b.

Thereby, in the semiconductor device 1 of the second embodiment, the parasitic resistance and parasitic capacitance of the signal line SW are small, so high-speed signals can be stably transmitted, and the operation reliability of the semiconductor device 1 can be improved.

[3] The third embodiment The third embodiment is a modified example of the layout and capacitance design of the capacitor CP included in the semiconductor device 1 of the second embodiment. Hereinafter, points different from those of the second embodiment will be described with respect to the semiconductor device 1 of the third embodiment.

[3-1] Composition FIG. 23 shows an example of the circuit configuration of the semiconductor device 1 according to the third embodiment. As shown in FIG. 23, the semiconductor device 1 according to the third embodiment includes capacitor banks CS1 to CS3 as the capacitance unit 2, and includes a circuit 3c as the circuit unit 3. The power line PW includes nodes N1 to N3. In addition, the resistance components of the power supply line PW are represented by resistors RP6 to RP8.

The power line PW is provided from the pad P1 to the power end of the circuit 3c. The distance between the circuit 3c and the power supply end becomes longer in the order of the node N1, the node N2, and the node N3. In addition, the resistance component of the power supply line PW from the pad P1 to the node N3 is represented by the resistance RP6. The resistance component of the power supply line PW from the node N3 to the node N2 is represented by a resistance RP7. The resistance component of the power supply line PW from the node N2 to the node N1 is represented by a resistance RP8.

The capacitor banks CS1 to CS3 respectively include a plurality of capacitors CP. The capacitances of the capacitor banks CS1 to CS3 are different from each other. The capacitance of the capacitor bank CS2 is greater than the capacitance of the capacitor bank CS1. The capacitance of the capacitor bank CS3 is greater than the capacitance of the capacitor bank CS2. For example, the capacitance of the capacitor bank CS2 is 10 times that of the capacitor bank CS1, and the capacitance of the capacitor bank CS3 is 10 times that of the capacitor bank CS2. For example, the capacitance of the capacitor banks CS1 to CS3 is determined by the number of capacitors CP included in each capacitor bank. Capacitor banks CS1 to CS3 are provided between the power line PW and the ground node. Specifically, one side electrodes of the capacitor banks CS1 to CS3 are respectively connected to the nodes N1 to N3.

FIG. 24 shows an example of the planar layout of the semiconductor device 1 according to the third embodiment. As shown in FIG. 24, the semiconductor device 1 according to the third embodiment further includes contact portions CT10 to CT13. In addition, the capacitor banks CS1 to CS3 respectively include a plurality of capacitors CP. The number of capacitors CP included in the capacitor bank increases in the order of capacitor bank CS1, capacitor bank CS2, and capacitor bank CS3. Also, in the example shown in FIG. 24, the number of capacitors CP is simplified.

The power line PW is extended from the pad P1 to the X direction. Along the power supply line PW, a capacitor bank CS3 , a capacitor bank CS2 , a capacitor bank CS1 , and a circuit 3 c are arranged in order close to the pad P1 .

The contact part CT10 connects the power line PW and the power terminal of the circuit 3c. The contact part CT11 connects the power supply line PW and one electrode of the capacitor CP included in the capacitor bank CS1. The plurality of contact portions CT12 each connect the power supply line PW and one electrode of the capacitor CP included in the capacitor bank CS2. The contact portions CT13 each connect the power supply line PW and one electrode of the capacitor CP included in the capacitor bank CS3.

In the example shown in FIG. 24 , the resistance component of the power supply line PW from the pad P1 to the portion where the plurality of contact portions CT13 are connected corresponds to the resistance RP6 . Among the power supply lines PW, the resistance components from the part where the plurality of contact parts CT13 are connected to the part where the plurality of contact parts CT12 are connected correspond to the resistance RP7. Among the power supply line PW, the resistance component from the part where the some contact part CT12 is connected to the part where the contact part CT11 is connected corresponds to resistance RP8. Other configurations of the semiconductor device 1 of the third embodiment are the same as those of the second embodiment.

[3-2] Effects of the third embodiment According to the semiconductor device 1 of the third embodiment described above, the operational reliability of the semiconductor device 1 can be improved. Hereinafter, detailed effects of the semiconductor device 1 according to the third embodiment will be described.

The power supply voltage may vary over a wide frequency range from low frequency to high frequency. Preferably, the bypass capacitor can suppress fluctuations in the power supply voltage in a wide frequency band from low frequency to high frequency. In order to suppress fluctuations in the power supply voltage in the low frequency band, it is preferable that the capacitance of the bypass capacitor is large. On the other hand, even if a bypass capacitor having a capacitance smaller than that in the low frequency band is used, fluctuations in the power supply voltage in the high frequency band can be suppressed. In addition, if the area around the circuit cannot be ensured, it is conceivable to install a bypass capacitor at a position away from the circuit, but the power supply line connecting the circuit and the bypass capacitor may be long. As the power line connecting the circuit and the bypass capacitor becomes longer, the resistance value of the wiring becomes larger. Furthermore, as the length of the power supply line connecting the bypass capacitor and the circuit becomes longer, the ability of the bypass capacitor to suppress voltage fluctuations in the high frequency band may be limited.

In contrast, the semiconductor device 1 of the third embodiment includes capacitor banks CS1 to CS3 having different capacitances. The capacitances of the capacitor banks CS1 to CS3 are designed to be smaller as they are closer to the circuit and larger as they are farther away from the circuit.

For example, the capacitor bank CS1 is provided to have a small capacitance near the power supply terminal of the circuit 3c. Since the capacitor bank CS1 is connected to the circuit 3c via the short-distance power supply line PW, it has an excellent ability to suppress voltage fluctuations even in a high-frequency band. In addition, since the capacitor bank CS1 has a small capacitance, it occupies a small area and does not hinder the layout around the circuit 3c. The capacitor bank CS1 mainly suppresses fluctuations in the power supply voltage in the high frequency band.

The capacitor bank CS2 is provided at a position where the power supply line PW extends from the power supply terminal of the circuit 3c until the resistance value becomes equivalent to the resistance RP8, and has a larger capacitance than CS1. Since the capacitor bank CS2 has a large capacity, it occupies a large area, but since it is separated from the circuit 3c, it does not hinder the layout of other circuits. In addition, since the capacitor bank CS2 has a large capacitance, an effect up to a frequency band lower than that of the capacitor bank CS1 can be expected. Since the capacitor bank CS2 is connected to the circuit 3c via the medium-distance power supply line PW, the ability to suppress voltage fluctuations in the high frequency band may be appropriately limited. When the effects of capacitance magnitude and wiring length are combined, the capacitor bank CS2 suppresses fluctuations in the power supply voltage in a lower frequency band than the capacitor bank CS1.

The capacitor bank CS3 is provided at a position where the power supply line PW extends from the power supply terminal of the circuit 3c until the resistance value is equal to the sum of RP7 and RP8, and has a larger capacitance than CS2. Since the capacitor bank CS3 has a larger capacitance, it occupies a larger area, but because it is far away from the circuit 3c, it will not interfere with the layout of other circuits. In addition, since the capacitor bank CS3 has a larger capacitance, an effect up to a frequency band lower than that of the capacitor bank CS2 can be expected. Since the capacitor bank CS3 is connected to the circuit 3c via the long-distance power supply line PW, the ability to suppress voltage fluctuations in the high frequency band may be greatly limited. When the effects of capacitance and wiring length are combined, the capacitor bank CS3 suppresses fluctuations in the power supply voltage in a frequency band lower than that of the capacitor bank CS2.

As described above, according to the semiconductor device 1 of the third embodiment, fluctuations in the power supply voltage can be suppressed over a wide frequency band without concentrating capacitors around the circuit. Furthermore, in the semiconductor device 1 according to the third embodiment, by using the capacitor CP having a portion along the recess CC, it is possible to suppress an increase in the area occupied by the capacitor around the circuit.

[4] Other modified examples, etc. In the first embodiment, an example is described in which the semiconductor layer 12 and the conductor 13 are separated between adjacent recesses CC in the capacitor region CA, but the structure of the capacitor region CA is not limited to this. For example, the semiconductor layer 12 and the conductor 13 may not be separated in the capacitor region CA. FIG. 25 shows an example of a cross-sectional structure in a capacitor region CA in a modified example. As shown in FIG. 25 , in the capacitor region CA, the semiconductor layer 12 and the conductor 13 are continuously provided, thereby connecting a plurality of capacitors CP in parallel. In addition, in the example shown in FIG. 25, one electrode of the capacitor CP is connected to the conductor 17 via one contact portion CT, but it may be connected via a plurality of contact portions CT.

In the first embodiment, an example of a series of manufacturing processes up to the formation of the capacitor CP and the transistor TR was described, but the manufacturing process is not limited to this. For example the insulator layer may be a multilayer structure. For example, the insulator layer 21 may be a multilayer structure of silicon oxide and silicon nitride. For example, a barrier metal may be provided between the semiconductor layer 12 and the conductor 13 . For example, titanium nitride (TiN) may be provided between polysilicon and tungsten. In addition, tungsten nitride may be provided between polysilicon and tungsten.

In the first embodiment, one type of shape of the capacitor CP is shown and described, but the shape of the capacitor CP is not limited to the example. FIG. 26 shows an example of a cross-sectional structure of capacitors CPa to CPc in a modified example. As shown in FIG. 26 , among the capacitors CPa to CPc, the shape of the concave portion CC is different from each other. The capacitor CPa is the same as the capacitor CP described in the first embodiment. Compared with the capacitor CPa, the capacitor CPb is provided in the recess CC which is formed relatively wider and deeper. Compared with the capacitor CPc, the capacitor CPc is provided in the recess CC formed to be relatively narrow and shallow. That is, the cross-sectional area of the recess is changed by changing the width and depth of the recess. For example, by separately forming the recessed portion CC as described above, capacitors having different cross-sectional shapes may be formed separately. That is, capacitors having different capacitances may be formed separately by forming recesses CC of different cross-sectional areas separately.

In the third embodiment, an example in which the magnitude of the capacitance is realized by the number of capacitors CP included is described for the capacitor bank CS, but the present invention is not limited thereto. For example, as described with reference to FIG. 26 , capacitor banks with different capacitances may be formed using capacitors with different cross-sectional shapes. For example, the small-capacity capacitor bank CS1 may be formed using a narrow and shallow capacitor CPc, the capacitor bank CS2 may be formed using a capacitor CPa, and the large-capacity capacitor bank CS3 may be formed using a wide and deep capacitor CPb.

In the first to third embodiments, an example of the case where the capacitor CP is formed in the concave portion CC is shown, but the shape of the portion where the capacitor CP is formed is not limited to the concave portion. For example, the capacitor CP may be formed in a slit formed in the semiconductor substrate 10 . In such a case, the semiconductor layer 12 in the capacitor CP has a portion extending in a direction parallel to the surface of the semiconductor substrate 10 .

In the third embodiment, the number of capacitors CP respectively included in the capacitor banks CS1 to CS3 is described with reference to the example of FIG. 24 , but the number of capacitors CP respectively included in the capacitor banks CS1 to CS3 is not limited thereto. In addition, the ratio of the respective capacitances of the capacitor groups CS1 to CS3 is not limited to the example described with reference to FIG. 24 . For example, as an example of a circuit layout suitable for high-speed operation, it is conceivable to set the ratio of the respective capacitances of the capacitor banks CS1 to CS3 to 1:10:1000. In addition, the size of the capacitor bank CS3 may be changed within a range of, for example, 10 to 1000 times the capacitor bank CS2. In addition, for example, the capacitance of the capacitor bank CS2 may be greater than the capacitance of the capacitor bank CS1 by 1 digit, and the capacitance of the capacitor bank CS3 may be greater than the capacitance of the capacitor bank CS2 by 1 to 3 digits.

In the first to third embodiments, an example of a case where the pad P1 is connected to the power supply line GW and the capacitor unit 2 is connected to the power supply line GW will be described. However, the wiring to which the capacitor unit 2 is connected is not limited to the power line GW connected to the pad P1. FIG. 27 shows a configuration example of a semiconductor device 1 according to a modified example. As shown in FIG. 27, the semiconductor device 1 of the modified example differs from the semiconductor device 1 of the first embodiment in that it further includes a voltage generating circuit 4 and a power line PW2, and the capacitor unit 2 and the circuit unit 3 are connected between the power line PW2 and the power line GW. As described above, the capacitor unit 2 may be connected to, for example, a wiring to which a voltage generated inside the semiconductor device is applied.

In the first to third embodiments, an example is described in which the power line PW and the capacitor CP are connected via one contact portion CT. However, a plurality of contact portions may be connected between the power line PW and the capacitor CP, and different wirings may be routed midway.

In the third embodiment, an example of a case where a plurality of capacitors CP is connected to the power line PW via the contact portion CT will be described for the capacitor bank. However, the configuration of the capacitor bank is not limited to the example described in the third embodiment. For example, a capacitor bank is formed by collectively connecting one electrode of a plurality of capacitors CP arranged collectively in a certain area. When a plurality of capacitor banks are provided on the semiconductor substrate, each of the plurality of capacitor banks can be divided into independent capacitor banks by the capacitance of each capacitor bank and the connection position between each capacitor bank and the power line PW.

The shape referred to as the concave portion CC in this specification can be called differently. For example, the semiconductor substrate 10 having the recess CC can be said to be the semiconductor substrate 10 having a first surface, a second surface facing the first surface, and a third surface provided between the first surface and the second surface. The first surface is, for example, the surface of the semiconductor substrate 10 . The second surface is, for example, the back surface of the semiconductor substrate 10 . The third surface is, for example, the bottom of the concave portion CC. In addition, the semiconductor layer 12 provided along the concave portion CC can be said to be the semiconductor layer 12 provided along the first surface from the third surface. In addition, for example, a capacitor having a fourth surface provided between the first surface and the second surface and having a semiconductor layer arranged along the first surface from the fourth surface may have a capacitance different from that of a capacitor having a semiconductor layer arranged along the first surface from the third surface. As described above, capacitors having different capacitances may be formed separately by providing a plurality of surfaces such as the third surface and the fourth surface between the first surface and the second surface. That is, by providing a plurality of surfaces such as the third surface and the fourth surface, the recesses CC having different cross-sectional areas may be formed separately.

"Connection" in this specification means electrical connection, for example, does not exclude the interposition of other elements therebetween. In addition, the "electrical connection" may be made via an insulator as long as it can operate in the same way as the electrical connector.

[5] Fourth Embodiment The semiconductor device of the fourth embodiment is a specific example in which the semiconductor device 1 of the third embodiment includes a plurality of circuits. Hereinafter, the difference between the semiconductor device 1 of the fourth embodiment and the first to third embodiments will be described.

[5-1] Composition FIG. 28 shows an example of the circuit configuration of the semiconductor device 1 according to the fourth embodiment. As shown in FIG. 28 , the semiconductor device 1 according to the fourth embodiment includes capacitor banks CS10d, CS10e, CS10f, CS20 and CS30 as capacitor unit 2 and circuits 3d, 3e and 3f as circuit unit 3 . The power line PW includes a node N4.

The power line PW is provided from the pad P1 to the respective power terminals of the circuits 3d, 3e, and 3f. Specifically, the corresponding portion of the power line PW from the pad P1 to the node N4 is shared by the circuits 3d, 3e and 3f. On the other hand, the corresponding portions of the power supply line PW from the node N4 to the respective power supply terminals of the circuits 3d, 3e and 3f are independently provided in the circuits 3d, 3e and 3f.

One electrode of each of the capacitor banks CS10d, CS10e, CS10f, CS20, and CS30 is connected to the power supply line PW, and the other electrode of each is grounded. One electrode of the capacitor bank CS10d is connected between the power supply terminal of the circuit 3d and the node N4. One electrode of the capacitor bank CS10e is connected between the power supply terminal of the circuit 3e and the node N4. One electrode of the capacitor bank CS10f is connected between the power supply terminal of the circuit 3f and the node N4. Between the node N4 and the pad P1, one electrode of each of the capacitor banks CS20 and CS30 is sequentially connected in the direction from the node N4 to the pad P1.

The respective capacitances of the capacitor banks CS10d, CS10e, and CS10f are, for example, substantially equal. The capacitance of the capacitor bank CS20 is greater than that of any one of the capacitor banks CS10d, CS10e, and CS10f. The capacitance of the capacitor bank CS20 is, for example, 10 times the capacitance of the capacitor bank CS10d. The capacitance of the capacitor bank CS30 is greater than the capacitance of the capacitor bank CS20. The capacitance of the capacitor bank CS30 is, for example, 10 times the capacitance of the capacitor bank CS20.

That is, the capacitor banks CS10d, CS20, and CS30 are arranged in order of smaller capacitance from the circuit 3d toward the pad P1. The capacitor banks CS10e, CS20, and CS30 are arranged in order of smaller capacitance from the circuit 3e toward the pad P1. The capacitor banks CS10f, CS20, and CS30 are arranged in order of smaller capacitance from the circuit 3f toward the pad P1.

FIG. 29 shows an example of the planar layout of the semiconductor device 1 according to the fourth embodiment. As shown in FIG. 29, the semiconductor device 1 according to the fourth embodiment further includes contact portions CT20d, CT20e, CT20f, CT21d, CT21e, CT21f, CT22, and CT23. In addition, the capacitor banks CS10d, CS10e, CS10f, CS20, and CS30 each include a plurality of capacitors CP. The number of capacitors CP included in the capacitor bank increases, for example, in the order of capacitor bank CS10d, capacitor bank CS20, and capacitor bank CS30. Also, in the example shown in FIG. 29, the number of capacitors CP is simplified.

The power line PW is extended from the pad P1 to the X direction. The capacitor bank CS30, the capacitor bank CS20, the capacitor bank CS10d, and the circuit 3d are arranged in this order from a position close to the pad P1 along the power supply line PW. The circuit 3e is arranged in parallel with the capacitor bank CS20 in the Y direction. The circuit 3f is arranged in parallel with the capacitor bank CS20 in the Y direction and on the opposite side of the circuit 3e. The capacitor bank CS10e is arranged in parallel with the circuit 3e in the X direction and between the capacitor bank CS10d and the capacitor bank CS20 in the Y direction. The capacitor bank CS10f is arranged in parallel with the circuit 3f in the X direction and between the capacitor bank CS10d and the capacitor bank CS20 in the Y direction. Moreover, the power supply line PW has the branch part F1 between capacitor bank CS10d and capacitor bank CS20, and extends from branch part F1 to a Y direction. The branch part F1 corresponds to the node N4.

The contact portions CT20d, CT20e, and CT20f connect the respective power supply terminals of the circuits 3d, 3e, and 3f to the power supply line PW, respectively. The contacts CT21d, CT21e, CT21f, CT22, and CT23 connect one electrode of each of the capacitor banks CS10d, CS10e, CS10f, CS20, and CS30 to the power line PW, respectively. Other configurations of the semiconductor device 1 of the fourth embodiment are the same as those of the third embodiment.

[5-2] Effects of the fourth embodiment As described above, in the semiconductor device 1 according to the fourth embodiment, the power line PW of a plurality of circuits has a portion shared by the plurality of circuits and a portion independently provided corresponding to the plurality of circuits. Similar to the third embodiment, in the power lines PW connected to the circuits 3d, 3e, and 3f, capacitor banks with smaller capacitance are connected closer to the circuits, and capacitor banks with larger capacitance are connected farther from the circuits. In the semiconductor device 1 of the fourth embodiment, by arranging the capacitor bank as described above, even if there are a plurality of circuits, fluctuations in the power supply voltage can be suppressed similarly to the third embodiment.

[5-3] Modification of the fourth embodiment The semiconductor device 1 of the fourth embodiment can be modified in various ways. Hereinafter, the first to fifth modifications of the fourth embodiment will be sequentially described.

[5-3-1] Modification 1 FIG. 30 shows an example of the planar layout of the semiconductor device 1 according to the first modified example of the fourth embodiment. As shown in FIG. 30, the semiconductor device 1 of the first modified example has a configuration in which the capacitor banks CS10d, CS10e, and CS10f are replaced with capacitor banks CS11d, CS11e, and CS11f, respectively, in the semiconductor device 1 of the fourth embodiment.

The capacitor banks CS11d, CS11e, and CS11f each include a plate capacitor FC. That is, in the semiconductor device 1 according to the first modification, among a plurality of capacitor banks with different capacitances, the capacitor bank with a small capacitance includes the plate capacitor FC. In addition, similarly to the fourth embodiment, among the plurality of capacitor banks CS, the closer to the circuit, the smaller the capacitance, and the farther away from the circuit, the larger the capacitance. Other configurations in the first modified example of the fourth embodiment are the same as those of the fourth embodiment.

As described above, in the semiconductor device 1 according to the first modified example of the fourth embodiment, some capacitor banks CS include plate capacitors FC. In the semiconductor device 1, the capacitance of each capacitor bank is designed according to the consumption current of the circuit, the amount of allowable voltage fluctuation, and the like. Therefore, when the capacitance of the capacitor bank close to the circuit is very small, sufficient performance can be obtained even if the capacitor bank close to the circuit includes the plate capacitor FC. Therefore, the semiconductor device 1 according to the first modified example of the fourth embodiment can obtain the same effect as that of the fourth embodiment.

[5-3-2] Second modified example FIG. 31 shows an example of a planar layout of a semiconductor device 1 according to a second modified example of the fourth embodiment. As shown in FIG. 31, the semiconductor device 1 of the second modified example has a configuration in which the capacitor bank CS30 is replaced with the capacitor bank CS31 in the semiconductor device 1 of the fourth embodiment.

Capacitor bank CS31 includes plate capacitor FC. That is, in the semiconductor device 1 according to the second modified example, among a plurality of capacitor banks with different capacitances, the capacitor bank with a large capacitance has a configuration of the plate capacitor FC. In addition, similarly to the fourth embodiment, a plurality of capacitor banks CS are provided such that the closer to the circuit, the smaller the capacitance, and the farther away from the circuit, the larger the capacitance. Other configurations in the second modified example of the fourth embodiment are the same as those of the fourth embodiment.

As described above, in the semiconductor device 1 according to the second modified example of the fourth embodiment, some of the capacitor banks CS are formed using the plate capacitors FC. In the semiconductor device 1, the area of the region where the capacitor bank CS is provided varies depending on the design. Therefore, when the circuit is not densely packed and the area of the substrate has a margin, the large-capacity capacitor bank can also be composed of the plate capacitor FC. Therefore, the semiconductor device 1 according to the second modified example of the fourth embodiment can obtain the same effect as that of the fourth embodiment.

[5-3-3] The third modified example FIG. 32 shows an example of a circuit configuration of a semiconductor device 1 according to a third modified example of the fourth embodiment. As shown in FIG. 32 , a semiconductor device 1 according to the third modified example further includes capacitor banks CS12e and CS21 as capacitor units 2 in the semiconductor device 1 according to the fourth embodiment. The power line PW further includes a node N5. Circuit 3e further includes a second power supply terminal. Also, hereinafter, the power supply terminal of the circuit 3e described in the fourth embodiment is referred to as the first power supply terminal of the circuit 3e to distinguish it from the second power supply terminal of the circuit 3e.

The node N5 of the power supply line PW corresponds to a point where one electrode of the capacitor bank CS30 is connected and a point where one electrode of the capacitor bank CS20 is connected. The node N5 is connected to the second power supply end of the circuit 3e by a power supply line PW. In the power line PW, between the node N5 and the second power supply terminal of the circuit 3e, one electrode of the capacitor bank CS21 and one electrode of the capacitor bank CS12e are sequentially connected from the node N5 to the second power supply terminal of the circuit 3e.

The capacitance of the capacitor bank CS12e is substantially equal to the capacitance of the capacitor bank CS10e, for example. The capacitance of the capacitor bank CS21 is larger than the capacitance of the capacitor bank CS12e and smaller than the capacitance of the capacitor bank CS30. Capacitance of the capacitor bank CS21 is substantially equal to that of the capacitor bank CS20, for example.

FIG. 33 shows an example of a planar layout of a semiconductor device 1 according to a third modification. As shown in FIG. 33 , the semiconductor device 1 according to the third modification further includes contact portions CT20e2 , CT21e2 , and CT24 . The number of capacitors CP included in capacitor bank CS12e is equal to the number of capacitors CP included in capacitor bank CS10e, for example. The number of capacitors CP included in capacitor bank CS21 is equal to the number of capacitors CP included in capacitor bank CS20, for example.

The power line PW has a branch part F2 between the capacitor bank CS20 and the capacitor bank CS30, and extends from the branch part F2 in the Y direction. The divergence part F2 corresponds to the node N5. The branch portion F2 extends in the Y direction along the power line PW, and the capacitor bank CS21 and the capacitor bank CS12e are arranged in order from the branch portion F2.

The contact portion CT20e2 connects the second power supply terminal of the circuit 3e and the power supply line PW. The contact portion CT21e2 connects one electrode of the capacitor bank CS12e to the power line PW. The contact portion CT24 connects one electrode of the capacitor bank CS21 to the power line PW. Other configurations of the semiconductor device 1 of the third modified example are the same as those of the fourth embodiment.

That is, in the semiconductor device 1 of the third modified example, in the power line PW connecting the first power supply terminal and the second power supply terminal of the circuit 3e, a capacitor bank with a smaller capacitance is connected closer to the circuit, and a capacitor bank with a larger capacitance is arranged farther from the circuit. Specifically, on the power line PW connecting the first power supply terminal of the circuit 3e and the pad P1, the capacitor bank CS10e, the capacitor bank CS20, and the capacitor bank CS30 are sequentially arranged from the first power supply terminal of the circuit 3e to the pad P1. On the power line PW connecting the second power supply terminal of the circuit 3e and the pad P1, the capacitor bank CS12e, the capacitor bank CS21, and the capacitor bank CS30 are sequentially arranged from the second power supply terminal of the circuit 3e to the pad P1.

As described above, in the semiconductor device 1 according to the third modified example of the fourth embodiment, when a plurality of different power supply lines are connected to the same circuit block, capacitor banks are respectively arranged on the plurality of power supply lines. Thereby, the jitter of the power supply voltage in the same circuit block can be suppressed very finely, and the effect of reducing jitter can be promoted. As described above, the semiconductor device 1 according to the third modified example of the fourth embodiment can obtain the same effect as that of the fourth embodiment.

Also, the relationship between the capacitance of the capacitor bank CS12e and the capacitance of the capacitor bank CS10e, and the relationship between the capacitance of the capacitor bank CS21 and the capacitance of the capacitor bank CS20 are not limited to being substantially equal to those illustrated in the third modified example. The respective capacitances of capacitor banks CS12e and CS21 can be changed within the range in which the capacitance of capacitor bank CS21 is smaller than that of capacitor bank CS30, and the capacitance of capacitor bank CS12e is smaller than that of capacitor bank CS21.

[5-3-4] Modification 4 FIG. 34 shows an example of a planar layout of a semiconductor device 1 according to a fourth modified example of the fourth embodiment. As shown in FIG. 34, the semiconductor device 1 of the fourth modification has a configuration in which the capacitor banks CS10d, CS10e, and CS10f are replaced with capacitor banks CS13d, CS13e, and CS13f, respectively, in the semiconductor device 1 of the fourth embodiment.

The circuits 3d, 3e, and 3f each include a plurality of elements constituting the circuit, for example, transistors, resistors, and capacitors. The multiple elements included in the circuit 3d are arranged in the circuit area A1 on the substrate. The capacitor bank CS13d is arranged in the circuit area A1. For example, elements included in the circuit 3d surround the capacitor bank CS13d.

A plurality of elements included in the circuit 3e are arranged in the circuit area A2 on the substrate. The capacitor bank CS13e is arranged in the circuit area A2. For example, the capacitor bank CS13e is surrounded by elements included in the circuit 3e.

A plurality of elements included in the circuit 3f are arranged in the circuit area A3 on the substrate. The capacitor bank CS13f is arranged in the circuit area A3. For example, the capacitor bank CS13f is surrounded by elements included in the circuit 3f. In other words, the capacitor groups CS13d, CS13e, and CS13f are respectively arranged in respective regions where the circuits 3d, 3e, and 3f are provided.

In the semiconductor device 1 according to the fourth modified example described above, among a plurality of capacitor banks having different capacitances, a capacitor bank with a small capacitance is provided in the region where the circuit is provided. Thereby, the distance between the power supply terminal of the circuit and the capacitor bank with small capacity can be shortened, the fluctuation of the power supply voltage can be further suppressed, and the jitter can be further reduced. Therefore, the semiconductor device 1 according to the fourth modified example of the fourth embodiment can obtain the same effect as that of the fourth embodiment.

[5-3-5] Fifth modified example FIG. 35 shows an example of the planar layout of the capacitor bank CS30 of the semiconductor device 1 according to the fifth modified example of the fourth embodiment. As shown in FIG. 35, the semiconductor device 1 of the fifth modification further includes wirings W1, W2, and W3 compared to the semiconductor device 1 of the fourth embodiment. Capacitor bank CS30 includes capacitors CPa, CPb, and CPc. As explained with reference to FIG. 26, the capacitors CPa, CPb, and CPc are capacitors of different sizes. In FIG. 35 , the description of the power supply line PW connected to one electrode of the capacitor bank CS30 is omitted for the convenience of viewing the structure. One electrode of each of the plurality of capacitors included in the capacitor bank CS30 is connected to the power supply line PW through the contact portion CT.

As shown in FIG. 35 , the wirings W1 , W2 , and W3 are arranged in such a manner as to overlap the area where the capacitor bank CS30 is provided. A plurality of capacitors CPa, CPb, and CPc are arranged so as not to overlap with the wirings W1, W2, and W3. Specifically, in the vicinity of the wiring W1 and in the region between the wiring W1 and the wiring W2, a plurality of small-sized capacitors CPc are arranged in such a manner that they can be arranged between the wiring W1 and the wiring W2. A plurality of capacitors CPa are arranged in a region between the wiring W2 and the wiring W3. A plurality of large-sized capacitors CPb are arranged in a region divided by the wiring W3 and where there is no other wiring region.

In the semiconductor device 1 according to the fifth modified example described above, one capacitor bank CS includes a plurality of types of capacitors CP of different sizes. The region where the capacitor bank CS is provided may overlap with the region where wiring is provided, for example. There are cases where the wiring and the capacitor CP cannot be installed overlapping each other. In the case where the capacitor CP is arranged avoiding the wiring, by using capacitors of a plurality of sizes, it is possible to suppress an increase in the area of the capacitor bank caused by avoiding the wiring. Therefore, the semiconductor device 1 according to the fifth modified example of the fourth embodiment can obtain the same effect as that of the fourth embodiment.

In addition, elements that cannot be provided overlapping the capacitor CP are not limited to wiring. For example, the configuration shown in the fifth modification is effective when the capacitor CP is arranged avoiding the contact portion connected to the semiconductor substrate, the dummy pattern, and the like.

The first to fifth modifications of the fourth embodiment described above can be combined. For example, the first modification and the fifth modification may be combined. In addition, capacitor CP and plate capacitor FC may be combined to form one capacitor bank CS.

In the embodiments and modifications described above, some examples were given to illustrate the capacitor CP having the semiconductor layer 12 and the conductor 13 provided along the recess CC as one electrode and the plate capacitor FC having the semiconductor layer 12 and the conductor 13 provided on the semiconductor substrate as one electrode. In addition, an example in which the semiconductor substrate 10 functions as the other electrode of the capacitor CP and the other electrode of the plate capacitor FC has been described. Also, the capacitor CP can be said to be, for example, a trench capacitor. The plate capacitor FC can be said to be, for example, a planar capacitor.

Although several embodiments of the present invention have been described, these embodiments are merely examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are also included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalent scope.

1: Semiconductor device 2: capacitor part 3: Circuit department P1, P2: Welding pads PW, GW: power cord CP: Capacitor 10: Semiconductor substrate 11: Insulator layer 12: Semiconductor layer 13: Conductor 14: Insulator 15: well area 16,19: Spread area 17,18: Conductor 30: Conductor CC: Concave CT: contact part TR: Transistor CA: capacitor area TA: Transistor area

[ Fig. 1] Fig. 1 is a block diagram showing a configuration example of a semiconductor device according to a first embodiment. [ Fig. 2] Fig. 2 is a circuit diagram showing a configuration example of the capacitor unit 2 included in the semiconductor device according to the first embodiment. [ Fig. 3] Fig. 3 is a plan view showing an example of a planar layout in a capacitor region of the semiconductor device according to the first embodiment. [ Fig. 4] Fig. 4 is a cross-sectional view showing an example of a cross-sectional structure of a capacitor region along line IV-IV in Fig. 3 . [ Fig. 5] Fig. 5 is a cross-sectional view showing an example of a cross-sectional structure of a transistor region of the semiconductor device according to the first embodiment. [ Fig. 6] Fig. 6 is a flow chart showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 7] Fig. 7 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 8] Fig. 8 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 9] Fig. 9 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 10] Fig. 10 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 11] Fig. 11 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 12] Fig. 12 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 13] Fig. 13 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 14] Fig. 14 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 15] Fig. 15 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device according to the first embodiment. [ Fig. 16] Fig. 16 is a plan view showing an example of a planar layout in a capacitor region of a semiconductor device according to a comparative example of the first embodiment. [ Fig. 17 ] A cross-sectional view showing an example of a cross-sectional structure of a capacitor region along line XVII-XVII in Fig. 16 . [ Fig. 18 ] A block diagram showing a configuration example of a semiconductor device according to the second embodiment. [ Fig. 19 ] A plan view showing an example of a planar layout of a semiconductor device according to a second embodiment. [ Fig. 20 ] A block diagram showing a configuration example of a semiconductor device as a comparative example of the second embodiment. [ Fig. 21 ] A plan view showing an example of a planar layout of a semiconductor device as a comparative example of the second embodiment. [ Fig. 22] Fig. 22 is a graph showing temporal changes of voltage and current in the semiconductor device of the second embodiment and its comparative example. [FIG. 23] A block diagram showing a configuration example of a semiconductor device according to a third embodiment. [ Fig. 24 ] A plan view showing an example of a planar layout of a semiconductor device according to a third embodiment. [ Fig. 25] Fig. 25 is a cross-sectional view showing an example of a cross-sectional structure of a capacitor region in a first modified example of the first to third embodiments. [ Fig. 26] Fig. 26 is a cross-sectional view showing an example of a cross-sectional structure of a capacitor region in a second modified example of the first to third embodiments. [FIG. 27] A block diagram showing a configuration example of a semiconductor device according to a third modified example of the first to third embodiments. [FIG. 28] A block diagram showing a configuration example of a semiconductor device according to a fourth embodiment. [ Fig. 29 ] A plan view showing an example of a planar layout of a semiconductor device according to a fourth embodiment. [ Fig. 30 ] A plan view showing an example of a planar layout of a semiconductor device according to a first modified example of the fourth embodiment. [ Fig. 31] Fig. 31 is a plan view showing an example of a planar layout of a semiconductor device according to a second modified example of the fourth embodiment. [FIG. 32] A block diagram showing a configuration example of a semiconductor device according to a third modified example of the fourth embodiment. [ Fig. 33 ] A plan view showing an example of a planar layout of a semiconductor device according to a third modified example of the fourth embodiment. [ Fig. 34 ] A plan view showing an example of a planar layout of a semiconductor device according to a fourth modification example of the fourth embodiment. [ Fig. 35 ] A plan view showing an example of a planar layout of a capacitor bank included in a semiconductor device according to a fifth modified example of the fourth embodiment.

CA: capacitor area

TA: Transistor area

PW: power cord

CP: Capacitor

TR: Transistor

10: Semiconductor substrate

11: Insulator layer

12: Semiconductor layer

13: Conductor

14: Insulator

15: well area

16: Diffusion area

17: Conductor

30: Conductor

CT: contact part

Claims (12)

A semiconductor device comprising: a semiconductor substrate having a first concave portion and a second concave portion, and having a surface, a back surface opposite to the surface, and a first bottom portion of the first concave portion disposed between the surface and the back surface; a first semiconductor layer disposed along the surface from the first bottom portion; a first conductor disposed on the first semiconductor layer; a first power line electrically connected to the first conductor; a second power line electrically connected to the semiconductor substrate; The substrate is connected to the first power line and the second power line; the semiconductor substrate further includes: the second bottom of the second recess disposed between the front surface and the back surface, and also includes: a third semiconductor layer disposed along the surface from the second bottom, and a third conductor disposed on the third semiconductor layer and electrically connected to the first power line. The gate electrode of the second conductor of the first layer, the first conductor functions as one electrode of the first capacitor, the semiconductor substrate functions as the other electrode of the first capacitor, the third conductor functions as one electrode of the second capacitor, the semiconductor substrate also functions as the other electrode of the second capacitor, and the capacitance of the second capacitor is greater than that of the first capacitor quantity. A semiconductor device comprising: a semiconductor substrate having a first concave portion and a second concave portion, and having a surface, a back surface opposite to the surface, and a first bottom portion of the first concave portion disposed between the surface and the back surface; a first semiconductor layer disposed along the surface from the first bottom portion; a first conductor disposed on the first semiconductor layer; a first power line electrically connected to the first conductor; a second power line electrically connected to the semiconductor substrate; The substrate is connected to the first power line and the second power line; the semiconductor substrate further includes: the second bottom of the second recess disposed between the front surface and the back surface, and further includes: a third semiconductor layer disposed along the surface from the second bottom, and a third conductor disposed on the third semiconductor layer and electrically connected to the first power line; It is formed of the same material, the aforementioned first electrical conductor and the aforementioned second conductive system are formed of the same material, the aforementioned first electrical conductor functions as one electrode of the first capacitor, the aforementioned semiconductor substrate functions as the other electrode of the aforementioned first capacitor, the aforementioned third electrical conductor functions as one electrode of the second capacitor, and the aforementioned semiconductor substrate also functions as the other electrode of the aforementioned second capacitor, The capacitance of the aforementioned second capacitor is greater than that of the aforementioned first capacitor. The semiconductor device according to claim 1 or 2, wherein one electrode of the first capacitor includes the first semiconductor layer, and one electrode of the second capacitor includes the third semiconductor layer. A semiconductor device comprising: a semiconductor substrate having a first concave portion and a second concave portion, and having a surface, a back surface opposite to the surface, and a first bottom portion of the first concave portion disposed between the surface and the back surface; a first semiconductor layer disposed along the surface from the first bottom portion; a first conductor disposed on the first semiconductor layer; a first power line electrically connected to the first conductor; a second power line electrically connected to the semiconductor substrate; The substrate is connected to the first power line and the second power line; the semiconductor substrate also includes: the second bottom of the second recess disposed between the surface and the back surface, and also has: a third semiconductor layer disposed along the surface from the second bottom, and a third conductor disposed on the third semiconductor layer and electrically connected to the first power line, the first conductor functions as one electrode of the first capacitor, the semiconductor substrate functions as the other electrode of the first capacitor, and the third conductor functions as a second capacitor The function of one electrode, the aforementioned semiconductor substrate also serves as the function of the other electrode of the aforementioned second capacitor, The capacitance of the aforementioned second capacitor is greater than that of the aforementioned first capacitor, and further includes: a first capacitor bank comprising a plurality of the aforementioned first capacitors, and a second capacitor bank comprising a plurality of the aforementioned second capacitors and having a capacitance greater than that of the aforementioned first capacitor bank. A semiconductor device comprising: a semiconductor substrate having a first recess and a second recess, and having a surface, a back surface opposite to the surface, and a first bottom of the first recess provided between the surface and the back surface; a first semiconductor layer provided along the surface from the first bottom; a first conductor provided on the first semiconductor layer; a second semiconductor layer provided on the surface and separately from the first semiconductor layer; a second conductor provided on the second semiconductor layer; The first power line on the first electrical conductor; the second power line electrically connected to the semiconductor substrate; and the circuit, which is provided on the semiconductor substrate and connected to the first power line and the second power line; The third conductor on the body layer and electrically connected to the first power line, the second conductor is electrically connected to the first power line, the first conductor functions as one electrode of the first capacitor, the semiconductor substrate functions as the other electrode of the first capacitor, the third conductor functions as one electrode of the second capacitor, the semiconductor substrate also functions as the other electrode of the second capacitor, the capacitance of the second capacitor is greater than that of the first capacitor, and the first conductor functions as one of the trench capacitors The function of the electrodes, the function of the aforementioned second conductor as one electrode of the planar capacitor, the function of the aforementioned semiconductor substrate as the other electrode of the aforementioned trench capacitor and the function of the other electrode of the aforementioned planar capacitor, also includes: a plurality of capacitor banks, and each capacitor bank includes a plurality of the aforementioned trench capacitors and/or the aforementioned planar capacitors, and among the aforementioned plurality of capacitor banks, the capacitor bank with the smallest capacitance is closest to the aforementioned circuit arrangement. The semiconductor device according to claim 5, wherein the capacitor bank with the smallest capacitance includes the planar capacitor and does not include the trench capacitor. Such as the semiconductor device of claim 5, wherein the plurality of capacitor banks further include: a first capacitor bank, and a capacitance The second capacitor bank larger than the first capacitor bank, the first capacitor bank and the second capacitor bank are arranged in the order of the first capacitor bank and the second capacitor bank along the first power supply line from the aforementioned circuit. The semiconductor device according to claim 7, wherein the plurality of capacitor banks further include: a third capacitor bank having a larger capacitance than the second capacitor bank, and the third capacitor bank is arranged in the order of the first capacitor bank, the second capacitor bank, and the third capacitor bank from the circuit along the first power line. The semiconductor device according to claim 8, wherein the capacitance of the second capacitor bank is more than 10 times the capacitance of the first capacitor bank, and the capacitance of the third capacitor bank is more than 10 times the capacitance of the second capacitor bank. A semiconductor device comprising: a semiconductor substrate having a first recess and a second recess, and having a surface, a back surface opposite to the surface, and a first bottom of the first recess provided between the surface and the back surface; a first semiconductor layer provided along the surface from the first bottom; a first conductor provided on the first semiconductor layer; a second semiconductor layer provided on the surface and separately from the first semiconductor layer; a second conductor provided on the second semiconductor layer; a first power line electrically connected to the first electrical conductor; a second power line electrically connected to the semiconductor substrate; and a circuit provided on the semiconductor substrate and connected to the first power line and the second power line; the semiconductor substrate further includes: a second bottom of the second recess disposed between the surface and the back surface, a third semiconductor layer disposed along the surface from the second bottom, and a third conductor disposed on the third semiconductor layer and electrically connected to the first power line. 2. The conductor is electrically connected to the first power line. The first conductor functions as one electrode of the first capacitor. The semiconductor substrate functions as the other electrode of the first capacitor. The third conductor functions as one electrode of the second capacitor. The semiconductor substrate also functions as the other electrode of the second capacitor. The capacitance of the second capacitor is greater than that of the first capacitor. As the function of the other electrode of the trench capacitor and the other electrode of the planar capacitor, it also includes: a pad connected to the first power line; and The 1st to 5th capacitor groups, which respectively include a plurality of the aforementioned trench capacitors and/or the aforementioned planar capacitors; the aforementioned circuit includes a first power supply terminal and a second power supply terminal electrically connected to the aforementioned first power supply line, and the aforementioned first power supply line includes: a first part from the aforementioned welding pad to the branch part, a second part from the aforementioned branch part to the aforementioned first power supply terminal, and a third part from the aforementioned branch part to the aforementioned second power supply terminal, the aforementioned first capacitor bank and the aforementioned second capacitor bank are arranged in the aforementioned second part, and the aforementioned first capacitor bank is arranged as follows: The third capacitor bank and the fourth capacitor bank are arranged in the third part, the third capacitor bank is arranged closer to the second power supply terminal than the fourth capacitor bank, the fifth capacitor bank is arranged in the first part, the capacitance of the second capacitor bank is greater than that of the first capacitor bank, the capacitance of the fourth capacitor bank is greater than that of the third capacitor bank, and the capacitance of the fifth capacitor bank is greater than either of the second capacitor bank and the fourth capacitor bank. The capacitance. A semiconductor device comprising: a semiconductor substrate having a first recess and a second recess, and having a surface, a back surface opposite to the surface, and a first bottom of the first recess provided between the surface and the back surface; The first semiconductor layer arranged along the aforementioned surface from the aforementioned first bottom; the first conductor arranged on the aforementioned first semiconductor layer; the second semiconductor layer arranged on the aforementioned surface and separated from the aforementioned first semiconductor layer; the second conductor arranged on the aforementioned second semiconductor layer; the first power line electrically connected to the aforementioned first electrical conductor; The second bottom of the aforementioned second concave portion between the aforementioned surface and the aforementioned back surface further includes: a third semiconductor layer disposed along the aforementioned surface from the aforementioned second bottom, and a third electrical conductor disposed on the aforementioned third semiconductor layer and electrically connected to the aforementioned first power supply line, the aforementioned second electrical conductor is electrically connected to the aforementioned first power supply line, the aforementioned first electrical conductor functions as one electrode of the first capacitor, the aforementioned semiconductor substrate functions as the other electrode of the aforementioned first capacitor, the aforementioned third electrical conductor functions as one electrode of the second capacitor, and the aforementioned semiconductor substrate also functions as The function of the other electrode of the second capacitor, the capacitance of the second capacitor is greater than the capacitance of the first capacitor, the function of the first conductor as one electrode of the trench capacitor, and the function of the second conductor as one electrode of the planar capacitor Able, the aforementioned semiconductor substrate functions as the other electrode of the aforementioned trench capacitor and the other electrode of the aforementioned planar capacitor, and also includes: a plurality of capacitor banks, each capacitor bank comprising a plurality of the aforementioned trench capacitors and/or the aforementioned planar capacitors, the aforementioned circuit is arranged on the first area on the aforementioned semiconductor substrate, and the capacitor bank with the smallest capacitance among the aforementioned plurality of capacitor banks is arranged in the aforementioned first area. A semiconductor device comprising: a semiconductor substrate having a first concave portion and a second concave portion, and having a surface, a back surface opposite to the surface, and a first bottom portion of the first concave portion disposed between the surface and the back surface; a first semiconductor layer disposed along the surface from the first bottom portion; a first conductor disposed on the first semiconductor layer; a first power line electrically connected to the first conductor; a second power line electrically connected to the semiconductor substrate; The substrate is connected to the aforementioned first power line and the aforementioned second power line; the aforementioned semiconductor substrate also includes: the second bottom of the aforementioned second concave portion disposed between the aforementioned surface and the aforementioned back surface, and also includes: a third semiconductor layer disposed along the aforementioned surface from the aforementioned second bottom, and a third conductor disposed on the aforementioned third semiconductor layer and electrically connected to the aforementioned first power line, the aforementioned first electrical conductor functions as one electrode of the first capacitor, and the aforementioned semiconductor substrate functions as the other electrode of the aforementioned first capacitor, The aforementioned third conductor functions as one electrode of the second capacitor, and the aforementioned semiconductor substrate also functions as the other electrode of the aforementioned second capacitor. The capacitance of the aforementioned second capacitor is greater than that of the aforementioned first capacitor. It also includes: a first capacitor bank comprising a plurality of the aforementioned first capacitors, and a second capacitor bank comprising a plurality of the aforementioned first capacitors and a plurality of the aforementioned second capacitors. The capacity of the aforementioned second capacitor bank is greater than that of the aforementioned first capacitor bank. Arrange according to the order of the aforementioned first capacitor bank and the aforementioned second capacitor bank.

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