TW202125782A - Semiconductor device - Google Patents

Abstract

Embodiments provide a semiconductor device in which an increase in the area of a semiconductor substrate is suppressed. The semiconductor device (1) according to an embodiment is provided with a semiconductor substrate (10), a first semiconductor layer (12), a first conductor (13), a first power supply line (PW), a second power supply line (GW), and a circuit (3). The semiconductor substrate (10)has a first surface, a second surface facing the first surface, and a third surface provided between the first surface and the second surface. The first semiconductor layer (12) is provided along the first surface from the third surface. The first conductor (13) is provided on the first semiconductor layer (12). The first power supply line (PW) is electrically connected to the first conductor (13). The second power supply line (GW) is electrically connected to the semiconductor substrate (10). The circuit (3) is provided on the semiconductor substrate (10) and is connected to the first power supply line (PW) and the second power supply line (GW).

Description

Semiconductor device

The embodiment of the present invention relates to a semiconductor device including a bypass capacitor. [Related Application]

This application claims the priority of Japanese Patent Application No. 2019-169564 (application date: September 18, 2019) and Japanese Patent Application No. 2020-029110 (application date: February 25, 2020), which are the basic applications. This application contains all the contents of the basic application by referring to the basic application.

It is known to provide a bypass capacitor on a semiconductor substrate in order to suppress fluctuations in the power supply voltage.

The problem to be solved by the present invention is to provide a semiconductor device that can suppress the increase in the area of the semiconductor substrate.

The semiconductor device of the embodiment includes a semiconductor substrate, a first semiconductor layer, a first conductor, a first power supply line, a second power supply line, and a circuit. The semiconductor substrate has a first surface, a second surface facing the first surface, and a third surface provided between the first surface and the second surface. The first semiconductor layer is provided along the first surface from the third surface. The first conductor is provided on the first semiconductor layer. The first power line is electrically connected to the first conductor. The second power supply line is electrically connected to the semiconductor substrate. The circuit is provided on the semiconductor substrate and connected to the first power line and the second power line.

The embodiment will be described below with reference to the drawings. Each embodiment is an example of an apparatus or method that embodies the technical idea of the invention. The drawings are schematic or conceptual representations, and the dimensions and ratios of the drawings may not necessarily be the same as the actual ones. The technical idea of the present invention is not defined by the shape, structure, arrangement, etc. of the constituent elements.

In addition, in the following description, components having substantially the same function and configuration are marked with the same reference numerals. The numbers after the characters constituting the reference symbols are referred to by reference symbols containing the same characters, and are used when distinguishing elements with the same composition from each other. When there is no need to distinguish the elements indicated by the reference signs containing the same characters from each other, these elements are referred to by the reference signs containing only characters respectively.

[1] The first embodiment Hereinafter, the semiconductor device 1 of the first embodiment will be described.

[1-1] Configuration of semiconductor device 1 [1-1-1] Overall structure of semiconductor device 1 FIG. 1 shows a configuration example of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 is integrated on one semiconductor substrate, for example. As shown in FIG. 1, the semiconductor device 1 includes power supply lines PW and GW, pads P1 and P2, a capacitor portion 2, and a circuit portion 3.

The power supply lines PW and GW are respectively used for supplying power supply voltages to the circuits included in the semiconductor device 1. The pads P1 and P2 are respectively configured to be connectable to devices outside the semiconductor device 1. The pad P1 is a power pad on the positive side of the semiconductor device 1 and is connected to the power line PW. The power supply voltage VDD is applied to the pad P1, for example. The pad P2 is a power pad on the negative side of the semiconductor device 1 and is connected to the power line GW. The pad P2 is connected to the ground node GND, for example.

The capacitor 2 is connected between the power supply line PW and the power supply line GW. The capacitor 2 is used to suppress the fluctuation of the voltage of the power line PW. The circuit unit 3 is connected to the power supply lines PW and GW, respectively. The circuit unit 3 includes a circuit that operates in accordance with the voltage supplied via the power supply line PW. The circuit included in the circuit section 3 may be, for example, a peripheral circuit of a NAND flash memory.

FIG. 2 shows an example of the configuration of the capacitor portion 2 included in the semiconductor device 1 of the first embodiment. As shown in FIG. 2, the capacitance portion 2 includes, for example, a plurality of capacitors CP. One electrode of each of the plurality of capacitors CP is connected to the power supply line PW, and the other electrode is connected to the power supply line GW. That is, a plurality of capacitors CP are connected in parallel between the power supply line PW and GW. Each of the plurality of capacitors CP is also referred to as, for example, a bypass capacitor.

[1-1-2] Structure of semiconductor device 1 Hereinafter, an example of the structure of the capacitor portion 2 in the first embodiment will be described.

In the drawings referred to below, the plane defined by the X direction and the Y direction corresponds to the surface of the semiconductor substrate 10 on which the semiconductor device 1 is formed, and the Z direction corresponds to the surface of the semiconductor substrate 10 on which the semiconductor device 1 is formed. The vertical direction. In the plan view, hatching is appropriately added for the convenience of observing the map. The hatching added to the floor plan is not necessarily related to the materials or characteristics of the elements that have the hatching added. In the cross-sectional view, constituent elements such as insulating layers (interlayer insulating films), wiring, and contact portions are appropriately omitted in order to facilitate the observation of the drawings.

In the following description, the area including the capacitor CP included in the capacitor portion 2 in the semiconductor substrate 10 is referred to as a capacitor area CA. In addition, the area including the transistor included in the circuit portion 3 in the semiconductor substrate 10 is referred to as a transistor area TA.

FIG. 3 shows an example of the planar layout in the capacitor area CA of the semiconductor device 1 of the first embodiment. As shown in FIG. 3, the capacitor part 2 includes a plurality of conductors 13, conductors 17 and 18, a diffusion region 19, and a plurality of contact parts CT.

Each conductor 13 corresponds to one electrode of the capacitor CP. The plurality of conductors 13 are arranged in, for example, a matrix of 4 rows and 3 columns. Each electric conductor 13 is arranged to overlap the electric conductor 17. The conductor 17 functions as a power line PW. Each electrical conductor 13 is electrically connected to the electrical conductor 17 via a contact portion CT.

The diffusion region 19 is provided on the surface of the semiconductor substrate 10. The diffusion region 19 is, for example, a P-type diffusion region, and is electrically connected to the semiconductor substrate 10. The conductor 18 is arranged overlappingly on the diffusion region 19. The conductor 18 functions as the power cord GW. The diffusion region 19 is electrically connected to the conductor 18 via the contact portion CT.

In addition, the number and arrangement of capacitors CP are not limited to the example shown in FIG. 3. In addition, the area of the diffusion region 19 or the positional relationship with the conductor 13 is not limited to the example shown in FIG. 3.

4 is a cross-sectional view taken along the line IV-IV of FIG. 3, showing an example of a cross-sectional structure in the capacitor region CA of the semiconductor device 1 of the first embodiment. As shown in FIG. 4, the semiconductor device 1 further includes an insulator layer 11 and a semiconductor layer 12. The semiconductor substrate 10 includes a plurality of recesses CC.

The insulator layer 11 is respectively provided on the surface of the semiconductor substrate 10, the side surface and the bottom of the recess CC. The insulator layer 11 provided on the surface of the semiconductor substrate 10 and the insulator layer 11 provided in the recess CC are continuously provided. The semiconductor layer 12 is provided on the insulator layer 11 in a region corresponding to each capacitor CP. The semiconductor layer 12 has a portion provided along the recessed portion CC, and is divided between adjacent recessed portions CC, for example. The conductor 13 is provided on the semiconductor layer 12. The recess CC is filled with the conductor 13. In the region corresponding to each capacitor CP, the side surfaces of the semiconductor layer 12 and the conductor 13 are aligned.

With this configuration, in each recess CC, the semiconductor layer 12 and the conductor 13 function as one of the electrodes of the capacitor CP, the insulator layer 11 functions as an insulator between the electrodes of the capacitor CP, and the semiconductor substrate 10 functions as the other side of the capacitor CP. The function of one electrode. One side electrode of the capacitor CP is connected to the conductor 17 which functions as the power supply line PW via the contact portion CT. The semiconductor substrate 10 which functions as the other electrode of the capacitor CP is connected to the conductor 18 which functions as the power supply line GW via the diffusion region 19 and the contact portion CT.

FIG. 5 shows an example of a cross-sectional structure in the transistor region TA of the semiconductor device 1 of the first embodiment. In addition, the area shown in FIG. 5 includes a part of the capacitor area CA. As shown in FIG. 5, the transistor area TA includes, for example, a transistor TR. In the transistor region TA, the semiconductor device 1 further includes an insulator 14, a well region 15, a diffusion region 16, and a conductor 30.

The insulator 14 is formed inside the semiconductor substrate 10 and its upper end contacts the upper surface of the semiconductor substrate 10. The insulator 14 is used as an insulating region STI (Shallow Trench Isolation) between adjacent well regions, and a part of the semiconductor substrate 10 is divided in the transistor region TA. The well region 15 is formed in a region divided by the insulator 14 inside the semiconductor substrate 10, and the upper end is in contact with the upper surface of the semiconductor substrate 10. The two diffusion regions 16 are formed inside the well region 15 and the upper ends are in contact with the upper surface of the semiconductor substrate 10.

A plurality of conductors 30 are provided above the well region 15. The plurality of conductors 30 are wirings corresponding to the drain, source, and gate of the transistor TR, respectively. The two diffusion regions 16 respectively serve as the drain or source of the transistor TR. The two diffusion regions 16 are electrically connected to the corresponding conductor 30 via the contact portion CT, respectively. The semiconductor layer 12 is disposed above the well region 15 and on the insulator layer 11. The conductor 13 is provided on the semiconductor layer 12. The semiconductor layer 12 and the conductor 13 function as the gate electrode of the transistor TR. The combination of the semiconductor layer 12 and the conductor 13 is electrically connected to the conductor 30 via the contact portion CT.

[1-2] Manufacturing method Hereinafter, an example of a series of manufacturing processes for forming the capacitor CP and the transistor TR in the first embodiment will be described with reference to FIG. 6 as appropriate. FIG. 6 is a flowchart showing an example of the manufacturing process of the semiconductor device 1 according to the first embodiment. FIGS. 7 to 15 each show an example of a cross-sectional structure including a structure corresponding to the capacitor CP and the transistor TR in the manufacturing process of the semiconductor device 1 of the first embodiment.

First, as shown in FIG. 7, an insulator layer 21 is formed on the semiconductor substrate 10 (step S101). The insulator layer 21 includes, for example, silicon nitride (SiN).

Next, as shown in FIG. 8, the etching part EP is processed (step S102). Specifically, first, a mask having an opening in a region corresponding to the etching portion EP is formed by photolithography or the like. Next, the etching part EP is formed by anisotropic etching using the formed mask. The etching part EP formed in this process penetrates the insulator layer 21 and stops in the semiconductor substrate 10. The etching part EP formed in the transistor region TA has a groove-like shape extending in the Y-axis direction. Compared with the etching part EP provided in the transistor region, the etching part EP formed in the capacitor region CA has a shorter length in the Y-axis direction, for example, a hole shape. The anisotropic etching in this project is, for example, RIE (Reactive Ion Etching).

Next, as shown in FIG. 9, the insulator 14 is formed (step S103). Specifically, first, the insulator 14 is formed so as to fill the etching portion EP. Next, the insulator 14 formed outside the etching portion EP is removed by, for example, CMP (Chemical Mechanical Polishing). The insulator 14 includes, for example, silicon oxide (SiO ₂ ).

Next, as shown in FIG. 10, the well region 15 is formed (step S104). Specifically, in the transistor region TA, a region partitioned by the insulator 14 is doped with, for example, phosphorus to form the well region 15.

Next, the insulator layer 22 is formed so as to cover the insulator 14 of the transistor area TA (step S105). Specifically, first, the insulator layer 22 is formed on the insulator layer 21 and the insulator 14. The insulator layer 22 includes, for example, silicon nitride. Next, a mask provided with an opening in the area corresponding to the capacitor area CA is formed by photolithography or the like. Next, the insulator layer 22 formed in the capacitor region CA is removed by anisotropic etching using the formed mask. The anisotropic etching in this process is, for example, RIE.

Next, as shown in FIG. 11, the insulator 14 in the capacitor area CA is removed (step S106). Specifically, for example, the insulator 14 in the capacitor area CA that is not covered by the insulator layer 22 is removed by wet etching to expose the etching part EP in the capacitor area CA.

Next, as shown in FIG. 12, the insulator layers 21 and 22 are removed (step S107). Specifically, for example, the insulator layers 21 and 22 are removed by wet etching. Next, the insulator 14 protruding from the semiconductor substrate 10 is removed by, for example, CMP.

Next, as shown in FIG. 13, the insulator layer 11, the semiconductor layer 12, and the conductor 13 are formed (step S108). Specifically, first, the insulator layer 11 is formed on the surface of the semiconductor substrate 10, the side and bottom of the etching portion EP, the surface of the insulator 14, and the surface of the well region 15. Next, a semiconductor layer 12 is formed on the surface of the insulator layer 11. In addition, a conductor 13 is formed on the surface of the semiconductor layer 12 to fill the etching part EP. The insulator layer 11 includes, for example, silicon oxide. The semiconductor layer 12 includes, for example, silicon (Si). The conductor 13 includes, for example, tungsten (W).

Next, the formation and processing of the mask 23 are performed (step S109). Specifically, a mask 23 is formed on the conductor 13 by photolithography or the like. The mask 23 covers, for example, a region corresponding to one of the electrodes of the capacitor CP and a region corresponding to the gate electrode of the transistor TR, and an opening is provided in the other region.

Next, as shown in FIG. 14, the semiconductor layer 12 and the conductor 13 are processed (step S110). Specifically, a part of the semiconductor layer 12 and the conductor 13 is removed by anisotropic etching using the mask 23, and a part of the surface of the insulator layer 11 is exposed. Then, the mask 23 is removed by, for example, wet etching (step S111).

Next, as shown in FIG. 15, the diffusion region 16 is formed (step S112). Specifically, the diffusion region 16 is formed by doping, for example, boron in the well region 15. After that, various wirings including the conductor 17 and the conductor 30 are provided above the semiconductor substrate 10. Next, the conductor 17 and the capacitor CP are connected via the contact portion CT. The conductor 30 and the transistor TR are connected through the contact portion CT.

The capacitor CP and the transistor TR are respectively formed by the manufacturing process described above. In addition, the manufacturing process described above is only an example, and other processes can be inserted between each manufacturing process.

[1-3] Effects of the first embodiment According to the semiconductor device 1 of the first embodiment described above, the manufacturing cost of the semiconductor device 1 can be suppressed. Hereinafter, detailed effects of the semiconductor device 1 of the first embodiment will be described.

The consumption current of the circuit may vary, for example, in accordance with the operation of the circuit. In order to suppress the fluctuation of the voltage of the power line when the consumption current changes, for example, a bypass capacitor is used. When the consumption current of the circuit increases, the bypass capacitor supplies the charged electric charge to the circuit, thereby suppressing the fluctuation of the voltage of the power line.

However, when a bypass capacitor is provided on a semiconductor substrate, in order to obtain the expected capacitance, there is a bypass capacitor that requires a large area. FIG. 16 shows an example of the planar layout of the capacitor portion 2 included in the comparative example of the semiconductor device 1 of the first embodiment. FIG. 17 shows a cross-sectional view corresponding to the line XVII-XVII of FIG. 16 and shows a cross-sectional structure of the capacitor portion 2 provided in the comparative example.

As shown in FIG. 16, the capacitor part 2 with which the comparative example is equipped contains the plate capacitor FC. As shown in FIG. 17, the area where the semiconductor layer 12 and the conductor 13 are provided on the surface of the semiconductor substrate 10 functions as a plate capacitor FC. In the plate capacitor FC, the occupied area on the semiconductor substrate 10 is approximately equal to the surface area of one electrode.

In contrast, the semiconductor device 1 of the first embodiment includes a plurality of capacitors CP, and each capacitor CP has a portion provided along the recess CC. The surface area of one electrode of the capacitor CP is larger than the occupied area on the semiconductor substrate 10. That is, compared with the plate capacitor FC of the comparative example, the capacitor CP of the semiconductor device 1 of the first embodiment has a larger capacitance per unit area with respect to the occupied area on the semiconductor substrate 10.

Thereby, according to the semiconductor device 1 of the first embodiment, it is possible to reduce the area occupied by the capacitor while maintaining the capacitance of the capacitor. The area occupied by the bypass capacitor can be reduced, so the size of the semiconductor substrate 10 on which the semiconductor device 1 is installed can be reduced, and the manufacturing cost of the semiconductor device 1 can be suppressed.

In addition, in the semiconductor device 1 of the first embodiment, some steps of the process of forming the transistor TR and the capacitor CP can be integrated. Specifically, as shown in step S102 of FIG. 6, the shapes corresponding to the recesses CC and the insulating regions STI can be processed as a plurality of etching portions EP at the same time. In addition, one side electrode of the capacitor CP, namely the semiconductor layer 12 and the conductor 13, and the gate electrode of the transistor, namely the semiconductor layer 12 and the conductor 13, can be formed and processed at the same time.

Thereby, in the semiconductor device 1 of the first embodiment, it is possible to suppress an increase in the number of processes accompanying the formation of the capacitor CP. Therefore, the semiconductor device 1 of the first embodiment can suppress the manufacturing cost.

[2] The second embodiment The second embodiment is a specific example of the layout of the capacitor CP included in the semiconductor device 1 of the first embodiment. Hereinafter, the difference between the semiconductor device 1 of the second embodiment and the first embodiment will be described.

[2-1] Composition FIG. 18 shows an example of the circuit configuration of the semiconductor device 1 according to the second embodiment. As shown in FIG. 18, the semiconductor device 1 of the second embodiment includes capacitor units CU1 to CU4 as a capacitor unit 2, includes circuits 3a and 3b as a circuit unit 3, and further includes a signal line SW. In addition, the resistance component of the power line PW is represented by resistors RP1 and RP2. In addition, the description related to the pad P2 and the power supply line GW is omitted, and it is indicated by a ground symbol.

The signal CLK is input to the circuit 3a. Next, the circuit 3a outputs a signal based on the signal CLK to the circuit 3b via the signal line SW. The circuits 3a and 3b are supplied with power supply voltage from the power supply line PW. Hereinafter, the connection part between the power line PW and the circuit 3a or 3b is referred to as the power terminal of the circuit 3a and the power terminal of the circuit 3b. The voltage at the power supply terminal of the circuit 3a is called voltage VDD1, and the current consumed by the circuit 3a is called current I1.

The capacitor units CU1 to CU4 each include, for example, a plurality of capacitors CP connected in parallel. One electrode of each of the capacitor units CU1 and CU2 is arranged so that the distance from the power terminal of the circuit 3a becomes shorter. One electrode of each of the capacitor units CU3 and CU4 is arranged so that the distance from the power terminal of the circuit 3b becomes shorter. In addition, the resistance component of the power supply line PW from the pad P1 to the capacitor units CU1 and CU2 and the circuit 3a is represented by a resistance RP1. The resistance component of the power supply line PW from the capacitor units CU1 and CU2 and the circuit 3a to the capacitor units CU3 and CU4 and the circuit 3b is represented by a resistance RP2.

FIG. 19 shows an example of the planar layout of the semiconductor device 1 of the second embodiment. As shown in FIG. 19, the semiconductor device 1 of the second embodiment further includes contact portions CT1 to CT8. As shown in FIG. 19, the power line PW extends from the pad P1 in the X direction.

The circuits 3a and 3b are arranged along the power supply line PW. The circuit 3a is arranged closer to the pad P1 than the circuit 3b. The power supply terminals of the circuits 3a and 3b are connected to the power supply line PW. The circuit 3a and the circuit 3b are connected via a signal line SW. The capacitor units CU1 and CU2 are arranged near the power terminal of the circuit 3a. The capacitor units CU3 and CU4 are arranged near the power terminal of the circuit 3b.

The contact portion CT1 connects the power line PW and one electrode of the capacitor unit CU1. The contact portion CT2 connects the power supply line PW and one electrode of the capacitor unit CU2. The contact portion CT3 connects the power line PW and one electrode of the capacitor unit CU3. The contact portion CT4 connects the power line PW and one electrode of the capacitor unit CU4. The contact portion CT5 connects the power line PW with the power terminal of the circuit 3a. The contact portion CT6 connects the power line PW with the power terminal of the circuit 3b. The contact portion CT7 connects the signal line SW with the signal output portion of the circuit 3a. The contact portion CT8 connects the signal line SW with the signal input portion of the circuit 3b.

In the example shown in FIG. 19, in the power supply line PW, the resistance component from the pad P1 to the part where the contact portions CT1, CT2, and CT5 are connected corresponds to the resistance RP1. In addition, the resistance component of the power line PW from the part where the contact parts CT1, CT2, and CT5 are connected to the part where the contact parts CT3, CT4, and CT6 are connected, corresponds to the resistance RP2. The other structure of the semiconductor device 1 of the second embodiment is the same as that of the first embodiment.

[2-2] Effects of the second embodiment According to the semiconductor device 1 of the second embodiment described above, the operation reliability of the semiconductor device 1 can be improved. Hereinafter, detailed effects of the semiconductor device 1 of the second embodiment will be described.

In the design of a semiconductor device, it is preferable to densely lay out constituent elements such as a plurality of circuits or a plurality of capacitors. When the elements are densely arranged, the size of the semiconductor substrate can be suppressed from increasing, and the manufacturing cost of the semiconductor device can be suppressed. In addition, the resistance component of the wiring provided between the bypass capacitor and the power terminal of the circuit is preferably small. When the resistance component of the wiring between the bypass capacitor and the power terminal of the circuit is small, the bypass capacitor can supply charge to the circuit as soon as possible, and can suppress the fluctuation of the power supply voltage.

However, when the size of a certain element is large, for example, when the size of the capacitor is large, if the circuit and the bypass capacitor are densely arranged, the wiring connecting the bypass capacitor and the power terminal of the circuit will become longer. condition. FIG. 20 shows an example of the circuit configuration of the semiconductor device 1 of the comparative example of the second embodiment. As shown in FIG. 20, the difference between the semiconductor device 1 of the comparative example and the second embodiment is that the capacitor portion 2 of the comparative example includes plate capacitors FC1 to FC4, and the resistance component of the power line PW is represented by resistors RP3 to RP5.

The panel capacitors FC1 to FC4 are set together. The circuit 3a is arranged not close to the plate capacitors FC1 to FC4 but close to the pad P1. The circuit 3b is arranged farther away from the pad P1 than the plate capacitors FC1 to FC4. In addition, the resistance component of the power supply line PW from the pad P1 to the power supply terminal of the circuit 3a is represented by a resistance RP3. The resistance component of the power supply line PW from the power supply terminal of the circuit 3a to the plate capacitors FC1 to FC4 is represented by a resistance RP4. The resistance component of the power supply line PW from the plate capacitors FC1 to FC4 to the power supply terminal of the circuit 3b is represented by a resistance RP5.

FIG. 21 shows an example of the planar layout of the semiconductor device 1 of the comparative example of the second embodiment. As shown in FIG. 21, the semiconductor device 1 of the comparative example further includes contact portions CT1 to CT8. Each of the plate capacitors FC1 to FC4 included in the comparative example and each of the capacitor units CU1 to CU4 included in the semiconductor device 1 of the second embodiment have substantially the same capacitance.

That is, compared with the capacitor unit CU included in the second embodiment, the flat capacitor FC included in the comparative example has a smaller capacitance per unit area on the semiconductor substrate 10. Therefore, the area occupied on the semiconductor substrate 10 of the plate capacitor FC is larger than that of the capacitor unit CU. In order to densely arrange the large plate capacitors FC, the layout of the comparative example is different from the layout of the semiconductor device 1 of the second embodiment.

Specifically, in the comparative example, the circuit 3a, the plate capacitors FC1 and FC2, the plate capacitors FC3 and FC4, and the circuit 3b are arranged in order from the pad P1 along the power supply line PW. The plate capacitors FC1 to FC4 are arranged between the circuit 3a and the circuit 3b. The power line PW is arranged to overlap the plate capacitors FC1 and FC3. The signal line SW is arranged to overlap the plate capacitors FC2 and FC4. In the comparative example, the resistance component of the power line PW from the pad P1 to the connection portion of the contact portion CT5 corresponds to the resistance RP3. The resistance component of the power line PW from the connection part of the contact part CT5 to the connection part of the contact parts CT1 to CT4 corresponds to the resistance RP4. The resistance component from the connection part of the contact parts CT1 to CT4 to the connection part of the contact part CT6 corresponds to the resistance RP5.

As described above, in the semiconductor device 1 of the comparative example, the power supply line PW connecting the power supply terminal of the circuit 3a and the plate capacitors FC1 to FC4 becomes longer and includes a resistance component equivalent to the resistance RP4. In addition, the power supply line PW connecting the circuit 3b and the plate capacitors FC1 to FC4 becomes longer and includes a resistance component equivalent to the resistance RP5.

In contrast, in the semiconductor device 1 of the second embodiment, the capacitor unit CU having a smaller area on the semiconductor substrate 10 than the plate capacitor FC is arranged near the power supply terminal of the circuit. The power supply line PW of the part where the power supply terminal of the circuit 3a is connected to the capacitor units CU1 and CU2 is shortened, and the resistance component of the power supply line PW of the connected part is reduced. In addition, the power supply line PW connecting the power supply terminal of the circuit 3b and the capacitor units CU3 and CU4 becomes short, and the resistance component is small.

Thereby, in the semiconductor device 1 of the second embodiment, when the circuit and the capacitor are densely arranged, the resistance component of the wiring provided between the bypass capacitor and the power terminal of the circuit can be reduced. FIG. 22 shows the relationship between voltage and current and time in the semiconductor device of the second embodiment and its modification. The three graphs shown in FIG. 22 respectively show the relationship between signal CLK and time, the relationship between current I1 and time, and the relationship between voltage VDD1 and time in order from the top. In the graph of the voltage VDD1, the solid line represents the second embodiment, and the broken line represents a comparative example.

The signal CLK changes from the "H" level to the "L" level or from the "L" level to the "H" level at times t1, t2, t3, and t4, respectively. The circuit 3a operates according to the signal CLK, and the current I1 corresponding to the consumption current of the circuit 3a increases at times t1, t2, t3, and t4, respectively. When the current I1 increases, the bypass capacitor supplies charge and suppresses the fluctuation of the voltage VDD1. In the comparative example, the resistance component between the circuit 3a and the bypass capacitor is large, and therefore the voltage VDD1 varies greatly. In contrast, in the semiconductor device 1 of the second embodiment, the resistance component between the circuit 3a and the bypass capacitor is small, and therefore the fluctuation of the voltage VDD1 is suppressed to be small. As described above, the semiconductor device 1 of the second embodiment can suppress the fluctuation of the power supply voltage more than the comparative example. Therefore, the semiconductor device 1 of the second embodiment can improve operation reliability more than the comparative example.

In addition, the fluctuation of the power supply voltage may also become the cause of jitter. When the circuit wants to operate at a high speed, it is better to suppress the generation of jitter. In contrast, as described above, the semiconductor device 1 of the second embodiment can suppress the fluctuation of the power supply voltage, and therefore can suppress the occurrence of jitter.

In addition, it is better that the parasitic resistance and parasitic capacitance of the signal wiring be smaller. When the parasitic resistance and parasitic capacitance of the signal wiring are small, high-speed signals can be transmitted stably.

In the semiconductor device 1 of the comparative example, the circuit 3a and the circuit 3b are located away from each other, and are connected by a long signal line SW. When the length of the signal line SW becomes longer, the parasitic resistance may become larger. In addition, the signal line SW is overlapped with the plate capacitors FC2 and FC4. When the signal line SW is overlapped with other elements such as capacitors, the parasitic capacitance may increase.

On the other hand, in the semiconductor device 1 of the second embodiment, the circuit 3a and the circuit 3b are provided close to each other and connected by a short signal line SW. In addition, the signal line SW is not overlapped with other elements other than the circuit 3a and the circuit 3b.

Thereby, in the semiconductor device 1 of the second embodiment, the parasitic resistance and the parasitic capacitance of the signal line SW are small, so high-speed signals can be stably transmitted, and the operation reliability of the semiconductor device 1 can be improved.

[3] The third embodiment The third embodiment is a modification of the layout and capacitance design of the capacitor CP included in the semiconductor device 1 of the second embodiment. Hereinafter, the difference between the semiconductor device 1 of the third embodiment and the second embodiment will be described.

[3-1] Composition FIG. 23 shows an example of the circuit configuration of the semiconductor device 1 according to the third embodiment. As shown in FIG. 23, the semiconductor device 1 of the third embodiment includes capacitor groups CS1 to CS3 as the capacitor section 2, and includes a circuit 3c as the circuit section 3. The power line PW includes nodes N1 to N3. In addition, the resistance component of the power line PW is represented by resistances RP6 to RP8.

The power line PW is arranged from the pad P1 to the power terminal of the circuit 3c. The distance between the circuit 3c and the power terminal becomes longer in the order of the node N1, the node N2, and the node N3. In addition, the resistance component of the power supply line PW from the pad P1 to the node N3 is represented by a resistance RP6. The resistance component of the power supply line PW from the node N3 to the node N2 is represented by a resistance RP7. The resistance component of the power supply line PW from the node N2 to the node N1 is represented by a resistance RP8.

The capacitor banks CS1 to CS3 each include a plurality of capacitors CP. The capacitances of the capacitor banks CS1 to CS3 are different from each other. The capacitance of the capacitor bank CS2 is greater than the capacitance of the capacitor bank CS1. The capacitance of the capacitor bank CS3 is greater than the capacitance of the capacitor bank CS2. For example, the capacitance of the capacitor bank CS2 is 10 times the capacitance of the capacitor bank CS1, and the capacitance of the capacitor bank CS3 is 10 times the capacitance of the capacitor bank CS2. For example, the capacitance of the capacitor banks CS1 to CS3 is determined by the number of capacitors CP included in each capacitor bank. The capacitor banks CS1 to CS3 are arranged between the power line PW and the ground node. Specifically, one electrode of the capacitor groups CS1 to CS3 is connected to the nodes N1 to N3, respectively.

FIG. 24 shows an example of the planar layout of the semiconductor device 1 of the third embodiment. As shown in FIG. 24, the semiconductor device 1 of the third embodiment further includes contact portions CT10 to CT13. In addition, the capacitor banks CS1 to CS3 each include a plurality of capacitors CP. The number of capacitors CP included in the capacitor bank increases in the order of the capacitor bank CS1, the capacitor bank CS2, and the capacitor bank CS3. In the example shown in FIG. 24, the number of capacitors CP is simplified.

The power line PW extends from the pad P1 in the X direction. Along the power line PW, a capacitor bank CS3, a capacitor bank CS2, a capacitor bank CS1, and a circuit 3c are arranged in the order of approaching the bonding pad P1.

The contact portion CT10 connects the power supply line PW with the power supply terminal of the circuit 3c. The contact portion CT11 connects the power supply line PW and one of the electrodes of the capacitor CP included in the capacitor group CS1. The plurality of contact portions CT12 respectively connect the power supply line PW and one electrode of the capacitor CP included in the capacitor group CS2. The contact portion CT13 respectively connects the power supply line PW and one electrode of the capacitor CP included in the capacitor group CS3.

In the example shown in FIG. 24, in the power supply line PW, the resistance component from the pad P1 to the portion where the plurality of contact portions CT13 are connected corresponds to the resistance RP6. In the power supply line PW, the resistance component from the portion where the plurality of contact portions CT13 are connected to the portion where the plurality of contact portions CT12 is connected corresponds to the resistance RP7. In the power supply line PW, the resistance component from the part where the contact part CT12 is connected to the part where the contact part CT11 is connected corresponds to the resistance RP8. The other structure of the semiconductor device 1 of the third embodiment is the same as that of the second embodiment.

[3-2] Effects of the third embodiment According to the semiconductor device 1 of the third embodiment described above, the operation reliability of the semiconductor device 1 can be improved. Hereinafter, detailed effects of the semiconductor device 1 of the third embodiment will be described.

The power supply voltage may vary in a wide frequency range from low frequency to high frequency. Preferably, the bypass capacitor can suppress the fluctuation of the power supply voltage in a wide frequency band from low frequency to high frequency. In order to suppress the fluctuation of the power supply voltage in the low frequency band, it is preferable that the capacitance of the bypass capacitor be large. On the other hand, even if a bypass capacitor with a smaller capacitance than that in the low frequency band is used, the fluctuation of the power supply voltage in the high frequency band can be suppressed. In addition, when the area around the circuit cannot be ensured, a bypass capacitor can be considered at a location away from the circuit, but the power line connecting the circuit and the bypass capacitor may be longer. As the power line connecting the circuit and the bypass capacitor becomes longer, the resistance value of the wiring becomes larger. In addition, as the length of the power supply line connecting the bypass capacitor and the circuit becomes longer, the ability of the bypass capacitor to suppress voltage fluctuations in a high frequency band may be limited.

In contrast, the semiconductor device 1 of the third embodiment includes capacitor banks CS1 to CS3 having different capacitances. The capacitances of the capacitor banks CS1 to CS3 are designed to be smaller when they are closer to the circuit, and larger when they are farther away from the circuit.

For example, the capacitor bank CS1 is provided near the power supply terminal of the circuit 3c to have a small capacitance. Since the capacitor bank CS1 is connected to the circuit 3c via the short-distance power line PW, it has an excellent ability to suppress voltage fluctuations even in a high frequency band. In addition, since the capacitor bank CS1 has a small capacitance, it occupies a small area and does not interfere with the layout around the circuit 3c. The capacitor bank CS1 mainly suppresses the fluctuation of the power supply voltage in the high frequency band.

The capacitor bank CS2 is provided at a position where the power supply line PW extends from the power supply terminal of the circuit 3c until the resistance value becomes equivalent to the resistance RP8, and has a capacitance greater than CS1. Since the capacitor bank CS2 has a large capacity, it occupies a large area, but since it is separated from the circuit 3c, it does not hinder the layout of other circuits. In addition, since the capacitor bank CS2 has a large capacitance, it is possible to expect an effect up to a frequency band lower than the frequency band of the capacitor bank CS1. Since the capacitor bank CS2 is connected to the circuit 3c via the medium-distance power supply line PW, the ability to suppress voltage fluctuations in the high frequency band may be appropriately limited. When the influence of the capacitance size and the wiring length is combined, the capacitor bank CS2 suppresses the fluctuation of the power supply voltage in a lower frequency band than the capacitor bank CS1.

The capacitor bank CS3 is provided at a position where the power supply line PW extends from the power supply terminal of the circuit 3c until the resistance value is equal to the sum of RP7 and RP8, and has a larger capacitance than CS2. Since the capacitor bank CS3 has a larger capacitance, it occupies a larger area, but because it is far away from the circuit 3c, it will not interfere with the layout of other circuits. In addition, since the capacitor bank CS3 has a larger capacitance, an effect up to the frequency band of the capacitor bank CS2 can be expected. Since the capacitor bank CS3 is connected to the circuit 3c via the long-distance power supply line PW, the ability to suppress voltage fluctuations in the high frequency band may be greatly restricted. When the influence of the capacitance and the wiring length is combined, the capacitor bank CS3 suppresses the fluctuation of the power supply voltage in a frequency band lower than the capacitor bank CS2.

As described above, according to the semiconductor device 1 of the third embodiment, the fluctuation of the power supply voltage can be suppressed in a wide frequency band, without the need to provide capacitors in the periphery of the circuit. In addition, in the semiconductor device 1 of the third embodiment, by using the capacitor CP having a portion along the recessed portion CC, it is possible to suppress an increase in the area occupied by the capacitor in the periphery of the circuit.

[4] Other modifications, etc. In the first embodiment, an example in the case where the semiconductor layer 12 and the conductor 13 are separated between adjacent recesses CC in the capacitor area CA is described, but the structure of the capacitor area CA is not limited to this. For example, the semiconductor layer 12 and the conductor 13 may not be separated in the capacitor area CA. FIG. 25 shows an example of the cross-sectional structure in the capacitor area CA in the modification. As shown in FIG. 25, in the capacitor area CA, the semiconductor layer 12 and the conductor 13 are continuously provided, and a plurality of capacitors CP may be connected in parallel by this. Furthermore, in the example shown in FIG. 25, one electrode of the capacitor CP is connected to the conductor 17 via one contact portion CT, but it may be connected via a plurality of contact portions CT.

In the first embodiment, an example of a series of manufacturing processes until the capacitor CP and the transistor TR are formed is described, but the manufacturing process is not limited to this. For example, the insulator layer may have a multilayer structure. For example, the insulator layer 21 may be a multilayer structure of silicon oxide and silicon nitride. For example, a barrier metal may be provided between the semiconductor layer 12 and the conductor 13. For example, titanium nitride (TiN) may be provided between polysilicon and tungsten. In addition, tungsten nitride may be provided between polysilicon and tungsten.

In the first embodiment, the shape of one type of capacitor CP is shown for description, but the shape of the capacitor CP is not limited to the example. FIG. 26 shows an example of the cross-sectional structure of the capacitors CPa to CPc in the modification. As shown in FIG. 26, in the capacitors CPa to CPc, the shapes of the recesses CC are different from each other. The capacitor CPa is the same as the capacitor CP described in the first embodiment. Compared with the capacitor CPa, the capacitor CPb is provided in the recess CC formed to be relatively wide and deep. Compared with the capacitor CPc, the capacitor CPc is provided in the recess CC formed to be relatively narrow and shallow. That is, the cross-sectional area of the recess is changed by changing the width and depth of the recess. As described above, for example, the recesses CC may be formed separately, and capacitors with different cross-sectional shapes may be formed separately. That is, by separately forming the recesses CC with different cross-sectional areas, it is also possible to separately create capacitors with different capacitances.

In the third embodiment, regarding the capacitor bank CS, an example in which the capacitance is realized by the number of capacitors CP included is described, but it is not limited to this. For example, referring to the description of FIG. 26, capacitors with different cross-sectional shapes may be used to form capacitor banks with different capacitances. For example, a small-capacitance capacitor bank CS1 is formed using a narrow and shallow capacitor CPc, a capacitor CPa is used to form a capacitor bank CS2, and a large-capacitance capacitor CPb formed with a wide width and deep depth is used. Group CS3 is also available.

In the first to third embodiments, an example of the case where the capacitor CP is formed in the recessed portion CC is shown, but the shape of the portion for forming the capacitor CP is not limited to the recessed portion. For example, the capacitor CP may be formed in a slit formed in the semiconductor substrate 10. In this case, the semiconductor layer 12 in the capacitor CP has a portion extending in a direction parallel to the surface of the semiconductor substrate 10.

In the third embodiment, the number of capacitors CP included in each of the capacitor banks CS1 to CS3 is described with reference to the example of FIG. 24, but the number of capacitors CP included in each of the capacitor banks CS1 to CS3 is not limited to this. In addition, the ratio of the respective capacitances of the capacitor banks CS1 to CS3 is not limited to the example described with reference to FIG. 24. For example, as an example of the layout of a circuit suitable for high-speed operation, it can be considered to set the ratio of the respective capacitances of the capacitor banks CS1 to CS3 to 1:10:1000. In addition, the size of the capacitor bank CS3 may be changed within the range of 10 to 1000 times that of the capacitor bank CS2, for example. In addition, for example, the capacitance of the capacitor bank CS2 may be 1 digit larger than the capacitance of the capacitor bank CS1, and the capacitance of the capacitor bank CS3 may be 1 to 3 digits larger than the capacitance of the capacitor bank CS2.

In the first to third embodiments, an example of a case where the pad P1 is connected to the power line GW and the capacitor 2 is connected to the power line GW will be described. However, the wiring connected to the capacitor portion 2 is not limited to the power line GW connected to the pad P1. FIG. 27 shows a configuration example of a semiconductor device 1 according to a modification example. As shown in FIG. 27, the semiconductor device 1 of the modified example is different from the semiconductor device 1 of the first embodiment in that it further includes a voltage generating circuit 4 and a power supply line PW2, and the capacitor section 2 and the circuit section 3 are connected to the power supply line PW2 and the power supply. Between GW. As described above, the capacitor portion 2 may be connected to, for example, a wiring to which a voltage generated inside the semiconductor device is applied.

In the first to third embodiments, an example of the case where the power line PW and the capacitor CP are connected via one contact portion CT will be described. However, a plurality of contact portions may be connected between the power line PW and the capacitor CP, and a different cloth may be used in the middle. Line can also be used.

In the third embodiment, an example of a case where a plurality of capacitors CP are connected to the power supply line PW via the contact portion CT will be described with respect to the capacitor bank. However, the configuration of the capacitor bank is not limited to the example described in the third embodiment. For example, a capacitor bank is formed by connecting one electrode of each of a plurality of capacitors CP collectively arranged in a certain area. When multiple capacitor banks are provided on the semiconductor substrate, each of the multiple capacitor banks can be divided into an independent capacitor bank by the size of the capacitance of each capacitor bank and the connection position between each capacitor bank and the power line PW .

The shape referred to as the recess CC in this specification can be changed. For example, the semiconductor substrate 10 having the concave portion CC can be said to be a semiconductor substrate 10 having a first surface, a second surface facing the first surface, and a third surface provided between the first surface and the second surface. The first surface is, for example, the surface of the semiconductor substrate 10. The second surface is, for example, the back surface of the semiconductor substrate 10. The third surface is, for example, the bottom of the recess CC. In addition, the semiconductor layer 12 provided along the recess CC can be said to be the semiconductor layer 12 provided along the first surface from the third surface. In addition, for example, a capacitor with a fourth surface provided between the first surface and the second surface and a semiconductor layer provided from the fourth surface along the first surface has the same capacitance as the capacitor provided from the third surface along the first surface. The capacitance of the capacitor of the semiconductor layer is different. As described above, a plurality of surfaces, such as a third surface and a fourth surface, may be provided between the first surface and the second surface, so that capacitors having different capacitances may be separately manufactured. That is, by providing a plurality of surfaces such as the third surface and the fourth surface, the recesses CC having different cross-sectional areas may be formed separately.

In this specification, "connected" means electrical connection, for example, it does not exclude the insertion of other elements in between. In addition, "electrical connection" may be made via an insulator as long as it can operate in the same manner as the electrically connected person.

[5] Fourth Embodiment The semiconductor device of the fourth embodiment is a specific example in the case where the semiconductor device 1 of the third embodiment includes a plurality of circuits. Hereinafter, the difference between the semiconductor device 1 of the fourth embodiment and the first to third embodiments will be described.

[5-1] Composition FIG. 28 shows an example of the circuit configuration of the semiconductor device 1 of the fourth embodiment. As shown in FIG. 28, the semiconductor device 1 of the fourth embodiment includes capacitor groups CS10d, CS10e, CS10f, CS20, and CS30 as the capacitor unit 2, and includes circuits 3d, 3e, and 3f as the circuit unit 3. The power line PW includes a node N4.

The power supply line PW is provided from the pad P1 to the respective power supply terminals of the circuits 3d, 3e, and 3f. Specifically, the corresponding portion of the power line PW from the pad P1 to the node N4 is shared by the circuits 3d, 3e, and 3f. On the other hand, the corresponding parts of the power line PW from the node N4 to the respective power terminals of the circuits 3d, 3e, and 3f are independently provided in the circuits 3d, 3e, and 3f.

One electrode of each of the capacitor groups CS10d, CS10e, CS10f, CS20, and CS30 is connected to the power supply line PW, and the other electrode of each is grounded. One side electrode of the capacitor bank CS10d is connected between the power terminal of the circuit 3d and the node N4. One side electrode of the capacitor bank CS10e is connected between the power terminal of the circuit 3e and the node N4. One side electrode of the capacitor bank CS10f is connected between the power terminal of the circuit 3f and the node N4. Between the node N4 and the pad P1, one electrode of each of the capacitor groups CS20 and CS30 is sequentially connected from the node N4 to the pad P1.

The capacitances of the capacitor banks CS10d, CS10e, and CS10f are, for example, approximately equal. The capacitance of the capacitor bank CS20 is greater than the capacitance of any of the capacitor banks CS10d, CS10e and CS10f. The capacitance of the capacitor bank CS20 is, for example, 10 times the capacitance of the capacitor bank CS10d. The capacitance of the capacitor bank CS30 is greater than the capacitance of the capacitor bank CS20. The capacitance of the capacitor bank CS30 is, for example, 10 times the capacitance of the capacitor bank CS20.

That is, the capacitor banks CS10d, CS20, and CS30 are arranged in the order of the smallest capacitance from the circuit 3d to the pad P1. The capacitor banks CS10e, CS20, and CS30 are arranged in the order of the smallest capacitance from the circuit 3e to the pad P1. The capacitor banks CS10f, CS20, and CS30 are arranged in the order of smaller capacitance from the circuit 3f to the pad P1.

FIG. 29 shows an example of the planar layout of the semiconductor device 1 of the fourth embodiment. As shown in FIG. 29, the semiconductor device 1 of the fourth embodiment further includes contact portions CT20d, CT20e, CT20f, CT21d, CT21e, CT21f, CT22, and CT23. In addition, the capacitor banks CS10d, CS10e, CS10f, CS20, and CS30 each include a plurality of capacitors CP. The number of capacitors CP included in the capacitor bank increases, for example, in the order of the capacitor bank CS10d, the capacitor bank CS20, and the capacitor bank CS30. In the example shown in FIG. 29, the number of capacitors CP is simplified.

The power line PW extends from the pad P1 in the X direction. The capacitor bank CS30, the capacitor bank CS20, the capacitor bank CS10d, and the circuit 3d are sequentially arranged along the power supply line PW from a position close to the pad P1. The circuit 3e and the capacitor bank CS20 are arranged side by side in the Y direction. The circuit 3f is juxtaposed with the capacitor bank CS20 in the Y direction and arranged on the opposite side of the circuit 3e. The capacitor bank CS10e is parallel to the circuit 3e in the X direction, and is arranged between the capacitor bank CS10d and the capacitor bank CS20 in the Y direction. The capacitor bank CS10f is parallel to the circuit 3f in the X direction, and is arranged between the capacitor bank CS10d and the capacitor bank CS20 in the Y direction. In addition, the power supply line PW has a branch portion F1 between the capacitor bank CS10d and the capacitor bank CS20, and extends from the branch portion F1 in the Y direction. The branch F1 corresponds to the node N4.

The contact portions CT20d, CT20e, and CT20f respectively connect the respective power terminals of the circuits 3d, 3e, and 3f to the power line PW. The contact portions CT21d, CT21e, CT21f, CT22, and CT23 respectively connect one electrode of each of the capacitor banks CS10d, CS10e, CS10f, CS20, and CS30 to the power supply line PW. The other configuration of the semiconductor device 1 of the fourth embodiment is the same as that of the third embodiment.

[5-2] Effects of the fourth embodiment As described above, in the semiconductor device 1 of the fourth embodiment, the power supply line PW of the plurality of circuits has a portion shared between the plurality of circuits and a portion independently provided corresponding to the plurality of circuits. As in the third embodiment, in the power supply lines PW respectively connected to the circuits 3d, 3e, and 3f, the closer the circuit is, the smaller the capacitor bank is connected, and the farther the circuit is, the larger the capacitor bank is connected. In the semiconductor device 1 of the fourth embodiment, by arranging the capacitor banks as described above, even when there are a plurality of circuits, the fluctuation of the power supply voltage can be suppressed as in the third embodiment.

[5-3] Modifications of the fourth embodiment The semiconductor device 1 of the fourth embodiment can have various modifications. Hereinafter, the first to fifth modified examples of the fourth embodiment will be described in order.

[5-3-1] First modification FIG. 30 shows an example of the planar layout of the semiconductor device 1 according to the first modification of the fourth embodiment. As shown in FIG. 30, the semiconductor device 1 of the first modification example is the semiconductor device 1 of the fourth embodiment, and has a configuration in which the capacitor banks CS10d, CS10e, and CS10f are replaced with capacitor banks CS11d, CS11e, and CS11f, respectively.

The capacitor banks CS11d, CS11e, and CS11f each include a plate capacitor FC. That is, in the semiconductor device 1 of the first modification example, among the plurality of capacitor banks with different capacitances, the capacitor bank with a small capacitance includes the plate capacitor FC. In addition, as in the fourth embodiment, the plurality of capacitor banks CS are provided so that the closer to the circuit, the smaller the capacitance, and the farther from the circuit, the larger the capacitance. The other configurations in the first modification of the fourth embodiment are the same as those of the fourth embodiment.

As described above, in the semiconductor device 1 of the first modification of the fourth embodiment, some of the capacitor banks CS include the plate capacitors FC. In the semiconductor device 1, the capacitance of each capacitor bank is designed based on the consumption current of the circuit or the allowable voltage fluctuation amount. Therefore, when the capacitance of the capacitor bank close to the circuit becomes a very small value, even when the capacitor bank close to the circuit includes a plate capacitor FC, sufficient performance can be obtained. Therefore, the semiconductor device 1 of the first modification of the fourth embodiment can obtain the same effect as the fourth embodiment.

[5-3-2] Second modification FIG. 31 shows an example of the planar layout of the semiconductor device 1 according to the second modification of the fourth embodiment. As shown in FIG. 31, the semiconductor device 1 of the second modification example has a configuration in which the capacitor bank CS30 is replaced with the capacitor bank CS31 in the semiconductor device 1 of the fourth embodiment.

The capacitor bank CS31 includes a plate capacitor FC. That is, in the semiconductor device 1 of the second modification example, among the plurality of capacitor banks with different capacitances, the capacitor bank with a large capacitance has the structure of the plate capacitor FC. In addition, as in the fourth embodiment, the plurality of capacitor banks CS are arranged so that the closer they are to the circuit, the smaller the capacitance, and the farther away from the circuit, the larger the capacitance. The other configurations in the second modification of the fourth embodiment are the same as those of the fourth embodiment.

As described above, in the semiconductor device 1 of the second modification of the fourth embodiment, some of the capacitor banks CS are formed using the plate capacitors FC. In the semiconductor device 1, the area of the region where the capacitor bank CS is provided varies depending on the design. Therefore, when the circuit is not dense and the area of the substrate has a margin, a large-capacity capacitor bank can also be composed of a plate capacitor FC. Therefore, the semiconductor device 1 of the second modification of the fourth embodiment can obtain the same effect as the fourth embodiment.

[5-3-3] Third modification FIG. 32 shows an example of the circuit configuration of the semiconductor device 1 according to the third modification of the fourth embodiment. As shown in FIG. 32, the semiconductor device 1 of the third modification example is the semiconductor device 1 of the fourth embodiment, and further includes capacitor groups CS12e and CS21 as capacitor portions 2. The power line PW further includes a node N5. The circuit 3e further includes a second power supply terminal. In addition, the power supply terminal of the circuit 3e described in the fourth embodiment will be referred to as the first power supply terminal of the circuit 3e, so as to be easily distinguished from the second power supply terminal of the circuit 3e.

The node N5 of the power supply line PW corresponds to the point between the point where one electrode of the capacitor bank CS30 is connected and the point where the one electrode of the capacitor bank CS20 is connected. The node N5 and the second power terminal of the circuit 3e are connected by a power line PW. In the power line PW, between the node N5 and the second power terminal of the circuit 3e, one electrode of the capacitor bank CS21 and one electrode of the capacitor bank CS12e are sequentially connected from the node N5 to the second power terminal of the circuit 3e. .

The capacitance of the capacitor bank CS12e is approximately equal to the capacitance of the capacitor bank CS10e, for example. The capacitance of the capacitor bank CS21 is greater than the capacitance of the capacitor bank CS12e, and is less than the capacitance of the capacitor bank CS30. The capacitance of the capacitor bank CS21 is approximately equal to that of the capacitor bank CS20, for example.

FIG. 33 shows an example of the planar layout of the semiconductor device 1 of the third modification. As shown in FIG. 33, the semiconductor device 1 of the third modification example further includes contact portions CT20e2, CT21e2, and CT24. The number of capacitors CP included in the capacitor bank CS12e is equal to the number of capacitors CP included in the capacitor bank CS10e, for example. The number of capacitors CP included in the capacitor bank CS21 is equal to the number of capacitors CP included in the capacitor bank CS20, for example.

The power line PW has a branch portion F2 between the capacitor bank CS20 and the capacitor bank CS30, and extends from the branch portion F2 in the Y direction. The branch F2 corresponds to the node N5. The power line PW extends from the branch F2 in the Y direction, and the capacitor bank CS21 and the capacitor bank CS12e are sequentially arranged from the branch F2.

The contact portion CT20e2 connects the second power terminal of the circuit 3e and the power line PW. The contact portion CT21e2 connects one electrode of the capacitor bank CS12e to the power supply line PW. The contact portion CT24 connects one electrode of the capacitor bank CS21 and the power supply line PW. The other configuration of the semiconductor device 1 of the third modification example is the same as that of the fourth embodiment.

That is, in the semiconductor device 1 of the third modification, in the power line PW connecting the first power terminal and the second power terminal of the circuit 3e, the closer the circuit is to the capacitor group with the smaller capacitance, the farther away the circuit is. Arrange a capacitor bank with a larger capacitance. Specifically, in the power line PW connecting the first power terminal of the circuit 3e and the pad P1, the capacitor bank CS10e, the capacitor bank CS20, and the capacitor bank CS30 are sequentially arranged from the first power terminal of the circuit 3e to the pad P1 . In the power line PW connecting the second power terminal of the circuit 3e and the pad P1, a capacitor bank CS12e, a capacitor bank CS21, and a capacitor bank CS30 are sequentially arranged from the second power terminal of the circuit 3e to the pad P1.

As described above, in the semiconductor device 1 of the third modification of the fourth embodiment, when a plurality of different power supply lines are connected to the same circuit block, the capacitor banks are respectively arranged on the plurality of power supply lines. Thereby, the jitter of the power supply voltage in the same circuit block can be suppressed extremely finely, and the effect of reducing jitter can be promoted. As described above, the semiconductor device 1 of the third modification of the fourth embodiment can obtain the same effects as the fourth embodiment.

In addition, the relationship between the capacitance of the capacitor bank CS12e and the capacitance of the capacitor bank CS10e, and the relationship between the capacitance of the capacitor bank CS21 and the capacitance of the capacitor bank CS20 are not limited to approximately the same as those exemplified in the third modification. condition. The respective capacitances of the capacitor banks CS12e and CS21 can be changed within the range where the capacitance of the capacitor bank CS21 is smaller than the capacitance of the capacitor bank CS30, and the capacitance of the capacitor bank CS12e is smaller than the capacitance of the capacitor bank CS21.

[5-3-4] Fourth modification FIG. 34 shows an example of the planar layout of the semiconductor device 1 according to the fourth modification of the fourth embodiment. As shown in FIG. 34, the semiconductor device 1 of the fourth modification example is the semiconductor device 1 of the fourth embodiment, and has a configuration in which the capacitor banks CS10d, CS10e, and CS10f are replaced with capacitor banks CS13d, CS13e, and CS13f, respectively.

The circuits 3d, 3e, and 3f each include a plurality of elements constituting the circuit, such as a transistor, a resistor, and a capacitor. The multiple elements included in the circuit 3d are arranged in the circuit area A1 on the substrate. The capacitor bank CS13d is arranged in the circuit area A1. For example, the elements included in the circuit 3d surround the capacitor bank CS13d.

A plurality of elements included in the circuit 3e are arranged in the circuit area A2 on the substrate. The capacitor bank CS13e is arranged in the circuit area A2. For example, the capacitor bank CS13e is surrounded by elements included in the circuit 3e.

The multiple elements included in the circuit 3f are arranged in the circuit area A3 on the substrate. The capacitor bank CS13f is arranged in the circuit area A3. For example, the capacitor bank CS13f is surrounded by elements included in the circuit 3f. In other words, the capacitor banks CS13d, CS13e, and CS13f are respectively arranged in the respective regions where the circuits 3d, 3e, and 3f are provided.

In the semiconductor device 1 of the fourth modification described above, among the plurality of capacitor banks of different capacitances, the capacitor bank of small capacitance is provided in the area where the circuit is provided. Thereby, the distance between the power terminal of the circuit and the capacitor bank of small capacitance can be shortened, the fluctuation of the power supply voltage can be further suppressed, and the jitter can be further reduced. Therefore, the semiconductor device 1 of the fourth modification of the fourth embodiment can obtain the same effect as the fourth embodiment.

[5-3-5] The fifth modification FIG. 35 shows an example of the planar layout of the capacitor bank CS30 of the semiconductor device 1 according to the fifth modification of the fourth embodiment. As shown in FIG. 35, the semiconductor device 1 of the fifth modification is related to the semiconductor device 1 of the fourth embodiment further including wirings W1, W2, and W3. The capacitor bank CS30 includes capacitors CPa, CPb, and CPc. As described with reference to FIG. 26, the capacitors CPa, CPb, and CPc are capacitors of different sizes. In FIG. 35, the description of the power supply line PW to which one electrode of the capacitor bank CS30 is connected is omitted in order to facilitate the observation of the structure. One electrode of each of the plurality of capacitors included in the capacitor group CS30 is connected to the power supply line PW through the contact portion CT.

As shown in FIG. 35, the wirings W1, W2, and W3 are arranged in a manner overlapping with the area where the capacitor group CS30 is provided. A plurality of capacitors CPa, CPb, and CPc are arranged in a manner not to overlap with the wirings W1, W2, and W3. Specifically, in the vicinity of the wiring W1 and the area between the wiring W1 and the wiring W2, a plurality of smaller-sized capacitors CPc are arranged in a manner that can be arranged between the wiring W1 and the wiring W2. A plurality of capacitors CPa are arranged in the area between the wiring W2 and the wiring W3. A plurality of larger-sized capacitors CPb are arranged in the area divided by the wiring W3 and there is no other wiring area.

In the semiconductor device 1 of the fifth modified example described above, one capacitor bank CS includes a plurality of types of capacitors CP of different sizes. The area where the capacitor group CS is provided may overlap with the area where the wiring is provided, for example. There are cases where the wiring and the capacitor CP cannot be overlapped. In the case of arranging the capacitor CP while avoiding the wiring, by using capacitors of multiple sizes, it is possible to suppress the increase in the area of the capacitor bank caused by avoiding the wiring. Therefore, the semiconductor device 1 of the fifth modification of the fourth embodiment can obtain the same effect as the fourth embodiment.

In addition, the element that cannot be arranged to overlap the capacitor CP is not limited to the wiring. For example, when the capacitor CP is arranged to avoid the contact portion connected to the semiconductor substrate, the dummy pattern, or the like, the configuration shown in the fifth modification is effective.

The first to fifth modification examples of the fourth embodiment described above can be combined. For example, the first modification example and the fifth modification example can be combined. In addition, the capacitor CP and the plate capacitor FC may be combined to form one capacitor bank CS.

In the above-described embodiments and modifications, some examples are given to illustrate the capacitor CP having the function of the semiconductor layer 12 and the conductor 13 provided along the recess CC as one electrode, and the semiconductor layer provided on the semiconductor substrate 12 and the conductor 13 function as a plate capacitor FC of one electrode. In addition, an example of the function of the semiconductor substrate 10 as the other electrode of the capacitor CP and the other electrode of the plate capacitor FC has been described. In addition, the capacitor CP can be said to be a trench capacitor, for example. The plate capacitor FC can be said to be a planar capacitor, for example.

Several embodiments of the present invention have been described, but these embodiments are only examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments or their modifications are also included in the scope or spirit of the invention, and are also included in the invention described in the scope of the patent application and its equivalent scope.

1: Semiconductor device 2: Capacitor 3: Circuit Department P1, P2: solder pad PW, GW: power cord CP: Capacitor 10: Semiconductor substrate 11: Insulator layer 12: Semiconductor layer 13: Conductor 14: Insulator 15: Well area 16,19: Diffusion area 17,18: Conductor 30: Conductor CC: recess CT: Contact TR: Transistor CA: Capacitor area TA: Transistor area

[Fig. 1] A block diagram showing a configuration example of the semiconductor device of the first embodiment. [Fig. 2] Fig. 2 is a circuit diagram showing a configuration example of a capacitor section 2 included in the semiconductor device of the first embodiment. [FIG. 3] A plan view showing an example of the planar layout in the capacitor region of the semiconductor device of the first embodiment. [Fig. 4] A cross-sectional view showing an example of the cross-sectional structure of the capacitor region along the line IV-IV in Fig. 3. [Fig. [FIG. 5] A cross-sectional view showing an example of the cross-sectional structure of the transistor region of the semiconductor device of the first embodiment. [FIG. 6] A flowchart showing an example of the manufacturing process of the semiconductor device of the first embodiment. [FIG. 7] A cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. [FIG. 8] A cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. [FIG. 9] A cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. [FIG. 10] A cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. [FIG. 11] A cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. [FIG. 12] A cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. [FIG. 13] A cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. Fig. 14 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. [FIG. 15] A cross-sectional view showing an example of the manufacturing process of the semiconductor device of the first embodiment. [FIG. 16] A plan view showing an example of the planar layout in the capacitor region of the semiconductor device of the comparative example of the first embodiment. [Fig. 17] A cross-sectional view showing an example of the cross-sectional structure of the capacitor region along the line XVII-XVII of Fig. 16. [Fig. [Fig. 18] A block diagram showing a configuration example of the semiconductor device of the second embodiment. [FIG. 19] A plan view showing an example of the planar layout of the semiconductor device of the second embodiment. [Fig. 20] Fig. 20 is a block diagram showing a configuration example of a semiconductor device of a comparative example of the second embodiment. [FIG. 21] A plan view showing an example of a planar layout of a semiconductor device of a comparative example of the second embodiment. [FIG. 22] A graph showing the time change of voltage and current in the semiconductor device of the second embodiment and its comparative example. [Fig. 23] A block diagram showing a configuration example of a semiconductor device of the third embodiment. [FIG. 24] A plan view showing an example of the planar layout of the semiconductor device of the third embodiment. [FIG. 25] A cross-sectional view showing an example of the cross-sectional structure of the capacitor region in the first modification of the first to third embodiments. [Fig. 26] Fig. 26 is a cross-sectional view showing an example of a cross-sectional structure of a capacitor region in a second modification of the first to third embodiments. [Fig. 27] A block diagram showing a configuration example of a semiconductor device according to a third modification of the first to third embodiments. [Fig. 28] A block diagram showing a configuration example of a semiconductor device of the fourth embodiment. [FIG. 29] A plan view showing an example of the planar layout of the semiconductor device of the fourth embodiment. [Fig. 30] A plan view showing an example of a planar layout of a semiconductor device according to a first modification of the fourth embodiment. [Fig. 31] A plan view showing an example of a planar layout of a semiconductor device according to a second modification of the fourth embodiment. [Fig. 32] A block diagram showing a configuration example of a semiconductor device according to a third modification of the fourth embodiment. [FIG. 33] A plan view showing an example of a planar layout of a semiconductor device according to a third modification of the fourth embodiment. [FIG. 34] A plan view showing an example of a planar layout of a semiconductor device according to a fourth modification of the fourth embodiment. [FIG. 35] A plan view showing an example of the planar layout of the capacitor bank included in the semiconductor device according to the fifth modification of the fourth embodiment.

CA: Capacitor area

TA: Transistor area

PW: Power cord

CP: Capacitor

TR: Transistor

10: Semiconductor substrate

11: Insulator layer

12: Semiconductor layer

13: Conductor

14: Insulator

15: Well area

16: diffusion area

17: Conductor

30: Conductor

CT: Contact

Claims (27)

A type of semiconductor device with: A semiconductor substrate having a first surface, a second surface facing the first surface, and a third surface provided between the first surface and the second surface; A first semiconductor layer provided along the first surface from the third surface; A first conductor disposed on the aforementioned first semiconductor layer; The first power line electrically connected to the aforementioned first electrical conductor; The second power line electrically connected to the aforementioned semiconductor substrate; and An electric circuit is provided on the semiconductor substrate and connected to the first power line and the second power line. Such as the semiconductor device of claim 1, wherein The first conductive system functions as one electrode of the capacitor, and the semiconductor substrate functions as the other electrode of the capacitor. Such as the semiconductor device of claim 2, wherein One side electrode of the capacitor includes the first semiconductor layer. Such as the semiconductor device of claim 1, wherein The circuit further has a transistor including a gate electrode including a second semiconductor layer provided on the same layer as the first semiconductor layer, and a second conductor provided on the same layer as the first electrical conductor. Such as the semiconductor device of claim 1, wherein The aforementioned circuit includes a transistor including a second semiconductor layer that functions as a gate electrode and a second electrical conductor; The first semiconductor layer and the second semiconductor layer include the same material, and the first electrical conductor and the second electrical conductor include the same material. Such as the semiconductor device of claim 2, wherein It also contains a number of capacitor banks, each of which contains a number of the aforementioned capacitors, The capacitor group with the smallest capacitance among the aforementioned plurality of capacitor groups is closest to the aforementioned circuit arrangement. Such as the semiconductor device of claim 6, wherein The plurality of capacitor banks further includes: a first capacitor bank, and a second capacitor bank having a larger capacitance than the first capacitor bank, The first capacitor bank and the second capacitor bank are arranged in the order of the first capacitor bank and the second capacitor bank from the circuit along the first power line. Such as the semiconductor device of claim 7, wherein The first capacitor bank includes the first number of capacitors, The second capacitor group includes the second number of capacitors which is larger than the first number. Such as the semiconductor device of claim 7, wherein The plurality of capacitor banks further include: a third capacitor bank having a larger capacitance than the second capacitor bank, The third capacitor group is arranged from the circuit along the first power line in the order of the first capacitor group, the second capacitor group, and the third capacitor group. Such as the semiconductor device of claim 9, wherein The capacitance of the second capacitor bank is more than 10 times the capacitance of the first capacitor bank, The capacitance of the third capacitor bank is more than 10 times the capacitance of the second capacitor bank. Such as the semiconductor device of claim 1, wherein The semiconductor substrate further includes a fourth surface provided between the first surface and the second surface, and further includes a third semiconductor layer provided along the first surface from the fourth surface, and a third semiconductor layer provided on the first surface. 3rd conductor on the semiconductor layer and electrically connected to the aforementioned first power line, The first conductor functions as one electrode of the first capacitor, and the semiconductor substrate functions as the other electrode of the first capacitor, The third conductor functions as one electrode of the second capacitor, and the semiconductor substrate also functions as the other electrode of the second capacitor, The capacitance of the second capacitor is greater than the capacitance of the first capacitor. Such as the semiconductor device of claim 11, wherein The one side electrode of the first capacitor includes the first semiconductor layer, The one side electrode of the second capacitor includes the third semiconductor layer. Such as the semiconductor device of claim 11, wherein It further includes: a first capacitor bank including a plurality of the first capacitors, and a second capacitor bank including a plurality of the second capacitors and having a larger capacitance than the first capacitor bank, The first capacitor bank and the second capacitor bank are arranged in the order of the first capacitor bank and the second capacitor bank from the circuit along the first power line. Such as the semiconductor device of claim 1, wherein Also has: Connect the aforementioned first power line and serve as the first pad for applying power voltage, and Connect the aforementioned second power cord and ground the second pad. Such as the semiconductor device of claim 1, wherein The aforementioned circuit is a peripheral circuit of a NAND flash memory. Such as the semiconductor device of claim 1, wherein Also has: A second semiconductor layer provided on the first surface and separated from the first semiconductor layer, and A second conductor disposed on the aforementioned second semiconductor layer; The second conductor is electrically connected to the first power line. Such as the semiconductor device of claim 16, wherein The aforementioned first conductor functions as a side electrode of the trench capacitor, The aforementioned second conductor functions as a square electrode of a planar capacitor, The semiconductor substrate functions as the other electrode of the trench capacitor and the other electrode of the planar capacitor. Such as the semiconductor device of claim 17, wherein One of the side electrodes of the trench capacitor includes the first semiconductor layer, One side electrode of the planar capacitor includes the second semiconductor layer. Such as the semiconductor device of claim 17, wherein It also includes a plurality of capacitor banks, and each capacitor bank includes a plurality of the aforementioned trench capacitors and/or the aforementioned planar capacitors, The capacitor bank with the smallest capacitance among the aforementioned plurality of capacitor banks is closest to the aforementioned circuit arrangement. Such as the semiconductor device of claim 19, wherein The aforementioned capacitor bank with the smallest capacitance includes the aforementioned planar capacitor and does not include the aforementioned trench capacitor. Such as the semiconductor device of claim 19, wherein The plurality of capacitor banks further include: a first capacitor bank, and a second capacitor bank having a larger capacitance than the first capacitor bank, The first capacitor bank and the second capacitor bank are arranged in the order of the first capacitor bank and the second capacitor bank from the circuit along the first power line. Such as the semiconductor device of claim 21, wherein The plurality of capacitor banks further include: a third capacitor bank having a larger capacitance than the second capacitor bank, The third capacitor bank is arranged in the order of the first capacitor bank, the second capacitor bank, and the third capacitor bank from the circuit along the first power line. Such as the semiconductor device of claim 22, wherein The capacitance of the second capacitor bank is more than 10 times the capacitance of the first capacitor bank, The capacitance of the third capacitor bank is more than 10 times the capacitance of the second capacitor bank. Such as the semiconductor device of claim 17, wherein Also contains: The solder pad connected to the aforementioned first power cord; and The first to fifth capacitor banks each include a plurality of the aforementioned trench capacitors and/or the aforementioned planar capacitors; The aforementioned circuit includes a first power terminal and a second power terminal electrically connected to the first power line, The first power cord includes: the first part from the pad to the branch, the second part from the branch to the first power terminal, and the third part from the branch to the second power terminal, The first capacitor bank and the second capacitor bank are arranged in the second part, and the first capacitor bank is arranged closer to the first power terminal than the second capacitor bank, The third capacitor bank and the fourth capacitor bank are arranged in the third part, and the third capacitor bank is arranged closer to the second power supply terminal than the fourth capacitor bank, The fifth capacitor bank is arranged in the first part, The capacitance of the aforementioned second capacitor bank is greater than the capacitance of the aforementioned first capacitor bank, The capacitance of the aforementioned fourth capacitor bank is greater than that of the aforementioned third capacitor bank, The capacitance of the fifth capacitor bank is greater than the capacitance of any one of the second capacitor bank and the fourth capacitor bank. Such as the semiconductor device of claim 17, wherein It also includes a plurality of capacitor banks, each of which includes a plurality of the aforementioned trench capacitors and/or the aforementioned planar capacitors, The aforementioned circuit is provided in the first area on the aforementioned semiconductor substrate, The capacitor bank with the smallest capacitance among the plurality of capacitor banks is arranged in the first region. Such as the semiconductor device of claim 11, wherein It further includes: a first capacitor bank including a plurality of the first capacitors, and a second capacitor bank including a plurality of the first capacitors and a plurality of the second capacitors. Such as the semiconductor device of claim 26, wherein The capacitance of the aforementioned second capacitor bank is greater than the capacitance of the aforementioned first capacitor bank, The first capacitor bank and the second capacitor bank are arranged in the order of the first capacitor bank and the second capacitor bank from the circuit along the first power line.

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