JP2010118563A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide atechnique for forming capacitance small in capacitance value variance between chips of the same kind. <P>SOLUTION: A friniging capacitor includes interconnections M1A, M2A, M3A, and M4A as one capacitor electrode, interconnections M1B, M2B, M3B, and M4B as the other capacitor electrode, and interlayer insulating films 9, 13, 16, and 19 as capacitance insulating films, wherein an arrangement pitch LP of the interconnections M1A, M1B, M2A, M2B, M3A, M3B, M4A, and M4B is equalized to an arrangement pitch of the interconnections M4A and M4B having the largest interconnection width among those interconnections. An inter-adjacent-interconnection distance L1 of the interconnections M1A, M1B, M2A, M2B, M3A, and M3B is larger than an interconnection width LW of the interconnections M1A, M1B, M2A, M2B, M3A, and M3B, and 1.3 to 3, preferably, 2 to 3 times as large as a minimum processing size. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a technique for accurately forming a fringe capacitance between metal wirings.

Japanese Patent Laying-Open No. 2008-172135 (Patent Document 1) discloses a standard deviation of the total capacitance value in each wiring layer in a semiconductor device having a capacitive element by adjusting the electrode size of each capacitive element in each wiring layer. A technique is disclosed in which the value divided by the total capacitance value is substantially the same in all wiring layers. In other words, a technique for suppressing an increase in variation in integrated capacitance values in all capacitive elements in all wiring layers is disclosed.
JP 2008-172135 A

  A non-contact type IC card is a card that can only read / write data to / from a memory circuit in a semiconductor chip (hereinafter simply referred to as a chip) using a microwave, and is configured with a lead frame or the like. It has a structure in which a chip is mounted on an antenna.

  The non-contact IC card does not include a power supply inside, generates a voltage by electromagnetic induction, and obtains a desired output voltage value by a resonance operation of a resonance circuit including an internal capacitance. Therefore, if the capacitance value varies due to a manufacturing error, there is a concern that the communication distance may change even in a non-contact IC card having the same type of chip.

  The capacitor is formed of a plurality of wiring layers formed on, for example, a semiconductor substrate (hereinafter simply referred to as a substrate). In addition, since the voltage generated by the electromagnetic induction has a large value such as about 30 V, a large voltage is applied to the wiring (electrode) forming the wiring layer. Here, if the distance between the two wirings that serve as the capacitor electrode is narrow, there is a risk that a leakage current will occur between the two wirings, and if a leakage current occurs, the capacitor cannot accumulate charges. There is a concern about the malfunction.

  An object of the present invention is to provide a technique capable of forming a capacitor with little variation in capacitance value between chips of the same type.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A semiconductor device according to the present invention is a semiconductor device having one or more first wiring layers formed on a main surface of a semiconductor substrate,
The first wiring layer forms a capacitor;
Each of the plurality of first wirings forming the first wiring layer serves as a pair of capacitance electrodes of the capacitance, and the distance between the adjacent first wirings is 1.3 to 3 times the minimum processing dimension. The capacity value of the capacity is determined under the conditions
The opposing lengths of the pair of first wirings serving as the pair of capacitive electrodes are determined based on the manufacturing error of the capacitance, the capacitance value, and the distance between the adjacent first wirings. .

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Capacitances with little variation in capacitance values can be formed between the same type of chips.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. In addition, when referring to the constituent elements in the embodiments, etc., “consisting of A” and “consisting of A” do not exclude other elements unless specifically stated that only the elements are included. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In addition, when referring to materials, etc., unless specified otherwise, or in principle or not in principle, the specified material is the main material, and includes secondary elements, additives It does not exclude additional elements. For example, unless otherwise specified, the silicon member includes not only pure silicon but also an additive impurity, a binary or ternary alloy (for example, SiGe) having silicon as a main element.

  In addition, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  In the drawings used in the present embodiment, even a plan view may be partially hatched to make the drawings easy to see.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The semiconductor device of the first embodiment is, for example, a chip included in a non-contact type IC card. FIG. 1 is a plan view of the main part of the chip, and FIG. 2 is a cross-sectional view of the main part of the chip.

  As shown in FIGS. 1 and 2, the chip is formed from a substrate 1 made of, for example, p-type single crystal silicon as a semiconductor substrate. An n-type isolation layer 2 for element isolation is formed on the main surface of the substrate 1, and a p-type well 3 and an n-type well 4 are formed on the n-type isolation layer 2. The main surface of the substrate 1 defines an active region in which a semiconductor element is formed by the element isolation region 5. The element isolation region 5 is formed as an insulating film by, for example, embedding silicon oxide in a shallow groove formed in the main surface of the substrate 1. Furthermore, a dummy element isolation region 5A that does not contribute to the definition of the actual active region is also formed on the main surface of the substrate 1. That is, the dummy element isolation region 5A is provided to partition the n-type semiconductor region 6 formed between the dummy element isolation regions 5A as a dummy pattern. The element isolation region 5 and the dummy element isolation region 5A are formed in the same process. For example, a silicon oxide film is deposited on the substrate 1, and a shallow groove formed on the main surface of the substrate 1 with the silicon oxide film. Then, the silicon oxide film outside the shallow trench is removed by CMP (Chemical Mechanical Polishing) or the like. At that time, a step is generated on the surface between the active region and the element isolation region 5 in the main surface of the substrate 1 and the surface of the active region is depressed, so that the step shape is reflected in the arrangement state of the upper layer wiring. There is a concern that an error may occur in the capacitance (fringe capacitance) value formed by the upper layer wiring. Therefore, by arranging the dummy element isolation region 5A in a region that does not contribute to circuit formation, the depression of the surface of the active region can be reduced.

  In the active region, an n-type semiconductor region 6 and a p-type semiconductor region are formed. A part of these n-type semiconductor region 6 and p-type semiconductor region forms a MISFET (Metal Insulator Semiconductor Field Effect Transistor) which is a semiconductor element together with a gate electrode formed on the main surface of the substrate 1. In addition, the n-type semiconductor region 6 and a part of the p-type semiconductor region electrically connect the lower p-type well 3 or the n-type well 4 and the upper wiring, and supply a reference potential to the upper wiring. Used for that. Unlike the gate electrode, a dummy gate electrode (first gate electrode) 7 that does not contribute to the formation of the MISFET is formed on the main surface of the substrate 1. The gate electrode and the dummy gate electrode 7 are formed in the same process, and are formed, for example, by patterning a polycrystalline silicon film. In the main surface of the substrate 1, if there is a difference in density between the arrangement states of the gate electrodes, the surface of the interlayer insulating film deposited on the gate electrode in a later step is depressed at a portion where there is no gate electrode. There is a concern that Since such a depression is reflected in the arrangement state of the upper layer wiring, there is a concern that an error may occur in the capacitance (fringe capacitance) value formed by the upper layer wiring. Therefore, by arranging the dummy gate electrode 7 so as to eliminate the difference in density of the arrangement state of the gate electrode on the plane, it is possible to prevent the formation of a depression on the surface of the interlayer insulating film.

  On the main surface of the substrate 1 on which the gate electrode and the dummy gate electrode 7 are formed, an interlayer insulating film 8 made of, for example, silicon oxide is formed so as to cover the gate electrode and the dummy gate electrode 7. As described above, the surface of the interlayer insulating film 8 can be made flat by disposing the dummy gate electrode 7 so as to eliminate the difference in density between the arrangement states of the gate electrodes.

  An interlayer insulating film 9 is formed on the interlayer insulating film 8, and a wiring groove 10 formed in the interlayer insulating film 9 has a wiring (first wiring) M 1 A having copper or a copper alloy as a main conductive layer, wiring (First wiring) M1B and wiring M1C are formed, and a first wiring layer (first wiring layer) is formed by these wirings. The interlayer insulating film 9 is made of a material having a low dielectric constant (dielectric constant of about 3.9 or less) as compared with a silicon oxide film formed by a CVD (Chemical Vapor Deposition) method. Alternatively, an insulating film mainly containing silicon oxide formed by a coating method can be exemplified. By using such a low dielectric constant material as the interlayer insulating film 9, high-speed circuit operation can be realized. Further, the wiring M1C is electrically connected to the n-type semiconductor region 6 or the p-type semiconductor region formed on the main surface of the substrate 1 through the plug 12 formed in the contact hole 11 opened in the interlayer insulating film 8. And a reference potential (fixed potential) is supplied.

  An interlayer insulating film 13 is deposited on the first wiring layer. By embedding a wiring groove 14 formed in the interlayer insulating film 13 and a contact hole 15 opened below the wiring groove 14 and reaching the lower wiring with copper or a copper alloy, wiring (first wiring) M2A, wiring ( A first wiring) M2B and a wiring M2C are formed, and a second wiring layer (first wiring layer) is formed by these wirings. These wirings M2A, M2B, and M2C are connected to the wirings M1A, M1B, and M1C, respectively. The interlayer insulating film 13 is formed of a material having a lower dielectric constant than the silicon oxide film formed by the CVD method, similarly to the interlayer insulating film 9. Further, on the second wiring layer, the same interlayer insulating film 16, wiring groove 17, contact hole 18, wiring (first wiring) M3A, wiring (first wiring) as the second wiring layer are formed. ) The third wiring layer (first wiring layer) is formed by forming M3B and wiring M3C, and the second and third layers are formed on the third wiring layer. By forming the same interlayer insulating film 19, wiring trench 20, contact hole 21, wiring (second wiring) M4A, wiring (second wiring) M4B and wiring M4C as the wiring layer, the fourth layer wiring A layer (second wiring layer) is formed. The wirings M4A, M4B, and M4C are formed with a wiring width larger than that of the lower wirings M1A, M1B, M2A, M2B, M3A, and M3B. This is because the fourth wiring layer is the same as the lower wiring layer. The reason for this is that the wiring is not densely packed and that the wiring through which a large current flows, such as a power supply wiring, is included, so that the wiring width is increased to reduce the resistance value. Further, the wirings M1A, M1B, M2A, M2B, M3A, and M3B have the same planar pattern (see FIG. 1) having a planar comb-like pattern, and the comb-like patterns are different in the same wiring layer. Is arranged.

  The wirings M1A, M2A, M3A, and M4A are connected to each other and are formed to be upper or lower. Further, the wirings M1B, M2B, M3B, and M4B are connected to each other and are formed to be upper or lower. That is, the wiring M1A, M2A, M3A, M4A is one of the capacitive electrodes, the wiring M1B, M2B, M3B, M4B is the other of the capacitive electrodes, and the fringe capacitance has the interlayer insulating films 9, 13, 16, 19 as the capacitive insulating films. Is formed. In the present embodiment, the AC voltage can be applied to the wirings M1A, M1B, M2A, M2B, M3A, M3B, M4A, and M4B. In addition, the wirings (third wirings) M1C, M2C, M3C, and M4C are connected to each other and formed to be upper or lower, respectively, supplied with a reference potential, and in a plane, the wirings M1A, M1B, M2A, M2B, The pattern surrounds M3A, M3B, M4A, and M4B. That is, the wirings M1C, M2C, M3C, and M4C have a structure in which the fringe capacitance formed by the wirings M1A, M1B, M2A, M2B, M3A, M3B, M4A, and M4B is electrically shielded.

  The wirings M1C, M2C, M3C, and M4C may be dummy wirings (fifth wirings) that are not electrically connected to the reference potential (fixed potential) and do not function as a circuit. This is at the outermost periphery of the plane when a copper film or a copper alloy film is embedded in the wiring groove formed in the interlayer insulating film and the copper film or the copper alloy film outside the wiring groove is removed by a CMP (Chemical Mechanical Polishing) method. This is because the wiring may be reduced in the height direction. If there is a wiring that forms fringe capacitance on the outermost periphery of the plane, there is a concern that the capacitance value may decrease due to such a reduction, so by arranging dummy wiring on the outermost periphery of the plane, the fringe capacitance is reduced. It becomes possible to prevent.

  The arrangement pitch LP of the wirings M1A, M1B, M2A, M2B, M3A, M3B, M4A, and M4B is matched to the arrangement pitch of the wirings M4A and M4B having the largest wiring width among these wirings. The distance L1 between adjacent wirings of the wirings M1A, M1B, M2A, M2B, M3A, and M3B is larger than the wiring width LW of the wirings M1A, M1B, M2A, M2B, M3A, and M3B, and is 1.3 to 3 times the minimum processing dimension. About twice, preferably about 2 to 3 times. Here, the minimum processing dimension in this embodiment refers to the minimum dimension of a wiring pattern that can be transferred to a substrate by a photolithography technique. As the processing accuracy between these wirings and the wirings approaches the minimum processing size, a manufacturing error relative to the minimum processing size and the design size increases. For this reason, as shown in this embodiment, it is possible to suppress a relative manufacturing error with respect to the minimum processing dimension and the design dimension by widely separating adjacent wirings. Can be reduced. As a result, it is possible to prevent the occurrence of a problem that the communication distance changes in the non-contact IC card having the same type of chip. On the other hand, if the increase in the variation of the fringe capacitance value to be formed is allowed within a predetermined value, it is possible to finely process the wiring and the wiring within the allowable range. As a result, the distance between the capacitive electrodes and the thickness of the capacitive electrode can be reduced, so that a large fringe capacitance value per unit area can be secured.

  As described above, in the present embodiment, the distance L1 between adjacent wires of the wires M1A, M1B, M2A, M2B, M3A, and M3B is about 1.3 to 3 times, preferably 2 to 3 times the minimum processing dimension. Although illustrated as a degree, this value is the same regardless of the actual value of the minimum feature size. This is because the actual manufacturing error value also increases / decreases as the minimum processing dimension increases / decreases, so that the relative manufacturing error with respect to the minimum processing dimension and the design dimension does not substantially change.

  The capacitance value of the fringe capacitance is determined by the opposing areas of the two capacitance electrodes. Two capacitance electrodes, namely, the distance between the wirings M1A, M2A, M3A and the wirings M1B, M2B, M3B, and the opposing length of the wirings M1A, M2A, M3A and the wirings M1B, M2B, M3B The facing area of the capacitive electrode is determined, and the capacitance value is also determined. Therefore, in the present embodiment, the dimensions L2, L3, and L3 in the wirings M1A, M1B, M2A, M2B, M3A, and M3B are set so as to obtain a desired capacitance value in consideration of the variation (manufacturing error) of the fringe capacitance value. The dimension L6 of L4, L5 and the contact holes 15, 18, 21 is determined.

  Here, FIG. 3 shows that the wiring width LW (see FIGS. 1 and 2) of the wirings M1A, M1B, M2A, M2B, M3A, and M3B is 0.14 μm in the minimum processing dimension and the applied voltage is 0V. The relationship between the distance L1 between adjacent wirings of the wirings M1A, M1B, M2A, M2B, M3A, and M3B and the fringe capacitance value of the chip is shown, and a plurality of chips and a TEG (Test Element Group) are formed 1 A median value in TEG of a single wafer and a value of 3σ when the variation between chips is represented by σ are shown. FIG. 4 shows the measurement result shown in FIG. 3 in another form, and the value obtained by dividing 6σ by the median and the distance between adjacent wirings of the wirings M1A, M1B, M2A, M2B, M3A, and M3B. The relationship with L1 is shown. 3 and 4 show the measurement results for two wafers. Further, FIG. 5 shows that in a single wafer in which a plurality of chips are formed, the wiring width LW of the wirings M1A, M1B, M2A, M2B, M3A, and M3B is 0.14 μm as the minimum processing dimension, and the wirings M1A, M1B, The fringe capacitance value of each chip when the distance L1 between adjacent wirings of M2A, M2B, M3A, and M3B is 0.42 μm (three times the wiring width LW) is shown as a wafer map. The value is 0.0436 fF / μm, and 3σ is 0.0020. In the results shown in FIG. 5, the chips whose fringe capacity is larger than the median value in the wafer by σ or more are indicated by hatching. In the results shown in FIG. 5, there was no chip whose fringe capacity was smaller than the median value in the wafer by σ or more.

  As shown in FIGS. 3 to 5, the distance L1 between adjacent wirings of the wirings M1A, M1B, M2A, M2B, M3A, and M3B described above is about 1.3 to 3 times, preferably 2 times to the minimum processing dimension. The effect of about 3 times can also be confirmed from the experimental results. That is, by widely separating the adjacent wirings, it becomes possible to suppress a relative manufacturing error with respect to the minimum processing dimension and the design dimension, so that the variation in the fringe capacitance value between chips can be reduced. Note that if the distance L1 between adjacent wirings of the wirings M1A, M1B, M2A, M2B, M3A, and M3B is made larger than about three times the minimum processing size, the variation in the fringe capacitance value between chips can be reduced, while the size of the chip is large. There is a risk that Therefore, the upper limit is preferably about 3 times as described above.

  6 and 7 show the variation in capacitance values between the first layer wiring M1A and the wiring M1B in the wafer, and the distance L1 between the adjacent wiring M1A and the wiring M1B. Is set to a value smaller than about 1.5 to 3 times the minimum processing dimension in order to make the variation of the capacitance value become apparent. FIG. 6 shows variations in capacitance values when the distance L1 between the adjacent wiring M1A and the wiring M1B is 0.12 μm, 0.13 μm, 0.14 μm, 0.15 μm, and 0.16 μm. 7 is a wafer map showing variations in capacitance values when the distance between adjacent wirings M1A and M1B is 0.12 μm. FIGS. 8 and 9 show the variation of the capacitance value between the second layer wiring M2A and the wiring M2B. The distance L1 between the adjacent wiring M2A and the wiring M2B is as follows. In order to make the variation of the capacitance value manifest, the value is set to a value smaller than about 1.3 to 3 times the minimum processing dimension. FIG. 8 shows variation in capacitance value when the distance L1 between the adjacent wiring M2A and wiring M2B is 0.14 μm, 0.16 μm, and 0.18 μm, and FIG. 9 shows the variation in capacitance value. It is shown as a wafer map. As shown in FIGS. 6 to 9, in the same wiring layer, the capacitance value is smaller at the center of the wafer and larger at the outer periphery.

  FIG. 10 is an explanatory diagram showing a layout of circuit blocks in a chip in which the fringe capacitance is formed.

  As shown in FIG. 10, the chip CHP in which the fringe capacitance is formed includes, for example, a high frequency analog circuit RFC, a ROM circuit MC1, a logic circuit LGC, a RAM circuit MC2, a nonvolatile memory circuit EMC, a power supply as a plurality of circuit blocks. A voltage circuit VDC, a reference voltage circuit VSC, a power switch circuit VDSC, input / output circuits IOC1, IOC2 and the like are included.

  The high frequency analog circuit RFC includes a regulator circuit, a detector circuit, a resonance circuit for amplifying a voltage generated by electromagnetic induction, and the like, and the fringe capacitor FC is included in the resonance circuit. An antenna (not shown) connected to the chip CHP serves as a coil to cause electromagnetic induction, and the antenna and the fringe capacitor form a resonance circuit. Although there is a concern about the electromagnetic influence on the operation of other circuits due to the resonance operation of the resonance circuit, as described above, the wirings M1A, M1B, M2A, M2B, M3A, M3B, M4A, and M4B, which are fringe capacitors, have a reference potential. The structure is surrounded by wirings M1C, M2C, M3C, and M4C electrically connected to (fixed potential), and the fringe capacitance is electrically shielded (see FIG. 2). Therefore, it is possible to prevent an electromagnetic influence on the operation of other circuits due to the resonance operation of the resonance circuit. In addition, when the distance between the capacitor electrodes is set so that the electric field between the capacitor electrodes of the fringe capacitor FC becomes a large value, for example, about 1.5 MV / cm, other circuit due to the resonance operation of the resonance circuit in particular. There is a concern about the electromagnetic influence on the operation. Therefore, as shown in FIG. 10, by arranging the fringe capacitor FC as close to the outer periphery of the chip CHP as possible and away from other circuit blocks, the resonance operation of the resonance circuit including the fringe capacitor FC becomes the operation of the other circuit block. Interference can be prevented.

  Further, as described above, the interlayer insulating films 9, 13, 16, and 19 are made of a low dielectric constant material having a lower dielectric constant than the silicon oxide film formed by the CVD method, for example, silicon oxide formed by the coating method. It is formed from an insulating film or the like containing as a main component. Such a low dielectric constant material is likely to generate a leakage current as compared with a silicon oxide film formed by a CVD method. Therefore, if the distance L1 between the adjacent wiring M1A and the wiring M1B is too small, the low dielectric constant material is adjacent to it. There is a concern that a current leaks between the wiring M1A and the wiring M1B, and the function does not function as a fringe capacitor. However, in this embodiment, as described above, the distance L1 between adjacent wirings of the wirings M1A, M1B, M2A, M2B, M3A, and M3B is larger than the wiring width LW of the wirings M1A, M1B, M2A, M2B, M3A, and M3B. In addition, the minimum processing dimension is about 1.3 to 3 times, preferably about 2 to 3 times. Accordingly, the adjacent wiring M1A and the wiring M1B can be sufficiently separated from each other, so that it is possible to prevent the occurrence of a problem that current leaks between the adjacent wiring M1A and the wiring M1B.

  Further, as described above, in the present embodiment, the dummy element isolation region 5A and the dummy gate electrode 7 are arranged on the main surface of the substrate 1, so that the depressions on the surfaces of the interlayer insulating films 9, 13, 16, and 19 are obtained. Is prevented. Thereby, the dimensional accuracy and position of the wirings M1A, M1B, M2A, M2B, M3A, M3B, M4A, and M4B formed in these interlayer insulating films 9, 13, 16, and 19, especially the dimensional accuracy and placement in the height direction. Since the position can be improved, it is possible to prevent an error that occurs in the capacitance value of the fringe capacitance formed from these wirings M1A, M1B, M2A, M2B, M3A, M3B, M4A, and M4B, particularly a problem that the capacitance value becomes small.

(Embodiment 2)
FIG. 11 is a fragmentary cross-sectional view of the semiconductor device according to the second embodiment.

  The semiconductor device of the second embodiment is a chip included in a non-contact type IC card as in the first embodiment, and the chip is an n-type semiconductor region 6 formed on the substrate 1 or a p-type. The capacitor C1 has a semiconductor region and the dummy gate electrode 7 as a capacitor electrode and a gate insulating film 7A under the dummy gate electrode 7 as a capacitor insulating film. The capacitor C1 is used, for example, in a filter circuit in a PLL (Phase-Locked Loop) circuit. In addition, a wiring M1C electrically connected to a reference potential (fixed potential) extends on the capacitor C1. Other structures are almost the same as those of the first embodiment.

  In the second embodiment, the fringe capacitance formed from the wirings M2A, M2B, M3A, M3B, M4A, and M4B described in the first embodiment is arranged on the capacitor C1. However, since the wiring M1C extends on the capacitor C1 and the two capacitors are electromagnetically shielded, the wirings M1A and M1B do not contribute to the formation of the fringe capacitance on the capacitor C1.

  As described above, the area of the chip can be reduced by providing a structure in which two capacitors overlap in a plane. According to the experiments conducted by the present inventors, the chip area could be reduced by about 20% by adopting the above structure.

  According to the second embodiment as described above, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
In the first embodiment, the case where the fringe capacitor is used as the capacitor of the resonance circuit has been described. In the third embodiment, the case where the fringe capacitor is used in the sample hold circuit in the analog-digital converter will be described.

  In providing a capacitor in the sample and hold circuit, in addition to the fringe capacitor, a wiring (first layer wiring M1A or wiring M1B) and another metal film M1D (for example, a titanium film or a titanium nitride film) are used as capacitive electrodes, An example is the use of a capacitor C2 formed by disposing a capacitor insulating film 13A made of a thin silicon nitride film or the like between these two capacitor electrodes (see FIG. 12). The present inventor has examined the case where such a capacitor C2 is used and the case where a fringe capacitor formed from the wirings M1A, M1B, M2A, M2B, M3A, M3B, M4A, and M4B is used. It was found that the chip area can be reduced by about 50% compared to the case where the capacitor C2 is used. That is, the chip can be miniaturized by using the fringe capacitor in the sample and hold circuit in the analog-digital converter.

  According to the third embodiment as described above, the same effect as in the first embodiment can be obtained.

(Embodiment 4)
FIG. 13 is a fragmentary cross-sectional view of the semiconductor device of the fourth embodiment.

  As shown in FIG. 13, the semiconductor device of the fourth embodiment has a structure substantially similar to that of the first embodiment. Although not described in the first embodiment, a wiring (third wiring layer) that forms the uppermost wiring layer (third wiring layer) is formed on the fourth wiring layer via an insulating film 22 such as a silicon oxide film. Fourth wiring) 23 is formed. A part of the wiring 23 becomes a bonding pad and is electrically connected to an antenna outside the chip by a bonding wire such as gold. Instead of connecting the chip and the antenna by the bonding wire, a bump electrode is formed on the wiring 23 serving as a bonding pad and the bump electrode is connected to the antenna. Good. A silicon nitride film 24 and a silicon oxide film 25 are sequentially formed on the uppermost wiring layer including the wiring 23 to cover the wiring 23. These silicon nitride film 24 and silicon oxide film 25 function as protective films that prevent moisture and impurities from entering from the outside and suppress the transmission of α rays. In addition, on the wiring 23 serving as a bonding pad, an opening (not shown) reaching the wiring 23 is formed in the silicon nitride film 24 and the silicon oxide film 25.

  Since the wiring 23 forming the uppermost wiring layer is mainly used as a bonding pad for electrically connecting the chip to the outside, the uppermost wiring layer is a bonding pad. There are many areas that are gaps between the wirings 23 where the wirings 23 do not exist. Therefore, in the fourth embodiment, wirings (fourth wirings) 23A and 23B that do not serve as bonding pads are arranged in the gap, and the capacitor C3 is formed by these wirings 23. The wiring 23 forming the capacitor C3 is appropriately electrically connected to the wirings M1A, M1B, M2A, M2B, M3A, M3B, M4A, and M4B described in the first embodiment, thereby increasing the chip area. Without increasing the fringe capacitance value in the chip.

  According to the fourth embodiment as described above, the same effect as in the first embodiment can be obtained.

(Embodiment 5)
FIG. 14 is a cross-sectional view of a main part of the semiconductor device according to the fifth embodiment.

  As shown in FIG. 14, in the fifth embodiment, wirings M1A, M1B, M1C, M2A, M2B, M2C, M3A, M3B, M3C, M4A, M4B, and M4C are formed using aluminum or an aluminum alloy as a main conductive layer. ing. When these wirings are formed using aluminum as the main conductive layer, the wiring is formed by patterning an aluminum film or an aluminum alloy film deposited on the interlayer insulating film by etching. Further, contact holes 15, 18, and 21 are formed in the interlayer insulating films 9, 13, and 16, and wirings M1A and M1B are connected via plugs 15A, 18A, and 21A formed in the contact holes 15, 18, and 21, respectively. , M1C, M2A, M2B, M2C, M3A, M3B, M3C, M4A, M4B, and M4C are electrically connected to the upper or lower wiring. The plugs 15A, 18A, 21A are formed by, for example, embedding a tungsten film in the contact holes 15, 18, 21.

  Even when the wirings M1A, M1B, M1C, M2A, M2B, M2C, M3A, M3B, M3C, M4A, M4B, and M4C are made of aluminum or an aluminum alloy as the main conductive layer, the wirings M1A, M1B, M2A, and M2B are used. , M3A, M3B adjacent wiring distance L1 (see FIG. 1 and FIG. 2) is larger than wiring width LW (see FIG. 1 and FIG. 2) of wiring M1A, M1B, M2A, M2B, M3A, M3B, and minimum processing The size is about 1.3 to 3 times, preferably about 2 to 3 times the size. As a result, it becomes possible to suppress a relative manufacturing error with respect to the minimum processing dimension and the design dimension, so that variation in fringe capacitance value between chips can be reduced, and a non-contact IC card having the same type of chip. Therefore, it is possible to prevent the occurrence of problems such as the communication distance changing.

  According to the fifth embodiment as described above, the same effect as in the first embodiment can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above embodiment, the chip included in the non-contact type IC card has been described as an example. However, the same technique is applied to a chip included in the non-contact type electronic tag in addition to the IC card. be able to.

  The semiconductor device of the present invention includes electronic money, credit card, mobile phone, pay satellite broadcasting receiver, identification card, license, insurance card, electronic medical record, electronic ticket, etc., finance, medical care, transportation, transportation and education It can be used as various storage media.

1 is a main part plan view of a semiconductor device according to a first embodiment of the present invention; It is principal part sectional drawing of the semiconductor device which is Embodiment 1 of this invention. It is explanatory drawing which showed the relationship between the distance between adjacent wiring in the chip | tip which the semiconductor device which is Embodiment 1 of this invention has, and the fringe capacitance value of a chip | tip. It is explanatory drawing which showed the relationship between the distance between adjacent wiring in the chip | tip which the semiconductor device which is Embodiment 1 of this invention has, and the fringe capacitance value of a chip | tip. It is explanatory drawing which showed the fringe capacity value of the chip | tip which the semiconductor device which is Embodiment 1 of this invention has as a wafer map in a manufacturing process. It is explanatory drawing which shows the dispersion | variation in the capacitance value between the wiring of the 1st layer of the chip | tip which the semiconductor device which is Embodiment 1 of this invention has. It is explanatory drawing which shows the dispersion | variation in the wafer in the capacitance value between the wiring of the 1st layer of the chip | tip which the semiconductor device which is Embodiment 1 of this invention has. It is explanatory drawing which shows the dispersion | variation in the capacitance value between the wiring of the 2nd layer of the chip | tip which the semiconductor device which is Embodiment 1 of this invention has. It is explanatory drawing which shows the dispersion | variation in the wafer in the capacitance value between the wiring of the 2nd layer of the chip | tip which the semiconductor device which is Embodiment 1 of this invention has. It is explanatory drawing which shows the layout of the circuit block in the chip | tip which the semiconductor device which is Embodiment 1 of this invention has. It is principal part sectional drawing of the semiconductor device which is Embodiment 2 of this invention. It is sectional drawing explaining the capacitive structure compared with the capacitive structure in the semiconductor device which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor device which is Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor device which is Embodiment 4 of this invention.

Explanation of symbols

1 substrate 2 n-type isolation layer 3 p-type well 4 n-type well 5 element isolation region 5A dummy element isolation region 6 n-type semiconductor region 7 dummy gate electrode (first gate electrode)
7A Gate insulating film 8 Interlayer insulating film 9 Interlayer insulating film 10 Wiring groove 11 Contact hole 12 Plug 13 Interlayer insulating film 13A Capacitance insulating film 14 Wiring groove 15 Contact hole 15A Plug 16 Interlayer insulating film 17 Wiring groove 18 Contact hole 18A Plug 19 Interlayer Insulating film 20 Wiring groove 21 Contact hole 21A Plug 22 Insulating film 23, 23A, 23B Wiring (fourth wiring)
24 Silicon nitride film 25 Silicon oxide film C1 capacity C2 capacity C3 capacity CHP chip EMC nonvolatile memory circuit FC fringe capacity IOC1, IOC2 I / O circuit LGC logic circuits M1A, M1B, M2A, M2B, M3A, M3B wiring (first wiring) )
M1C, M2C, M3C, M4C wiring (third wiring)
M1D metal film M4A, M4B wiring (second wiring)
MC1 ROM circuit MC2 RAM circuit RFC High frequency analog circuit VDC Power supply voltage circuit VDSC Power supply switch circuit VSC Reference voltage circuit

Claims (8)

A semiconductor device having one or more first wiring layers formed on a main surface of a semiconductor substrate,
The first wiring layer forms a capacitor;
Each of the plurality of first wirings forming the first wiring layer serves as a pair of capacitance electrodes of the capacitance, and the distance between the adjacent first wirings is 1.3 to 3 times the minimum processing dimension. The capacity value of the capacity is determined under the conditions
The facing length of the pair of first wirings serving as the pair of capacitive electrodes is determined based on the manufacturing error of the capacitance, the capacitance value, and the distance between the adjacent first wirings. A semiconductor device. The semiconductor device according to claim 1,
The semiconductor device, wherein the distance between the adjacent first wirings is determined so that an electric field between the adjacent first wirings is 1.5 MV / cm or less. The semiconductor device according to claim 2,
The semiconductor device is characterized in that the capacitor is included in an analog circuit in a circuit to which power is supplied without contact. The semiconductor device according to claim 1,
A second wiring layer that forms the capacitance together with the first wiring layer is formed on the first wiring layer;
The plurality of second wirings included in the second wiring layer have a wiring width larger than that of the first wiring and are arranged at the same arrangement pitch as the plurality of first wirings. A semiconductor device. The semiconductor device according to claim 1,
A third wiring that surrounds the first wiring layer in a plane;
The semiconductor device is characterized in that the third wiring is electrically connected to a reference potential. The semiconductor device according to claim 5.
A plurality of circuit blocks are defined for each function on the semiconductor substrate,
The semiconductor device, wherein the first wiring layer and the third wiring are included in one of the plurality of circuit blocks. The semiconductor device according to claim 1,
A third wiring layer serving as the uppermost wiring layer is formed on the first wiring layer;
A part of a plurality of fourth wirings included in the third wiring layer is used for electrical connection with an external circuit and forms the capacitor. The semiconductor device according to claim 1,
In the region of the first wiring layer in which the capacitance is formed, the semiconductor substrate, an element isolation region formed on the main surface of the semiconductor substrate, an element isolation region, and A first gate electrode that is not electrically connected to the first wiring;
5. A semiconductor device, wherein a fifth wiring that is not electrically connected to the plurality of first wirings is formed in the first wiring layer.

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