JP2005072233A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor technology which can reduce an apparatus area of a semiconductor device having a capacity element. <P>SOLUTION: The semiconductor device includes the capacity element 7 using a line capacity of a semiconductor line electrically insulated with conductive element 3 directly above the capacity element 3 including two-layer polysilicon layers 3a, 3b and an insulating film 3c inserted among them. Thus, since the capacity elements 3, 7 are accumulated mutually, the apparatus area is reducible. Further, since the capacity elements 3 and 7 are insulated electrically mutually, the capacity element 3 with comparatively small error of the capacity value, and the capacity element 7 with comparatively large error of the capacity value, can be used properly for every use. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a capacitive element.

  In recent years, with the development of process technology for semiconductor devices including integrated circuits, transistors and wiring structures have been miniaturized. With this miniaturization, it is possible to reduce the chip size or to increase the functionality and functionality of the chip in the same area. However, these are mainly intended for digital circuits in integrated circuits, and are often difficult to realize with analog circuits. The reason is that even if the process technology can cope with miniaturization, it is difficult to miniaturize the element itself in order to maintain the characteristics of the passive element such as the capacitor element, inductor element, or resistance element used in the analog circuit. is there.

  As a capacitor element of an analog circuit, a capacitor element (hereinafter referred to as “polysilicon capacitor element”) composed of two polysilicon layers and an insulating film sandwiched between them, two metal layers, There is an MIM (Metal Insulator Metal) capacitive element composed of an insulating film sandwiched between them. In addition, there is a structure in which a part of the structure of the MOS transistor is used as a capacitive element. Specifically, a gate capacitance composed of a gate electrode of a MOS transistor, a source / drain region, and a gate insulating film sandwiched between them is used as a capacitive element.

  Since these capacitor elements have a structure in which a lower electrode, a dielectric film, and an upper electrode are laminated in this order, generally, when the dependency on bias voltage does not become a problem, additional capacitance is required when forming these capacitors. Masks and processes are required.

  Capacitance elements employed in analog circuits include what are called “fringe capacitance elements” and “interdigital capacitance elements” (hereinafter collectively referred to as “fringe capacitance elements”). A fringe capacitive element uses the lateral capacitance between two conductor lines formed in the same wiring layer of a semiconductor device, and the distance between the lines decreases as the process becomes finer. A relatively large capacitance value can be obtained. In addition, since the structure uses a parasitic element, no additional mask and process are required at the time of formation.

  The fringe capacitive element is described in Patent Documents 1 to 3 and Non-Patent Documents 1 and 2. Moreover, the inductor elements of the analog circuit are described in Patent Documents 3 to 5.

JP-A-7-283075 JP-A-7-283076 JP-A-7-202134 Japanese Patent Laid-Open No. 11-126873 JP-A-6-166904 H. Samavati et al., “Fractal Capacitors”, IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1998, p.256, 257 D. Leenaerts et al., “Circuit Design for RF Transceivers”, Kluwer Academic Publishers, p.35-37, 2001

  In a semiconductor device including a plurality of capacitive elements such as the polysilicon capacitive element as described above, or a semiconductor device including a capacitive element and an inductor element, it is difficult to reduce the device area.

  Therefore, the present invention has been made in view of the above-described problems, and an object thereof is to provide a semiconductor technology capable of reducing the device area of a semiconductor device including a capacitive element.

  According to a first semiconductor device of the present invention, a first capacitive element having two polysilicon layers and an insulating film sandwiched between them, and two conductor lines arranged in the same layer A second capacitive element using an inter-capacitance, wherein the first and second capacitive elements are stacked on top of each other and are electrically insulated from each other.

  According to a second semiconductor device of the present invention, an insulated gate structure formed on a semiconductor substrate and a gate capacitor having an impurity region formed in the upper surface of the semiconductor substrate are arranged on the same layer. A capacitive element that uses a capacitance between conductor lines, and the capacitive element is disposed immediately above the gate capacitance, and the gate capacitance and the capacitive element are electrically insulated from each other. .

  The third semiconductor device of the present invention includes a capacitive element having two polysilicon layers and an insulating film sandwiched between them, and an inductor element, wherein the capacitive element, the inductor element, Are arranged one on top of the other.

  According to the first semiconductor device of the present invention, since the first and second capacitive elements are stacked on each other, the device area is larger than the case where the first and second capacitive elements are arranged side by side in the same layer. Can be reduced. Further, since the first and second capacitive elements are electrically insulated from each other, the first capacitive element having a relatively small capacitance value error, and the second capacitive element having a relatively large capacitance value error, Can be used for different purposes.

  Further, according to the second semiconductor device of the present invention, since the capacitive element is provided immediately above the gate capacitance, the device area can be reduced as compared with the case where the gate capacitance and the capacitive element are arranged side by side in the same layer. Can be reduced. Furthermore, since the gate capacitance and the capacitive element are electrically insulated from each other, by using the gate capacitance as another capacitive element, a gate capacitance having a relatively small capacitance value error and a capacitance value error can be obtained. A relatively large capacitive element using line capacitance can be used for each application.

  Further, according to the third semiconductor device of the present invention, since the capacitive element and the inductor element are stacked on each other, the area of the device is larger than the case where the capacitive element and the inductor element are arranged side by side in the same layer. Can be reduced. Furthermore, the polysilicon layer of the capacitive element has a weak capacitive coupling with the inductor element as compared with the conductor layer made of metal, and thus it is easy to realize the designed capacitance value.

Embodiment 1 FIG.
FIG. 1 is a plan view showing the structure of the semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA in FIG. In FIG. 1, for convenience of explanation, the illustration of the interlayer insulating films 4, 8, and 9, the contact plugs 5a and 5b, and the wirings 6a and 6b in FIG. 2 is omitted. Therefore, the capacitive element 3 that should not actually be shown in the plan view is shown in FIG.

  As shown in FIGS. 1 and 2, the semiconductor device according to the first embodiment includes a semiconductor substrate 1 which is a silicon substrate, for example. On the semiconductor substrate 1, there is provided an insulating film 2 employing, for example, a silicon oxide film.

  On the insulating film 2, a capacitive element 3 which is a polysilicon capacitive element is provided. The capacitive element 3 includes two polysilicon layers 3a and 3b and an insulating film 3c sandwiched between them. The polysilicon layer 3a, the insulating film 3c, and the polysilicon layer 3b are arranged in this order from the lower layer. It is laminated on the insulating film 2. An interlayer insulating film 4 is provided on the insulating film 2 so as to cover the capacitive element 3.

  On the interlayer insulating film 4, interlayer insulating films 8 and 9 are laminated in this order from the bottom. Capacitance elements 7 are provided in the interlayer insulating films 8 and 9 and on the interlayer insulating film 9, and these capacitor elements 7 are stacked on each other via the interlayer insulating films.

  Each capacitive element 7 is a fringe capacitive element, and is provided immediately above the capacitive element 3 while being electrically insulated from the capacitive element 3. Each capacitive element 7 is composed of a pair of comb-shaped conductor plates 17 and 27, and each comb-shaped conductor plate 17 and 27 is composed of, for example, aluminum. The comb-shaped conductor plates 17 and 27 of the capacitor element 7 in the interlayer insulating film 8 are provided on the interlayer insulating film 4, and the comb-shaped conductor plates 17 and 27 of the capacitor element 7 in the interlayer insulating film 9 are on the interlayer insulating film 8. Is provided.

  The comb-shaped conductor plate 17 includes a single linear conductor line 17a and a plurality of linear conductor lines 17b. The conductor lines 17b are arranged at predetermined intervals in a direction perpendicular to the longitudinal direction thereof, and one end in the longitudinal direction of the conductor line 17b is connected to one end in the short direction of the conductor line 17a. Has been. In other words, the plurality of conductor wires 17b extend from one end in the short direction of the conductor wire 17a to the outside at a predetermined distance from each other.

  Similarly, the comb-shaped conductor plate 27 includes a single linear conductor line 27a and a plurality of linear conductor lines 27b. The conductor lines 27b are arranged at predetermined intervals in a direction perpendicular to the longitudinal direction thereof, and one end in the longitudinal direction of the conductor line 27b is connected to one end in the short direction of the conductor line 27a. Has been.

  The comb-shaped conductor plates 17 and 27 are arranged so that the conductor wires 17b and 27b are alternately opposed to each other in parallel. Then, the line capacity formed between the conductor lines 17b and 27b facing each other, the line capacity formed in the area where the conductor line 17a and the conductor line 27b face each other, the conductor line 27a and the conductor line The total sum of the capacitances between the lines formed in the region facing 17 b is the total capacitance of the capacitive element 7.

  Thus, the capacitive element 7 is an element that uses the line capacitance in the lateral direction of two conductor lines facing each other formed in the same layer.

  The comb-shaped conductor plate 17 in the capacitor element 7 in the interlayer insulating film 8 and the comb-shaped conductor plate 17 in the capacitor element 7 in the interlayer insulating film 9 are electrically connected to each other by the contact plug 10 provided in the interlayer insulating film 8. The comb-shaped conductor plate 17 in the capacitor element 7 in the interlayer insulating film 9 and the comb-shaped conductor plate 17 in the capacitor element 7 on the interlayer insulating film 9 are contact plugs provided in the interlayer insulating film 9. 10 are electrically connected to each other.

  Further, the comb-shaped conductor plate 27 in the capacitor element 7 in the interlayer insulating film 8 and the comb-shaped conductor plate 27 in the capacitor element 7 in the interlayer insulating film 9 are mutually connected by the contact plug 11 provided in the interlayer insulating film 8. The comb-shaped conductor plate 27 in the capacitor element 7 in the interlayer insulating film 9 and the comb-shaped conductor plate 27 in the capacitor element 7 on the interlayer insulating film 9 are electrically connected and provided in the interlayer insulating film 9. The contact plugs 11 are electrically connected to each other.

  In the interlayer insulating film 8, wirings 6a and 6b are also provided. The wiring 6 a is electrically connected to the polysilicon layer 3 a of the capacitive element 3 by a contact plug 5 a provided in the interlayer insulating film 4, and the wiring 6 b is a contact plug 5 b provided in the interlayer insulating film 4. Are electrically connected to the polysilicon layer 3b of the capacitive element 3. The wirings 5a and 5b are made of aluminum, for example.

  Each layer in which the capacitor element 7 is provided is a wiring layer, and not only the wirings 6a and 6b but also other wirings (not shown) are formed. For example, a wiring for electrically connecting other passive elements (not shown) such as a resistance element and an inductor element or active elements (not shown), the other passive elements, the active elements, and a capacitive element Wirings and the like that are electrically connected to each other are provided in the interlayer insulating films 8 and 9 and on the interlayer insulating film 9. The capacitive element 7 is formed simultaneously with these wirings. Therefore, no additional process occurs when the capacitor element 7 is formed.

  As described above, in the semiconductor device according to the first embodiment, since the capacitive elements 3 and 7 are arranged to be stacked on each other, the apparatus is more than the case where the capacitive elements 3 and 7 are arranged side by side in the same layer. The area can be reduced.

  Further, since the capacitive elements 3 and 7 are electrically insulated from each other, the capacitive element 3 having a relatively small capacitance value error and the capacitive element 7 having a relatively large capacitance value error are selectively used for each application. be able to. This will be specifically described below.

  In general, an error of a capacitance value in a polysilicon capacitive element such as the capacitive element 3 is about ± 10%. On the other hand, in the fringe capacitive element such as the capacitive element 7, the accuracy of the conductor width greatly affects the accuracy of the capacitance value, so that the capacitance value error is larger than the polysilicon capacitance element and is about ± 30%. .

  As described above, since the capacitance error of the polysilicon capacitance element is relatively small, the polysilicon capacitance element is generally adopted as an element that requires absolute accuracy, such as a capacitance element used for a signal filter or the like. On the other hand, a fringe capacitive element having a relatively large capacitance value error is employed as a capacitive element that does not require much absolute accuracy, such as a bypass capacitor for removing noise in a power supply line or a capacitive element in a capacitive coupling circuit. Therefore, as in the first embodiment, by electrically insulating the capacitive elements 3 and 7 from each other, they can be used properly for each application.

  In the first embodiment, since the capacitive element 7 is provided immediately above the capacitive element 3, a parasitic element with respect to the semiconductor substrate 1 is hardly generated in the capacitive element 7. Therefore, the parasitic elements with respect to the semiconductor substrate 1 are mainly generated only in the lower capacitive element 3.

  In the first embodiment, since the capacitive element 3 is not formed using the wiring layer, the capacitive element 3 does not interfere with the formation of the capacitive element 7 provided in the wiring layer.

Embodiment 2. FIG.
FIG. 3 is a sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention. In the first embodiment described above, the capacitive element 3 is provided immediately below the capacitive element 7. However, in the second embodiment, a plurality of MOS transistors 40 are provided immediately below the capacitive element 7. The cross-sectional structure of the capacitive element 7 shown in FIG. 3 is a cross-sectional composition at a position corresponding to the arrow AA in FIG.

  As shown in FIG. 3, the semiconductor substrate 1 is provided with a plurality of MOS transistors 40. An element isolation insulating film 30 made of, for example, a silicon oxide film is formed on the semiconductor substrate 1, and a well region 33 is formed in the upper surface of the semiconductor substrate 1.

  In the upper surface of the semiconductor substrate 1, more specifically, in the upper surface of the well region 33 provided in the semiconductor substrate 1, a plurality of source / drain regions 41 are formed at a predetermined distance from each other. Each source / drain region 41 is, for example, an n-type impurity region. An insulated gate structure comprising a gate insulating film 42 and a gate electrode 43 on a well region 33 sandwiched between adjacent source / drain regions 41 and on a part of each of the adjacent source / drain regions 41. 46 is provided. The gate insulating film 42 and the gate electrode 43 are stacked in this order from the semiconductor substrate 1 side. Each MOS transistor 40 includes a pair of adjacent source / drain regions 41 and an insulated gate structure 46.

  In the second embodiment, the MOS transistor 40 is not used as a transistor but a part thereof is used as a capacitive element. Specifically, a gate capacitance 45 including a source / drain region 41, a gate electrode 43, and a gate insulating film 42 sandwiched between them is used as a capacitive element. That is, by using the source / drain region 41 as the lower electrode, the gate electrode 43 as the upper electrode, and the gate insulating film 42 sandwiched between them as the dielectric film, the gate capacitance 45 is used as a capacitive element. As described above, the gate capacitance 45 having the source / drain region 41 and the insulated gate structure 46 has a capacitance value error of about ± 10% and a relatively capacitance value error, similar to the capacitive element 3 of the first embodiment. Is small. Therefore, for example, it can be used as a capacitive element of a signal filter.

  An interlayer insulating film 34 is formed on the semiconductor substrate 1 and the element isolation structure so as to cover the insulated gate structure 46. On the interlayer insulating film 34, interlayer insulating films 38 and 39 are stacked in this order from the bottom. Capacitance elements 7 are provided in the interlayer insulating films 38 and 39 and on the interlayer insulating film 39, and these capacitor elements 7 are stacked on each other via the interlayer insulating films as in the first embodiment. It has been.

  Each capacitor element 7 is electrically insulated from each gate capacitor 45. Each capacitive element 7 is disposed immediately above each gate capacitance 45. The comb-shaped conductor plate 17 in the capacitor element 7 in the interlayer insulating film 38 and the comb-shaped conductor plate 17 in the capacitor element 7 in the interlayer insulating film 39 are electrically connected to each other by the contact plug 35 provided in the interlayer insulating film 38. The comb-shaped conductor plate 17 in the capacitor element 7 in the interlayer insulating film 39 and the comb-shaped conductor plate 17 in the capacitor element 7 on the interlayer insulating film 39 are contact plugs provided in the interlayer insulating film 39. 35 are electrically connected to each other.

  Further, the comb-shaped conductor plate 27 in the capacitor element 7 in the interlayer insulating film 38 and the comb-shaped conductor plate 27 in the capacitor element 7 in the interlayer insulating film 39 are mutually connected by contact plugs 36 provided in the interlayer insulating film 38. The comb-shaped conductor plate 27 in the capacitor element 7 in the interlayer insulating film 39 and the comb-shaped conductor plate 27 in the capacitor element 7 on the interlayer insulating film 39 are provided in the interlayer insulating film 39. The contact plugs 36 are electrically connected to each other.

  As in the first embodiment, each layer provided with the capacitor 7 is a wiring layer, and wiring (not shown) is also formed in the wiring layer. For example, wiring for electrically connecting other passive elements (not shown) such as resistance elements and inductor elements, or active elements (not shown), the other passive elements and the active elements, and the capacitive element 7 Wiring or the like for electrically connecting the two to each other is provided in the interlayer insulating films 38 and 39 or on the interlayer insulating film 39. The capacitive element 7 is formed simultaneously with these wirings.

  The interlayer insulating film 38 is also provided with a wiring (not shown) electrically connected to the gate electrode 43 of the MOS transistor 40 and the source / drain region 41. The insulated gate structure 46 and the source / drain region 41 extend to a region where the capacitive element 7 is not located immediately above in the direction perpendicular to the paper surface of FIG. 3, and these wirings are provided in the interlayer insulating film 34. A contact plug (not shown) is electrically connected to the extended portion of the gate electrode 43 and the source / drain region 41.

  Thus, in the semiconductor device according to the second embodiment, since the capacitive element 7 is provided immediately above the gate capacitance 45, the gate capacitance 45 and the capacitive element 7 are arranged side by side in the same layer. The device area can be reduced.

  Furthermore, since the gate capacitor 45 and the capacitor element 7 are electrically insulated from each other, the gate capacitor 45 can be used as a capacitor element different from the capacitor element 7 as in the second embodiment, thereby The gate capacitance 45 having a relatively small value error and the capacitor element 7 having a relatively large capacitance value error can be used for each application as in the first embodiment.

  In the second embodiment, since the gate capacitor 45 is not formed by using the wiring layer, the gate capacitor 45 does not interfere with the formation of the capacitor element 7 provided in the wiring layer.

  Further, an impurity region having the same conductivity type as that of the source / drain region 41 is formed in the upper surface of the well region 33 between the adjacent source / drain regions 41, and the adjacent source / drain regions 41 are arranged in the impurity region. May be connected to each other. In this case, since not only the source / drain region 41 but also a newly provided impurity region can be used as the lower electrode, the gate capacitance 45 includes the impurity region and source / drain region 41 and the gate electrode 43. And the gate insulating film 42 sandwiched between them.

Embodiment 3 FIG.
4 is a plan view showing the structure of the semiconductor device according to the third embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the line BB in FIG. In the above-described first embodiment, the capacitive element 7 is provided immediately above the capacitive element 3, but in the present third embodiment, the inductor element 50 is provided immediately above the capacitive element 3. In FIG. 4, the illustration of the interlayer insulating film 51 in FIG. 5 is omitted for convenience of explanation. Therefore, the capacitive element 3 that should not actually be shown in the plan view is shown in FIG.

  As shown in FIGS. 4 and 5, an insulating film 2 is provided on the semiconductor substrate 1, and a plurality of capacitive elements 3 are provided on the insulating film 2 so as to be separated from each other. The polysilicon layer 3a, the insulating film 3c, and the polysilicon layer 3b of each capacitive element 3 are stacked on the insulating film 2 in this order from the bottom. An interlayer insulating film 51 is provided on the insulating film 2 so as to cover each capacitive element 3.

  An inductor element 50 is provided on the interlayer insulating film 51. The inductor element 50 is a spiral inductor, for example, and is made of a conductor, for example, aluminum. The inductor element 50 is electrically insulated from each capacitor element 3 and is disposed immediately above the plurality of capacitor elements 3.

  The layer in which the inductor element 50 is provided is a wiring layer, and other wiring (not shown) is also formed in the wiring layer. For example, wiring that electrically connects other passive elements (not shown) such as resistance elements and capacitive elements, or active elements (not shown), the other passive elements and the active elements, and the inductor element 50 Wirings and the like electrically connected to each other are provided on the interlayer insulating film 51. The inductor element 50 is formed simultaneously with these wirings. Therefore, no additional process occurs when the inductor element 50 is formed.

  On the interlayer insulating film 51, wirings (not shown) that are electrically connected to the polysilicon layers 3a and 3b of the capacitive element 3 are also provided. These wirings are electrically connected to a region where the inductor element 50 is not located immediately above the polysilicon layers 3 a and 3 b by a contact plug (not shown) provided in the interlayer insulating film 51.

  As described above, in the semiconductor device according to the third embodiment, since the capacitive element 3 and the inductor element 50 are arranged to be stacked on each other, the capacitive element 3 and the inductor element 50 are arranged side by side in the same layer. The device area can be reduced as compared with the case of doing so.

  Further, since the polysilicon layers 3a and 3b of the capacitive element 3 are weak in capacitive coupling with the inductor element 50 via the interlayer insulating film 51, compared to the conductor layer made of metal, it is easy to realize the designed capacitance value. Become.

  In the third embodiment, the capacitive element 3 and the inductor element 50 are electrically insulated from each other. However, a contact plug may be provided in the interlayer insulating film 51 and connected to each other by the contact plug. good.

  In the first embodiment, a plurality of capacitive elements 3 are provided on the insulating film 2 in the same manner as in the third embodiment, and a capacitive element 7 is provided immediately above the plurality of capacitive elements 3. Also good.

It is a top view which shows the structure of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 2 of this invention. It is a top view which shows the structure of the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 3, 7 Capacitor element, 3a, 3b Polysilicon layer, 3c Insulating film, 17a, 17b, 27a, 27b Conductor line, 40 MOS transistor, 41 Source / drain region, 45 Gate capacity, 46 Insulated gate structure, 50 Inductor element.

Claims (3)

A first capacitive element having two polysilicon layers and an insulating film sandwiched between them;
A second capacitive element that utilizes the line capacitance of two conductor lines arranged in the same layer,
The semiconductor device in which the first and second capacitor elements are stacked on top of each other and are electrically insulated from each other. An insulated gate structure formed on the semiconductor substrate and a gate capacitance having an impurity region formed in the upper surface of the semiconductor substrate;
A capacitive element that uses the capacitance between two conductor wires arranged in the same layer, and
The capacitive element is disposed immediately above the gate capacitance;
The semiconductor device, wherein the gate capacitor and the capacitor are electrically insulated from each other. A capacitive element having two polysilicon layers and an insulating film sandwiched between them;
An inductor element,
The semiconductor device, wherein the capacitive element and the inductor element are stacked on top of each other.

Images