JP2006032536A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a protection circuit excellent in the bypass performance of an abnormal voltage with a small area in an integrated circuit, and to provide its manufacturing method. <P>SOLUTION: A conductive layer pattern 11 is connected with a gate electrode of an MOS element Q1, for example, wherein the impression of an abnormal voltage causes anxiety for gate breakdown. Moreover, the conductive layer pattern 11 has a connecting relation with an external connection terminal 12. The abnormal voltage caused by charge up and ESD (electro-static discharge) resulting from plasma treatment used in a manufacturing process is transmitted to the conductive layer pattern 11. Then, the conductive layer pattern 11 is formed with a gap G1 which makes only the abnormal voltage energized. The gap G1 comprises ends 11A1 and 11A2 counterposed mutually with a predetermined clearance in order that the semiconductor substrate may make only the abnormal voltage transmitted to the MOS element Q1 bypass reference potential (grounding potential). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a protection circuit for protecting a MOS transistor or the like from the influence of abnormal voltage in a semiconductor integrated circuit and a method for manufacturing the same.

  MOS transistors are susceptible to charge-up phenomena during the wafer process and external noise. The abnormal voltage is an excessive voltage that is not specified, and is likely to be generated due to a charge-up phenomenon or external noise. In the MOS transistor, when such an abnormal voltage is transmitted to the gate electrode, the gate insulating film may be damaged, resulting in dielectric breakdown.

  For example, plasma processing such as CVD, sputtering, etching, and ashing is frequently used in the wafer process. Thereby, the wiring pattern increases charging (charge accumulation). Such an abnormal voltage due to charge-up is transmitted to the gate electrode of the MOS transistor connected to the wiring pattern, and the gate insulating film underneath is damaged. Also, abnormal voltage due to external noise, so-called ESD (electrostatic discharge), is transmitted to the gate electrode of the MOS transistor connected to the wiring pattern, and the gate insulating film underneath is damaged. Concerned.

As a measure for preventing the breakdown of the gate insulating film of the MOS transistor, there is a technique of providing a protection diode or a protection MOS transistor (for example, see Patent Document 1). For example, the protection diode or the protection MOS transistor is provided in parallel to the connection path from the input / output terminal to the gate electrode of the MOS transistor. Such a protective diode or protective MOS transistor requires a relatively large area in order to disperse and bypass abnormal voltages.
JP-A-5-235344 (4th and 5th pages, FIGS. 1 to 4)

  A conventional protection diode or protection MOS transistor requires a relatively large area in a semiconductor integrated circuit. Also, it is important to control the impurity concentration in order to adjust the breakdown voltage. A large amount of MOS type transistors are included in the IC. It is difficult to connect the protection diode or the protection MOS transistor in parallel to all the MOS transistors from the viewpoint of the occupied area. Therefore, the protective diode or the protective MOS transistor is provided at a point that is easily exposed to the risk of abnormal voltage, for example, an external connection terminal such as an input / output. However, even if the protection diode or the protection MOS transistor has a small area, there is a risk of destruction due to application of an abnormal voltage. Therefore, even when the protective diode or the protective MOS transistor is provided at a critical point, the occupation area is inevitably increased.

  The present invention has been made in consideration of the above circumstances, and provides a semiconductor device having a protection circuit with a small area and excellent bypass performance of abnormal voltage in a semiconductor integrated circuit, and a method for manufacturing the same. is there.

  A semiconductor device according to the present invention comprises: a MOS type element formed on a semiconductor substrate; and a conductive layer pattern having a gap facing a tip that bypasses only an abnormal voltage to be transmitted to the MOS type element. Including.

  According to the semiconductor device of the present invention, the shape of the conductive layer pattern itself having a connection relationship with the MOS type element is devised. That is, the conductive layer pattern is provided with a gap shape with the tips facing each other in order to bypass only the abnormal voltage. Thereby, the abnormal voltage to be transmitted to the MOS type element is bypassed through the gap and does not affect the MOS type element. Since the gap is a device for the shape of the conductive layer pattern itself, it occupies a small area and contributes to high integration. Further, the gap is excellent in functional stability without being broken by an abnormal voltage.

Note that the semiconductor device according to the present invention has one of the following characteristics (a) and (b), so that a path of an abnormal voltage that occurs unexpectedly can be established more stably.
(A) The conductive layer pattern has a connection relationship with at least the gate electrode of the MOS type element on one side from the gap, and has a connection relationship with at least the semiconductor substrate on the other side from the gap.
(B) including an external connection terminal provided above the semiconductor substrate, wherein the conductive layer pattern has a connection relationship with at least the gate electrode of the MOS type element and the external connection terminal on one side from the gap; A connection relationship with at least the semiconductor substrate is provided on the other side from the gap.

  The semiconductor device according to the present invention includes an insulating film formed on a semiconductor substrate, a first wiring pattern and a second wiring pattern each having at least one sharp end formed on the insulating film, A connection portion to a reference potential applied to one of the first wiring pattern and the second wiring pattern, and energization between the first wiring pattern and the second wiring pattern when an abnormal voltage occurs, A gap in which the sharpened shapes are opposed to each other so that the abnormal voltage is relaxed by the reference potential.

According to the semiconductor device of the present invention, each of the first and second wiring patterns has a sharp shape at one end, and a gap shape is provided by facing the sharp shape. The abnormal voltage is energized through the gap and is relaxed by the reference potential. The gap is formed at the opposing portion of each end of the first and second wiring patterns. The occupied area is small and contributes to high integration. Further, the gap is excellent in functional stability without being broken by an abnormal voltage.
A plurality of the gaps may be provided while sharing a connection portion to which the reference potential is applied. Preferably, each of the first wiring pattern and the second wiring pattern has a point in a range of 30 ° to 90 ° as the sharp shape. Abnormal voltage can be energized stably.

  The semiconductor device according to the present invention includes an element isolation region on a semiconductor substrate, a gate electrode member formed on the semiconductor substrate surrounded by the element isolation region via an insulating film, and a first electrode connected to the gate electrode member. And a first metal wiring pattern having a sharp end formed through an interlayer insulating film and a second connecting part connected to the semiconductor substrate and through the interlayer insulating film. And a second metal wiring pattern having a sharp end opposite to the end of the first metal wiring pattern formed in the above manner.

  According to the semiconductor device of the present invention, the first metal wiring pattern connected to the gate electrode member formed through the insulating film in which dielectric breakdown is a concern, and the second metal having a discharge path to the semiconductor substrate. A wiring pattern is configured. The first metal wiring pattern and the second metal wiring pattern are opposed to each other with a sharp end portion. The opposing portion of the sharp end is energized when an abnormal voltage is generated, thereby forming a bypass. The facing portion of the sharp end has a small area and contributes to high integration. Moreover, it is excellent in functional stability without being destroyed by abnormal voltage.

Note that the semiconductor device according to the present invention has any one of the following characteristics (a) to (d), so that the path of the abnormal voltage that occurs unexpectedly can be established more stably.
(A) Both the first and second metal wiring patterns are constituted by a first metal wiring layer on the gate electrode member.
(B) The first and second metal wiring patterns constitute a gap that bypasses only the abnormal voltage between the sharpened shapes.
(C) The first and second metal wiring patterns constitute a gap that bypasses only an abnormal voltage between the sharpened shapes, and the gap is provided in a void region of the interlayer insulating film.
(D) an external connection terminal provided above the semiconductor substrate, and a third connection portion connected to the external connection terminal in the first metal wiring pattern, and the first metal wiring pattern, The third connecting portion is provided at a position closer to the sharp end than the first connecting portion.

  The semiconductor device according to the present invention includes an element isolation region on a semiconductor substrate, a gate electrode member formed on the semiconductor substrate surrounded by the element isolation region via an insulating film, and the gate electrode member including the element A first wiring pattern extending on the isolation region and having a sharp end, and a sharp end facing the end of the first wiring pattern on the element isolation region. And a second wiring pattern made of the gate electrode member to be joined.

  According to the semiconductor device of the present invention, the gate electrode member is formed by extending the gate electrode member formed through the insulating film in which dielectric breakdown is a concern, and the gate electrode member is provided with a sharp end. And has a second wiring pattern having a discharge path to the semiconductor substrate and provided with a sharp end. The first wiring pattern and the second wiring pattern have sharpened ends facing each other. The opposing portion of the sharp end is energized when an abnormal voltage is generated, thereby forming a bypass. The facing portion of the sharp end has a small area and contributes to high integration. Moreover, it is excellent in functional stability without being destroyed by abnormal voltage.

Note that the semiconductor device according to the present invention has any one of the following characteristics (a) to (c), so that the path of the abnormal voltage that occurs unexpectedly can be established more stably.
(A) The first and second wiring patterns constitute a gap that bypasses only the abnormal voltage between the sharpened shapes.
(B) It includes an interlayer insulating film covering the first and second wiring patterns, and the first and second wiring patterns constitute a gap that bypasses only abnormal voltage between the sharpened shapes, It is provided in the void region of the interlayer insulating film.
(C) including an external connection terminal provided above the semiconductor substrate and a connection portion connected to the external connection terminal in the first wiring pattern, wherein the connection portion includes: It is provided in the vicinity of the sharp end.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of elements on a semiconductor substrate,
Forming a wiring pattern of a predetermined layer that becomes at least a part of circuit wiring related to the element as a semiconductor integrated circuit, and the wiring pattern has a predetermined size to form a gap that is energized by at least an abnormal voltage The pointed portions facing each other are formed by etching with a separation distance within a range.

  According to the method for manufacturing a semiconductor device of the present invention, the tip portions facing each other are formed by etching in the wiring pattern of the predetermined layer with a predetermined distance. This constitutes a gap that is energized by the abnormal voltage.

In the method of manufacturing a semiconductor device according to the present invention, by having any of the following features (a) to (d), the protection of the element against the abnormal voltage that occurs unexpectedly and the discharge path are more stably established. Let
(A) The plurality of elements include MOS type elements, and the wiring pattern is formed using a gate electrode member of the MOS type elements.
(B) The circuit wiring includes a plurality of metal wiring layers, and the wiring pattern is formed using a predetermined layer in the metal wiring layers.
(C) including a step of forming an interlayer insulating film on the wiring pattern, wherein the interlayer insulating film forms a void region on the gap.
(D) with respect to the wiring pattern, including a step of simultaneously etching and forming a dummy pattern in the vicinity of the opposing tip, and a step of forming an interlayer insulating film on the wiring pattern, the interlayer insulating film being on the gap A void region is formed.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a configuration diagram showing the main part of the semiconductor device according to the first embodiment of the present invention.
The conductive layer pattern 11 has a connection relationship with elements on the semiconductor substrate. The conductive layer pattern 11 is connected to, for example, the gate electrode of the MOS type element Q1 where there is a concern about gate breakdown due to application of abnormal voltage. The conductive layer pattern 11 has a connection relationship with the external connection terminal 12. An abnormal voltage is transmitted to the conductive layer pattern 11 by charge-up or ESD (electrostatic discharge) caused by plasma processing used during the manufacturing process. Therefore, the conductive layer pattern 11 is provided with a gap G1 for energizing only the abnormal voltage, and is connected to the semiconductor substrate via the gap G1. The semiconductor substrate has a reference potential (ground potential). The gap G1 has pointed portions 11A1 and 11A2 that face each other with a predetermined separation distance in order to bypass only the abnormal voltage to be transmitted to the MOS element Q1.

  The conductive layer pattern 11 is suitably configured with a metal wiring layer. In addition, it is conceivable that the conductive layer pattern 11 is configured using a polysilicon wiring layer or a silicided wiring layer which is a gate electrode member of the MOS element Q1. The gap G1 sets a minimum design rule or a predetermined separation distance. In addition, each angle θ of the tip portions 11A1 and 11A2 is a predetermined angle of 30 ° ≦ θ ≦ 90 °. It is possible to adjust the abnormal voltage to be bypassed by setting both. The pointed portions 11A1 and 11A2 and the gap G1 are formed using, for example, a photolithography technique and an etching technique at the time of wiring formation.

  According to the configuration of the above embodiment, the shape of the conductive layer pattern 11 itself having a connection relationship with the MOS type element Q1 is devised. That is, the conductive layer pattern 11 is provided with a gap G1 in which the tips 11A1 and 11A2 face each other in order to bypass only the abnormal voltage. Thereby, the abnormal voltage to be transmitted to the MOS type element Q1 is absorbed by the reference potential (ground potential) of the semiconductor substrate through the gap G1, and does not affect the MOS type element Q1. Since the gap G1 is a device of the shape of the conductive layer pattern 11 itself, the occupied area is small and contributes to high integration. Further, the gap G1 is excellent in functional stability without being destroyed by an abnormal voltage.

  In addition, although the conductive layer pattern 11 showed the structure connected to the semiconductor substrate via the gap G1, in order to bypass an abnormal voltage, the other structure is also considered. In order to bypass the abnormal voltage, the conductive layer pattern 11 may be connected to a power supply wiring (not shown) such as a ground wiring through the gap G1.

FIG. 2 is a projected cross-sectional view showing the main part of the semiconductor device according to the second embodiment of the present invention. The element isolation region 21 is, for example, STI (shallow trench isolation), and has a configuration in which an oxide film is embedded in a trench formed in the semiconductor substrate 20. The MOS type element Q2 is formed on a semiconductor substrate 20 surrounded by the element isolation region 21, here a P-well. The MOS type element Q2 has a gate electrode 23 with a gate oxide film 22 interposed therebetween, and a spacer 24 on the side thereof. In the MOS element Q2, a source / drain low concentration N ⁻ type extension region 25 and a high concentration N ⁺ type source / drain diffusion layer 26 are arranged on the surface of the substrate 20 on both sides of the gate electrode 23. Circuit wirings related to the MOS type element Q2 and other elements are metal wirings via the interlayer insulating film 27 (including 271 272 273 274) and the connection member 28 (including 281 282 283), respectively. It is configured by patterns 291 to 294.

In the second embodiment, the first-layer metal wiring pattern 291 includes metal wiring patterns 291a and 291b. The metal wiring pattern 291a is connected to the gate electrode 23 by a connection member 281 and has one end portion having a sharp shape 291aA. The metal wiring pattern 291b is connected to the high-concentration P ⁺ -type diffusion layer 201 to the semiconductor substrate (P-well) 20 by a connecting member 282, and has one end portion having a sharp shape 291bA facing the sharp shape 291aA. A gap G2 is formed by the sharpened shapes 291aA and 291bA. The gap G2 energizes between the metal wiring patterns 291a and 291b when an abnormal voltage is generated, and maintains an insulated state otherwise.

  On the pattern 291a side, the metal wiring pattern 291 has a connection relationship with an electrode pad PAD for external connection composed of the upper metal wiring pattern 294. The metal wiring pattern 291a is provided with a connection member 283 as a part of a connection path to the electrode pad PAD. The connection member 283 is provided at a position closer to the sharpened shape 291aA side than the connection member 281 on the pattern 291a side.

With reference to FIG. 2, the manufacturing method of this 2nd Embodiment structure is demonstrated.
A MOS type element (N-channel MOSFET) Q2 is formed by a well-known method on the semiconductor substrate 20 surrounded by the element isolation region 21, here a P-well. For example, the gate oxide film 22 is formed through a gate oxidation process (not shown). The gate electrode 23 is formed by patterning by depositing a polysilicon layer on the gate oxide film 22. Next, using the gate electrode 23 as a mask, a low concentration N ⁻ type extension region 25 of source / drain is formed by ion implantation. Next, a spacer 24 is formed by depositing an insulating film and anisotropic etching. Next, a high concentration N ⁺ type source / drain diffusion layer 26 is formed using the gate electrode 23 and the spacer 24 as a mask. The high-concentration P ⁺ -type diffusion layer 201 for connection to the semiconductor substrate (P-well) 20 is formed in the same process as the formation of other elements not shown, for example, the source / drain diffusion layers of the P-channel MOSFET.

  Next, an interlayer insulating film 271 that covers the MOS type element Q2 is formed. Thereafter, the interlayer insulating film 271 is planarized. This planarization process uses a CMP (Chemical Mechanical Polishing) technique. Thereafter, a contact hole is formed at a necessary portion by using a photolithography technique. A barrier metal and a main wiring metal such as W are embedded in the contact hole, and a connecting member is formed through a CMP process. In the drawing, the connection members 281 and 282 are formed, but a plurality of connection members (not shown) are formed.

  Next, a metal wiring pattern 291 is formed. The metal wiring pattern 291 has a laminated structure (not shown) including, for example, a barrier metal, a metal layer mainly composed of aluminum, and an antireflection film. Such a laminated structure is formed on the entire surface of the interlayer insulating film 271 by using a CVD technique or a sputtering technique. Thereafter, patterning is performed using a photolithography technique. The metal wiring pattern 291a is disposed on the connection member 281 and forms a sharp shape 291aA at one end. The metal wiring pattern 291b is disposed on the connection member 28 and forms a sharpened shape 291bA whose one end faces the sharpened shape 291aA. The metal wiring pattern 291 forms a part of circuit wiring related to other elements (not shown).

  The metal wiring pattern 291 (291a, 291b) forms a gap G2 that bypasses only the abnormal voltage between the sharpened shapes 291aA and 291bA. An example is as follows. When the wiring width of the metal wiring pattern 291 is 0.26 μm, the gap G2 is about 0.1 μm apart, and the tip angle θ of the sharpened shapes 291aA and 291bA is a predetermined angle of 30 ° ≦ θ ≦ 90 °, for example 60 About °.

  Next, an interlayer insulating film 272 that covers the metal wiring pattern 291 is deposited using a CVD technique. Thereafter, the interlayer insulating film 272 is planarized. This planarization process uses a CMP technique. Thereafter, a via hole is formed in a necessary portion by using a photolithography technique. A barrier metal and a main wiring metal such as W are embedded in the via hole, and a connection member is formed through a CMP process. In the figure, the connection member 283 is formed, but a plurality of other connection members (not shown) are formed. Here, the connection member 283 is provided at a position closer to the sharpened shape 291aA side than the connection member 281 on the metal wiring pattern 291a side. The connection member 283 is a part of a signal transmission path from the upper layer. The connection member 283 is arranged so that when an abnormal voltage is transmitted, it is preferentially discharged to the substrate through the gap G2.

  Next, a metal wiring pattern 292 is formed. The metal wiring pattern 292 has a laminated structure (not shown) including, for example, a barrier metal, a metal layer mainly composed of aluminum, and an antireflection film. Such a laminated structure is formed on the entire surface of the interlayer insulating film 272 by using a CVD technique or a sputtering technique. Thereafter, patterning is performed using a photolithography technique. The metal wiring pattern 292 is disposed on the connection member 283 and forms a lower layer electrode 292u for forming an electrode pad. The metal wiring pattern 292 forms a part of circuit wiring related to other elements (not shown).

  Next, an interlayer insulating film 273 that covers the metal wiring pattern 292 is formed using the CVD technique in the same manner as described above, and planarized by the CMP technique. Also in the interlayer insulating film 273, a via hole (not shown) is formed at a necessary place, and the connection member 28 is embedded. Next, a metal wiring pattern 293 is formed. The metal wiring pattern 293 is also formed in the same manner as the above-described metal wiring pattern 292, and a desired pattern is obtained. In the figure, a lower layer electrode 293u for forming an electrode pad is formed. The metal wiring pattern 293 forms a part of circuit wiring related to other elements (not shown).

  Next, an interlayer insulating film 274 that covers the metal wiring pattern 293 is formed using the CVD technique in the same manner as described above, and is planarized by the CMP technique. Also in the interlayer insulating film 274, a via hole (not shown) is formed at a necessary place, and the connection member 28 is embedded. Next, a metal wiring pattern 294 is formed. The metal wiring pattern 294 is also formed in the same manner as the above-described metal wiring pattern 292, and a desired pattern is obtained. In the figure, the formation of the electrode pad PAD is shown. The metal wiring pattern 294 forms part of circuit wiring related to other elements (not shown). Thereafter, although not shown, a protective film, a so-called passivation film is formed on the uppermost layer.

  According to the configuration and method of the above-described embodiment, the gap G2 is provided as a protection circuit for the MOS element Q2 that is likely to be broken down. That is, a metal wiring pattern 291 a connected to the gate electrode 23 and a metal wiring pattern 291 b having a discharge path to the semiconductor substrate 20 are configured. The metal wiring patterns 291a and 291b have end portions of sharpened shapes 291aA and 291bA and are opposed to each other to form a gap G2. Abnormal voltages can be caused by charge-up due to plasma processing utilized during the manufacturing process. Alternatively, the abnormal voltage may be caused by ESD (electrostatic discharge) that is suddenly transmitted from the electrode pad PAD generated in an inspection process or a mounting process after the IC is manufactured. The gap G2 forms a bypass that energizes the metal wiring patterns 291a and 291b when an abnormal voltage is generated and absorbs the abnormal voltage to the reference potential (ground potential) of the semiconductor substrate 20. The protection circuit including such a gap G2 has a smaller occupied area than conventional protection diodes and protection transistors, and contributes to higher integration. Moreover, it is excellent in functional stability without being destroyed by abnormal voltage.

  In the second embodiment, the MOS element Q2 may be configured through a salicide process (not shown). That is, the MOS element Q2 may form a silicided surface in the gate electrode 23 and the source / drain diffusion layer 26.

  The gap G2 is filled with the interlayer insulating film 272. However, the gap G2 may be disposed in a void region where the interlayer insulating film 272 does not exist. The gap G2 is fine, and there is a possibility that the interlayer insulating film 272 is not reliably embedded. If the gap G2 is in the cavity region, better insulation can be obtained during normal operation.

FIG. 3 is a plan view showing the main part of the semiconductor device and the manufacturing method thereof according to the third embodiment of the present invention. 4 is a cross-sectional view taken along line F4-F4 of FIG. The same parts as those in the second embodiment will be described with the same reference numerals.
For example, consider the formation of the gap G2 of the second embodiment. In the process of the gap G2, a dummy pattern is added. The dummy pattern 291d is formed by the metal wiring pattern 291 in the vicinity of the sharpened shapes 291aA and 291bA when the metal wiring patterns 291a and 291b are patterned. Thereby, the interlayer insulating film 272 formed in the next step exceeds the limit of the coverage performance around the gap G2. Thus, the gap G2 is disposed in the void region 41 where the interlayer insulating film 272 does not exist. As a result, better insulation can be obtained during normal operation.

FIG. 5 is a projected cross-sectional view showing the main part of the semiconductor device according to the fourth embodiment of the present invention. The element isolation region 51 is, for example, STI (shallow trench isolation), and has a configuration in which an oxide film is embedded in a trench formed in the semiconductor substrate 50. The MOS element Q3 is formed on a semiconductor substrate 50 surrounded by the element isolation region 51, here, a P-well. The MOS type element Q3 has a gate electrode 53 through a gate oxide film 52 and a spacer 54 on the side thereof. In the MOS element Q3, a low concentration N ⁻ type extension region 55 of source / drain and a high concentration N ⁺ type source / drain diffusion layer 56 are arranged on the surface of the substrate 50 on both sides of the gate electrode 53. Circuit wirings related to the MOS type element Q3 and other elements include metal wiring patterns 591 and 592 through an interlayer insulating film 57 (including 571 and 572) and a connecting member 58 (including 581 and 582), respectively. The upper layer wiring is not shown. Of course, the gate electrode 53 of the MOS element Q3 finally has some connection relationship with an electrode pad for external connection (not shown).

In the fourth embodiment, the gate electrode 53 extends as a gate electrode member pattern 531 a on the element isolation region 51 so as to include a contact portion with the connection member 581. One end of the gate electrode member pattern 531a has a sharp shape 531aA. Further, a gate electrode member pattern 531b is arranged on the element isolation region 51. The gate electrode member pattern 531 b is connected to the high concentration P ⁺ type diffusion layer 501 to the semiconductor substrate (P-well) 20. The gate electrode member pattern 531b has a sharp shape 531bA whose one end faces the sharp shape 531aA. A gap G3 is formed by the sharp shapes 531aA and 531bA. The gap G3 energizes between the gate electrode member patterns 531a and 531b when an abnormal voltage is generated, and maintains an insulated state otherwise.

  The gate electrode 53 and the gate electrode member patterns 531a and 531b may be configured through a salicide process. That is, the MOS element Q3 forms a silicided surface in the gate electrode 53 and the source / drain diffusion layer 56. Therefore, 531b including the gate electrode member patterns 531a and 531bA including the sharpened shape 531aA is also formed of the silicided surface. The slanted line SIL in FIG. 5 indicates the silicidation surface.

  Further, the metal wiring pattern 591 is connected to the connection member 581 on the gate electrode member pattern 531a side, and constitutes necessary circuit wiring. The connection member 581 is provided at a position closer to the sharpened shape 531aA side than the gate electrode 53 of the MOS type element Q3 on the gate electrode member pattern 531a side. Further, the metal wiring pattern 592 is connected to a connection member 582 with the metal wiring pattern 591 to constitute necessary circuit wiring. The metal wiring pattern 592 has a connection relationship with an upper wiring pattern (not shown). As described above, the gate electrode 53 of the MOS element Q3 finally has some connection relationship with an electrode pad for external connection (not shown).

With reference to FIG. 5, the manufacturing method of this 4th Embodiment structure is demonstrated.
On the semiconductor substrate 50 surrounded by the element isolation region 51, here a P-well, a MOS-type element (N-channel MOSFET) Q3 is formed by a known method. For example, this is the same as the formation of the MOS type element Q2 in FIG. 2 of the second embodiment. However, at the time of patterning the gate electrode 53, the gate electrode member pattern 531a having one end portion having a sharp shape 531aA is formed. At the time of patterning the gate electrode 53, a gate electrode member pattern 531b having a sharpened shape 531bA whose one end faces the sharpened shape 531aA is formed. The gate electrode member pattern 531 b is patterned so as to be connected to the high concentration P ⁺ type diffusion layer 501 to the semiconductor substrate (P-well) 20. The P ⁺ -type diffusion layer 501 includes a step of removing a gate oxide film by patterning, a step of forming a gate electrode member pattern 531b in a region from which the gate oxide film has been removed, and a source / source of a P-channel MOSFET in the region of the gate electrode member pattern 531b. It is formed by adding the same process as the process of forming the drain diffusion layer.

  Thereafter, the MOS element Q3 undergoes a salicide process. Thereby, the surfaces of the source / drain diffusion layer 56, the gate electrode 53, and the gate electrode member patterns 531a and 531b are silicided (oblique lines). The gap G3 is configured to energize only the abnormal voltage by setting the separation distance and the tip angle θ (30 ° ≦ θ ≦ 90 °) of the sharp shapes 531aA and 531bA. The above setting varies depending on whether a condition for forming the spacer 54 on the side portions of the sharpened shapes 531aA and 531bA is selected or not.

  Next, an interlayer insulating film 571 is formed covering the MOS type element Q3. The interlayer insulating film 571 is planarized using a CMP technique. Thereafter, a contact hole is formed at a necessary portion by using a photolithography technique. A barrier metal and a main wiring metal such as W are embedded in the contact hole, and a connecting member is formed through a CMP process. In the drawing, the connection member 581 is formed, but a plurality of other connection members (not shown) are formed. Here, the connection member 581 is provided at a position closer to the sharpened shape 531aA side than the gate electrode 53 on the gate electrode member pattern 531a side. The connection member 581 is a part of a signal transmission path from the upper layer. The connection member 581 is arranged so that it is likely to be preferentially discharged through the gap G3 when an abnormal voltage is transmitted.

  Next, a metal wiring pattern 591 is formed. The metal wiring pattern 591 has a laminated structure including, for example, a barrier metal, a metal layer mainly composed of aluminum, and an antireflection film. Such a laminated structure is formed over the entire surface of the interlayer insulating film 571 using a CVD technique or a sputtering technique. Thereafter, patterning is performed using a photolithography technique. The metal wiring pattern 591 forms part of circuit wiring related to other elements (not shown).

  Next, an interlayer insulating film 572 covering the metal wiring pattern 591 is deposited using the CVD technique. Thereafter, the interlayer insulating film 572 is planarized. This planarization process uses a CMP technique. Thereafter, a via hole is formed in a necessary portion by using a photolithography technique. A barrier metal and a main wiring metal such as W are embedded in the via hole, and a connection member is formed through a CMP process. In the figure, the connection member 582 is formed, but a plurality of connection members (not shown) are formed. Next, a metal wiring pattern 292 is formed on the interlayer insulating film 572. The metal wiring pattern 292 forms a part of circuit wiring related to other elements (not shown). Such circuit wiring includes upper layer wiring (not shown). Eventually, electrode pads for external connection are formed and configured to have some connection relationship with the circuit wiring.

  According to the configuration and method of the above-described embodiment, the gap G3 is provided as a protection circuit for the MOS element Q3 that is concerned about dielectric breakdown. That is, a gate electrode member pattern 531 a configured as an extension portion of the gate electrode 53 and a gate electrode member pattern 531 b having a discharge path to the semiconductor substrate 50 are configured. The gate electrode member patterns 531a and 531b have ends of sharp shapes 531aA and 531bA facing each other to form a gap G3. The abnormal voltage can be caused by charge-up caused by plasma processing used during the manufacturing process, or ESD (electrostatic discharge) suddenly transmitted from an upper layer wiring or electrode pad (not shown). The gap G3 forms a bypass that energizes the gate electrode members 531a and 531b when an abnormal voltage is generated and absorbs the abnormal voltage to the reference potential (ground potential) of the semiconductor substrate 50. The protection circuit including such a gap G3 has a smaller occupied area than conventional protection diodes and protection transistors, and contributes to higher integration. Moreover, it is excellent in functional stability without being destroyed by abnormal voltage.

  In the fourth embodiment, the gap G3 is filled with the interlayer insulating film 571. However, the gap G3 may be disposed in a void region where the interlayer insulating film 571 does not exist. The gap G3 is fine, and there is a possibility that the interlayer insulating film 571 is not reliably embedded. If the gap G3 is in the cavity region, better insulation can be obtained during normal operation. A dummy pattern may be positively added as in the third embodiment shown in FIG. In this case, although not shown, the dummy pattern is a gate electrode member pattern such as polysilicon, and is disposed at an appropriate location near the gap G3. It is also necessary to consider the state of the spacer 54. By disposing the dummy pattern at a key point, the interlayer insulating film 572 formed in the next step exceeds the limit of the coverage performance around the gap G3. Accordingly, the gap G3 is arranged in a void region where the interlayer insulating film 572 does not exist. As a result, better insulation can be obtained during normal operation.

6 and 7 are plan views showing main parts of the semiconductor device according to the fifth and sixth embodiments of the present invention, respectively. A plurality of gaps that are energized only when an abnormal voltage is generated are provided while sharing a connection portion to which a reference potential is applied.
In FIG. 6, the conductive layer pattern 61 is formed on the insulating film 63 on the semiconductor substrate 60. The insulating film 63 can be an element isolation region or an interlayer insulating film. The conductive layer pattern 61 has patterns 611a, 612a, 613a, 614a, and 61b. The pattern 611a has a sharp shape 611aA at one end. The pattern 612a has a sharp shape 612aA at one end. The pattern 613a has a sharp shape 613aA at one end. The pattern 614a has a sharp shape 614aA at one end. The other end of each of the patterns 611a, 612a, 613a, 614a is connected to a part of an element (not shown) in which abnormal voltage is a concern. The pattern 61 b has a connection portion 62 to a reference potential, for example, the semiconductor substrate 60. The pattern 61b has sharpened shapes 61bA1, 61bA2, 61bA3, 61bA4 whose one end faces the sharpened shapes 611aA, 612aA, 613aA, 614aA, respectively. A gap G61 is formed by the sharpened shapes 611aA and 61bA1. A gap G62 is formed by the sharp shapes 612aA and 61bA2. A gap G63 is formed by the sharp shapes 613aA and 61bA3. A gap G64 is formed by the sharpened shapes 614aA and 61bA4. The gaps G61 to G64 are energized when an abnormal voltage is generated, and the semiconductor substrate 60 absorbs the abnormal voltage.

  As shown in the second embodiment, the conductive layer pattern 61 is appropriately configured with a metal wiring layer. In addition, the conductive layer pattern 61 may be configured using a polysilicon wiring layer or a silicided wiring layer which is a gate electrode member of a MOS type element. Each of the gaps G61 to G64 sets a minimum design rule or a predetermined separation distance. In addition, the tip angle in each sharp shape is set to a predetermined angle in the range of 30 ° to 90 °. It is possible to adjust the abnormal voltage to be bypassed by setting both. The gaps G61 to G64 are patterned using, for example, a photolithography technique and an etching technique.

  In FIG. 7, the conductive layer pattern 71 is formed on the insulating film 73 on the semiconductor substrate 70. The insulating film 73 can be an element isolation region or an interlayer insulating film. The conductive layer pattern 71 has patterns 711a, 712a, 713a, 714a, and 71b. One end of the pattern 711a has a sharp shape 711aA. One end of the pattern 712a has a sharp shape 712aA. One end of the pattern 713a has a sharp shape 713aA. One end of the pattern 714a has a sharp shape 714aA. The other end of each of the patterns 711a, 712a, 713a, 714a is connected to a part of an element (not shown) in which abnormal voltage is a concern. The pattern 71 b has a connection portion 72 to a reference potential, for example, the semiconductor substrate 70. The pattern 71b has sharpened shapes 71bA1, 71bA2, 71bA3, 71bA4 whose one end faces the sharpened shapes 711aA, 712aA, 713aA, 714aA, respectively. A gap G71 is formed by the sharpened shapes 711aA and 71bA1. A gap G72 is formed by the sharp shapes 612aA and 61bA2. A gap G73 is formed by the sharpened shapes 713aA and 71bA3. A gap G74 is formed by the sharpened shapes 714aA and 71bA4. The gaps G71 to G74 are energized when an abnormal voltage is generated, and the semiconductor substrate 70 absorbs the abnormal voltage.

  As shown in the fourth embodiment, the conductive layer pattern 71 may be configured using a polysilicon wiring layer or a silicided wiring layer which is a gate electrode member of a MOS type element. Moreover, the structure by a metal wiring layer may be sufficient. Each of the gaps G71 to G74 sets a predetermined separation distance in consideration of the minimum design rule. In addition, the tip angle in each sharp shape is set to a predetermined angle in the range of 30 ° to 90 °. It is possible to adjust the abnormal voltage to be bypassed by setting both. The gaps G71 to G74 are patterned using, for example, a photolithography technique and an etching technique.

  According to the configuration of each of the above embodiments, a plurality of gaps that are energized only when an abnormal voltage is generated are provided while sharing a connection portion to which a reference potential is applied. This contributes to higher integration of the protection circuit. The plurality of gaps sharing the connection portion to which the reference potential is applied are not limited to the fifth and sixth embodiments, and various configurations are conceivable.

  Further, although not shown, gaps G61 to G64 or gaps G71 to G74 may be arranged in void regions where no interlayer insulating film exists. If each gap is in the cavity region, better insulation can be obtained during normal operation. Although not shown, a dummy pattern may be positively added as shown in the third embodiment. As a result, in the interlayer insulating film (not shown), it may be considered that the periphery of each of the gaps G61 to G64 or the gaps G71 to G74 is a void region.

  As described above, according to the present invention, in a wiring to a gate electrode member where there is a concern about breakdown of an insulating film such as a MOS type element, a protection circuit having a gap that is energized only when an abnormal voltage is generated is added. The abnormal voltage can occur due to charge-up caused by plasma processing or ESD (electrostatic discharge). The gap in the present invention can bypass the abnormal voltage described above, eliminates charging damage to the MOS type element, and prevents breakdown of the insulating film. Moreover, the occupied area can be smaller than that of the conventional protection circuit. Thereby, the reliability of the elements constituting the integrated circuit is improved, and as a result, the product yield is improved. As a result, it is possible to provide a semiconductor device having a protection circuit with a small area and excellent abnormal voltage bypass performance in a semiconductor integrated circuit, and a manufacturing method thereof.

1 is a configuration diagram showing a main part of a semiconductor device according to a first embodiment. FIG. 6 is a projected cross-sectional view showing the main part of a semiconductor device according to a second embodiment. The top view which shows the principal part of the semiconductor device which concerns on 3rd Embodiment, and its manufacturing method. Sectional drawing which follows the F4-F4 line | wire of FIG. FIG. 10 is a projected cross-sectional view showing a main part of a semiconductor device according to a fourth embodiment. FIG. 9 is an exemplary plan view showing a main part of a semiconductor device according to a fifth embodiment; The top view which shows the principal part of the semiconductor device which concerns on 6th Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11, 61, 71 ... Conductive layer pattern, 11A1, 11A2 ... Point, 12 ... External connection terminal, 20, 50, 60, 70 ... Semiconductor substrate, 201, 501 ... High concentration diffusion layer, 21 ... Element isolation region, 22 , 52 ... Gate oxide film, 23, 53 ... Gate electrode, 24, 54 ... Spacer, 25, 55 ... Source / drain extension region, 26, 56 ... Source / drain diffusion layer, 27 (including 271 to 274), 57 (including 571, 572) ... interlayer insulating film, 28 (including 281 to 283), 58 (including 581, 582) ... connection member, 291 to 294, 291a, 291b, 591, 592 ... metal wiring pattern, 291aA, 291bA, 531aA, 531bA, 611aA, 612aA, 613aA, 614aA, 61bA1, 61bA2, 61b 3, 61bA4, 711aA, 712aA, 713aA, 714aA, 71bA1, 71bA2, 71bA3, 71bA4 ... Sharp shape, 291d ... Dummy pattern, 41 ... Void region, 531a, 531b ... Gate electrode member pattern, 63, 73 ... Insulating film, Q1 , Q2, Q3 ... MOS type elements, G1, G2, G3, G61-G64, G71-G74 ... gaps, PAD ... electrode pads.

Claims (20)

A MOS-type element formed on a semiconductor substrate;
A conductive layer pattern having a gap facing a tip that bypasses only the abnormal voltage to be transmitted to the MOS type element; and
A semiconductor device including: The semiconductor device according to claim 1, wherein the conductive layer pattern has a connection relationship with at least the gate electrode of the MOS type element on one side from the gap, and has a connection relationship with at least the semiconductor substrate on the other side from the gap. Including an external connection terminal provided above the semiconductor substrate;
2. The conductive layer pattern has a connection relationship with at least the gate electrode of the MOS element and the external connection terminal on one side from the gap, and has a connection relationship with at least the semiconductor substrate on the other side from the gap. The semiconductor device described. An insulating film formed on the semiconductor substrate;
A first wiring pattern and a second wiring pattern each having at least one sharp end formed on the insulating film;
A connection portion to a reference potential applied to one of the first wiring pattern and the second wiring pattern;
A gap in which the sharpened shapes that are energized between the first wiring pattern and the second wiring pattern when an abnormal voltage occurs and the abnormal voltage is relaxed by the reference potential are opposed to each other;
A semiconductor device including: The semiconductor device according to claim 4, wherein a plurality of the gaps are provided while sharing a connection portion to which the reference potential is applied. 6. The semiconductor device according to claim 4, wherein each of the first wiring pattern and the second wiring pattern has a point in a range of 30 ° to 90 ° as the sharp shape. An element isolation region on a semiconductor substrate;
A gate electrode member formed on the semiconductor substrate surrounded by the element isolation region via an insulating film;
A first metal wiring pattern having a first connection portion connected to the gate electrode member and having a sharp end formed through an interlayer insulating film;
A second metal wiring pattern having a second connecting portion connected to the semiconductor substrate and having a sharp end facing the end of the first metal wiring pattern formed via the interlayer insulating film; ,
A semiconductor device including: 8. The semiconductor device according to claim 7, wherein each of the first and second metal wiring patterns is constituted by a first metal wiring layer on the gate electrode member. 9. The semiconductor device according to claim 7, wherein the first and second metal wiring patterns constitute a gap that bypasses only an abnormal voltage between the sharpened shapes. The said 1st, 2nd metal wiring pattern comprises the gap which bypasses only an abnormal voltage only by the said sharp shape, The said gap is provided in the void area | region of the said interlayer insulation film. Semiconductor device. An external connection terminal provided above the semiconductor substrate;
A third connection portion connected to the external connection terminal in the first metal wiring pattern,
The said 1st metal wiring pattern WHEREIN: The said 3rd connection part is provided in the position closer to the said sharp-shaped end part than the said 1st connection part. Semiconductor device. An element isolation region on a semiconductor substrate;
A gate electrode member formed on the semiconductor substrate surrounded by the element isolation region via an insulating film;
A first wiring pattern in which the gate electrode member extends on the element isolation region and has a sharp end;
A second wiring pattern comprising the gate electrode member having a sharpened end facing the end of the first wiring pattern on the element isolation region and coupled to the semiconductor substrate;
A semiconductor device including: The semiconductor device according to claim 12, wherein the first and second wiring patterns constitute a gap that bypasses only an abnormal voltage between the sharpened shapes. An interlayer insulating film covering the first and second wiring patterns;
14. The semiconductor according to claim 12, wherein the first and second wiring patterns constitute a gap that bypasses only abnormal voltage between the sharpened shapes, and the gap is provided in a void region of the interlayer insulating film. apparatus. An external connection terminal provided above the semiconductor substrate;
A connection portion connected to the external connection terminal in the first wiring pattern,
The semiconductor device according to claim 12, wherein the connection portion is provided in the vicinity of the sharp end portion with respect to the first wiring pattern. Forming a plurality of elements on a semiconductor substrate;
Forming a wiring pattern of a predetermined layer to be at least part of circuit wiring related to the element as a semiconductor integrated circuit,
A method of manufacturing a semiconductor device, wherein the wiring pattern forms a gap that is energized by at least an abnormal voltage to etch pointed portions facing each other with a predetermined distance. 17. The method of manufacturing a semiconductor device according to claim 16, wherein the plurality of elements include a MOS type element, and the wiring pattern is formed using a gate electrode member of the MOS type element. The method of manufacturing a semiconductor device according to claim 16, wherein the circuit wiring includes a plurality of metal wiring layers, and the wiring pattern is formed using a predetermined layer in the metal wiring layers. The method of manufacturing a semiconductor device according to claim 16, further comprising a step of forming an interlayer insulating film on the wiring pattern, wherein the interlayer insulating film forms a void region on the gap. Concerning the wiring pattern, a step of simultaneously etching and forming a dummy pattern in the vicinity of the facing tip portion;
Forming an interlayer insulating film on the wiring pattern,
The method of manufacturing a semiconductor device according to claim 16, wherein the interlayer insulating film forms a void region on the gap.

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