JP2013004577A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents information from being read.SOLUTION: A semiconductor device 10 disclosed in the present specification comprises: a second insulation layer 15 having a contact 15a; a third insulation layer 17 having a contact 17a; and a second wiring layer 16 arranged between the second insulation layer 15 and the third insulation layer 17. A wiring is not arranged at a part of the second wiring layer 16 between the contact 15a and the contact 17a. A distance between the contact 15a and the contact 17a is shorter than a distance between the contact 15a or the contact 17a, and another contact or another wiring in the second insulation layer 15, the third insulation layer 17 and the second wiring layer 16.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Conventionally, a semiconductor device having a storage function or an arithmetic function has been used. In addition, a card on which a semiconductor device having such a storage function or calculation function is mounted is used. An example of such a card is a smart card.

  In a smart card, a semiconductor device (memory) having a storage function is mounted in the card, so that the amount of stored information is greatly improved as compared with a conventional magnetic stripe card. For example, information such as user personal information is stored and used in the smart card.

  In addition, by mounting a semiconductor device having an arithmetic function such as a CPU in a card, information processing can be performed in the card. In this case, the program executed by the CPU can also be stored in the memory in the card.

  Since information to be protected is stored in the smart card, a technique for protecting the information by encrypting the information is used.

JP 2002-324799 A JP-A-10-69054 JP 2008-172182 A

  However, even with smart cards that have taken measures to protect information, information stored in the card or information processing information is read and stored using techniques such as failure use analysis or reverse engineering. There is a risk that the stored information will be altered.

  In failure utilization analysis, using a focused ion beam (FIB) device or the like, the wiring of the semiconductor device mounted on the smart card is exposed and a high voltage is applied while keeping the smart card usable. Is done.

  Therefore, an object of the present specification is to provide a semiconductor device that prevents reading of information.

  It is another object of the present specification to provide a method for manufacturing a semiconductor device that prevents reading of information.

  According to one embodiment of a semiconductor device disclosed in this specification, a first insulating layer having a first contact, a second insulating layer having a second contact, the first insulating layer, and the second insulating layer A wiring layer disposed between the first contact and the second contact, wherein no wiring is disposed in the portion of the wiring layer between the first contact and the second contact. Is shorter than the distance between the first contact or the second contact and the other contact or wiring in the first insulating layer, the second insulating layer, and the wiring layer.

  In addition, according to one embodiment of the semiconductor device disclosed in this specification, the semiconductor device includes a wiring layer including a first wiring and a second wiring, and the distance between the first wiring and the second wiring is the first wiring. The distance between the wiring or the second wiring and the other wiring in the wiring layer is shorter, and the first wiring and the second wiring are not electrically connected to the circuit element.

  According to one embodiment of the method for manufacturing a semiconductor device disclosed in this specification, the step of forming a wiring layer on the first insulating layer having the first contact and the second contact on the wiring layer are provided. Forming a second insulating layer, and in the step of forming the wiring layer, the wiring layer is formed so as not to dispose the wiring between the first contact and the second contact. In the step of forming the second insulating layer, the distance between the first contact and the second contact is such that the first contact or the second contact, the first insulating layer, the second insulating layer, and the The second insulating layer is formed so as to be shorter than the distance between other contacts or wirings in the wiring layer.

  Furthermore, according to one mode of the method for manufacturing a semiconductor device disclosed in the present specification, the method includes a step of forming a wiring layer having a first wiring and a second wiring, and the step between the first wiring and the second wiring. Forming the first wiring and the second wiring so that the distance between the first wiring or the second wiring and the other wiring in the wiring layer is shorter, and The first wiring and the second wiring are formed so as not to be electrically connected to the circuit element.

  According to one embodiment of the semiconductor device disclosed in this specification, information is prevented from being read.

  According to one embodiment of the method for manufacturing a semiconductor device disclosed in this specification, a semiconductor device that prevents reading of information can be obtained.

  The objects and advantages of the invention will be realized and obtained by means of the elements and combinations particularly pointed out in the appended claims.

  Both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed.

(A) is sectional drawing which shows 1st Embodiment of the semiconductor device disclosed to this specification, (B) is the top view. It is a figure which shows a mode that the ion beam is irradiated with respect to the semiconductor device shown in FIG. (A) is sectional drawing which shows the modification 1 of 1st Embodiment of the semiconductor device disclosed to this specification, (B) is the top view. It is sectional drawing which shows the modification 2 of 1st Embodiment of the semiconductor device disclosed to this specification. (A) is sectional drawing which shows 2nd Embodiment of the semiconductor device disclosed by this specification, (B) is the top view. It is a figure which shows a mode that the ion beam is irradiated with respect to the semiconductor device shown in FIG. It is a figure which shows the modification 1 of 2nd Embodiment of the semiconductor device disclosed to this specification. It is a figure which shows the modification 2 of 2nd Embodiment of the semiconductor device disclosed to this specification. The manufacturing process (the 1) of 1st Embodiment of the manufacturing method of the semiconductor device disclosed to this specification is shown, (A) is sectional drawing, (B) is the top view. The manufacturing process (the 2) of 1st Embodiment of the manufacturing method of the semiconductor device disclosed to this specification is shown, (A) is sectional drawing, (B) is the top view. The manufacturing process (the 3) of 1st Embodiment of the manufacturing method of the semiconductor device disclosed to this specification is shown, (A) is sectional drawing, (B) is the top view. The manufacturing process (the 4) of 1st Embodiment of the manufacturing method of the semiconductor device disclosed to this specification is shown, (A) is sectional drawing, (B) is the top view. The manufacturing process (the 5) of 1st Embodiment of the manufacturing method of the semiconductor device disclosed to this specification is shown, (A) is sectional drawing, (B) is the top view. The manufacturing process (the 1) of 2nd Embodiment of the manufacturing method of the semiconductor device disclosed to this specification is shown, (A) is sectional drawing, (B) is the top view. The manufacturing process (the 2) of 2nd Embodiment of the manufacturing method of the semiconductor device disclosed to this specification is shown, (A) is sectional drawing, (B) is the top view. The manufacturing process (the 3) of 2nd Embodiment of the manufacturing method of the semiconductor device disclosed to this specification is shown, (A) is sectional drawing, (B) is the top view. The manufacturing process (the 4) of 2nd Embodiment of the manufacturing method of the semiconductor device disclosed to this specification is shown, (A) is sectional drawing, (B) is the top view. The manufacturing process (the 5) of 2nd Embodiment of the manufacturing method of the semiconductor device disclosed to this specification is shown, (A) is sectional drawing, (B) is the top view. The manufacturing process (the 1) of 3rd Embodiment of the manufacturing method of the semiconductor device disclosed to this specification is shown, (A) is sectional drawing, (B) is the top view. (A)-(C) are figures which show the manufacturing process (the 2) of 3rd Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. (A) And (B) is a figure which shows the manufacturing process (the 3) of 3rd Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. The manufacturing process (the 4) of 3rd Embodiment of the manufacturing method of the semiconductor device disclosed to this specification is shown, (A) is sectional drawing, (B) is the top view.

  Hereinafter, a preferred first embodiment of a semiconductor device disclosed in this specification will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the invention described in the claims and equivalents thereof.

  FIG. 1A is a cross-sectional view illustrating a first embodiment of a semiconductor device disclosed in this specification, and FIG. 1B is a plan view thereof. FIG. 1A is a cross-sectional view taken along line X1-X1 in FIG.

  The semiconductor device 10 includes an element layer 12 disposed on a substrate 11. In the element layer 12, circuit elements 12a, 12b, and 12c such as transistors are arranged.

  On the element layer 12, a first insulating layer 13 having a contact 13a is disposed. On the first insulating layer 13, a first wiring layer 14 having wirings 14a and 14b is disposed. The wirings 14a and 14b are wirings that are grounded. The contact 13a electrically connects the upper wiring 14b and the lower circuit element 12c.

  On the first wiring layer 14, a second insulating layer 15 having contacts 15a, 15b, and 15c is disposed. On the second insulating layer 15, a second wiring layer 16 having wirings 16a and 16b is disposed. The contacts 15a and 15b are electrically connected to the underlying wiring 14a. The contact 15c electrically connects the upper wiring 16b and the lower wiring 14b.

  On the second wiring layer 16, a third insulating layer 17 having contacts 17a, 17b, and 17c is disposed. On the third insulating layer 17, a third wiring layer 18 having wirings 18a, 18b, and 18c is disposed. The contact 17a is electrically connected to the upper wiring 18a. The contact 17b is electrically connected to the upper wiring 18b. The contact 17c electrically connects the upper wiring 18c and the lower wiring 16b.

  On the third wiring layer 18, a protective layer 19 and a cover layer 20 are arranged in order. FIG. 1B shows a plan view of the third wiring layer 18, and the protective layer 19 and the cover layer 20 are not shown.

  In the semiconductor device 10, no wiring is arranged in the portion of the second wiring layer 16 between the contact 15a and the contact 17a. Further, no wiring is arranged in the portion of the second wiring layer 16 between the contact 15b and the contact 17b.

  In the semiconductor device 10, the distance between the contact 15 a and the contact 17 a is the distance between the contact 15 a or the contact 17 a and another contact or wiring in the second insulating layer 15, the third insulating layer 17, and the second wiring layer 16. It is shorter than the distance between. In this specification, the distance between the contact 15a and the contact 17a is the shortest distance among the distances between the contact 15a and the contact 17a.

  For example, the distance between the contact 17a and the contact 15a is shorter than the distance between the contact 15a and the wiring 16a. Similarly, the distance between the contact 15a and the contact 17a is shorter than the distance between the contact 15a and the contact 15b. Further, the distance between the contact 15a and the contact 15b is shorter than the distance between the contact 15a and the wiring 16a. Further, the distance between the contact 15a and the contact 15b is shorter than the distance between the contact 17a and the contact 17b. Further, the distance between the contact 15a and the contact 15b is shorter than the distance between the contact 17a and the wiring 16a.

  The contact 15a and the contact 17a are opposed to each other so that at least a part thereof is overlapped with the second wiring layer 16 interposed therebetween, so that the distance between the contact 15a and the contact 17a is between another wiring or the contact. It is preferable to make it shorter than the distance. In the semiconductor device 10, the contact 15 a and the contact 17 a have the same shape in plan view and are arranged so as to overlap with each other.

  The contact 15a and the contact 17a face each other in parallel, and the distance between the contact 15a and the contact 17a is constant between the faces facing each other.

  Similarly, in the semiconductor device 10, the distance between the contact 15b and the contact 17b is such that the contact 15b or the contact 17b and other contacts in the third insulating layer 17, the second insulating layer 15, and the second wiring layer 16 or It is shorter than the distance to the wiring. The distance between the contact 15b and the contact 17b is the shortest distance among the distances between the contact 15b and the contact 17b.

  The contact 15b has the same shape as the contact 15a, the contact 17b has the same shape as the contact 17a, and the contact 15b and the contact 17b have the same arrangement relationship as the contact 15a and the contact 17a. Therefore, the above description for the contact 15a and the contact 17a is also applied to the contact 15b and the contact 17b as appropriate.

  In the semiconductor device 10, the contacts 15a, 15b, 17a, and 17b are dummy contacts that are not electrically connected to the circuit elements including the circuit elements 12a, 12b, and 12c in the semiconductor device 10. Similarly, the wirings 14a, 16a, 18a, and 18b are dummy wirings that are not electrically connected to the circuit elements including the circuit elements 12a, 12b, and 12c in the semiconductor device 10. As used herein, circuit elements include passive elements such as resistors or capacitors or coils and active elements such as diodes or transistors. In this specification, the dummy contact or the dummy wiring means a circuit that does not form a circuit for executing a function such as an original storage function or an arithmetic function of the semiconductor device.

  As the wiring forming material, for example, aluminum, copper, tungsten, or the like can be used. As a contact forming material, for example, tungsten or the like can be used. As a material for forming the insulating layer, a silicon oxide film, a silicon nitride film, an organic film, an epoxy resin, a phenol resin, or the like can be used.

  The semiconductor device 10 is preferably used by being mounted in a card such as a smart card, for example. When the card on which the semiconductor device 10 is mounted is analyzed for failure use, for example, and the ion beam is irradiated using a focused ion beam (FIB) device, the semiconductor device 10 uses the irradiated charge, By inducing internal discharge and destroying the circuit, analysis can become impossible. Next, this function of the semiconductor device 10 will be described below.

  FIG. 2 is a diagram illustrating a state in which the semiconductor device illustrated in FIG. 1 is irradiated with an ion beam.

  In the semiconductor device 10 irradiated with the ion beam 31 from the ion gun 30 of the FIB apparatus, the wiring 18b of the third wiring layer 18 is exposed. The exposed wiring 18b is irradiated with the ion beam 31 and supplied with positive charges. Then, a positive charge is supplied and accumulated in the lower layer contact 17b electrically connected to the wiring 18b.

  The contact 15b facing the contact 17b via the second wiring layer 16 that is an insulator is supplied with negative charge from the ground and accumulates corresponding to the accumulation of positive charge in the contact 17b.

  As the ion beam 31 is irradiated from the ion gun 30, the amount of charge accumulated in the contact 17b and the contact 15b increases, and the voltage applied to the second wiring layer 16 between the contact 17b and the contact 15b increases. To do. When the voltage applied to the second wiring layer 16 exceeds the dielectric breakdown voltage of the second wiring layer 16, a discharge is generated between the contact 17b and the contact 15b as shown in FIG. The electrical energy of the discharge can destroy the second wiring layer 16 of the contact 17b and the contact 15b, and can destroy the surrounding contacts, wiring, and circuit elements.

  At this time, even if the circuit element is not destroyed, the resistance or the capacitance of the semiconductor device 10 can be changed by destroying a part of the wiring or the contact, so that the semiconductor device 10 operates normally. Can be eliminated. Such a change in resistance or capacitance is particularly effective for causing malfunction in an analog circuit.

  The electrical energy that destroys the circuit by the discharge corresponds to the amount of charge accumulated between the opposing contacts. Therefore, the larger the area of the opposing contact portion, the greater the amount of stored charge. Also, the higher the dielectric constant of the insulator between the opposing contacts, the greater the amount of stored charge.

  In the example of FIG. 2, the ion beam is applied to the wiring 18 b of the third wiring layer 18. However, when the ion beam is applied to the wiring 18 a of the third wiring layer 18, the contact is similarly performed. A discharge can be induced between 17a and contact 15a.

  In the example of FIG. 2, the semiconductor device 10 is irradiated with an ion beam. However, if the semiconductor device 10 is irradiated with a charged particle beam having a positive or negative charge, the distance between the contacts is increased. Can induce a discharge. As the charged particle beam, for example, an electron beam may be used.

  According to the semiconductor device of the present embodiment described above, information is prevented from being read by inducing a discharge between the contacts when the charged particles are irradiated, thereby preventing the semiconductor device 10 from operating normally. it can. Accordingly, unauthorized analysis is prevented.

  In the embodiment described above, the contacts 15a, 15b, 17a, and 17b are dummy contacts that are not electrically connected to the circuit elements including the circuit elements 12a, 12b, and 12c. However, the contacts 15a, 15b, 17a, and 17b may be contacts that are electrically connected to circuit elements including the circuit elements 12a, 12b, and 12c. Similarly, the wirings 14a, 16a, 18a, and 18b may be wirings that are electrically connected to circuit elements including the circuit elements 12a, 12b, and 12c.

  In the above-described embodiment, the contact 15a, 17a and the contact 15b, 17b have two dummy contact pairs. However, the contact 15a, 17a or only one dummy contact pair of the contacts 15b, 17b is used. You may have.

  Next, Modification Example 1 and Modification Example 2 of the semiconductor device of the first embodiment described above will be described below with reference to the drawings.

  FIG. 3A is a cross-sectional view showing Modification Example 1 of the first embodiment of the semiconductor device disclosed in this specification, and FIG. 3B is a plan view thereof. FIG. 3A is a cross-sectional view taken along line X2-X2 of FIG.

  In the semiconductor device 10 of the first modification, the contact 15a and the contact 17a are arranged so that the edges are in contact with each other when seen in a plan view, and do not overlap. The distance between the edge of the contact 15a and the edge of the contact 17a is the shortest distance between the two contacts.

  In the modified example 1, when charged particles are irradiated, a discharge is induced between the edge of the contact 15a and the edge of the contact 17a so that the discharge location between the contacts can be controlled. It has become. Therefore, in the modified example 1, the reliability of controlling the induction of discharge between the contacts is improved.

  FIG. 4 is a cross-sectional view illustrating a second modification example of the first embodiment of the semiconductor device disclosed in this specification.

  In the semiconductor device 10 of Modification Example 2, a plurality of insulating layers and wiring layers are disposed between the third wiring layer 18 and the protective layer 19. The wirings 18a, 18b, and 18c of the third wiring layer 18 are electrically connected to the upper layer wirings through contacts.

  Next, a second embodiment of the semiconductor device described above will be described below with reference to FIGS. For points that are not particularly described in the second embodiment, the description in detail regarding the first embodiment is applied as appropriate.

  FIG. 5A is a cross-sectional view illustrating a second embodiment of the semiconductor device disclosed in this specification, and FIG. 5B is a plan view thereof. FIG. 5A is a cross-sectional view taken along line X3-X3 in FIG.

  The semiconductor device 40 includes an element layer 42 disposed on a substrate 41. In the element layer 42, circuit elements 42a, 42b, 42c such as transistors are arranged.

  A first insulating layer 43 having a contact 43a is disposed on the element layer. On the first insulating layer 43, a first wiring layer 44 having wirings 44a, 44b, 44c, 44d, and 44e is disposed. The wirings 44a, 44c, and 44e are wirings that are grounded. As shown in FIG. 5B, the wiring 44a and the wiring 44c are portions of the wiring protruding from the wiring 44ac, and the wiring 44a, the wiring 44c, and the wiring 44ac are electrically connected. The contact 43a electrically connects the upper wiring 44e and the lower circuit element 42c.

  On the first wiring layer 44, a second insulating layer 45 having contacts 45a, 45b, 45c is disposed. On the second insulating layer 45, a second wiring layer 46 having wirings 46a, 46b, and 46c is disposed. The contact 45a electrically connects the upper wiring 46a and the lower wiring 44b. The contact 45b electrically connects the upper layer wiring 46b and the lower layer wiring 44d. The contact 45c electrically connects the upper wiring 46c and the lower wiring 44e.

  The contact 45a and the wiring 44b have the same shape when viewed in plan, and are arranged at the same position when viewed in plan. Similarly, the contact 45b and the wiring 44d have the same shape when viewed in plan, and are arranged at the same position when viewed in plan.

  On the second wiring layer 46, a third insulating layer 47 having contacts 47a is disposed. On the third insulating layer 47, a third wiring layer 48 having wirings 48a, 48b and 48c is disposed. The contact 47a electrically connects the upper wiring 48c and the lower wiring 46c.

  On the third wiring layer 48, a protective layer 49 and a cover layer 50 are disposed in order. FIG. 5B shows a plan view of the third wiring layer 48, and the protective layer 49 and the cover layer 50 are not shown.

  In the semiconductor device 40, the distance between the wiring 44 a and the wiring 44 b in the first wiring layer 44 is shorter than the distance between the wiring 44 a or the wiring 44 b and other wiring in the first wiring layer 44. In this specification, the distance between the wiring 44a and the wiring 44b is the shortest distance among the distances between the wiring 44a and the wiring 44b. In this specification, the other wiring in the first wiring layer 44 means a wiring that is not electrically connected to the wiring 44a or the wiring 44b. Accordingly, the wiring 44ac and the wiring 44c that are electrically connected to the wiring 44a do not correspond to other wirings.

  Similarly, the distance between the wiring 44c and the wiring 44d in the first wiring layer 44 is shorter than the distance between the wiring 44c or the wiring 44d and another wiring in the first wiring layer 44. In this specification, the distance between the wiring 44c and the wiring 44d is the shortest distance among the distances between the wiring 44c and the wiring 44d. In this specification, the other wiring in the first wiring layer 44 means a wiring that is not electrically connected to the wiring 44c or the wiring 44d. Therefore, the wiring 44ac and the wiring 44a that are electrically connected to the wiring 44c do not correspond to other wirings.

  For example, the distance between the wiring 44c and the wiring 44d is shorter than the distance between the wiring 44d and the wiring 44e.

  In the semiconductor device 40, the distance between the wiring 44a and the wiring 44b is shorter than the distance between the wiring 44b and the wiring 44c. The distance between the wiring 44c and the wiring 44d is shorter than the distance between the wiring 44c and the wiring 44b.

  In the semiconductor device 40, the wirings 44a, 44c, and 44ac and the wirings 44b and 44d are dummy wirings that are not electrically connected to the circuit elements including the circuit elements 42a, 42b, and 42c. The wirings 46a and 46b and the wirings 48a and 48b are also dummy wirings that are not electrically connected to the circuit elements including the circuit elements 42a, 42b, and 42c. Similarly, the contacts 45a and 45b are dummy contacts that are not electrically connected to the circuit elements including the circuit elements 42a, 42b, and 42c.

  The wiring 44a has a recess S1 formed by a combination of the wiring 44ac and the wiring 44c. The wiring 44b is disposed in the recess S1. Since the wiring 44a is a dummy wiring, it is preferable to reduce the area of the wiring pattern to suppress parasitic capacitance and the like, thereby reducing the influence on the circuit. Therefore, in the semiconductor device 40, the recess 44 is provided in the wiring 44a, the wiring 44b is disposed in the recess S1, and the wiring 44d is disposed in the recess S2.

  Similarly, the wiring 44c has a recess S2 formed in combination with the wiring 44ac. The wiring 44d is disposed in the recess S2.

  For example, the semiconductor device 40 is preferably mounted and used in a card such as a smart card. For example, when the card on which the semiconductor device 40 is mounted is subjected to failure utilization analysis and is irradiated with an ion beam using a focused ion beam (FIB) device, the semiconductor device 40 uses the irradiated charge, By inducing internal discharge and destroying the circuit, analysis can become impossible. Next, this function of the semiconductor device 40 will be described below.

  FIG. 6 is a diagram illustrating a state in which the semiconductor device illustrated in FIG. 5 is irradiated with an ion beam.

  In the semiconductor device 40 irradiated with the ion beam 31 from the ion gun 30 of the FIB apparatus, the wiring 46b of the second wiring layer 46 is exposed. The exposed wiring 46b is irradiated with the ion beam 31 and supplied with positive charges. Then, a positive charge is supplied and accumulated in the lower wiring 44d electrically connected to the wiring 46b via the contact 45b.

  The wiring 44c opposed to the wiring 44d through the insulator portion of the first wiring layer 44 is supplied with negative charges from the ground corresponding to the accumulation of positive charges in the wiring 44d and accumulates.

  As the ion beam 31 is irradiated from the ion gun 30, the amount of charge accumulated in the wiring 44d and the wiring 44c increases and is applied to the insulator portion of the first wiring layer 44 between the wiring 44d and the wiring 44c. Increased voltage. When the voltage applied to the insulator portion of the first wiring layer 44 exceeds the dielectric breakdown voltage, a discharge is generated between the wiring 44d and the wiring 44c as shown in FIG. The electrical energy of the discharge can destroy the insulating portion of the first wiring layer 44 and can destroy surrounding contacts, wiring, and circuit elements.

  The induction of discharge depends on the distance between the wiring 44d and the wiring 44c. The distance between the wiring 44d and the wiring 44c can be set as appropriate within the precision of the microfabrication technique used. Thus, the discharge can be controlled by setting the distance between the wiring 44d and the wiring 44c.

  In the example of FIG. 6, the ion beam is applied to the wiring 46 b of the second wiring layer 46. However, when the ion beam is applied to the wiring 46 a of the second wiring layer 46, the wiring is similarly performed. A discharge can be induced between 44b and the wiring 44a.

  According to the semiconductor device of the present embodiment described above, information is prevented from being read by inducing a discharge between the wirings when the charged particles are irradiated, thereby preventing the semiconductor device 40 from operating normally. it can. Accordingly, unauthorized analysis is prevented.

  The above-described embodiment has two pairs of dummy wirings, that is, the wirings 44a and 44b and the wirings 44c and 44d. You may do it.

  Next, Modification Example 1 and Modification Example 2 of the semiconductor device according to the second embodiment described above will be described below with reference to the drawings.

  FIG. 7 is a diagram illustrating a first modification of the second embodiment of the semiconductor device disclosed in this specification. FIG. 7 shows a plan view of the first wiring layer 44.

  In the semiconductor device of Modification Example 1, the wiring 44a has a convex portion 44f protruding toward the wiring 44b. The wiring 44b has a convex portion 44g that protrudes toward the wiring 44a. The convex portion 44f and the convex portion 44g oppose each other with an interval.

  When a discharge is generated between the wiring 44a and the wiring 44b, the probability that the discharge is generated between the convex portion 44f and the convex portion 44g is high, and the discharge location between the wirings can be controlled. Therefore, in the modified example 1, the reliability of controlling the induction of discharge between the wirings is improved.

  Similarly, the wiring 44c has a convex portion 44h protruding toward the wiring 44d. Further, the wiring 44d has a convex portion 44i protruding toward the wiring 44c. The convex portion 44h and the convex portion 44i are opposed to each other with an interval therebetween.

  FIG. 8 is a diagram illustrating a second modification example of the second embodiment of the semiconductor device disclosed in this specification. FIG. 8 is a plan view of the first wiring layer 44.

  In the semiconductor device of Modification Example 2, the wiring 44a does not have a recess formed in combination with the wiring 44ac. The wiring 44a and the wiring 44b are arranged so that the top of the wiring 44a and the top of the wiring 44b face each other. The distance between the top of the wiring 44a and the top of the wiring 44b is the shortest distance between the two wirings.

  When a discharge is generated between the wiring 44a and the wiring 44b, the probability that the discharge occurs between the tops is high, and the discharge location between the wirings can be controlled. Therefore, in the modified example 2, the reliability of controlling the induction of discharge between the wirings is improved.

  Similarly, the wiring 44c does not have a recess formed in combination with the wiring 44ac. The wiring 44c and the wiring 44d are arranged so that the top of the wiring 44c and the top of the wiring 44d face each other. The distance between the top of the wiring 44c and the top of the wiring 44d is the shortest distance between the two wirings.

  Next, a preferred first embodiment of a method for manufacturing a semiconductor device disclosed in this specification will be described below with reference to the drawings.

  This embodiment is an example of a method for manufacturing the semiconductor device shown in FIGS.

  First, as shown in FIGS. 9A and 9B, a first insulating layer 13 having a contact 13a and a first wiring layer having wirings 14a and 14b on an element layer 12 disposed on the substrate 11. 14 are formed in order. FIG. 9A shows a cross-sectional view taken along line X4-X4 of FIG.

  Next, as shown in FIGS. 10A and 10B, a second insulating layer 15 having contacts 15a, 15b, and 15c is formed on the first wiring layer. FIG. 10A shows a cross-sectional view taken along line X5-X5 of FIG. The contacts 15a and 15b are electrically connected to the lower wiring 14a. The contact 15c is electrically connected to the lower wiring 14b.

  Next, as shown in FIGS. 11A and 11B, the second wiring layer 16 having the wirings 16 a and 16 b is formed on the second insulating layer 15. FIG. 11A is a cross-sectional view taken along line X6-X6 of FIG. The wiring 16b is electrically connected to the lower layer contact 15c.

  Next, as shown in FIGS. 12A and 12B, the third insulating layer 17 having contacts 17 a, 17 b, and 17 c is formed on the second wiring layer 16. FIG. 12A is a cross-sectional view taken along line X7-X7 in FIG. The contact 17c is electrically connected to the lower wiring 16c. Here, in the step of forming the second wiring layer 16 shown in FIG. 11, the wiring is not arranged between the contact 15a and the contact 17a, and the wiring is not arranged between the contact 15b and the contact 17b. Then, the second wiring layer 16 is formed.

  In the step of forming the third insulating layer 17, the distance between the contact 15 a and the contact 17 a is such that the contact 15 a or the contact 17 a, the second insulating layer 15, the third insulating layer 17, and the second wiring layer 16 are inside. The third insulating layer 17 is formed so as to be shorter than the distance between the other contact or wiring. Similarly, in the step of forming the third insulating layer 17, the distance between the contact 15b and the contact 17b is such that the contact 15b or the contact 17b, the second insulating layer 15, the third insulating layer 17, and the second wiring layer 16 are separated. The third insulating layer 17 is formed so as to be shorter than the distance between the other contacts or wirings.

  Next, as shown in FIGS. 13A and 13B, a third wiring layer 18 having wirings 18 a, 18 b, and 18 c is formed on the third insulating layer 17. FIG. 13A is a cross-sectional view taken along line X8-X8 in FIG. The wiring 18a is electrically connected to the lower layer contact 17a. The wiring 18b is electrically connected to the lower layer contact 17b. The wiring 18c is electrically connected to the lower layer contact 17c.

  Then, the protective layer 19 and the cover layer 20 are sequentially formed on the third wiring layer 18 to form the semiconductor device shown in FIGS.

  Next, a second preferred embodiment of the method for manufacturing a semiconductor device disclosed in this specification will be described below with reference to the drawings.

  This embodiment is an example of a method for manufacturing the semiconductor device shown in FIGS.

  First, as shown in FIGS. 14A and 14B, a first insulating layer 43 having a contact 43a and wirings 44a, 44b, 44c, 44d, 44e on an element layer 42 disposed on a substrate 41. , 44ac and the first wiring layer 44 are formed in order. FIG. 14A is a cross-sectional view taken along line X9-X9 in FIG. Here, the wiring 44 a and the wiring 44 b are formed so that the distance between the wiring 44 a and the wiring 44 b is shorter than the distance between the wiring 44 a or the wiring 44 b and the other wiring in the first wiring layer 44. Is done. Further, the wiring 44c and the wiring 44d are formed so that the distance between the wiring 44c and the wiring 44d is shorter than the distance between the wiring 44c or the wiring 44d and the other wiring in the first wiring layer 44. The

  Next, as shown in FIGS. 15A and 15B, a second insulating layer 45 having contacts 45 a, 45 b and 45 c is formed on the first wiring layer 44. FIG. 15A is a cross-sectional view taken along line X10-X10 in FIG. The contact 45a is electrically connected to the underlying wiring 44b. The contact 45b is electrically connected to the underlying wiring 44d. The contact 45c is electrically connected to the underlying wiring 44e.

  Next, as shown in FIGS. 16A and 16B, a second wiring layer 46 having wirings 46 a, 46 b and 46 c is formed on the second insulating layer 45. FIG. 16A is a cross-sectional view taken along line X11-X11 in FIG. The wiring 46a is electrically connected to the lower layer contact 45a. The wiring 46b is electrically connected to the lower layer contact 45b. The wiring 46c is electrically connected to the lower layer contact 45c.

  Next, as shown in FIGS. 17A and 17B, a third insulating layer 47 having contacts 47 a is formed on the second wiring layer 46. FIG. 17A is a cross-sectional view taken along line X12-X12 in FIG. The contact 47a is electrically connected to the lower wiring 46c.

  Next, as shown in FIGS. 18A and 18B, a third wiring layer 48 having wirings 48 a, 48 b and 48 c is formed on the third insulating layer 47. FIG. 18A is a cross-sectional view taken along line X13-X13 in FIG. The wiring 48c is electrically connected to the lower layer contact 47a.

  Then, the protective layer 49 and the cover layer 50 are formed in order on the third wiring layer 48, and the semiconductor device shown in FIGS. 5A and 5B is formed.

  In the present embodiment, the wirings 44a, 44c, 44ac and the wirings 44b, 44d are dummy wirings that are not electrically connected to the circuit elements including the circuit elements 42a, 42b, 42c. It is formed so as not to be connected. Similarly, the wirings 46a and 46b, the wirings 48a and 48b, and the contacts 45a and 45b are formed so as not to be electrically connected to the circuit elements.

  Next, a third preferred embodiment of a method for manufacturing a semiconductor device disclosed in this specification will be described below with reference to the drawings.

  The present embodiment is another example of the method for manufacturing the semiconductor device shown in FIGS.

  First, as shown in FIGS. 19A and 19B, a first insulating layer 43 having a contact 43a and wirings 44a, 44c, 44e, and 44ac are provided on an element layer 42 disposed on a substrate 41. The first wiring layer 44 is formed in order. FIG. 19A shows a cross-sectional view taken along line X14-X14 of FIG.

  Next, as shown in FIG. 20A, a second insulating layer 45 is formed on the first wiring layer 44. In the second insulating layer 45, the portion of the second insulating layer 15 where the contact 45c is to be formed is etched to form a groove 61 in which the wiring 44e is exposed.

  Next, as illustrated in FIG. 20B, a resist layer 60 is formed over the second insulating layer 45. A part of the resist layer 60 is also filled in the groove 61.

  Next, as shown in FIG. 20C, the resist layer 60 is patterned to form openings at positions where the contacts 45a and 45b of the second insulating layer 45 are formed, and the second insulating layer 45 is exposed. To do.

  Next, as shown in FIG. 21A, using the resist layer 60 as a mask, the second insulating layer 45 and the first wiring layer 44 are etched to form grooves 62 and 63 to form the first insulating layer 43. Exposed.

  Next, as shown in FIG. 21B, the resist layer 60 is removed and the grooves 61 are exposed again.

  Next, as shown in FIGS. 22A and 22B, the conductors are filled in the grooves 61, 62, and 63, and the contact 45c, the wiring 44b and the contact 45a, and the wiring 44d and the contact 45b are formed. It is formed. FIG. 22A is a cross-sectional view taken along line X15-X15 in FIG.

  Then, through the same steps as those in FIGS. 16 to 18, the semiconductor device shown in FIGS. 5A and 5B is formed.

  According to the semiconductor device manufacturing method of the present embodiment described above, a semiconductor device can be manufactured using an existing mask pattern. In the present embodiment, an existing mask pattern is used in the step of forming the first wiring layer 44 shown in FIG. However, this mask pattern does not include the wirings 44b and 44d. Therefore, in the present embodiment, as shown in FIG. 20C, the resist layer 60 is patterned to form the wirings 44b and 44d together with the contacts 45a and 45b.

  In the present invention, the semiconductor device and the manufacturing method of the semiconductor device according to the above-described embodiments can be appropriately changed without departing from the gist of the present invention. In addition, the configuration requirements of one embodiment can be applied to other embodiments as appropriate.

  In the semiconductor device of the first embodiment described above, a discharge is induced using a pair of contacts, and in the semiconductor device of the second embodiment, a discharge is induced using a pair of wirings. Whether a pair of contacts or a pair of wirings is used as a structure for inducing discharge can be selected as appropriate for the structure of the circuit to be destroyed, and the semiconductor device can be designed.

  All examples and conditional words mentioned herein are intended for educational purposes to help the reader deepen and understand the inventions and concepts contributed by the inventor. All examples and conditional words mentioned herein are to be construed without limitation to such specifically stated examples and conditions. Also, such exemplary mechanisms in the specification are not related to showing the superiority and inferiority of the present invention. While embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions or modifications can be made without departing from the spirit and scope of the invention.

  Regarding the above-described embodiments, the following additional notes are disclosed.

(Appendix 1)
A first insulating layer having a first contact;
A second insulating layer having a second contact;
A wiring layer disposed between the first insulating layer and the second insulating layer;
With
No wiring is disposed in the portion of the wiring layer between the first contact and the second contact,
The distance between the first contact and the second contact is the first contact or the second contact and the other contact or wiring in the first insulating layer, the second insulating layer, and the wiring layer. Semiconductor device shorter than the distance between.

(Appendix 2)
The semiconductor device according to appendix 1, wherein a distance between an end of the first contact and an end of the second contact is the shortest distance between two contacts.

(Appendix 3)
The semiconductor device according to appendix 1 or 2, wherein the first contact and the second contact are opposed to each other so that at least a part thereof is overlapped with the wiring layer interposed therebetween.

(Appendix 4)
The semiconductor device according to claim 1, wherein the first contact is connected to a grounded wiring.

(Appendix 5)
A wiring layer having a first wiring and a second wiring;
A distance between the first wiring and the second wiring is shorter than a distance between the first wiring or the second wiring and another wiring in the wiring layer, and the first wiring. And the second wiring is not electrically connected to the circuit element.

(Appendix 6)
The semiconductor device according to appendix 5, wherein the second wiring is connected to a wiring arranged in another wiring layer on an upper layer through a contact.

(Appendix 7)
The semiconductor device according to appendix 5 or 6, wherein the first wiring has a recess, and the second wiring is disposed in the recess.

(Appendix 8)
The semiconductor according to any one of appendices 5 to 7, wherein a distance between the top of the first wiring and the top of the second wiring is the shortest distance between two wirings. apparatus.

(Appendix 9)
The semiconductor device according to any one of appendices 5 to 8, wherein the first wiring is a grounded wiring.

(Appendix 10)
Forming a wiring layer on the first insulating layer having the first contact;
Forming a second insulating layer having a second contact on the wiring layer;
With
In the step of forming the wiring layer, the wiring layer is formed so as not to place a wiring between the first contact and the second contact,
In the step of forming the second insulating layer, the distance between the first contact and the second contact is the first contact or the second contact, the first insulating layer, the second insulating layer, and the A method of manufacturing a semiconductor device, wherein the second insulating layer is formed so as to be shorter than a distance between another contact or wiring in the wiring layer.

(Appendix 11)
Forming a wiring layer having a first wiring and a second wiring;
The first wiring such that a distance between the first wiring and the second wiring is shorter than a distance between the first wiring or the second wiring and another wiring in the wiring layer. And a method of manufacturing a semiconductor device, wherein the second wiring is formed, and the first wiring and the second wiring are formed so as not to be electrically connected to a circuit element.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Board | substrate 12 Element layer 12a, 12b, 12c Circuit element 13 1st insulating layer 13a Contact 14 1st wiring layer 14a, 14b Wiring 15 2nd insulating layer 15a, 15b, 15c Contact 16 2nd wiring layer 16a, 16b Wiring 17 Third insulating layer 17a, 17b, 17c Contact 18 Third wiring layer 18a, 18b, 18c Wiring 19 Protective layer 20 Cover layer 30 Ion gun 31 Ion beam 40 Semiconductor device 41 Substrate 42 Element layer 42a, 42b, 42c Circuit element 43 First insulating layer 43a Contact 44 First wiring layer 44a, 44b, 44c, 44d, 44e Wiring 44f, 44g, 44h, 44i Wiring protrusion 45 Second insulating layer 45a, 45b, 45c Contact 46 Second wiring layer 46a , 46b, 46c Wiring 47 Edge layer 47a Contact 48 Third wiring layer 48a, 48b, 48c Wiring 49 Protective layer 50 Cover layer 60 Resist layer 61, 62, 63 Groove

Claims (5)

A first insulating layer having a first contact;
A second insulating layer having a second contact;
A wiring layer disposed between the first insulating layer and the second insulating layer;
With
No wiring is disposed in the portion of the wiring layer between the first contact and the second contact,
The distance between the first contact and the second contact is the first contact or the second contact and the other contact or wiring in the first insulating layer, the second insulating layer, and the wiring layer. Semiconductor device shorter than the distance between.   2. The semiconductor device according to claim 1, wherein the first contact and the second contact face each other so that at least a part thereof is overlapped with the wiring layer interposed therebetween.   The semiconductor device according to claim 1, wherein the first contact is connected to a grounded wiring. A wiring layer having a first wiring and a second wiring;
A distance between the first wiring and the second wiring is shorter than a distance between the first wiring or the second wiring and another wiring in the wiring layer, and the first wiring. And the second wiring is not electrically connected to the circuit element. Forming a wiring layer on the first insulating layer having the first contact;
Forming a second insulating layer having a second contact on the wiring layer;
With
In the step of forming the wiring layer, the wiring layer is formed so as not to place a wiring between the first contact and the second contact,
In the step of forming the second insulating layer, the distance between the first contact and the second contact is such that the first contact or the second contact, the first insulating layer, the second insulating layer, and A method of manufacturing a semiconductor device, wherein the second insulating layer is formed so as to be shorter than a distance between other contacts or wirings in the wiring layer.

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