JPH11204767A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration or the like of a gate oxide film which is to be generated in forming a metal wiring connected with a gate electrode by using plasma etching, without specially preparing a region for antenna ratio countermeasure. SOLUTION: A gate array is provided with a PMOS transistor group 11 formed in a first region AR1 in and on the surface of a silicon substrate 6, an NMOS transistor group 12 formed in a second region AR2, and an aluminum wiring 7 which is stretched and formed along the arrangement direction AD1 of both of the transistors, in a third region AR3 between the first and the second regions, and whose one end portion side is electrically connected with gate electrodes 1-1 and 1-2. The aluminum wiring 7 is further branched into two directions in the way of wiring, and a branch wiring 9-1 or 9-2 is electrically connected with a diffusion region 22-1 or 22-2, respectively, of a transistor 20 which has not been used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for improving an antenna ratio in a semiconductor device having a gate array, and more particularly to a deterioration of a gate insulating film caused by a plasma etching process in a manufacturing process of a MOS transistor. Related to technologies that can be used to prevent such problems.

[0002]

2. Description of the Related Art In recent years, demand for ICs and LSIs for specific applications has been steadily increasing. Among them, one of the representative AISCs is a gate array, which is a Pch (p
(Type), Nch (n-type) basic cells composed of a pair of MOS transistors are arranged in an array in advance, and wiring based on a logic circuit for a specific application or user is arranged for the arranged gates. To obtain a desired IC. For this reason, in the gate array, it is only necessary to form a predetermined wiring on a chip (wafer) completed before the wiring process, so that the development period is very short as compared with a full custom IC. There is. Such an advantage is cited as one of the factors for the demand increase of the ASIC as described above.

As described above, the basic cell is constituted by four MOS transistors at the gate. Therefore,
The basic structure of one MOS transistor will be described with reference to cross-sectional structural diagrams (FIGS. 7 to 9) in each manufacturing process.

First, as shown in FIG. 7, a field oxide film (LOCOS) 64 is formed on one surface of a p-type semiconductor substrate 56 made of a silicon wafer as a base material. An element region that is electrically insulated and separated from the element (not shown) is formed. The gate insulating film 53 is formed on the active region on the surface of the semiconductor substrate 56 and the gate electrode 51 (here, polysilicon is used as the material) on the surface of the gate insulating film 53 by photolithography. And is formed as shown in FIG. Then, using the gate electrode 51, the gate insulating film 53 and the field oxide film 64 as a mask, an n-type impurity such as phosphorus (P) is entirely ion-implanted from the surface of the semiconductor substrate 56 to a predetermined depth. Then, the impurities implanted in the semiconductor substrate 56 are diffused by performing a heat treatment on the semiconductor substrate 56.
By this implantation / diffusion step, a diffusion region 52 serving as a source region and a drain region of the MOS transistor is formed, and at the same time, an n-type impurity is implanted /
Since the diffusion is performed, the conductivity of the gate electrode 51 can be improved.

Thereafter, the exposed diffusion region 52, gate electrode 51, gate insulating film 53, field oxide film 64
Is formed so as to cover all of the layers.

[0008] Next, as shown in FIG.
Is selectively etched to form a contact hole reaching the gate electrode 51 and the diffusion region 52, fill the inside of the contact hole, and entirely cover the upper surface of the interlayer insulating film 62. Here, aluminum is used as the material).

Then, by selectively etching the conductive film 65, as shown in FIG.
The wiring 57 or 58 electrically connected to the first or diffusion region 52 is formed. Thereafter, an insulating film 63 made of SiO2, PSG or the like is further formed so as to cover the wirings 57 and 58 and the exposed surface of the interlayer insulating film 62, and a MOS transistor having a cross-sectional structure as shown in FIG. 9 is completed. I do. Note that, in a highly integrated semiconductor chip such as a gate array, wiring and the like are further formed on the surface of the insulating film 63, and thus the insulating film may be referred to as an interlayer insulating film 63.

As described above, in an ASIC including a MOS transistor as a basic component, similarly to a semiconductor device such as a memory, a high integration of mounted elements such as a transistor and a miniaturization of a chip are strongly demanded. Recently, a channelless ASIC has been developed, and it is becoming possible to achieve higher integration and smaller size.

[0009]

In the above-described manufacturing process, the conductive film 65 formed entirely on the upper surface of the interlayer insulating film 62 in FIG. 8 is replaced with a wiring 57 as shown in FIG.
And 58, a method is employed in which an unnecessary portion of the conductive film 65 is removed by etching using a photolithography technique and a plasma etching technique. During the plasma etching, a portion of the conductive film 65 to be etched is exposed to the plasma, so that the conductive film 65 is charged with electric charge due to the plasma region via the portion, and thus the conductive film 65 and the conductive film 65 are charged. A portion electrically connected to the conductive film 65 is charged by the electric charge. Therefore, at the time of plasma etching, the gate electrode 51 electrically connected to the conductive film 65 is in a charged state. For this reason, the gate insulating film 53 sandwiched between the gate electrode 51 and the surface of the semiconductor substrate 56 has An electric field resulting from such a charged state is applied, and the electric field induces deterioration of the film quality of the gate insulating film 53. In particular, when this electric field is high, the gate insulating film 53 does not function at all. The deterioration of the film quality of the gate insulating film 53 not only leads to deterioration of various performances of the MOS transistor, for example, fluctuation of the threshold voltage, but also hinders even the original operation of the MOS transistor.

Further, in order to meet the demand for miniaturization and high integration of a semiconductor integrated circuit including an ASIC as described above,
As the miniaturization of the MOS transistor, which is a basic component, is advanced, the gate insulating film is also thinned accordingly,
The electric field applied to the gate insulating film at the time of the above-described plasma etching becomes larger, and the quality of the gate insulating film deteriorates and the above-mentioned problems resulting therefrom become more serious.

Here, the conductive film 6 at the time of plasma etching is used.
The charged state of the gate electrode 5 and the gate electrode 51 will be considered with reference to FIGS.

In the step of forming the wiring 57 connected to the gate electrode 51 and the wiring 58 connected to the diffusion region 52, the conductive film 65 is subjected to plasma etching.
The charge Q charged to the gate insulating film 53 and the interlayer insulating film 62 is represented by ε, the width and length (in the direction perpendicular to the paper) of the gate electrode 51 are respectively set to W and L (not shown), and the gate electrode 5
1 is the distance between the surface of the semiconductor substrate 56 and D
Is the width and length (in the direction perpendicular to the paper) of w, l (not shown), the distance between the wiring 57 and the surface of the semiconductor substrate 56 is d, and the charging potential of the wiring 57, that is, the gate electrode 51 is V. Then, it is represented by the following equation.

[0013]

(Equation 1)

The density ρ of the charge distributed on the gate electrode 51 is expressed by the following equation.

[0015]

(Equation 2)

Therefore, the area (L · W) of the gate electrode 51
Is smaller than the area (l · w) of the wiring 57 electrically connected to the gate electrode 51, that is, when the antenna ratio described later is large, the density ρ of the charge distributed to the gate electrode 51 increases. Therefore, the electric field applied to the gate insulating film 53 increases, which may cause deterioration of the film quality of the gate insulating film 53 and the like. Here, since the antenna ratio is defined as the ratio of the area of the wiring 57 electrically connected to the gate electrode 51 to the area of the gate electrode 51, the charged gate electrode 51 and the wiring 57 And the charge distribution ratio. In other words, the antenna ratio can be used as an index indicating the easiness of deterioration of the gate insulating film 53 during the above-described plasma etching.

Incidentally, the gate insulating film 53 as described above
As a countermeasure for preventing a phenomenon such as deterioration of the antenna, it is conceivable to improve the antenna ratio, that is, to reduce the antenna ratio. From this point of view, when the first-layer wiring 57 electrically connected to the gate electrode 51 in the gate array becomes longer, as shown in FIG. The second-layer wiring 67 (corresponding to the wiring 57 in FIG. 9) is formed above the first-layer wiring 67 via an interlayer insulating film (not shown; corresponding to the insulating film 63 in FIG. 9). The first wiring 69 is formed by filling the first wiring 69 with a conductive material therein.
Hole 7 for electrically connecting the wiring 7 to the second-layer wiring 69
0 (hereinafter, referred to as "through hole 70") has been proposed (see JP-A-8-306922). When the first layer wiring 67 is formed by plasma etching by such means, the length of the first layer wiring 67 on the side connected to the gate electrode 68 (corresponding to the gate electrode 51 in FIG. 9) is reduced. This is shorter than the case where the first layer wiring 67 is not divided, so that the antenna ratio can be reduced as compared with the case where the second layer wiring 69 is not provided, and the gate insulation can be reduced. Deterioration of the film 53 (not shown, which corresponds to the gate insulating film 53 in FIG. 9) can be reduced.

However, compared to the structure having only the first-layer wiring 67, the above-described means further requires the second-layer wiring 69 and the through hole 70.
The wiring to be originally formed on the surface of the interlayer insulating film (not shown; corresponding to the insulating film 63 in FIG. 9) on which the wiring 69 of the layer is formed is designed to bypass the wiring 69 of the second layer. Therefore, there is a new problem that the wiring efficiency of the entire semiconductor chip deteriorates.

On the other hand, there is a prior art proposed in JP-A-8-306922. The prior art relates to suppression of accumulated charges when a polysilicon gate is formed by plasma etching. However, since the same measures as described above have been taken, the above-described plasma etching of the first-layer wiring is not performed. However, the same problem occurs.

Further, Japanese Patent Laid-Open Nos. 9-74200 and 9-74200 disclose a prior art in which a separate path is provided for releasing charges generated during plasma etching of wiring to the substrate side via a diffusion layer formed on the substrate surface. It has been proposed in JP-A-8-97416. However, Japanese Patent Application Laid-Open No. 9-742
According to the method proposed in Japanese Patent Publication No. 00 (00), (i) a wiring for releasing charges and a diffusion layer electrically connected to the wiring must be separately provided in proximity to a wiring connected to the gate electrode of the MOS transistor. (Ii) When the wiring and the diffusion layer are formed in the MOS transistor formation region, the MOS transistor formation region including the wiring and the diffusion layer becomes large. (Iii) Even when the wiring and the diffusion layer are formed in a space between antenna wirings (wirings connected to gate electrodes),
There is no change in reducing the wiring efficiency of the first layer wiring.

Further, the prior art proposed in Japanese Patent Application Laid-Open No. 8-97416 has the same problem as the above (ii).

Therefore, it is considered that it is not preferable to apply these three prior arts to an ASIC in which high integration of mounted elements and miniaturization of a chip are strongly required, similarly to a semiconductor device such as a memory.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is intended to improve the wiring efficiency of a semiconductor chip and effectively prevent the deterioration of the quality of a gate insulating film during a plasma etching process. It is an object of the present invention to provide a semiconductor device which can be prevented.

[0024]

(1) In the semiconductor device according to the first aspect of the present invention, a part of a wiring, one end of which is electrically connected to a gate electrode of a transistor to be used, in a gate array, It is electrically connected to a predetermined region of an unused transistor in the gate array.

(2) A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the predetermined region of the unused transistor is a diffusion region.

(3) The semiconductor device according to the third aspect of the present invention is the semiconductor device according to the first aspect, wherein the predetermined region of the unused transistor is a gate electrode.

(4) The semiconductor device according to the fourth aspect of the present invention is a semiconductor device wherein M
A wiring region having a diffusion layer formed in the surface of the semiconductor substrate is provided between the OS transistor groups, and a first portion thereof connected to a gate electrode of a transistor to be used is provided in the wiring region. And a second portion, which is electrically connected to each other via the diffusion layer, is formed so as to extend in the arrangement direction of the MOS transistors.

[0028]

(First Embodiment) FIG. 1 is a partial plan view showing an example of the configuration of a gate array which is a semiconductor device according to a first embodiment.

As shown in FIG. 1, the gate array is formed in a first region AR1 in and on the surface of the p-type silicon substrate 6.
A plurality of p-type MOS transistors 11 (first conductivity type transistor group) formed therein and a plurality of n-type MOS transistors 12 (second conductivity type transistor group) formed in the second region AR2 are provided. I have. Here, each of the transistor groups 11 and 12 includes a gate electrode 1 and a diffusion region 2 forming a source and a drain.
The gate electrode 1 of the OS transistor is denoted by the symbol 1-1, n-type M
The gate electrode of the OS transistor is denoted by reference numeral 1-2,
A hyphen and a numeral indicating whether it is the first conductivity type side or the second conductivity type side are further added to each code, so that the distinction is clearly specified as necessary. The same applies to the diffusion region 2 and other components.

The gate array shown in FIG. 1 has first and second gate arrays.
In the third region AR3 between the regions, the arrangement direction A of both
A first-layer aluminum wiring 7 extending along D1 and having one end electrically connected to the gate electrode 1 of the transistor to be used is further provided.

As shown in FIG. 1, power supply wirings 8 made of a conductive material such as aluminum are formed in the outer areas of both transistor groups 11 and 12 in parallel with the transistor arrangement direction AD1. The power supply wiring 8 and a predetermined gate electrode 1 of both transistor groups 11 and 12 are formed by wiring partially extending from the power supply wiring 8.
Alternatively, a predetermined diffusion region 2 is electrically connected.

Here, in the gate array, transistors connected to the power supply wiring 8 or the like, or transistors are electrically connected to each other as shown in FIG. "Used transistor") and transistors other than the used transistor (hereinafter, "transistor")
"Unused transistors"). Unused transistors are surrounded by broken lines 20 in FIG. Therefore, when it is necessary to specify the used transistor and the unused transistor, the reference numeral 10 (see FIG. 2) or the reference numeral 20 (see FIG.
Reference). Needless to say, the concept of an unused transistor includes a transistor to which no wiring is connected, and furthermore, even if a wiring or the like is connected, the transistor does not perform its original function, and a desired operation of the entire chip is not performed. This includes transistors that are not involved in the realization.

Further, as shown in FIG. 1, the aluminum wiring 7 is branched in two directions in the middle of the wiring, and a branched wiring 9- is formed.
Reference numeral 1 or 9-2 denotes a diffusion region 22-1 of an unused transistor.
Or 22-2.

The branch wiring 9 is formed simultaneously with the formation of the aluminum wiring 7 connected to the gate electrode 1 of the transistor to be used by plasma etching and without being separated from the aluminum wiring 7. By providing the branch wiring 9, charges charged to the aluminum wiring 7 and the branch wiring 9 during the plasma etching can be released to the substrate 6 via unused transistors. This will be described in detail below.

FIG. 2 is a sectional view taken along the line II ′ of the gate array shown in FIG.
It is the figure which looked at the longitudinal section by the line from the arrow direction. Since FIG. 2 shows a state after the formation of the aluminum wiring 7 and the branch wiring 9, an interlayer insulating film above the aluminum wiring 7 and the branch wiring 9 formed in a later step, or
The illustration of the second-layer aluminum wiring and the like formed on the interlayer insulating film is omitted.

As shown in FIG. 2, since the branch wiring 9-2 is electrically connected to the diffusion region 22-2 of the unused transistor 20, the aluminum wiring 7 and the branch wiring 9-2 are formed by plasma etching. At this time, the electric charges charged to the wirings 7 and 9-2 can escape to the silicon substrate 6 through the path indicated by the arrow A1 in FIG. 2, and the potential difference between the gate electrode 1 and the substrate 6 can be reduced. . Therefore, since the electric field applied to the gate insulating film 3 of the transistor 10 to be used can be greatly reduced, deterioration of the film quality of the gate insulating film 3 can be prevented. As described above, by reducing the charge density of the gate electrode 1, the antenna ratio can be improved (smaller) and deterioration of the film quality of the gate insulating film 3 can be prevented. The n-type diffusion region 22-
The diode structure formed by the p-type silicon substrate 6 and the p-type silicon substrate 6 acts particularly effectively on negative charges from the direction.

Since the p-type diffusion region 22-1 to which the branch wiring 9-1 is electrically connected is formed inside the n-type well 5 (see FIG. 1), the diffusion region 22-1 and the p-type diffusion region 22-1 are connected to each other. A pnp transistor is formed between the substrates. In such a case, when a positive charge flows into the diffusion region 22-1 through the branch wiring 9-1, the p-type diffusion region 22-1
Since a forward current flows through the diode structure formed between -1 and the n-type well 5, the transistor structure is turned on.
By discharging the electric charge charged to 1 through the transistor structure to the silicon substrate 6, the potential difference between the gate electrode 1 and the substrate 6 can be reduced. Accordingly, since the electric field applied to the gate insulating film 3 of the transistor 10 to be used can be greatly reduced, deterioration of the film quality of the gate insulating film 3 can be prevented as in the case of the branch wiring 9-2. As described above, the path for releasing the charge on the branch wiring 9-1 side particularly effectively acts on the positive charge.

The branch wiring 9 need not be in two directions as shown in FIG. 1, but may be in one direction. However, as described above, in the first embodiment, the branch wiring 9 is not used. By connecting to the p-type and n-type diffusion regions 22 of the transistor 20, it is possible to cope with both positive and negative charges and to effectively prevent deterioration of the film quality of the gate insulating film 3 and the like. It can be said that this is a preferable mode.

(Embodiment 2) An example of a configuration of a gate array which is a semiconductor device according to Embodiment 2 will be described with reference to a partial plan view shown in FIG.

In the second embodiment, instead of the branch line 9 (see FIG. 1) connected to the diffusion region 22 in the first embodiment, a branch electrically connected to the gate electrode 21 of the unused transistor 20 is used. The wiring 19 is employed, and the other configuration is the same as that of the first embodiment. Therefore, the following description will be focused on such differences. In FIG. 3, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. The notation after the hyphen is the same as that described in the first embodiment.

In the second embodiment, as shown in FIG.
The aluminum wiring 7 is branched in two directions in the middle of the wiring, and the branch wiring 19-1 or 19-2 is electrically connected to the gate electrode 21-1 or 21-2 of the unused transistor 20, respectively. Similar to the first embodiment, the branch wiring 19 is formed integrally with the aluminum wiring 7 connected to the gate electrode 1 of the transistor to be used by plasma etching and without being separated from the aluminum wiring 7. .

By providing the branch wiring 19, the antenna ratio can be improved, so that deterioration of the film quality of the gate insulating film 3 of the transistor 10 to be used due to charging of the wirings 7 and 19 during plasma etching can be prevented. it can. The reason will be described below with reference to FIG.

FIG. 4 is a sectional view taken along the line II-II 'of the gate array shown in FIG.
It is the figure which looked at the longitudinal section by the line from the arrow direction. In FIG. 4, as in FIG.
The illustration of the interlayer insulating film and the like above 9 is omitted.

As shown in FIG. 4, since the branch wiring 19-2 is electrically connected to the gate electrode 21-2 of the unused transistor 20, the aluminum wiring 7 and the branch wiring 19-2 are formed by plasma etching. The electric charges that are sometimes charged on these wirings 7 and 19-2 are indicated by arrows A2 in FIG.
Gate electrode 2 of the unused transistor 20 through the path of
1-2. Similarly, such charges can be dispersed to the gate electrode 21-1 by the branch wiring 19-1 in FIG. That is, in the gate array according to the second embodiment, the area of the gate electrode connected to the aluminum wiring
The antenna ratio is improved (reduced) by increasing the area of the gate electrode 21 of 0, thereby dispersing and reducing the amount of charge charged on the gate electrode 3 of the transistor 10 to be used. Therefore, the electric field applied to the gate insulating film 3 of the transistor 10 to be used can be reduced, so that the quality of the gate insulating film 3 can be prevented from being deteriorated.

In the gate array according to the second embodiment, the above-described effects can be exhibited irrespective of the polarity of the problematic charge.

According to the gate array which is the semiconductor device according to the first and second embodiments, the transistor 10
The wiring 7 connected to the gate electrode 1 is branched in the middle of the wiring, and the branch wiring 9 or 19 is connected to the unused transistor 2.
Since it is connected to a predetermined region of 0 (that is, the diffusion region 22 or the gate electrode 21), a portion that is originally an unused region can be effectively used.

Therefore, according to the present device, as in the conventional gate array and the second-layer aluminum wiring as in the prior art proposed in Japanese Patent Application Laid-Open No. Hei 8-306922,
It is no longer necessary to connect to the first layer of aluminum wiring which has been divided in advance,
It is no longer necessary to provide a separate area for releasing electric charges as in the prior art proposed in Japanese Patent Application Laid-Open No. H10-260,036. As described above, the technologies according to the first and second embodiments can improve the wiring efficiency of the entire semiconductor chip as compared with the above-described prior art, and can further reduce the chip size of the semiconductor device. That is what makes it work.

Third Embodiment Next, a structure of a semiconductor device according to a third embodiment will be described with reference to FIGS.

FIG. 5 is a plan view schematically showing the connection relationship between wirings 30 in wiring (channel) region AR4 formed between MOS transistor groups facing each other at a predetermined distance in the gate array. FIG. 6 is an enlarged plan view near the wiring area AR4 in FIG. In addition, FIG.
6, the same components as those in FIG. 1 or FIG. 3 are denoted by the same reference numerals, the description thereof will be omitted, and the gate array regions AR1 to AR3 will be described in order to avoid complication of the drawing.
Although the illustration of the connection state in is omitted, it does not affect the effect according to the third embodiment.

As shown in FIG. 6, in the wiring area AR4,
Wiring 30 divided into first portion 31 and second portion 32
(Made of aluminum or the like) is formed on the surface of the silicon substrate 6, and one end of the first portion 31 and one end of the second portion 32 of the wiring 30 are connected to the surface of the p-type silicon substrate 6. Are electrically connected to each other via an n-type diffusion layer 33 formed in advance. In this manner, one or a plurality of wirings 30 in which the first part 31 and the second part 32 are connected via the diffusion layer 33 are formed extending along the arrangement direction AD of the MOS transistor group. . In addition,
5 to 6, the wiring 30 is sandwiched between the diffusion layers 33.
Of the wiring 30 is connected to the diffusion layer 33, and the other end is connected to the gate electrode of a certain MOS transistor. The portion on the other side is defined as a first portion 31, and the portion on the other end connected to the wiring on the drive circuit side of the gate electrode is defined as a second portion 32. Further, the gate electrode to which the other end of the first portion 31 of the wiring 30 is connected is not limited to the gate electrode of the gate array, but may be any gate electrode of the MOS transistor in the semiconductor chip. As shown in FIG. 5, it may be a gate electrode of a MOS transistor in a memory module in the same chip.

Since the wiring 30 is formed in the form shown in FIG. 6, the wiring 30 is connected to the gate electrode (not shown) as compared with the case where the wiring 30 is not divided into the first portion and the second portion. The area of the wiring (first portion 31) becomes smaller, and the antenna ratio can be improved (smaller).

In addition, since the first portion 31 and the second portion 32 of the wiring 30 are electrically connected via the diffusion layer 33, the wiring 30 is charged when the wiring 30 is formed by plasma etching. The charge can be released to the substrate 6 through the diode structure including the n-type diffusion layer 33 and the p-type silicon substrate 6. Accordingly, the potential difference between the gate electrode to which the other end of the first portion 31 of the wiring 30 is connected and the substrate 6 can be reduced, and the gate insulating film existing between the gate electrode and the substrate 6 can be reduced. The electric field applied to the gate insulating film (not shown) can be reduced, and deterioration of the gate insulating film can be effectively prevented. Thus, from the viewpoint of the amount of charge charged to the gate electrode,
It can be said that the antenna ratio is improved (reduced).

Further, the first portion 3 of the wiring 30 is formed by the diffusion layer 33 formed in the surface of the semiconductor substrate 6 in the wiring region.
Since one end portions of the first and second portions 32 are connected to each other,
In other words, since the diffusion layer 33 is formed immediately below the region where one wire 30 is formed, the area of the semiconductor chip in which elements such as a gate array are formed does not increase. Therefore, it is not necessary to separately form a diffusion layer in the MOS transistor region unlike the prior arts proposed in JP-A-8-97416 and JP-A-9-74200. It is not necessary to form the wiring in the wiring region so as to bypass the charge release wiring as disclosed in the above. Therefore, the semiconductor device according to the third embodiment has an advantage that the integration of mounted elements and the size of the semiconductor chip can be further reduced as compared with the above-described prior art.

[0054]

(1) According to the first aspect of the present invention, a part of the wiring whose one end is connected to the gate electrode of the used transistor in the gate array is electrically connected to a predetermined region of the unused transistor. Therefore, through holes for electrically connecting the second-layer aluminum wiring and the first-layer aluminum wiring to the second-layer aluminum wiring as in the conventional gate array are not required (particularly). The same applies to the technology proposed in Japanese Unexamined Patent Publication No. Hei 8-306922), and further, as in the prior art proposed in Japanese Unexamined Patent Application Publication No. 9-74200, it is accumulated in the wiring when the wiring is formed by plasma etching. There is no need to provide a separate region for releasing charges. Therefore, the invention according to claim 1 can improve the wiring efficiency of the entire semiconductor chip from the viewpoint of the above and the above compared with the conventional gate array and the two prior arts. This also has the effect that the chip size can be further reduced.

(2) According to the second aspect of the invention, in addition to the effect (1) of the first aspect, a part of the wiring whose one end is connected to the gate electrode of the transistor used in the gate array is provided. Since it is electrically connected to the diffusion region of the unused transistor, electric charges charged to the wiring when the wiring is formed by plasma etching can be released to the semiconductor substrate side via the diffusion region of the unused transistor. That is, the antenna ratio can be improved (smaller) from the viewpoint of the electric charge charged to the gate electrode of the transistor used. Therefore, the potential difference between the gate electrode of the used transistor and the semiconductor substrate can be reduced as compared with the conventional gate array, and as a result, the electric field applied to the gate insulating film of the used transistor can be reduced. The effect that deterioration of the film quality of the gate insulating film during the plasma etching step can be effectively prevented can be obtained.

(3) According to the third aspect of the invention, in addition to the effect (1) of the first aspect, a part of the wiring whose one end is connected to the gate electrode of the transistor used in the gate array is provided. Since the gate electrode of the unused transistor is electrically connected to the gate electrode of the unused transistor, the area of the gate electrode (irrespective of used and unused transistors) connected to the wiring can be increased. The antenna ratio with respect to the wiring can be improved (smaller). For this reason, when the wiring is formed by the plasma etching, the electric charge charged to the wiring can be dispersed also to the gate electrode of the unused transistor, and the deterioration of the film quality of the gate insulating film during the plasma etching step can be effectively prevented. The effect described above can be obtained.

(4) According to the fourth aspect of the present invention, in the wiring in the wiring region, the first portion and the second portion are electrically connected to each other via the diffusion layer formed in advance on the surface of the semiconductor substrate. Connected from the viewpoint of the area ratio between the gate electrode of the transistor to be used and the first portion connected to the gate electrode, and also from the viewpoint of the amount of charge charged to the gate electrode and the first portion. Also, since the antenna ratio can be improved (smaller), the same effects as the above (1) and (2) can be obtained. In addition, since the diffusion layer is formed in a wiring region existing outside the MOS transistor region, (i)
There is no need to form a diffusion layer in the MOS transistor region as in the prior art proposed in JP-A-97416 and JP-A-9-74200, and further (ii) disclosed in JP-A-9-74200. As described above, it is not necessary to form the wiring in the wiring region so as to bypass the charge release wiring. Therefore, the invention according to claim 4 provides the above (i)
And (ii) have an advantage over the prior art in that they can contribute to the miniaturization of the chip size of the semiconductor device without hindering the miniaturization of the MOS transistor.

Further, according to the fourth aspect of the present invention, the effect of preventing the gate insulating film from deteriorating in film quality can be sufficiently exhibited regardless of the presence or absence of unused transistors in the gate array.

(5) As described above, the inventions according to claims 2 to 4 have a common feature that deterioration of the film quality of the gate insulating film of the transistor used can be effectively prevented by improving the antenna ratio in any case. It has an effect.

(6) In addition, according to the first to third aspects of the present invention, a predetermined region of an unused transistor can be selected at the time of wiring design of a transistor to be used on each chip. The effects (1) to (3) can be obtained without increasing mask design and manufacturing steps.

Similarly, according to the invention of claim 4, the diffusion layer for electrically connecting the first portion and the second portion of the wiring in the wiring region is formed by another diffusion layer in each chip. Since it can be formed at the same time as the formation of the region (for example, the n-type diffusion region of the n-type MOS transistor), only a small change of the mask used in the relevant manufacturing process is required, and no additional mask design and manufacturing process are required. Thus, the effect (4) can be obtained.

[Brief description of the drawings]

FIG. 1 is a partial plan view showing a configuration of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a longitudinal sectional view illustrating a configuration of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a partial plan view showing a configuration of a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a longitudinal sectional view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a partial plan view showing a configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a partial plan view showing a configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a longitudinal sectional view showing a configuration in the middle of a manufacturing process of the MOS transistor.

FIG. 8 is a longitudinal sectional view showing a configuration during a manufacturing process of the MOS transistor.

FIG. 9 is a longitudinal sectional view showing a configuration of a MOS transistor.

FIG. 10 is a partial plan view showing a configuration of a semiconductor device according to a conventional technique.

[Explanation of symbols]

1 gate electrode, 2 diffusion region, 3 gate insulating film, 7
1st layer aluminum wiring, 9 branch wiring, 10 transistors used, 11 p-type MOS transistor, 12
n-type MOS transistor, 19 branch wiring, 20 unused transistor area, 21 gate electrode, 22 diffusion area, 30 wiring, 31 first part of wiring 30, 32
The second part of the wiring 30, the diffusion layer, the AR1 p-type MO
S transistor region, AR2 n-type MOS transistor region, AR3 first layer aluminum wiring region, AR4
Wiring (channel) area, AD MOS transistor array direction.

Claims (4)

[Claims] 1. A part of a wiring in a gate array, one end of which is electrically connected to a gate electrode of a used transistor, is electrically connected to a predetermined region of an unused transistor in the gate array. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the predetermined region of the unused transistor is a diffusion region. 3. The semiconductor device according to claim 1, wherein the predetermined region of the unused transistor is a gate electrode. 4. A wiring region having a diffusion layer formed in the surface of a semiconductor substrate is provided between a group of MOS transistors facing each other at a predetermined distance in a gate array. A wiring in which a first portion and a second portion connected to the gate electrode of a certain transistor are electrically connected to each other via the diffusion layer;
A semiconductor device, which is formed to extend along the direction in which S transistors are arranged.