JPH11317458A - Manufacture of semiconductor integrated circuit device and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the occurrences of defects in a gate insulating film by forming gate insulating films, having different thicknesses on a single-crystal semiconductor layer after the semiconductor layer is formed on a semiconductor substrate by the epitaxial method. SOLUTION: After a single-crystal semiconductor layer 1e is formed on a semiconductor substrate 1s by the epitaxial method without through an element forming process, gate insulating films 16i1 and 16i2 having relatively different thicknesses are formed on the epitaxial layer 1e containing very few crystal defects. Consequently, the occurrences of the defects in the gate insulating film 16i1 can be reduced in the forming process of the gate insulating films 16i1 and 16i2. Thus the decomposition of a defect in the gate insulating film 16i1 into such a serious defect that causes insulation breakdown of the insulating film 16i1 can be suppressed, in the course of cleaning treatment which is performed before second gate oxidation in the process of forming the two kinds of gate insulating films. Therefore, the possibility of the gate insulating films 16i1 and 16i2 causing insulation breakdown can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device technology, and more particularly, to a method of forming two or more gate insulating films having different design thicknesses on an element forming substrate. The present invention relates to a technology which is effective when applied to a manufacturing technology of a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Large scale integrated circuits (LSIs)
MIS (Metal Insula) that constitutes an Integrated Circuit
tor Semiconductor) Among the transistors, those that constitute the input / output circuit are supplied with a voltage determined by the external power supply and the input / output standards, while those that constitute the internal circuit optimize their performance. It is necessary to apply different voltages to the data. For example, a write / read storage device (DRAM; Dynamic
In Random Access Memory, it is more advantageous to apply a higher voltage to the MIS transistor in the memory cell than to the peripheral circuit in order to lengthen the data retention time. On the other hand, in the microcomputer / logic LSI, it is necessary to set the voltage applied to the MIS transistor of the internal circuit lower than the input voltage in order to reduce the power consumption.

By the way, in order to prevent the gate dielectric breakdown of the MIS transistor, it is necessary to keep the electric field intensity applied to the gate insulating film at about 4 MV / cm, so that only one kind of gate insulating film is formed on the semiconductor substrate. If not (hereinafter referred to as one type of gate insulating film process), the thickness is designed in accordance with the value required for the high-voltage portion. In this case, in the low voltage portion, the electric field strength is reduced, so that the driving capability of the transistor is reduced. As a result, LS
There is a problem that the processing speed of I decreases. In order to prevent this, it is necessary to make the gate insulating film in the low voltage part relatively thin while keeping the gate insulating film in the high voltage part relatively thick. That is, two or more types of gate insulating films having different designed thicknesses are formed on the semiconductor substrate.

A technique for forming two types of gate insulating films having different design thicknesses is disclosed in, for example,
-096378 (first document), JP-A-2-15
No. 374 (second document) and JP-A-8-1954.
No. 41 (third document).

In the first document, the gate insulating film of a low-voltage MIS transistor is made thinner than the gate insulating film of a high-voltage MIS transistor, and the gate electrodes of the low-voltage MIS transistor are used for low-voltage and high-voltage MIS transistors. In the second document, the first gate oxidation is performed, and after removing the gate insulating film other than the portion where the finished film thickness is increased, the second gate oxidation is performed. To form an MIS transistor having gate insulating films having different thicknesses by performing the above steps. Hereinafter, a technique for separately forming two types of gate insulating film thicknesses will be described in detail.

First, an element isolation film is formed on a semiconductor substrate pulled up by the Czochralski (hereinafter referred to as CZ) method.
After forming a well and a sacrificial oxide film, respectively, and performing ion implantation for adjusting the threshold voltage in the same manner as in the single-gate insulating film process, a first gate insulating film is formed. Subsequently, after selectively forming an etching mask on the region where the finished film thickness of the gate insulating film is to be increased, a gate insulating film which is not covered with the mask is formed using a solution having an effect of etching the insulating film. Remove the film. Then, after removing the etching mask and performing cleaning, a second gate oxidation is performed. At this time, in the region covered by the mask, further gate oxidation is performed with the insulating film formed by the first gate oxidation remaining, so that a gate insulating film thicker than the region not covered by the mask is formed. You. After that, the semiconductor device is completed through the same steps as the one-type gate insulating film process. In the following, regardless of the conventional method or the present invention,
A series of steps to create two types of gate insulating film thickness separately
This is referred to as a seed gate insulating film process.

Further, the above-mentioned third document (Japanese Unexamined Patent Publication No.
No. 95441) discloses a BiCMOS (Bipolar Complime) incorporating a bipolar transistor and a MOS transistor.
In an ntary MOS) type LSI, there is an example in which two types of gate insulating films having different thicknesses are formed after an epitaxial thin film is grown on the surface of a semiconductor substrate. In this example, first, high concentration n-type and p-type buried diffusion layers are formed. Since these diffusion layers need to be selectively formed, usually, a series of steps including a heat treatment at 800 ° C. or higher for the purpose of forming a resist mask, introducing a dopant by ion implantation, removing the resist, and recovering the implantation damage. It is formed by.

[0008]

However, the above-mentioned 2
The present inventors have found that there are the following problems in the seed gate insulating film process technology.

First, in the techniques of the first and second documents, since the semiconductor substrate formed by the CZ method is used, the first gate insulating film (relatively formed in the first oxidation step) is used. Defects due to crystal defects peculiar to the CZ method are formed in the gate insulating film to be thickened, and many of these defects are generally minor defects that are practically no problem.
After a necessary cleaning process in the subsequent two-type gate insulating film process, the gate insulating film is transformed into a severe defect that causes dielectric breakdown. As a result, the thick gate insulating film formed through the subsequent second oxidation process is subjected to dielectric breakdown. There is a problem that defects occur.

That is, as described above, after selectively forming an etching mask on a region where the finished film thickness of a gate insulating film is to be increased, and then etching away the gate insulating film in a region not covered by the mask, Contaminants adhere to the semiconductor wafer by the etching mask forming process and the etching process. If the second gate oxidation treatment is performed without sufficiently removing the contaminants, there is a problem that defects are formed in the gate insulating film not only in the region covered with the resist but also in the region not covered with the resist. Occurs. In addition, there is a problem that pollution accumulates in an oxidation furnace or the like. Therefore, in the two-type gate insulating film process, it is important to sufficiently remove contamination in the cleaning process before the second gate oxidation process, and the gate insulating film formed in the first oxidation process during the cleaning process is removed. The contaminants are removed by a so-called lift-off action that removes the etching to some extent. However, in the above technology,
Since a semiconductor substrate made by the CZ method is used,
A defect caused by a crystal defect peculiar to the CZ method is formed in the first gate insulating film. Many of these defects are generally minor defects that have no practical problem, but after the above-mentioned cleaning step, they are transformed into serious defects that cause dielectric breakdown due to the etching action in the cleaning step. Therefore, a dielectric breakdown failure occurs in the thick gate oxide film formed through the second oxidation step after the cleaning step. This problem is described in detail in, for example, Technil Digest of IDM, 1985, pp. 372-375.

In the technique of the third document,
Since the epitaxial thin film is formed after the dopant is implanted, a number of defects occur in the epitaxial thin film. In addition, the gate insulating film formed on the epitaxial thin film has a problem that dielectric breakdown failure occurs frequently. That is, in a semiconductor substrate into which a dopant is implanted at a high concentration, crystal defects caused by implantation damage cannot be eliminated even with a heat treatment at 1100 ° C. or more. According to the results of experiments conducted by the present inventors using the Zirtle etching method, about 10,000 crystal defects were observed per square centimeter. Since at least a part of these defects reach the surface of the semiconductor substrate as dislocations,
Due to these factors, a number of defects also occur in an epitaxial thin film formed thereafter. As a result, there is a problem that a gate insulating film formed on such an epitaxial thin film has many dielectric breakdown defects. Such a problem,
The total area of the gate insulating film is increasing with the increase in the degree of integration of the LSI, and is becoming more serious.

An object of the present invention is to provide a technique capable of reducing defects in a gate insulating film in a semiconductor integrated circuit device in which two or more gate insulating films having different thicknesses are provided on a semiconductor substrate. Is to do.

Another object of the present invention is to provide a technique capable of improving the yield and reliability of a semiconductor integrated circuit device in which two or more gate insulating films having different thicknesses are provided on a semiconductor substrate. Is to do.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a semiconductor single crystal layer is formed on a semiconductor substrate by an epitaxial method without going through a process for forming an element, and then a thickness is formed on the semiconductor single crystal layer. Forming different gate insulating films.

Further, the method for manufacturing a semiconductor integrated circuit device according to the present invention comprises: (a) a step of forming a semiconductor single crystal layer on a semiconductor substrate by an epitaxial method without going through a process for forming an element; First on the semiconductor single crystal layer
(C) forming a mask on the first gate insulating film to expose a formation region of the second gate insulating film, and then using the mask as an etching mask 1) removing the gate insulating film, (d) after the step (c), removing the mask, performing a cleaning process, and (e) after the step (d).
Forming a second gate insulating film, (f) forming a gate electrode on the first gate insulating film and the second gate insulating film subjected to the second gate insulating film forming process,
(G) forming a source / drain semiconductor region of a field effect transistor in the semiconductor single crystal layer.

Further, the method of manufacturing a semiconductor integrated circuit device according to the present invention includes a step of adding a gettering ability for capturing a contaminant element to the semiconductor substrate.

Further, the method for manufacturing a semiconductor integrated circuit device according to the present invention comprises: (a) forming a semiconductor single crystal layer on a semiconductor substrate by an epitaxial method without going through a process for forming an element; First on the semiconductor single crystal layer
(C) forming a first mask on the first gate insulating film to expose a formation region of a second gate insulating film, and then using the first mask as an etching mask, Removing the first gate insulating film exposed from the mask, (d) after the step (c), removing the first mask, performing a cleaning process, and (e) performing the step (d). After that, a step of forming a second gate insulating film,
(F) After forming a second mask on the first gate insulating film and the second gate insulating film which have been subjected to the second gate insulating film forming process, a region for forming a third gate insulating film is exposed. Removing the first or second gate insulating film exposed from the second mask using the same as an etching mask, (g) removing the second mask after the step (f), and then cleaning the substrate. (H) after the step (g), a step of forming a third gate insulating film, and (i) a step of forming the second or third or both of the gate insulating films. Forming a gate electrode on the gate insulating film, the second gate insulating film subjected to the third gate insulating film forming process, and the third gate insulating film, and (j) forming a field effect transistor on the semiconductor single crystal layer. Semiconductor region for source / drain Those that have a step of forming a.

The outline of the present invention other than the above is briefly described as follows.

That is, the method of manufacturing a semiconductor integrated circuit device according to the present invention comprises: (a) forming a semiconductor single crystal layer on a semiconductor substrate by an epitaxial method without going through a process for forming an element; Forming a first gate insulating film on the semiconductor single crystal layer; (c) forming a mask on the first gate insulating film to expose a formation region of the second gate insulating film; Removing the first gate insulating film exposed from the mask as an etching mask; (d) after the step (c), removing the mask and performing a cleaning process; (e) the step (d) Forming a second gate insulating film, (f) forming a gate electrode on the first gate insulating film and the second gate insulating film, and (g) applying an electric field to the semiconductor single crystal layer. Effect transistor A field-effect transistor having a step of forming a source / drain semiconductor region and having a gate insulating film formed by subjecting the first gate insulating film to a second gate insulating film forming a peripheral circuit of a memory MI
An S-transistor and a field-effect transistor having the second gate insulating film;
It is a transistor.

Further, in the method for manufacturing a semiconductor integrated circuit device according to the present invention, the semiconductor substrate and the semiconductor single crystal layer are made of silicon single crystal.

In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the thickness of the semiconductor single crystal layer is about 1 μm.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the semiconductor single crystal layer has a semiconductor region (well) having a distribution up to a position shallower than its thickness.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, the plurality of field effect transistors include a p-channel type MIS transistor and an n-channel type MIS transistor, and both of them have a channel conductivity type MIS transistor.
The transistors constitute a complementary MIS transistor.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that components having the same functions in all drawings for describing the embodiments are denoted by the same reference numerals.) , And the repeated explanation is omitted).

(Embodiment 1) FIG. 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a sectional view of a main part of the semiconductor integrated circuit device of FIG. 1, and FIGS. Is a cross-sectional view of a main part during a manufacturing process of the semiconductor integrated circuit device in FIG. 1,
8 and 9 are graphs and graphs showing the relationship between the electric field strength of the gate oxide film and the cumulative defect density of the gate oxide film, which are experimental results for further clarifying the improvement of the reliability of the gate oxide film according to the present invention. 10 is a graph showing the relationship between the electric field strength of the gate oxide film and the cumulative defect density of the gate oxide film, and FIG. 11 is a graph showing the relationship between the electric field strength of the gate oxide film and the cumulative defect density of the gate oxide film. FIG. 12 is a graph for explaining the grounds for judging the value at 8 MV / cm, and is a graph showing the relationship between the electric field strength of the gate oxide film and the average lifetime. FIG. For explaining the range of the etching film thickness and 8 MV / c
FIG. 4 is a graph showing a relationship between the cumulative defect density and the cumulative defect density at m.

The technical idea of the present invention is to provide gate insulating films having different thicknesses on an epitaxial layer formed on the surface of a semiconductor substrate. Hereinafter, in the first embodiment,
Although the technical idea of the present invention is not particularly limited, for example, a microprocessor (semiconductor integrated circuit device)
A description will be given of a case where the present invention is applied.

As shown in FIG. 1, for example, the main surface of a semiconductor chip 1C formed in a plane rectangular shape has an input / output circuit area 2, a phase lock loop circuit area 3, an instruction cache circuit area 4, a data cache circuit area. 5, floating point arithmetic circuit area 6, bus interface circuit area 7, input / output control circuit area 8, central arithmetic circuit area 9, arithmetic control circuit area 10, cache control circuit area 11, and other circuit areas 12 are arranged. I have. In the input / output circuit region 2 arranged near the outer periphery of the semiconductor chip 1C, a plurality of bonding pads BP having a small flat square shape are arranged at a predetermined distance along the outer periphery of the semiconductor chip 1C. . The bonding pad BP is an electrode for electrically connecting an integrated circuit inside the semiconductor chip 1C and an external device. The bonding pad BP has an input circuit, an output circuit, or both an input circuit and an output circuit of the input / output circuit area 2 on the semiconductor chip 1C side. And is electrically connected to wiring such as a package board or a printed wiring board through a bonding wire or a solder bump on the external device side. As a material of the bonding pad BP, for example, aluminum or an aluminum-silicon-copper alloy is used.

Of these circuit regions 2 to 12, the input / output circuit region 2 and the phase locked loop circuit region 3 and the other circuit regions 4 to 12 have respective MIS • FETs.
(Metal Insulator Semiconductor Field Effect Trans
In the former where the thickness of the gate insulating film constituting istor is different and a relatively high voltage is applied, a relatively thick gate insulating film of, for example, about 8 nm is formed and a relatively low voltage is applied. For the latter, which is expected to improve operation speed,
For example, a relatively thin gate insulating film of about 4.5 nm is formed. This makes it possible to prevent a gate breakdown failure in the input / output circuit region 2 and the phase-locked loop circuit region 3, and to improve the operation speed in the other circuit regions 4 to 12.
Although not particularly limited, the drive voltages of the circuits in the input / output circuit area 2 and the phase-locked loop circuit area 3 are relatively high in order to achieve consistency with an external device.
For example, it is about 3.3 V, and other circuit regions 4-1
The drive voltage of the second circuit is relatively low, for example, about 1.8 V, from the viewpoint of improving the operation speed, reducing the power consumption and securing the reliability.

Next, FIG. 2 is a sectional view of a main part of the semiconductor chip 1C. The element forming substrate 1 constituting the semiconductor chip 1C is configured by forming an epitaxial layer (semiconductor single crystal layer) 1e on the surface of a semiconductor substrate 1s.

The semiconductor substrate 1s has, for example, a plane orientation (10
0), made of a p-type silicon single crystal having a specific resistance of about 10 Ωcm, and formed by, for example, a crystal growth method using a CZ method. For example, boron is used as an impurity that determines the conductivity type of the semiconductor substrate 1s, and the impurity concentration distribution is substantially uniform in the semiconductor substrate 1s.
The impurity concentration of the semiconductor substrate 1s is, for example, 1.5 × 10 ¹⁵ c
m ⁻³ .

The semiconductor substrate 1s is provided with a means for improving the gettering ability for capturing the contaminant metal element. This is because the epitaxial wafer has almost no defects in the epitaxial layer, and the quality of the gate insulating film can be improved by forming the gate insulating film on the epitaxial layer, but the gettering ability is reduced. If the cleanliness in the etching mask forming process and the etching process described above is not appropriate when forming gate insulating films having different thicknesses, the contamination cannot be sufficiently removed by cleaning, and defects in the formed gate insulating film may be reduced. This is because there is an increased risk.
To prevent this, it is desirable to add gettering capability to the semiconductor substrate 1s.

The first method is a method of epitaxially growing a silicon film using a semiconductor substrate 1s having a high boron concentration (a density of 1 × 10 ¹⁷ / cm ³ or more), for example. The second method is a method in which a silicon film is epitaxially grown using a semiconductor substrate 1s in which a polycrystalline silicon film is previously formed on the back surface.

The third method is a method in which a relatively low temperature (600 ° C. to 900 ° C.) heat treatment is applied to the semiconductor substrate 1s in advance, and then a silicon film is epitaxially grown. A fourth method is a method in which the heat treatment of the third method is performed after the epitaxial growth of the silicon film, and this method is also effective in compensating for the decrease in the gettering ability. When the third method is compared with the fourth method, the third method has a higher gettering ability and a shorter processing time.

Further, the fifth method is a method of performing a heat treatment at 1100 ° C. or more in a step before the gate oxidation step. This is a method for improving the ability to capture metal contamination by promoting the growth of oxygen precipitates in the semiconductor substrate 1s, and is more effective when combined with the third method described above.

The improvement of the gettering ability makes the second
Since the cleaning process before the gate oxidation can be reduced, it is possible to obtain an excellent effect that the controllability and uniformity of the thickness of the relatively thick gate insulating film can be improved.

The epitaxial layer 1e is made of, for example, p-type silicon single crystal, and its thickness is set to be at least half the thickness of the relatively thick gate insulating film. In the first embodiment, the thickness of the epitaxial layer 1e is not particularly limited in consideration of various characteristics such as the characteristics of the device formed on the epitaxial layer 1e, the growth time of the epitaxial layer 1e, and economics. , For example, 1μ
m. The impurity concentration of the epitaxial layer 1e is the same as that of the semiconductor substrate 1s.

The epitaxial layer 1e has n wells 13NW1, 13NW2 and p wells 13PW1, 13P.
W2 is formed. n-well 13NW1, 13NW2
Is, for example, phosphorus introduced, and the p-well 13PW1,
13PW2 is, for example, boron introduced. This n
Wells 13NW1, 13NW2 and p-wells 13PW1,
The impurity concentration of 13PW2 is, for example, approximately 3 × 10 ¹⁷ cm ^-3. Each of the n-wells 13NW1, 13NW2 and the p-wells 13PW1, 13PW2 extends from the main surface of the epitaxial layer 1e in the thickness direction of the epitaxial layer 1e and extends to a depth in the middle of the epitaxial layer 1e. In addition, n well 13NW1,13
In some cases, the NW2 and the p-wells 13PW1 and 13PW2 may be formed to extend to a deeper position beyond the epitaxial layer 1e.

The main surface of the epitaxial layer 1e includes:
A shallow groove type separation part 14 is formed. This separation unit 14
Is a shallow groove 1 dug in the thickness direction of the epitaxial layer 1e.
An isolation insulating film 14b made of, for example, a silicon oxide film or the like is buried and formed in 4a. In addition, shallow groove 1
4a is dug to a position shallower than the n-wells 13NW1, 13NW2 and the p-wells 13PW1, 13PW2.

In the element formation region surrounded by the isolation portion 14, a p-channel MIS • FET (hereinafter abbreviated as pMIS) QP1, Q having a gate length of, for example, about 0.25 μm is provided.
P2 and n-channel type MIS-FET (hereinafter referred to as nM
QN1 and QN2 are formed. And
The complementary MIS-FE is formed by the pMIS and the nMIS.
In some areas, T is configured.

Each of the pMISs QP1 and QP2 has a pair of semiconductor regions 15pd and 15pd formed in each of the n-wells 13NW1 and 13NW2 and an epitaxial layer 1e.
Gate insulating films 16i1, 16i2 formed on the main surface of
And a gate electrode 17g formed on each of them. Each of the nMISs QN1 and QN2 has a pair of semiconductor regions 15nd and 15nd formed in each of the p-wells 13PW1 and 13PW2 and an epitaxial layer 1e.
Gate insulating films 16i1, 16i2 formed on the main surface of
And a gate electrode 17g formed on each of them.

The pair of semiconductor regions 15pd, 15pd are
This is a region for forming source / drain regions of pMISQP1 and QP2, and is formed apart from each other with a channel region interposed therebetween. Also, a pair of semiconductor regions 15n
Reference numerals d and 15nd denote regions for forming source / drain regions of the nMISs QN1 and QN2, which are formed apart from each other with the channel region interposed therebetween.

Each of the semiconductor regions 15pd and 15nd has low-concentration regions 15pd1 and 15nd1 and high-concentration regions 15pd2 and 15nd2.
15nd2 and a silicide layer 15d3.
The low concentration regions 15pd1 and 15nd1 are regions mainly for suppressing the hot carrier effect, and are adjacent to the channel region. In addition, the high concentration regions 15pd2, 15nd
2 is formed at a position two-dimensionally separated from the channel region by the plane dimension of the low concentration regions 15pd1 and 15nd1. The low density region 15pd1 and the high density region 15
pd2 is set to a p-type by introducing, for example, boron. The low-concentration region 15nd1 and the high-concentration region 15nd2 are formed, for example, by introducing phosphorus or arsenic.
Set to type. Note that the low-concentration regions 15pd1, 15
The impurity concentration that determines the conductivity type of nd1 is set lower than those of the high concentration regions 15pd2 and 15nd2.

The silicide layer 15d3 has a function of reducing the contact resistance between the semiconductor regions 15pd and 15nd and the wiring, and is made of, for example, titanium silicide, and is formed on the semiconductor regions 15pd and 15nd.
A pocket region for suppressing punch-through between the source and the drain may be provided near the bottom corner of the low-concentration regions 15pd1 and 15nd1 on the channel region side. This pocket region is set to a conductivity type opposite to the conductivity type of semiconductor regions 15pd and 15nd.

The gate insulating films 16i1 and 16i2 are both
For example, it consists of a silicon oxide film, but its thickness is different,
The thickness of the gate insulating film (first gate insulating film) 16i1 is formed to be larger than the thickness of the gate insulating film (second gate insulating film) 16i2. Gate insulating film 16i1
Has a thickness of, for example, about 8 nm, and has the input / output circuit area 2 and the phase-locked loop circuit area 3 (FIG. 1).
MISFET), and the gate insulating film 16i
The thickness of 2 is, for example, about 4.5 nm, and constitutes the MIS-FET of the above-described circuit regions 4 to 12 (see FIG. 1). By forming any of the gate insulating films 16i1 and 16i2 on the epitaxial layer 1e, the film quality can be improved, so that high reliability is obtained.

Note that both or the thinner of the gate insulating films 16i1 and 16i2 may be formed of an oxynitride film (SiON). As a result, the generation of interface states in the gate insulating films 16i1 and 16i2 can be suppressed.
Since electron traps in 6i1 and 16i2 can be reduced, it is possible to improve hot carrier resistance in gate insulating films 16i1 and 16i2. Therefore, the reliability of the gate insulating films 16i1 and 16i2 (particularly, the reliability of the thin gate insulating film 16i2) can be improved.

Such a gate insulating film 16i1, 16i2
As an oxynitriding method, for example, the gate insulating film 16i1,1
A method of performing a high-temperature heat treatment in an NH ₃ gas atmosphere or a NO ₂ gas atmosphere when forming 6i2 by oxidation, a gate insulating film 16i1,1 made of a silicon oxide film or the like;
After the formation of 6i2, a method of forming a nitride film on the upper surface thereof, a method of performing an oxidation treatment for forming gate insulating films 16i1 and 16i2 after ion-implanting nitrogen into the main surface of the epitaxial layer 1e, or a method of forming a gate electrode. After ion implantation of nitrogen into the polysilicon film, heat treatment is performed to deposit nitrogen on the gate insulating films 16i1 and 16i2.

The gate electrode 17g is made of a conductive film 17g.
1 has a two-layer structure in which a silicide layer 17g2 is provided. The conductor film 17g1 is made of, for example, low-resistance polysilicon. The silicide layer 17g2 has a function of lowering the electric resistance of the gate electrode 17g and lowering the contact resistance with the wiring. The silicide layer 17g2 is made of, for example, titanium silicide, and is formed in the same forming step as the silicide layer 15d3. .

However, the structure of the gate electrode 17g is not limited to this, and can be variously changed. For example, a single-layer structure of low-resistance polysilicon or a barrier such as titanium nitride or tungsten nitride is formed on low-resistance polysilicon. A polymetal structure in which a metal film such as tungsten is provided via a metal film may be used. When a polymetal structure is employed, the electric resistance of the gate electrode 17g can be significantly reduced. This structure is particularly effective when the gate width of the gate electrode 17g is long.

A side wall 18 made of, for example, a silicon oxide film, a silicon nitride film, or a composite film thereof is formed on the side surface of the gate electrode 17g. When the side wall 18 is formed of a silicon nitride film, the side wall 1 is formed when a connection hole exposing the semiconductor regions 15pd and 15nd is formed in the interlayer insulating film.
By making the hole 8 function as an etching stopper, the connection hole can be formed in a self-aligned manner with good alignment, so that the layout area of the element can be miniaturized, the reliability can be improved, and the characteristics can be improved.

On the main surface of such an element forming substrate 1,
Wirings 19L1 to 19L5 of the first to fifth layers are formed. An interlayer insulating film 20a is provided between the wiring layer of the first wiring 19L1 and the main surface of the epitaxial layer 1e. A connection hole 21a is formed in a part of the interlayer insulating film 20a so that the semiconductor regions 15pd and 15nd are exposed. In the connection hole 21a, for example, low-resistance polysilicon is buried to form a plug 22a. ing. The first-layer wiring 19L1 is made of, for example, tungsten or the like, and is formed through the plug 22a.
pd, 15nd.

Further, the wirings 19L2 to 19L2 to
19L5 is, for example, aluminum or aluminum-
It is made of a silicon-copper alloy, and interlayer insulating films 20b to 20e are provided between the respective wiring layers. In a part of each of the interlayer insulating films 20b to 20e, connection holes 21b to 21e are formed so as to expose the underlying wiring, and plugs 22b to 22e are formed in each of them. The plugs 22b to 22e are made of, for example, low-resistance polysilicon, tungsten, or titanium nitride, and the upper and lower wirings are electrically connected through the plugs. The interlayer insulating films 20a to 20e are made of, for example, a silicon oxide film. On this interlayer insulating film 20e, a surface protective film 23 is deposited, and thereby the fifth wiring 19L5 is covered. The surface protection film 23 is formed of, for example, a single film of a silicon oxide film or a composite film in which a silicon nitride film is deposited on a silicon oxide film.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS. Note that FIG.
7 are partially extracted from FIG. 1 for simplicity of description.

First, as shown in FIG. 3, the semiconductor substrate 1s
An element forming substrate 1 having an epitaxial layer 1e formed thereon is prepared.

The semiconductor substrate 1s is obtained by subjecting a semiconductor ingot obtained by, for example, the CZ method to appropriate processing steps such as external shape shaping, cutting (slicing), peripheral shape processing, lapping, etching, mirror polishing, cleaning, and inspection. Have been created. Note that boron and the like in the semiconductor substrate 1s are introduced during crystal growth by the CZ method or the like.

The epitaxial layer 1e is made of, for example, C
It is formed by the VD method. That is, for example, a source gas such as silicon tetrachloride, silane trichloride, dichlorosilane or monosilane is put on a carrier gas such as hydrogen and flowed over the surface of the semiconductor substrate 1s, and silicon is reduced on the surface of the semiconductor substrate 1s by hydrogen reduction or thermal decomposition. Is formed.

Subsequently, a shallow trench type isolation portion 14 is formed on the element forming substrate 1. This separation portion 14 is formed by digging a shallow groove 14a in the epitaxial layer 1e by photolithography and dry etching, and then forming the shallow groove 14a.
Is deposited on the epitaxial layer 1e containing, for example, a silicon oxide film or the like by a CVD method or the like, and furthermore, the isolation insulating film 14b is formed by CMP (Chem.
ical Mechanical Polishing) method, etc., shallow groove 1
It is formed by leaving the isolation insulating film 14b only in 4a.

Thereafter, a process of forming a sacrificial oxide film which serves both to modify the surface layer of the epitaxial layer 1e and to protect the surface from contamination in the next and subsequent steps, and to form n-wells 13NW1 and 13NW
2 and p-wells 13PW1 and 13PW2 (see FIG. 1) and an ion implantation process for adjusting the threshold voltage of each MIS • FET are sequentially performed. Then, the sacrificial oxide film is removed using, for example, a dilute hydrofluoric acid aqueous solution. Remove. The steps up to this point were based on a normal method except that the above-mentioned element forming substrate 1 was used.

Next, by subjecting the element forming substrate 1 to a first oxidation treatment, a gate insulating film 16i is formed on the epitaxial layer 1e as shown in FIG. In this oxidation treatment, for example, a wet oxidation treatment at about 800 ° C. was employed. The thickness of the gate insulating film 16i at this stage is equal in design over the entire main surface of the epitaxial layer 1e, for example, about 7.7 nm.

Here, "design" means including an error range, and "equal in design" means that the thicknesses intended in the oxidation process are equal, and the actual product was observed. Strictly speaking, it means that even if there is a portion having a different thickness, if it is within an error range, it is considered equal.

Subsequently, as shown in FIG. 5, a region for forming a relatively thick gate insulating film is covered on the main surface of the element forming substrate 1, and a relatively thin gate insulating film is formed. Pattern 24 exposing regions to be exposed
After a is formed by photolithography, the gate insulating film 16i is exposed in a region exposed from the photoresist pattern 24a by performing an etching process using, for example, a mixed aqueous solution of hydrofluoric acid and ammonium fluoride using this as an etching mask. The gate insulating film 16i is left in the region covered with the photoresist pattern 24a.

Then, after removing the photoresist pattern 24a by an ozone asher or the like, for example, a mixed aqueous solution of ammonia water and hydrogen peroxide heated to about 50 ° C., hydrochloric acid and hydrogen peroxide heated to about 80 ° C. And a diluted aqueous solution of hydrofluoric acid.

At this time, in the first embodiment, since the gate insulating film 16i is formed on the epitaxial layer 1e, there are very few defects inducing elements in the gate insulating film 16i. Insulating film 16i
Can be significantly reduced as compared with a case where the gate insulating film is formed on a normal semiconductor substrate without the epitaxial layer 1e.

Next, the element forming substrate 1 is subjected to a second oxidation treatment, so that the gate insulating films 16 having different thicknesses are formed on the epitaxial layer 1e as shown in FIG.
i1, 16i2 are formed. In this oxidation treatment, for example, 7
A wet oxidation treatment at about 50 ° C. was employed. At this stage, the thicknesses of the gate insulating films 16i1 and 16i2 are different from each other, and the thickness of the relatively thick gate insulating film 16i1 is, for example, about 8 nm.
The thickness of i2 is, for example, about 4.5 nm.

The reason why the thickness of the relatively thick gate insulating film 16i1 is substantially equal to the thickness (about 7.7 nm) of the gate insulating film 16i after the first oxidation treatment is as follows. This is because the upper layer portion of the gate insulating film 16i is slightly removed by a later cleaning process and then subjected to an oxidizing process again.
However, since the gate insulating film 16i has a good film quality as described above, even if the upper layer portion of the gate insulating film 16i is shaved by a cleaning process or the like, it is within the range of design (error), and a fatal defect is caused. Can be greatly reduced. In the case of a gate insulating film formed on a normal semiconductor substrate on which no epitaxial layer is provided, if the upper layer portion is shaved by a cleaning process or the like, the gate insulating film is present in the gate insulating film and does not pose a problem until then. In some cases, a fine hole reaching the main surface of the semiconductor substrate is formed in the gate insulating film starting from the exposed defect portion, resulting in a fatal defect.

Subsequently, as shown in FIG. 7, a conductor film 17 made of, for example, low-resistance polysilicon is formed on the gate insulating films 16i1 and 16i2 and the isolation portion 14 by a CVD method or the like. The conductive film 1 of the gate electrode 17g shown in FIG.
7 g1 are formed.

Thereafter, an insulating film covering the surface of the conductor film 17g1 is formed on the main surface of the element forming substrate 1 by a CVD method or the like, and the insulating film is etched back by anisotropic dry etching. As a result, the conductive film 17g
A side wall 18 (see FIG. 1) is formed on the side surface of the first side.

Further, after exposing the upper surface of the conductor film 17g1 and the upper surfaces of the semiconductor regions 15pd and 15nd, a conductor film such as titanium is coated on the main surface of the element forming substrate 1 by a sputtering method or the like. By performing heat treatment, the silicide layer 1 is formed on the conductive film 17g1 and on the semiconductor regions 15pd and 15nd, respectively.
7g2,15d3,15d3 are formed. Thereafter, the microprocessor shown in FIGS. 1 and 2 was completed through a normal manufacturing process of the semiconductor integrated circuit device.

Next, experimental results for more clearly confirming the effect of improving the reliability of the gate insulating film according to the technical concept of the present invention will be described with reference to FIGS.

FIGS. 8 and 9 show a MOS (Metal Oxide Semiconductor) formed through the same steps as the first embodiment up to the step of forming the first gate electrode, except for the points described later.
uctor) The cumulative density of defects was calculated by assuming a Poisson distribution based on the number of capacitors that had broken down when the electric field applied to the gate oxide film was increased using a capacitor. It is shown as a function.

The method of making the MOS capacitor is as follows.
The point that the etching mask formed on the entire semiconductor chip and that not formed at all are formed on the same semiconductor wafer and that the gate electrode is formed so as to cover the entire element forming region is the same as that of the above embodiment. 1 is different from the creation method. Thus, the thickness of the gate oxide film was separately formed for each chip. The thickness of each gate oxide film is 4.5 nm and 8 nm, respectively.

FIGS. 8 and 9 show the cumulative defects of the thin and thick gate oxide films as a function of the electric field strength applied to the gate oxide film, respectively. The intensity of the electric field applied to the gate oxide film in a normal use state is about 4 MV / cm. However, in order to prevent dielectric breakdown even when used for a long time (usually 10 years), FIGS. It is necessary to prevent dielectric breakdown even when an electric field of about 8 MV / cm, which is higher than the normal state, is applied in the short term as in the case of the measurement in the above. In view of the degree of integration of today's LSIs, it is necessary to reduce the density of defects that cause dielectric breakdown to at most 2 / cm ² , preferably 1 / cm ² or less. From FIGS. 8 and 9, according to the present invention, the defect density that causes the dielectric breakdown of the gate oxide film is almost 0 for the thinner gate oxide film and 1 defect / cm ² or less for the thicker one, which is required for today's LSI. It can be seen that the level has been sufficiently reached.

FIG. 10 shows a comparison between the results obtained when an epitaxial silicon substrate or the like described in the present invention and a semiconductor substrate formed by the CZ method (abbreviated as a CZ substrate) are used as element forming substrates. The MOS capacitor used to obtain this figure is such that the first thermal oxide film has a thickness of 18 nm, the second thermal oxide film has a thickness of 12 nm, and the resist mask is heated at 120 ° C. while supplying ozone gas. 8 and 9 except that it was removed in concentrated sulfuric acid (hereinafter referred to as ozone sulfuric acid) heated in FIG. Finished gate oxide film thickness is 12nm and 25nm respectively
Met.

As is apparent from FIGS. 8 and 9, the reliability of the relatively thick gate oxide film is inferior.
A value of 0 indicates a result for a relatively thick gate oxide film. From FIG. 10, according to the present invention, the defect density causing dielectric breakdown of the gate oxide film is greatly reduced from 5 / cm ² of the technology using the CZ substrate to 0.7 / cm ² , The effectiveness of the present invention can be confirmed again.

When comparing the results of FIGS. 8 to 10, it can be seen that the defect density of the gate oxide film on the thick film side is at the same level regardless of whether the resist is removed with ozone asher or ozone sulfuric acid. Therefore, there is an advantage in manufacturing that removing the resist with an ozone asher can reduce dangerous work and the amount of harmful chemicals used. In addition, when a plasma asher called "low damage" is used for removing the resist, almost the same result can be obtained in terms of the reliability of the gate oxide film. In some cases, the dielectric breakdown of the oxide film is increased or the film thickness is reduced. Further, even when the same type of plasma asher is used, the dielectric breakdown of the gate oxide film may be increased depending on the production line as compared with the case where the ozone asher is equivalent. Therefore, when a plasma asher is used for removing the resist, sufficient examination is required.

Next, the basis for determining the defect density at 8 MV / cm will be described. Normal operating conditions (applied voltage 4M
(V / cm) within 10 years (3 × 10 ⁸ seconds), the defect that causes dielectric breakdown in the gate oxide film is 8M in the dielectric strength measurement.
It is estimated that an applied voltage of V / cm or less causes dielectric breakdown. The basis is as follows.

The defect-free gate oxide film is formed of Ta (I
NTRINSIC). The figure shows that t50 = Aexp (B / Fox) (where, however, based on the average life t50 experimentally obtained in the range of 11 to 15 MV / cm using a small (area 10 ⁻⁶ cm ² ) MOS capacitor). A and B have been interpolated and extrapolated using the relationship of a constant obtained by fitting with the experiment.
Note that the above equation is based on Proc. IEEE 1991 In.
t. Conf. MicroelectronicTes
t Structures 4, 17-21 (1991)
There is a description.

It is known that the acceleration of the electric field of dielectric breakdown caused by defects can be predicted by assuming that the thickness of an oxide film is locally thin. Therefore, the average life t50 under operating conditions (4 MV / cm) is 10 years (3 × 10
The thickness of the oxide film defect is determined by fitting so as to be ⁸ seconds. Assuming that a defect having a half of the original thickness exists in the oxide film, the life was predicted and the result of Tb in FIG.
(WEAK SPOT). In a normal dielectric breakdown voltage measurement (TZDB), a voltage is applied to the insulating film for about 0.1 second, and then the presence or absence of dielectric breakdown is determined. Therefore, the electric field strength corresponding to this is 8 MV when read from the above Tb.
/ Cm.

Next, in the examination process leading to the present invention,
Now that the present invention has found a range of the gate insulating film thickness that is particularly effective, this will be described with reference to FIG. The figure shows that a gate oxide film is formed by using a CZ substrate (technique studied by the inventor) and a substrate in which an epitaxial silicon film is formed on the CZ substrate (the present invention). For example, the oxide film is etched in a dilute hydrofluoric acid aqueous solution. FIG. 11 shows the results of measuring the defect density of the gate oxide film of the MOS capacitor formed by forming the gate electrode after the formation in the same manner as in FIGS.

In the experiment shown in the figure, samples prepared by varying the initial thickness of the gate oxide film from 5 nm to 150 nm and varying the etching amount were used for the measurement. As described above, even when the production conditions are various, when the value obtained by dividing the etching amount by the initial film thickness is used, 8
It has been found that the density of defects that cause dielectric breakdown at an electric field strength of MV / cm or less is generally distributed in the region indicated by hatching in FIG. In addition, when a case where oxidation was performed again after cleaning as in the two-type gate oxide film process was also examined, a result which was slightly different from that in FIG. 10 was obtained although the defect density tended to slightly decrease.

It is not easy to reduce the amount of etching of the oxide film to 2 nm or less, no matter how the simplified cleaning is used. Therefore, as in Embodiment 1, the initial film thickness is 10 nm.
When the thickness becomes thinner, the standardized etching amount becomes 0.2 or more. As a result, it is difficult to reduce the defect density of the gate oxide film to the target 2 defects / cm ² or less unless an epitaxial silicon substrate is used as in the present invention, as shown in FIG.
You can also check from 0. The thickness of the gate oxide film is 10
If it is about 0 nm or more, necessary reliability can be ensured even if an inexpensive CZ substrate is used. However, when the thickness of the gate oxide film is 30 nm or less, the standardized etching amount becomes 0.07 or more, and it is difficult to achieve the target value of the defect density.

According to the first embodiment, the following effects can be obtained.

(1) In the two-type gate insulating film process,
By forming the gate insulating films 16i1 and 16i2 having relatively different thicknesses on the epitaxial layer 1e having very few crystal defects, defects generated in the gate insulating film 16i during the process of forming the gate insulating film can be reduced. In the cleaning process before the second gate oxidation required in the two-type gate insulating film process, it is possible to suppress a phenomenon that a defect in the gate insulating film 16i is transformed into a severe defect that causes dielectric breakdown. Therefore, the rate of occurrence of dielectric breakdown of the gate insulating films 16i1 and 16i2 having relatively different thicknesses can be reduced, so that the rate of failure of the semiconductor integrated circuit device due to the dielectric breakdown can be reduced. .

(2) Since the gettering function is added to the semiconductor substrate 1s, the cleaning process before the second gate oxidation can be reduced, so that the thickness of the relatively thicker gate insulating film 16i1 can be reduced. Controllability and uniformity can be improved.

(3) According to the above (1) and (2), the yield, reliability and electrical characteristics of the semiconductor integrated circuit device can be improved.

(4) According to the above (1), (2) and (3), it is possible to promote cost reduction of a semiconductor integrated circuit device having high reliability and high electric performance.

(Embodiment 2) FIGS. 13 and 14 are cross-sectional views of main parts of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the second embodiment, the technical idea of the present invention is applied to, for example, a DRAM (Dynamic Random Access Memory).
The case where y) is applied will be described. FIG. 13 shows DRA
FIG. 14 shows a part of an M memory cell MC, and FIG. 14 shows a part of its peripheral circuit.

In the second embodiment, for example,
An element forming substrate 1 in which an epitaxial layer 1e made of a silicon single crystal film of about μm was formed by an epitaxial growth method was used. A DRAM was completed by an ordinary method except that the two kinds of gate insulating film processes were performed in the same manner as in the first embodiment.

A p-well 13PW3 is formed in the epitaxial layer 1e in the memory cell region, and a p-well 13PW3 is formed in the epitaxial layer 1e in the peripheral circuit region.
W4 is formed. This p-well 13PW3,13P
W4 is formed such that an impurity such as boron extends to a depth position in the middle of the epitaxial layer 1e. The whole of the memory cell region including the side and bottom of the p-well 13PW3 is surrounded by an n-type semiconductor region,
A well separation structure for suppressing external noise from entering the p-well 13PW3 may be formed. Separation unit 14A is LOC
It is formed of a field insulating film by an OS (Local Oxidization Of Silicon) method or the like. This separation portion 14A may be formed in a shallow groove type as in the first embodiment.

The memory cell MC is a memory cell selection MIS
-It has FETQ and capacitor C. The memory cell selection MIS • FETQ includes a pair of semiconductor regions 25nd,
25 nd, a gate insulating film 16i1 and a gate electrode 17g. For example, phosphorus or arsenic is introduced into the semiconductor region 25nd. The thickness of the gate insulating film 16i1 is, for example, about 8 nm. Gate electrode 17g
Is also a part of the word line WL of the DRAM. On the gate electrode 17g (word line WL), a cap insulating film 26 made of, for example, a silicon oxide film or a silicon nitride film is formed.

A capacitor C is electrically connected to one semiconductor region 25nd of the memory cell selection MIS • FET Q, and a bit line BL is electrically connected to the other semiconductor region 25nd. The capacitor C is connected to the storage electrode 2
7a via a capacitor insulating film 27b and a plate electrode 27c
Is provided. The storage electrode 27a is made of, for example, low-resistance polysilicon and is directly connected to the semiconductor region 25nd. The capacitance insulating film 27b is a portion for storing electric charges for information storage, and is formed of, for example, a silicon oxide film or a laminated structure of a silicon oxide film and a silicon nitride film. The plate electrode 27c is made of, for example, low-resistance polysilicon or tungsten. The bit line BL is
For example, the interlayer insulating film 20a is made of aluminum or an aluminum-silicon-copper alloy, and
Is formed through.

On the other hand, nMISQN3 is shown in the peripheral circuit area. This nMISQN3 has a pair of semiconductor regions 28nd, 28nd, a gate insulating film 16i2, and a gate electrode 17g. In the semiconductor region 28nd,
For example, phosphorus or arsenic has been introduced. The thickness of the gate insulating film 16i2 is, for example, about 4.5 nm.
On the gate electrode 17g, a cap insulating film 26 made of, for example, a silicon oxide film or a silicon nitride film is formed. One semiconductor region 28n of this nMISQN3
The first wiring 19L1 is electrically connected to d, and the second wiring 19L2 is electrically connected to the other semiconductor region 28nd. Note that FIGS. 13 and 14 show only the structure formed by the steps up to the second wiring layer, and the structures by the subsequent steps are omitted.

In the second embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained.

That is, a relatively thick gate insulating film 16i1 can be formed in the memory cell MC portion as compared with the case where the one-type gate insulating film process is used. The voltage can be set high, and the amount of accumulated charge has increased. Thereby, data retention characteristics, noise resistance, and soft error resistance have been improved. On the other hand, in the peripheral circuit, the gate insulating film 16i2 can be made thinner than in the case of using one type of gate insulating film process, so that the operation speed is improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the first and second embodiments, and the present invention is not limited thereto. It goes without saying that various changes can be made.

For example, in the second embodiment, the case where the bit line is provided above the capacitor has been described. However, the present invention is not limited to this. For example, the structure where the bit line is provided below the capacitor is used. It is good. Further, the capacitor is not limited to the planar type, and may be, for example, a crown type or a fin type.

In the first embodiment, the present invention is applied to a microprocessor, and in the second embodiment, the present invention is applied to a DRAM. However, the present invention is not limited to this. It is applicable, for example, SRAM and mask ROM (Read Only Memory)
The present invention can also be applied to other semiconductor integrated circuit devices such as a memory-logic mixed type semiconductor integrated circuit device in which another semiconductor memory such as y) or a memory circuit and a logic circuit are provided on the same element formation substrate. .

[0100]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, a plurality of types of gate insulating films having relatively different thicknesses are formed on a semiconductor single crystal layer having a very small number of crystal defects formed by an epitaxial growth method. Since defects generated in the gate insulating film during the process of forming the insulating film can be reduced, defects in the gate insulating film due to the cleaning treatment required in the process for forming two or more types of gate insulating films can be reduced. It is possible to reduce a phenomenon that the material is transformed into a severe defect that causes destruction. Therefore, the rate of occurrence of dielectric breakdown of gate insulating films having relatively different thicknesses can be reduced, so that the rate of failure of the semiconductor integrated circuit device due to the dielectric breakdown can be reduced.

(2) According to the present invention, by adding the gettering function to the semiconductor substrate, it is possible to reduce a cleaning process required in a process for forming two or more types of gate insulating films. The thickness controllability and uniformity of the relatively thicker gate insulating film can be improved.

(3) According to the above (1) and (2), the yield, reliability, and electrical characteristics of the semiconductor integrated circuit device can be improved.

(4) According to the above (1), (2) and (3), cost reduction of a semiconductor integrated circuit device having high reliability and high electrical performance can be promoted.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a main part of the semiconductor integrated circuit device of FIG. 1;

3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;

4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device shown in FIG. 1 during a manufacturing step following that of the previous figure;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device shown in FIG. 1 during a manufacturing step following that of FIG. 4;

6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device shown in FIG. 1 during a manufacturing step following that of FIG. 5;

7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device shown in FIG. 1 during a manufacturing step following that of FIG. 6;

FIG. 8 is an experimental result for clarifying the improvement of the reliability of the gate oxide film according to the present invention, and shows the electric field strength of the gate oxide film, the cumulative defect density of the gate oxide film, and the gate oxide film having a thickness of 4.5 nm. It is a graph which shows the relationship of.

FIG. 9 is an experimental result for further clarifying the improvement of the reliability of the gate oxide film according to the present invention, and relates to the relationship between the electric field intensity of the gate oxide film and the cumulative defect density of the gate oxide film in the gate oxide film having a thickness of 8 nm. FIG.

FIG. 10 is a graph showing the relationship between the electric field intensity of the gate oxide film and the cumulative defect density of the gate oxide film, which is an experimental result for further clarifying the improvement of the reliability of the gate oxide film according to the present invention.

FIG. 11 is a graph for explaining the grounds for determining the defect density of the gate oxide film at an electric field intensity of 8 MV / cm, and is a graph showing the relationship between the electric field intensity of the gate oxide film and the average life.

FIG. 12 is a graph for explaining a range of a gate insulating film thickness particularly effective for applying the present invention, and is a graph showing a relationship between an etching film thickness and a cumulative defect density at an electric field strength of 8 MV / cm. is there.

FIG. 13 is a fragmentary cross-sectional view of a memory cell of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 14 is a cross-sectional view of a principal part in a peripheral circuit region of a semiconductor integrated circuit device according to another embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 element forming substrate 1 s semiconductor substrate 1 e epitaxial layer (semiconductor single crystal layer) 2 input / output circuit region 3 phase lock loop circuit region 4 instruction cache circuit region 5 data cache circuit region 6 floating point arithmetic circuit region 7 bus interface circuit region Reference Signs List 8 input / output control circuit area 9 central processing circuit area 10 operation control circuit area 11 cache control circuit area 12 other circuit areas 13NW1, 13NW2 n-well 13PW1, 13PW2 p-well 14 separation part 14a shallow groove 14b separation insulating film 14A separation part 15pd semiconductor region 15pd1 low concentration region 15pd2 high concentration region 15nd1 low concentration region 15nd2 high concentration region 15d3 silicide layer 16i gate insulating film (first gate insulating film) 16i1 gate insulating film (first gate insulating film) 16i2 gate insulating Edge film (second gate insulating film) 16i3 Gate insulating film (third gate insulating film) 17 Conductive film 17g Gate electrode 17g1 Conductive film 17g2 Silicide layer 18 Sidewall 19L1 to 19L5 Wiring 20a to 20e Interlayer insulating film 21a to 21e Connection holes 22a to 22e Plug 23 Surface protective film 24a, 24b Photoresist pattern (first and second)
25nd semiconductor region 26 cap insulating film 27a storage electrode 27b capacitance insulating film 27c plate electrode 28nd semiconductor region 29a semiconductor region 29b semiconductor region 30f floating gate electrode 30c control gate electrode 31 interlayer film 32nd semiconductor region BP bonding pad QN1, QN2, QN3 n-channel type MIS • FET QP1, QP2 p-channel type MIS • FET Q memory cell selection MIS • FET C capacitor Qm MIS • FET BLs sub-bit line BLm main bit line

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Norio Suzuki 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Takayuki Kanda Gojocho, Kosui-shi, Tokyo Hitachi, Ltd. Semiconductor Division, Chome 20-1 (72) Inventor Kenji Takahashi 5--20-1, Josuihoncho, Kodaira-shi, Tokyo Semiconductor Division, Hitachi, Ltd. (72) Shimizu, Inventor Hirobumi 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Inventor Satoshi Sakai Hitachi, Ltd. Device Development Center at 6-16-16 Shinmachi, Ome-shi, Tokyo

Claims (19)

[Claims] 1. A step of forming a semiconductor single crystal layer on a semiconductor substrate by an epitaxial method without going through a process for forming an element, and then forming gate insulating films having different thicknesses on the semiconductor single crystal layer. A method for manufacturing a semiconductor integrated circuit device, comprising: 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the impurity concentration that determines the conductivity type of said semiconductor substrate is substantially uniform. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a relatively thickest gate insulating film among said gate insulating films has a thickness of 30 nm or less. Device manufacturing method. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of adding a gettering capability for trapping a contaminant element to said semiconductor substrate. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a thickness of said semiconductor single crystal layer is at least half of a thickness of a relatively thickest gate insulating film among said gate insulating films. A method for manufacturing a semiconductor integrated circuit device. 6. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a semiconductor single crystal layer on a semiconductor substrate by an epitaxial method without going through a process for forming an element; (B) forming a first gate insulating film on the semiconductor single crystal layer, and (c) forming a mask on the first gate insulating film so that a formation region of a second gate insulating film is exposed. Removing the first gate insulating film exposed from the mask by using it as an etching mask after the formation, (d)
After the step (c), a step of performing a cleaning process after removing the mask, (e) a step of forming a second gate insulating film after the step (d), and (f) a second gate. Forming a gate electrode on the first gate insulating film and the second gate insulating film which have been subjected to the insulating film forming process; and (g) forming a semiconductor region for a source / drain of a field effect transistor on the semiconductor single crystal layer. Forming a. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein an impurity concentration for determining a conductivity type of said semiconductor substrate is substantially uniform. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein said first gate insulating film has a thickness of 30.
nm or less, the method for manufacturing a semiconductor integrated circuit device. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 6, further comprising a step of adding a gettering capability for trapping a contaminant element to said semiconductor substrate. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the semiconductor substrate is formed by cutting a semiconductor ingot crystal-grown by a Czochralski method into a plate shape. Of manufacturing a semiconductor integrated circuit device. 11. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps: (a) forming a semiconductor single crystal layer on a semiconductor substrate by an epitaxial method without going through a process for forming an element; (B) forming a first gate insulating film on the semiconductor single crystal layer, and (c) forming a first gate insulating film on the first gate insulating film where a second gate insulating film forming region is exposed. After forming the mask, the first mask is used as an etching mask.
(D) removing the first gate insulating film exposed from the mask, (d) after the step (c), removing the first mask, and then performing a cleaning process; Forming a second gate insulating film after the step, (f) forming a second gate insulating film;
Forming a second mask on the first gate insulating film and the second gate insulating film which have been subjected to the first gate insulating film forming process to expose a region where a third gate insulating film is formed, and then etching the second mask with an etching mask Removing the first or second gate insulating film exposed from the second mask as
(G) after the step (f), removing the second mask and then performing a cleaning process; (h) after the step (g), forming a third gate insulating film; i) the first gate insulating film subjected to the second or third or both gate insulating film forming processes, the second gate insulating film subjected to the third gate insulating film forming process, and the third gate insulating film Forming a gate electrode on the film, and (j) forming a source / drain semiconductor region of a field effect transistor in the semiconductor single crystal layer. 12. The method for manufacturing a semiconductor integrated circuit device according to claim 11, wherein an impurity concentration for determining a conductivity type of said semiconductor substrate is substantially uniform. 13. The method for manufacturing a semiconductor integrated circuit device according to claim 11, wherein said first gate insulating film has a thickness of 3
A method for manufacturing a semiconductor integrated circuit device having a thickness of 0 nm or less. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 11, further comprising a step of adding a gettering ability for trapping a contaminant element to the semiconductor substrate. 15. A semiconductor device comprising a semiconductor single crystal layer formed on a semiconductor substrate by epitaxial growth without going through a process for forming an element, and a plurality of types of gate insulating films having different thicknesses formed on the semiconductor single crystal layer. A semiconductor integrated circuit device comprising a plurality of field effect transistors having a film. 16. The semiconductor integrated circuit device according to claim 15, wherein an impurity concentration for determining a conductivity type of said semiconductor substrate is substantially uniform. 17. The semiconductor integrated circuit device according to claim 15, wherein a relatively thickest gate insulating film among the plurality of types of gate insulating films has a thickness of 30 nm or less. apparatus. 18. The semiconductor integrated circuit device according to claim 15, wherein a gettering ability for capturing a contaminant element is added to said semiconductor substrate. 19. The semiconductor integrated circuit device according to claim 15, wherein a driving voltage of a field-effect transistor having a relatively thick gate insulating film among the plurality of field-effect transistors is relatively thin. A semiconductor integrated circuit device having a higher driving voltage than a field effect transistor having a film.