JP2005294858A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a surge current from flowing into an internal circuit. <P>SOLUTION: When positive or negative surge voltage is applied to a pad 14, a PMOS or an NMOS diode of a protective circuit 13 is turned on and the surge current is discharged to a power supply side or a ground side. Moreover, partial surge current flows into a substrate 11 through the protective circuit 13. This current will flow into the internal circuit 12 from the inside of the substrate 11 whose depth is deeper than a predetermined depth from a lower layer of the protective circuit 13 of the substrate 11. Since an insulation layer 16 is formed in a part used as a current path of this surge current between the protective circuit 13 and the internal circuit 12, the insulation layer 16 prevents the surge current from flowing into the internal circuit 12. Therefore, malfunction of the internal circuit 12 is eliminated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor device that prevents a current flowing from the inside of a substrate into an internal circuit through a protection circuit.

  In a semiconductor device, when a surge voltage outside the operating range is applied to an input / output terminal or an output terminal of an internal circuit, a surge current that is an excessive current flows to the internal circuit, causing a malfunction of the internal circuit. For this reason, a protection circuit is provided to discharge a current to the power supply side or the ground side when a surge voltage is applied.

  This protection circuit includes, for example, a first diode (for example, constituted by a P-channel MOS transistor (hereinafter referred to as PMOS)) connected to the power supply side to an input / output pad and a second diode connected to the ground side. And a load resistance connected to an input / output terminal of the internal circuit. The positive surge voltage is discharged to the power supply side via the first diode, and the negative surge voltage is discharged to the ground side via the second diode. Conventionally, this protection circuit is configured to be mounted on the same substrate as the internal circuit.

  Related art documents related to this include, for example, the following.

Japanese Patent Laid-Open No. 4-112561 JP-A-1-231361

However, the conventional semiconductor device has the following problems.
As described above, when current is discharged from the protection circuit, the current is always discharged to the power supply side or the ground side through the substrate. However, when a protection circuit is constituted by a MOS transistor or the like, a parasitic bipolar transistor is constituted by the protection circuit and the inside of the substrate, and the parasitic bipolar transistor is turned on to increase the potential inside the substrate. Furthermore, a parasitic bipolar transistor is constituted by the internal circuit and the inside of the substrate, and when the potential inside the substrate rises, the parasitic bipolar transistor is turned on, and a part of current flows from the inside of the substrate to the internal circuit. It reached the cause of internal circuit malfunction.

  In order to solve the above-described problems, the present invention provides a plurality of pads formed on a substrate and a surge current that is connected to each of the pads and is applied to the pad, partly to the outside through the substrate. In a semiconductor device comprising: a plurality of protection circuits that release the inside of the substrate; and an internal circuit in which an input terminal or an output terminal is electrically connected to each pad, between the protection circuit and the internal circuit In addition, the depth from the back surface of the substrate to the front surface direction is deeper than the depth of the fixed distance from the lower layer of the protection circuit in the direction of the back surface of the substrate based on the current path of the part of the surge current. An insulator layer, an electrode, or a recombination center layer is provided inside the dug groove.

  According to the first aspect of the present invention, since the surge current is prevented from flowing into the internal circuit through the inside of the substrate by the insulator layer, the internal circuit does not malfunction.

  According to the second and third aspects of the invention, since the electrode or the recombination center layer is provided in the surge current path directly under the protection circuit, the surge current flowing in the bulk of the substrate is prevented from flowing into the internal circuit. The internal circuit does not malfunction.

  The semiconductor device has a plurality of pads formed on the substrate, and is connected to each pad, and discharges a surge current due to a surge voltage applied to the pad to the outside through the substrate and a part to the inside of the substrate. A plurality of protection circuits and an internal circuit in which input terminals or output terminals are electrically connected to the pads are provided. And, between the protection circuit and the internal circuit, at a position spaced apart from the lower layer of the protection circuit by a certain distance set based on the current path of the part of the surge current in the direction of the back surface of the substrate. An insulator layer is provided in a groove dug deeper from the back surface to the front surface of the substrate than the depth.

  2A and 2B are configuration diagrams of a semiconductor device showing a reference example related to the first embodiment of the present invention. In particular, FIG. 2A is a plan view, and FIG. Is a cross-sectional view.

  This semiconductor device is composed of first and second substrates 1 and 2 made of, for example, a P-type silicon substrate. The substrate 1 is provided with a plurality of input / output pads 1c and a protection circuit 1b for each pad 1c. The pad 1c and the protection circuit 1b are connected by a wiring pattern 1d.

  On the other hand, the substrate 2 is provided with an internal circuit 2a. An input / output terminal (not shown) of the internal circuit 2a is electrically and physically connected to each pad 1c via a wiring pattern (not shown), a pad (not shown), a solder bump 3, and a load resistance of the protection circuit 1b.

  The protection circuit 1b is composed of, for example, a MOS transistor, and is electrically connected to a power source (not shown) via a first diode formed by PMOS that is turned on when a positive surge voltage is applied to the pad 1c. When the surge voltage is applied to the pad 1c, it is electrically connected to the ground side via the second diode formed by the NMOS that is turned on. When no surge voltage is applied to the pad 1c, the load resistance and It is configured to be connected to an input / output terminal of the internal circuit 2a through a pad that is not connected.

  The pad 1c is a terminal that is electrically connected to the lead by a bonding wire at the time of mounting. For example, the pad 1c has a size of about 80 μm × 80 μm and is formed of a conductor such as aluminum. The wiring pattern 1d is a wiring for electrically connecting the pad 1c and the input terminal of the protection circuit 1b, and is formed of a conductor such as aluminum.

  The internal circuit 2a is configured by a semiconductor integrated circuit such as a memory or a logic circuit. The solder bump 3 is for electrically and physically connecting the output terminal of the load resistor constituting the protection circuit 1b and the input / output terminal of the internal circuit 2a by respective pads (not shown).

Hereinafter, operations (a) and (b) of the semiconductor device of FIG. 2 will be described.
(A) When a surge voltage is applied When a positive or negative surge voltage is applied to the pad 1c, the PMOS or NMOS diode of the protection circuit 1b is turned on and a surge current is released to the power supply side or the ground side. At the same time, a part of the surge current flows inside the substrate 1 through the protection circuit 1b.

  Since the internal circuit 2a is formed on the substrate 2 different from the substrate 1, these surge currents do not flow into the input / output terminals of the internal circuit 2a. The input / output terminal of the internal circuit 2a is connected to the pad 1c via the load resistance of the protection circuit 1b and the solder bump 3, and the load resistance is larger than the on-resistance of the diode. Surge current does not flow. This prevents the internal circuit 2a from malfunctioning.

(B) When no surge voltage is applied When no surge voltage is applied to the pad 1c, both PMOS and NMOS are turned off, and the internal circuit 2a is electrically connected to the pad 1c through the load resistance of the solder bump 3 and the protection circuit 1b. Connected to the terminal for normal operation.

Next, an example of a method for manufacturing the semiconductor device of FIG. 2 will be described.
After forming a protection circuit 1b, a wiring pattern 1d such as an aluminum wiring, a pad (not shown) for a solder bump 3 and a pad 1c for wire bonding on a substrate 1 such as a P-type silicon substrate by a normal MOS process or the like. Then, the substrate 1 is diced.

  Further, after forming a wiring pattern (not shown) such as an internal circuit 2a and an aluminum wiring and a pad (not shown) for connecting to the solder bump 3 on a substrate 2 such as a P-type silicon substrate, etc. The substrate 2 is diced.

  Then, solder bumps 3 are mounted on pads (not shown) formed on the output side of the protection circuit 1b on the substrate 1, and further connected to the input / output terminals of the internal circuit 2a with the surface of the substrate 2 facing down by a mounting machine. The substrate 2 is mounted so that the pad to be contacted with the solder bump 3. Thereafter, the solder bumps 3 are melted, the substrates 1 and 2 are electrically and physically connected, the substrates 1 and 2 are mounted on the case, the pads 1c are wire-bonded, and sealed and mounted. Finish.

As described above, according to this reference example, there are the following advantages.
When a surge voltage is applied to the pad 1c, a current is released to the power supply side or the ground side through the protection circuit 1b, and the current generated along with the application of the surge voltage flows through the substrate 1, and the power supply side or Absorbed on the ground side. For this reason, since no current flows into the substrate 2 on which the internal circuit 2a is formed, malfunction of the internal circuit 2a does not occur.

  FIGS. 1A and 1B are configuration diagrams of a semiconductor device showing Embodiment 1 of the present invention. In particular, FIG. 1A is a plan view and FIG. 1B is a cross-sectional view. .

  As shown in FIG. 1, an internal circuit 12, a plurality of protection circuits 13, a plurality of pads 14, a plurality of wiring patterns 15, and an insulating layer 16 are formed on the substrate 11.

  The input terminal of each protection circuit 13 and each pad 14 are electrically connected by a wiring pattern 15. The output terminal of the protection circuit 13 and the input / output terminal of the internal circuit 12 are electrically connected by a wiring pattern (not shown).

  The insulator layer 16 surrounds the internal circuit 12 and separates the protective circuit 13 and the internal circuit 12 from the lower layer of the protective circuit 13 to about 100 μm to 10 μm. Is formed of SiO2 or the like.

  The internal circuit 12 and the protection circuit 13 have the same configuration as the internal circuit 2a and the protection circuit 1b in FIG. The pad 14 is a wire-bonded terminal, and the wiring pattern 15 is a wiring for connecting the pad 14 and the input terminal of the protection circuit 13. The insulator layer 16 is a layer for preventing a surge current flowing in the bulk of the substrate 11, not the power supply side or the ground side, from flowing into the internal circuit 12.

Hereinafter, the operation of the semiconductor device of FIG. 1 will be described.
When a positive or negative surge voltage is applied to the pad 14, the PMOS or NMOS diode of the protection circuit 13 is turned on, and a surge current is released to the power supply side or the ground side. A part of the surge current (about 10 ⁻⁴ of the current flowing on the power supply side or the ground side) flows into the substrate 11 through the protection circuit 13.

  According to the device simulation, it is found that this current tries to flow into the internal circuit 12 from the inside of the substrate 11 deeper than a certain depth (for example, about 100 μm) from the lower layer of the protection circuit 13 of the substrate 11. doing. And since the insulator layer 16 is formed in the place which becomes a current path of this surge current between the protection circuit 13 and the internal circuit 12, this insulator layer 16 flows the surge current into the internal circuit 12. Stop that. Therefore, the internal circuit 12 does not malfunction.

Next, an example of a method for manufacturing the semiconductor device of FIG. 1 will be described.
An internal circuit 12, a protection circuit 13, a wiring pattern 15, and a pad 14 are formed on a substrate 11 such as a P-type silicon substrate having a thickness of about 300 μm by a normal MOS process or the like.

Then, on the entire back surface of the substrate 11, the the Si ₃ N ₄ film formed by a CVD method, a photolithographic etching, and patterning by etching the Si ₃ N ₄ in the region for forming the grooves. Using the Si ₃ N ₄ pattern as a mask, the substrate 11 is selectively etched by anisotropic dry etching to form a groove having a depth of about 250 μm (hereinafter, the process of digging this groove is referred to as trench etching). Thereafter, an oxide film such as SiO ₂ is deposited by CVD, the back surface is polished and flattened, the substrate 11 is diced, mounted on a case, wire bonding of the pad 14 is performed, and sealing is performed. Finish.

As described above, the first embodiment has the following advantages.
When a surge voltage is applied to the pad 14, a current is discharged to the power supply side or the ground side through the protection circuit 13, and a part of the surge current flowing in the bulk of the substrate 11 is blocked by the insulator layer 16. For this reason, since a surge current does not flow into the internal circuit 12, the malfunction of the internal circuit 12 does not occur.

  FIGS. 3A and 3B are configuration diagrams of a semiconductor device showing a second embodiment of the present invention. In particular, FIG. 3A is a plan view and FIG. 3B is a cross-sectional view. .

  In this semiconductor device, an internal circuit 22, a plurality of protection circuits 23, a plurality of pads 24, a plurality of wiring patterns 25, two high concentration layers 26, and two electrodes 27 are formed on a substrate 21. Yes.

  The input terminal of each protection circuit 23 and each pad 24 are electrically connected by a wiring pattern 25. The output terminal of the protection circuit 23 and the input / output terminal of the internal circuit 22 are electrically connected by a wiring pattern (not shown).

  The high concentration layer 26 is a layer into which impurities of the same type as that of the substrate 21 are implanted. It is formed along. An electrode 27 made of a conductor such as aluminum is formed in the groove and on the entire back surface of the substrate 21.

The internal circuit 22 and the protection circuit 23 have the same configuration as the internal circuit 2a and the protection circuit 1b in FIG. The pad 24 is a terminal for wire bonding, and the wiring pattern 25 is a wiring for connecting the pad 24 and the input terminal of the protection circuit 23. The high-concentration layer 26 is a layer for making an ohmic contact with the electrode 27. For example, the impurity concentration of P ⁺ or N ⁺ is about 1 × 10 ²⁰ cm ⁻³ . The electrode 27 is made of a conductor such as aluminum and absorbs a surge current flowing inside the substrate 21.

Hereinafter, the operation of the semiconductor device of FIG. 3 will be described.
When a positive or negative surge voltage is applied to the pad 24, the PMOS or NMOS diode of the protection circuit 23 is turned on, and a surge current is released to the power supply side or the ground side. A part of the surge current (about 10 ⁻⁴ of the current flowing on the power supply side or the ground side) flows into the substrate 21 through the protection circuit 23.

  This current tends to flow into the internal circuit 22 from a depth deeper than a certain depth (for example, about 100 μm) from the lower layer of the protection circuit 23. However, since the electrode 27 is provided in the place that becomes the current path of the surge current, the electrode 27 absorbs the surge current and prevents the surge current from flowing into the internal circuit 22. This prevents the internal circuit 22 from malfunctioning.

Next, an example of a method for manufacturing the semiconductor device of FIG. 3 will be described.
On a substrate 21 such as a P-type silicon substrate having a thickness of about 300 μm, an internal circuit 22, a protection circuit 23, a wiring pattern 25, and a pad 24 are formed by a normal MOS process or the like.

Then, trenches are formed from the back surface of the substrate 21 by trench etching, and in order to obtain ohmic contact, impurity ions of the same type as that of the substrate 21 are, for example, a concentration of 1.5 × 10 ¹⁵ cm ⁻² , an energy of 70 keV (BF ₂ ) (40 keV (in case of AS)), ion implantation is performed and annealing is performed.

  Thereafter, aluminum or the like is sputtered to form the electrode 27 inside the groove and on the back surface of the substrate 21. Then, the back surface is polished and flattened, the substrate 21 is diced, mounted on a case, wire bonding of the pad 24 is performed, sealing is completed, and the mounting is completed.

As described above, the second embodiment has the following advantages.
When a surge voltage is applied to the pad 24, a current is discharged to the power supply side or the ground side through the protection circuit 23, and a part of the surge current flowing inside the substrate 21 is absorbed by the electrode 27. For this reason, since a surge current does not flow into the internal circuit 22, malfunction of the internal circuit 22 does not occur.

  FIGS. 4A and 4B are configuration diagrams of a semiconductor device showing Embodiment 3 of the present invention. In particular, FIG. 4A is a plan view and FIG. 4B is a cross-sectional view. Elements common to the elements in FIG. 3 are denoted by common reference numerals.

  In the third embodiment, the high concentration layer 26 and the electrode 27 of the second embodiment are changed to a recombination center layer 36 and an insulator layer 37.

The recombination center layer 36 is a layer in which a recombination center for recombination of carriers is formed, and is separated by a certain distance (for example, 10 μm to 100 μm) from directly below the lower layer of the protection circuit 23 to the back surface of the substrate 21. It is formed along the surface of the groove deeply dug from the back surface to the front surface of the substrate 21 rather than the position to the extent. An insulating layer 37 such as SiO ₂ is formed inside the groove and on the entire back surface.

Hereinafter, the operation of the semiconductor device of FIG. 4 will be described.
When a positive or negative surge voltage is applied to the pad 24, the PMOS or NMOS diode of the protection circuit 23 is turned on, and a surge current is released to the power supply side or the ground side. Further, a carrier current due to a part of the surge (about 10 ⁻⁴ of the current flowing on the power supply side or the ground side) flows into the substrate 21 through the protection circuit 23.

  The carrier current tries to flow from the lower layer of the protection circuit 23 into the internal circuit 22 from the inside of the substrate 21 having a certain depth (for example, about 100 μm). Since the layer 36 is provided, the carriers are recombined and absorbed by the recombination center layer 36.

The carrier current is of the order of 10 ^{−4 of the} surge current flowing on the power supply side or the ground side, and current flows into the internal circuit 22 by recombination of the carrier (by setting the concentration of the recombination center). To prevent. For this reason, the internal circuit 22 does not malfunction.

Next, an example of a method for manufacturing the semiconductor device of FIG. 4 will be described.
On a substrate 21 such as a P-type silicon substrate having a thickness of about 300 μm, an internal circuit 22, a protection circuit 23, a wiring pattern 25, and a pad 24 are formed by a normal MOS process or the like.

  Then, grooves are formed from the back surface of the substrate 21 by trench etching. After the formation of the groove, the recombination center layer 36 is formed by causing lattice defects in the ion implantation of the recombination center such as Au and Fe or Si on the surface of the groove.

Thereafter, an insulating film 37 is formed by depositing an oxide film such as SiO _{2 on} the inside of the groove and the entire back surface of the substrate 21 by CVD, and the back surface is flattened by polishing or the like, and the substrate 21 is diced. Then, it is mounted on the case, wire bonding of the pad 24 is performed, and sealing is performed to complete the mounting.

As described above, the third embodiment has the following advantages.
When a surge voltage is applied to the pad 24, a current is discharged to the power supply side or the ground side through the protection circuit 23, and a part of the surge current flowing inside the substrate 21 is absorbed by the recombination center layer 36. For this reason, since a surge current does not flow into the internal circuit 22, malfunction of the internal circuit 22 does not occur.

  The present invention is not limited to the reference examples and embodiments described above, and various modifications can be made. Examples of such modifications include the following.

  (1) In the reference example and the embodiment, the case of the MOS transistor has been described as an example. However, the internal circuit 2a, 12, 22 and the protection circuit 1b, 13, 23 are configured by other transistors such as a bipolar transistor. However, it is applicable.

  (2) Similarly to the reference example, the protection circuit 1b is formed on a substrate different from the internal circuit 2a, and is electrically connected to the output pad, the input pad, and the protection circuit 1b of the internal circuit 2a formed on two different substrates. -You may make it the structure connected by the solder bump 3 physically. Thereby, the protection circuit 1b can be shared by the two internal circuits 2a.

  (3) In the reference example and the embodiment, the pads 1c, 14, and 24 are configured to be formed in the periphery, but may be located anywhere on the substrates 1, 11 and 21.

  (4) In the second embodiment, the electrode 27 needs to cover the inside of the groove because the surge current is released to the back surface of the substrate 21 when the electrical connection between the substrate 21 and the substrate 21 is established. Instead, an insulator layer may be embedded in the groove.

It is a block diagram of the semiconductor device which shows Example 1 of this invention. It is a block diagram of the semiconductor device which shows the reference example of Example 1 of this invention. It is a block diagram of the semiconductor device which shows Example 2 of this invention. It is a block diagram of the semiconductor device which shows Example 3 of this invention.

Explanation of symbols

1, 2, 11, 21 Substrate 1b, 13, 23 Protection circuit 1c, 14, 24 Pad 2a, 12, 22 Internal circuit 3 Solder bump 36 Recombination center layer

Claims (3)

A plurality of pads formed on the substrate;
A plurality of protection circuits connected to each of the pads, and discharging a surge current due to a surge voltage applied to the pads to the outside through the substrate, and a part to the inside of the substrate;
In a semiconductor device including an internal circuit in which an input terminal or an output terminal is electrically connected to each pad,
From the depth of a position spaced apart from the protection circuit and the internal circuit by a certain distance set based on the current path of the part of the surge current from the lower layer of the protection circuit to the back surface of the substrate A semiconductor device characterized in that an insulator layer is provided in a groove dug deeply from the back surface to the front surface of the substrate. A plurality of pads formed on the substrate;
A plurality of protection circuits connected to each of the pads, and discharging a surge current due to a surge voltage applied to the pads to the outside through the substrate, and a part to the inside of the substrate;
In a semiconductor device including an internal circuit in which an input terminal or an output terminal is electrically connected to each pad,
Immediately below the protection circuit, the depth of the substrate is less than a certain distance away from the lower layer of the protection circuit, which is set based on a current path through which the part of the surge current flows in the depth direction of the substrate. 2. A semiconductor device, wherein an electrode is provided on the inside of a groove deeply dug from the back surface to the front surface and on the back surface of the substrate so as to be electrically connected to the inside. A plurality of pads formed on the substrate;
A plurality of protection circuits connected to each of the pads, and discharging a surge current due to a surge voltage applied to the pads to the outside through the substrate, and a part to the inside of the substrate;
In a semiconductor device including an internal circuit in which an input terminal or an output terminal is electrically connected to each pad,
Directly below the protection circuit, from the back surface of the substrate than a position spaced apart from the lower layer of the protection circuit by a certain distance set based on a current path through which the part of the surge current flows in the depth direction of the substrate. A semiconductor device characterized in that a recombination center layer is provided in a groove deeply dug in the surface direction.

Images