KR100391156B1 - Array pannel of liquid crystal display and fabricating method the same - Google Patents

Abstract

The present invention relates to a shorting bar formed on an array substrate for a liquid crystal display device including a thin film transistor (TFT), and a method of manufacturing the same; Forming a buffer layer on one surface of the substrate; Forming an island-like polycrystalline silicon layer on top of the buffer layer; Stacking a gate insulating film, a first metal layer including Al, and a second metal layer including Mo on top of the polycrystalline silicon layer and the buffer layer; Etching the first and second metal layers to form a gate electrode, a gate wiring, and a gate shorting bar; Forming an active region, a source, and a drain region in the polycrystalline silicon layer using the gate electrode as a mask; Forming an interlayer insulating film over the gate electrode and the gate insulating film; First and second contact holes exposing portions of the source and drain regions by etching the interlayer insulating layer and the gate insulating layer thereunder; an opening hole exposing the upper gate shorting bar and a lower layer first of the gate shorting bar; Forming metal layers spaced apart from each other; Stacking a third metal layer including Mo on the interlayer insulating film; Etching the third metal layer to remove the third metal layer and the lower second metal layer stacked on the gate shorting bar, and to form source and drain electrodes electrically connected to the source and drain regions, respectively. Provided are an array panel for a liquid crystal display device and a method of manufacturing the same.

Description

Array panel for liquid crystal display device and manufacturing method thereof {Array pannel of liquid crystal display and fabricating method the same}

The present invention relates to a liquid crystal display device (LCD), and more particularly, a shorting bar formed and cut on an array substrate for a liquid crystal display device including a thin film transistor (TFT); It relates to a manufacturing method.

Recently, as the information society has evolved rapidly, there is a need for a flat panel display having improved characteristics such as thinning, light weight, and low power consumption, and thus a liquid crystal display has been developed. It is currently being used in various ways.

A liquid crystal display device is formed by forming a field generating electrode on one surface of two substrates facing each other, and inserting a liquid crystal material therebetween with the two electrodes disposed to face each other. By driving a liquid crystal in response to a change in electric field generated by applying a voltage to an electrode, the device expresses various images with varying light transmittance.

In particular, a plurality of pixel electrodes and one-to-one thin film transistors corresponding to the pixel electrodes are arranged on the upper surface of the lower array substrate, which is one of two substrates constituting the liquid crystal display, as one of the components constituting the thin film transistor. Amorphous silicon (a-Si: H) is the main material of the in-active layer, because it has the advantage that it can be implemented by low temperature process on a large-scale low-cost substrate such as glass.

However, in recent years, the field effect mobility is about 100 to 200 times larger than that of amorphous silicon, resulting in fast response speed, excellent stability against temperature and light, and particularly, driving circuits can be formed on the same substrate. A method of implementing an active layer with poly-silicon (poly-Si) having various advantages has been developed and utilized. Hereinafter, an array substrate on which a thin film transistor having an active layer using polycrystalline silicon is arranged will be described with reference to the accompanying drawings. do.

1 is a plan view schematically illustrating a part of a general array panel, in which a plurality of gate wirings 51a and 51b and a plurality of parallel data wirings 71 orthogonal thereto are arranged in a matrix form. A pixel region is defined and a thin film transistor T and a pixel electrode 91 electrically connected to the thin film transistor T are positioned in the pixel region.

In this case, the plurality of gate lines 51a and 51b and the data line 71 extend in one direction or both directions of the substrate to be electrically connected to the external gate circuit S and the external data circuit (not shown), respectively. A plurality of gate wirings 51a are provided at the edge portion of the substrate to which the gate wirings 51a and 51b and the gate external circuit S are connected, and at the edge portion of the substrate to which the data wiring 71 and the data external circuit (not shown) are connected. , 51b) and a plurality of gate shorting bars 54 and data shorting bars (not shown) are formed to connect each of the plurality of data lines 71 in a single closed circuit, which are then electrically cut in an appropriate process, and finally, FIG. 1. It will have a configuration as shown in.

In this case, the thin film transistor T electrically connected to the gate shorting bar 54 and the gate lines 51a and 51b and the data line 71 adjacent to each other located in each pixel area is illustrated in FIG. 1. The cross section cut along the II-II line and the cross section cut along the II'-II 'line will be described with reference to FIG. 2.

First, the thin film transistor is divided into a buffer layer 20 deposited on the front surface of the transparent substrate 10 and an active region 31 and source and drain regions 32 and 33 depending on whether impurities are doped into the upper portion of the thin film transistor. The semiconductor layer is positioned, and the gate insulating layer 40 is positioned on the semiconductor layer.

In particular, the gate electrode 53 is positioned on the gate insulating film 40 stacked above the active region 31, which extends in the horizontal direction of the substrate as shown in FIG. 1. It is electrically connected to the gate wirings 51a and 51b. Above the gate electrode 53 and the gate insulating film 40, an interlayer insulating film 60 deposited on the entire surface of the substrate is positioned, and the interlayer insulating film 60 is formed on portions of the source and drain regions 32 and 33, respectively. Respectively, the first and second contact holes 64a and 64b are exposed so that the source and drain electrodes 72a and 72b formed thereon are electrically connected to the source and drain regions 32 and 33, respectively. .

At this time, in particular, the source electrode 72a is electrically connected to the data line 71 extending in the longitudinal direction of FIG. 1, and the drain electrode 72b is respectively formed on the substrate on which the source and drain electrodes 72a and 72b are formed. A protective film 62 having a third contact hole 81 penetrated so as to be exposed, and a planarization film 80 are sequentially formed so as to be electrically connected to the drain electrode 72b through the third contact hole 81. The pixel electrode 91 connected to is positioned.

On the other hand, to form the thin film transistor (T) on the substrate undergoes a number of chemical and physical treatment processes, the device may be fatally damaged by the static electricity generated at this time. Therefore, in order to prevent this, a gate shorting bar (54 in FIG. 1) and a data shorting bar (not shown) are provided to connect each gate wiring (51a and 51b of FIG. 1) and the data wiring (71 of FIG. 1) in a closed circuit. They are then electrically disconnected if there is no possibility of damaging the device due to static electricity.

The gate shorting bar 54 forms the gate electrode 53 of the thin film transistor on the buffer layer 20 and the gate insulating film 40 that are sequentially stacked on the substrate in order, as shown in the left side of FIG. 2. After being formed of the same material as the metal material to be cut in an appropriate process, the illustrated figure shows a state in which the gate shorting bar 54 is cut.

When the process of forming and cutting the gate shorting bar 54 is described in comparison with the manufacturing process of the thin film transistor, FIGS. 3A to 3D show the gate shorting bar 54 of FIG. The cross section taken along the line II and the II'-II 'line of the thin film transistor (T) is shown. For easy comparison, the cross section taken along the line II-II of the gate shorting bar 54 is shown on the left. The cross section cut along the II'-II 'line | wire which is a thin film transistor T part was arrange | positioned at the right side.

First, a buffer layer 20 made of a silicon oxide film SiO ₂ or the like is stacked on the entire surface of the transparent substrate 10, and an island-like polycrystalline silicon layer 30 is formed thereon. As shown in FIG. 3A, the substrate 10, the buffer layer 20, and the island-like polycrystalline silicon layer 30 are sequentially stacked on the portion where the thin film transistor T is formed, but on the gate shorting bar portion. Only the substrate 10 and the buffer layer 20 stacked thereon exist.

Subsequently, as shown in FIG. 3B, a gate insulating film 40 made of a material such as a silicon oxide film or a silicon nitride film and a conductive metal are sequentially stacked on the entire upper surface of the substrate on which the buffer layer 20 and the polycrystalline silicon layer 30 are formed. Patterning only the conductive metal to form a gate insulating film 40 deposited on the entire surface of the substrate, a gate electrode 53 formed on the upper portion thereof, and a gate shorting bar 54 which serves to discharge static electricity generated in a subsequent process. In this case, the gate wirings 51a and 51b of FIG. 1, which are electrically connected to the gate electrode 53 described above, are simultaneously implemented.

Subsequently, ion doping is performed on the polycrystalline silicon layer 30 through the gate insulating film 40 positioned below the gate electrode 53 having the double stacked structure as a mask, thereby forming an intrinsic semiconductor material. Source and drain regions 32 and 33 doped with ionic impurities, respectively, may be implemented with the in-active region 31 interposed therebetween.

On the other hand, in a large-area, high-resolution liquid crystal display device, when the wiring resistance of the gate electrode 53 and the gate wirings (51a and 51b of FIG. 1) is large, the image quality is degraded due to cross-talk due to signal delay. As the case is frequently observed, low resistance aluminum (Al) is usually used as the gate electrode and the gate wiring to prevent this. However, such aluminum (Al) is chemically weak in corrosion resistance, and the surface may be damaged by the high temperature required in a subsequent process, so that wiring coupling problems such as hillock may occur. The gate electrode 53 and the gate wiring (51a, 51b of FIG. 1) of the double laminated structure which laminate | stack are formed are used.

Therefore, in FIGS. 2 and 3B and the drawings below, reference numeral 52a is used for the first metal layer made of the Al material at the bottom constituting the gate electrode 53 and the gate shorting bar 54, and the Mo material thereon. The 2nd metal layer which consists of these is attached | subjected and described with the reference numeral 52b.

Subsequently, as shown in FIG. 3C, an interlayer insulating film 60 made of a silicon oxide film or a silicon nitride film is laminated on the entire surface of the substrate, and the interlayer insulating film 60 and the gate insulating film 40 thereunder are patterned, respectively. And first and second contact holes 64a and 64b exposing the drain regions 32 and 33, and an exposure hole 64c exposing the gate shorting bar 54. The interlayer insulating film 60 is to insulate the source and drain electrodes 72a and 72b and the gate electrode 53, which will be described later, and then, as shown in FIG. 3D, on the entire upper surface of the upper substrate of the interlayer insulating film 60, By depositing and patterning a third metal layer made of a metal material such as Mo, which is highly durable, the data line 71 of FIG. 1 and the source and drain electrodes 72a and 72b are formed.

In this case, the data line 71 of FIG. 1 is formed to be orthogonal to the gate lines 51a and 51b in an electrically connected state with the source electrode 72a, and the source and drain electrodes 72a and 72b are formed in a first manner. And second and second contact holes 64a and 64b, which are electrically connected to the source and drain regions 32 and 33, wherein a third metal layer is also stacked on the gate shorting bar 54. In addition, the gate shorting bar 54 having a double stacked structure underneath is removed in the patterning process for forming 72a and 72b, and is electrically disconnected in the same process.

Although not shown in the drawings, in the external gate circuit (S in FIG. 1) to which the gate wirings 51a and 51b are extended and connected, this is simultaneously implemented with the above-described source and drain electrodes 72a and 72b. This is because the antistatic circuit is completed and does not need to remain.

As shown in FIG. 2, the thin film transistor formed by such a process includes a protective film 62 made of a silicon nitride film, BCB, or the like over the entire surface of the substrate 10 on which the source and drain electrodes 72a and 72b are formed. By sequentially stacking and patterning the planarization film 80, a third contact hole 81 exposing a part of the drain electrode 72b is formed. Then, the third contact hole 81 is formed of a transparent conductive material. The pixel electrode 91 is electrically connected.

In the process of implementing and cutting the gate shorting bar and manufacturing the thin film transistor, the wet etching method is generally used to form the source and drain electrodes 72a and 72b by depositing and patterning a third metal layer. Bar, at this time, an additional wet process using another etchant for cutting the gate shorting bar 54 is required.

That is, as the third metal layer constituting the source and drain electrodes 72a and 72b, a Mo metal constituting the upper layer of the gate shorting bar 54 is generally used. The source and drain using an etchant capable of dissolving the Mo metal is used. Even though the patterning of the drain electrodes 72a and 72b and the electrical disconnection of the second metal layer 52b on the upper side of the gate shorting bar 54 are performed, the first metal layer 52a made of Al metal is still present. However, in order to dissolve and electrically disconnect, an additional wet etching process using another etchant is required.

Accordingly, the substrate is frequently damaged when exposed to two types of etchant for a long time, and in order to prevent the wet etching process, the gate shorting bar is not completely disconnected when the wet etching process is shortened.

The present invention has been made to solve the above problems, it provides more reliability in the cutting of the gate shorting bar in the process of implementing the source and drain electrodes, in particular to shorten the time the substrate is exposed to the etchant here It is an object of the present invention to provide an improved gate shorting bar and a method of manufacturing the same, which can minimize the impact applied.

1 is a view schematically illustrating a part of an array panel for a general liquid crystal display device;

FIG. 2 is a cross-sectional view taken along a line II-II and a line II'-II 'of FIG. 1, respectively;

3A to 3D are diagrams illustrating left and right cross-sections cut along the lines II-II and II'-II 'of FIG. 1 according to a manufacturing sequence of a general array panel, respectively.

4 is a view schematically illustrating a part of an array panel of a liquid crystal display according to the present invention.

FIG. 5 is a cross-sectional view taken along the line IV-IV and line IV'-IV 'of FIG. 4, respectively;

6A to 6D are diagrams showing left and right cross-sections cut along a line IV-IV and a line IV'-IV 'of FIG. 4 according to a manufacturing sequence of a general array panel, respectively.

<Description of the symbols for the main parts of the drawings>

10 substrate 120 buffer layer

131: active region 132, 133: source and drain region

140: gate insulating films 152a and 152b: first and second metal layers

153: gate electrode 154: gate shorting bar

160: interlayer insulating film 161, 162: first and second contact holes

The present invention comprises the steps of providing a substrate, to achieve the above object; Forming a buffer layer on one surface of the substrate; Forming an island-like polycrystalline silicon layer on top of the buffer layer; Stacking a gate insulating film, a first metal layer including Al, and a second metal layer including Mo on top of the polycrystalline silicon layer and the buffer layer; Etching the first and second metal layers to form a gate electrode, a gate wiring, and a gate shorting bar; Forming an active region, a source and a drain region in the polycrystalline silicon layer using the gate electrode as a mask; Forming an interlayer insulating film over the gate electrode and the gate insulating film; First and second contact holes exposing portions of the source and drain regions by etching the interlayer insulating layer and the gate insulating layer thereunder; an opening hole exposing the upper gate shorting bar and a lower layer first of the gate shorting bar. Forming metal layers spaced apart from each other; Stacking a third metal layer including Mo on the interlayer insulating film; Etching the third metal layer to remove the third metal layer and the lower second metal layer stacked on the gate shorting bar, and to form source and drain electrodes electrically connected to the source and drain regions, respectively. Provided is a method of manufacturing an array panel for a liquid crystal display device.

In this case, the interlayer insulating film is a silicon nitride film having a thickness of 6500 ~ 7500Å, the first metal layer is AlNd having a thickness of 2500 ~ 3500Å, the second and the third metal layer has a thickness of 450 ~ 550Å. The upper gate shorting bar may have a neck shape having a narrower width than other portions.

In addition, the present invention is a width of the neck-shaped upper gate shorting bar is 4㎛ or less, the angle formed between the inclined surface connecting the different widths and the neck-shaped gate shorting bar is 100 to 160 °, the upper gate shorting bar to the center As a result, the separation distance of the lower gate shorting bar is several μm or less.

In another aspect, the present invention provides an array panel for a liquid crystal display device comprising a gate shorting bar formed and removed in the above manner.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The gate shorting bar according to the present invention has a first metal layer spaced apart from each other at the bottom and a leg electrically connecting them at the top of the spaced first metal layer to provide reliability in cutting and minimize damage to the substrate. and a second metal layer having a bridge shape. In particular, the thin film transistor arranged on the array substrate to which the gate shorting bar according to the present invention is applied has an active layer made of poly-silicon (poly-Si). It is done.

4 is a plan view schematically illustrating a portion of an array substrate to which the gate shorting bar 154 is applied according to the present invention, which includes a plurality of gate wirings 151a and 151b arranged in parallel on a transparent substrate and a plurality of orthogonal to them. Parallel data lines 171 form a matrix to define pixel regions, and the pixel electrodes 191 electrically connected one-to-one with the thin film transistor T and the thin film transistor T, respectively. This is located.

In this case, the plurality of gate wires 151a and 151b and the data wire 171 extend in one direction or both directions of the substrate to be electrically connected to the external gate circuit S and the external data circuit (not shown), respectively. Occurs at the edge of the substrate to which the gate wirings 151a and 151b and the gate external circuit S are connected, and at the edge of the substrate to which the data wiring 171 and the data external circuit (not shown) are connected. The gate shorting bar 154 and the data shorting bar (not shown) are formed to prevent the device from being damaged by static electricity or the like, which are then electrically disconnected in a proper process.

IV-IV of FIG. 4 with respect to the gate shorting bar 154 and the thin film transistor T electrically connected to the adjacent gate lines 151a and 151b and the data line 171 in a state located in each pixel area. A cross section cut along a line and a cross section cut along IV'-IV 'will be described with reference to FIG. 5.

First, the thin film transistor includes a buffer layer 120 deposited on the front surface of the transparent substrate 10, an active region 131, which is an intrinsic semiconductor material, and a source connected therebetween, respectively, on the buffer layer 120. A semiconductor layer divided into the drain regions 132 and 133 is formed in an island shape, and the gate insulating layer 140 is positioned on the entire surface of the substrate.

In this case, the gate electrode 153 is positioned on the upper gate insulating layer 140 of the active region 131, which is electrically connected to the gate wires 151a and 151b of FIG. 4. In addition, an interlayer insulating layer 160 is disposed on the entire upper surface of the gate insulating layer 140 and the gate electrode 153. The source and drain regions 132 are respectively formed in the interlayer insulating layer 160 and the lower gate insulating layer 140. The first and second contact holes 164a and 164b exposing a part of the first and second portions 133 are formed, so that the source and drain electrodes 172a and 172b positioned on the interlayer insulating layer 160 are respectively the source and drain regions ( 132, 133 to be electrically connected.

In this case, the source electrode 172a is electrically connected to the data line 171 extending in the vertical direction as shown in FIG. 4, and is the same as a general case. The source and drain electrodes 172a and 172b are formed on the substrate. In turn, the passivation layer 162 and the planarization layer 180 are positioned. In particular, the passivation layer 162 and the planarization layer 180 are each formed with a third contact hole 181 penetrating to expose a part of the drain electrode 172b. In addition, the pixel electrode 191 positioned on the planarization layer is electrically connected to the drain electrode 172b through the pixel electrode 191.

On the other hand, in order to prevent damage to the device due to static electricity generated during the manufacturing process of the thin film transistor (T), the gate shorting bar portion for electrically connecting the respective gate wiring (151a, 151b of FIG. 4), The same material as that of the gate electrode 153 of the thin film transistor described above is cut in an appropriate process on the buffer layer 20 and the gate insulating film 40 which are sequentially layered on the substrate 10. In the drawing, the gate shorting bar 154 is electrically disconnected.

The process of the construction and cutting of the gate shorting bar 154 according to the present invention will be described in comparison with the manufacturing process of the thin film transistor. FIGS. 6A to 6D illustrate the gate shorting bar 154 of FIG. A cross section taken along line IV-IV, which is a portion, and line IV'-IV ', which is a thin film transistor portion (T), and is cut along line IV-IV, which is a portion of the gate shorting bar 154, for easy comparison. The cross section cut along the IV'-IV 'line | wire which is a thin film transistor (T) part is arrange | positioned to the right side at one cross section on the left side.

First, when a buffer layer 120 made of a material such as a silicon oxide film (SiO ₂ ) is deposited on the entire surface of the transparent substrate 10, an island-like polycrystalline silicon layer 130 is formed thereon. In order to form the silicon layer 130, a method of depositing polycrystalline silicon directly on a substrate or stacking amorphous silicon on top of the buffer layer 120 and converting the same into crystalline silicon may be used.

At this time, especially in the latter case, a laser heat treatment method of growing a polycrystal by irradiating an excimer laser while heating the substrate temperature on which the amorphous silicon is laminated to about 250 ° C., or depositing a metal on the amorphous silicon to seed the polycrystalline silicon. A metal induced crystallization (MIC) method or a solid phase crystallization (SPC) method for long-term heat treatment of amorphous silicon at a high temperature is used. In this case, the buffer layer 120 is an amorphous silicon layer. Film quality of the polycrystalline silicon layer 130 is reduced by alkali ions (eg, K +, Na +, etc.) present in the substrate 10 due to heat generated during the recrystallization of the polycrystalline silicon layer 130. This prevents the deterioration.

When the polycrystalline silicon layer 130 having an island shape is formed on the buffer layer 120 through the above process, as shown in FIG. 6A, each of the substrate 10 and the buffer layer (T) is formed in the thin film transistor (T). 120 and the island-like polycrystalline silicon layer 130 are sequentially stacked, and only the substrate 10 and the buffer layer 120 stacked thereon exist in the gate shorting bar portion.

Subsequently, as shown in FIG. 6B, the entire surface of the substrate is formed of a material such as a silicon oxide film or a silicon nitride film, and the thickness thereof is about 1800 GPa. The gate insulating layer 140 and the conductive metal are sequentially stacked, and only the conductive metal is patterned. The gate insulating layer 140 deposited on the front surface, the gate shorting bar 154 and the gate wirings 151a and 151b formed thereon, and the gate electrode 153 electrically connected thereto are formed.

In this case, in the present invention, a double stacked structure in which the first and second metal layers 152a and 152b are sequentially stacked is used as the gate wirings 151a and 151b of FIG. 4 and the gate electrode 153. The purpose is to reduce the wiring resistance and solve problems such as hillock caused by high temperature processes. 5 and 6b, the first metal layer at the bottom constituting the gate electrode 153 and the gate shorting bar 154 is denoted by reference numeral 152a and the second metal layer at the top thereof is denoted by reference numeral 152b. In this case, preferably, the first metal layer 152a has a metal containing Al, for example, AlNd, and has a thickness of about 3000 GPa, and the second metal layer 152b has a metal containing Mo. For example, it is advantageous to form Mo using a thickness of about 500 kPa.

Thereafter, the patterned gate electrode 153 is used as a mask, and ions are doped into the polycrystalline silicon layer 130 through the gate insulating layer 140 thereunder. Thus, the polycrystalline silicon layer 130 is ion-doped. The reason for this is to lower the contact resistance between the source and drain electrodes 172a and 172b and the polycrystalline silicon layer 130 to be formed in a later process to impart electrical characteristics thereto. Therefore, by using a gas containing elements of Groups 3 to 5 as a mask using the gate electrode 153 as a mask, ion doping is performed on a portion of the polycrystalline silicon layer 130 through the gate insulating layer 140 below. The two types of regions, the region and the intrinsic region, are distinguished, wherein the impurity regions are the source and drain regions 132 and 133, respectively, and the intrinsic region is the active region 131 of the thin film transistor.

Thereafter, as shown in FIG. 6C, an interlayer insulating film 160 made of a silicon oxide film, a silicon nitride film, or the like is laminated on the entire surface of the substrate so as to have a thickness of about 7000 Å, and the interlayer insulating film 160 and the gate insulating film 140 below it are stacked. By patterning the first and second contact holes 164a and 164b exposing the source and drain regions 132 and 133, and the exposure hole 164c exposing the gate shorting bar 154.

In this case, in particular, the present invention forms the first and second contact holes 164a and 164b and the exposure hole 164c as described above, and simultaneously etches the first metal layer 152a forming the lower layer of the gate shorting bar 154. In other words, the present invention is characterized in that the first and second contact holes 164a and 164b and the gate show in the above-described interlayer insulating film 160 and the gate insulating film 140 by a wet etching method, respectively. An exposure hole 164c is formed in the upper part of the putting bar 154.

Subsequently, when the first and second contact holes 164a and 164b and the exposure hole 164c are formed and then wet etching is continuously performed using the same etchant, the gate shorting bar 154 exposed to the etchant is performed. In addition, a portion of the first metal layer 152a and the second metal layer 152b which is particularly etched, the etching of the first metal layer of AlNd material having a relatively low chemical corrosion resistance is more active, especially its thickness Since it has a small size of about 3000 Å, the exposed area is spaced apart from each other around the center of the large exposure hole 164c.

Therefore, as shown in the enlarged view of part of FIG. 6C, the first metal layer 152a of the lower layer is spaced apart from each other, and the second metal layer 152b positioned at an upper portion thereof connects the upper portion of the first metal layer. It has a Mo-bridge shape, preferably an upper gate shorting bar made of an upper second metal layer 152b, i.e., a Mo-bridge, as in a circle drawing M 'showing a plan view of the inside drawing M. It will have a neck shape with a narrower width than the portion.

Forming the upper second metal layer 152b in the shape of a neck may include a portion of the second metal layer 152b made of Mo metal having a relatively high corrosion resistance in the wet etching process so as to separate the first metal layer 152a. Since it is etched, it can be naturally formed by adjusting the supply time of the etchant and the concentration thereof, in order to facilitate this, the present invention has a thickness of about 500 kPa, which forms the source and drain electrodes 172a and 172b described below. In order to enable more reliable cutting in the patterning process for.

At this time, if the width of the neck-shaped Mo-bridge formed by the second metal layer 152b is too small, it may be easily torn off by physical impact, so it is preferable to have a size of about 4 μm, The angle of the inclined surface connecting the neck-shaped portion having a width and another adjacent width portion is preferably about 100 to 160 °, and the first metal layer spaced apart from each other by the lower layer of the Mo-bridge, which is the upper second metal layer 152b. When the distance between 152a is too large, since the neck-like part which Mo-bridge of the 2nd metal layer 152b has may be damaged similarly to the above-mentioned, the distance of the lower 2nd metal layer 152a is preferable. It is advantageous to achieve a few μm.

Thereafter, as illustrated in FIG. 6D, a third metal layer is deposited on the entire surface of the substrate and patterned to form the data lines 171 and the source and drain electrodes 172a and 172b, respectively. In this case, the data lines 171 are the gate lines 151a. As described above, the first and second contact holes 61 are electrically connected to the source and drain regions 132 and 133 through the first and second contact holes 61.

As the material of the third metal layer for implementing the source and drain electrodes 172a and 172b and the data line 171, Mo metal is preferably used. In this case, the upper Mo-bridge type of the gate shorting bar 154 may be used. A third metal layer of the same material is stacked on the upper surface of the second metal layer 152b, but it is also removed in the patterning process for the source and drain electrodes 172a and 172b, and at the same time, the second metal layer 152b forming the lower upper gate shorting bar is also formed. It is removed together in the same process.

Particularly, in the present invention, the thickness of the second metal layer 152b made of the upper Mo metal is about 500 mm, and the shape of the second metal layer 152b is narrow, which is used in the aforementioned patterning process of the source and drain electrodes 172a and 172b. It can be easily cut with an etchant, and in particular, since the width of the second metal layer 152b is also small as about 4 μm, reliable cutting is possible.

Therefore, through this process, the gate shorting bar 154 is electrically disconnected, which is not shown in the drawings, but the external gate circuit (S of FIG. 4) to which the gate wirings 151a and 151b are extended and connected is described above. This is because the antistatic circuit implemented in the same process as the process of forming the source and drain electrodes 172a and 172b is completed, so it does not need to remain.

As shown in FIG. 5, the thin film transistor configured through this process is formed by sequentially stacking the protective film 162 and the planarization film over the entire surface of the substrate 10 on which the source and drain electrodes 172a and 172b are formed. As a result, a third contact hole 181 through which a portion of the drain electrode 172b is exposed is formed, and then a transparent conductive material electrically connected to the drain electrode 172b through the third contact hole 181. The pixel electrode 191 is formed.

The present invention provides a gate shorting bar having a double stacked structure in which first and second metals are laminated, and in particular, a first metal layer in a lower layer is spaced apart from each other, and a second metal layer in the upper portion is formed in a bridge shape connecting them. This enables more reliable cutting. In this case, the second metal layer is given a neck shape of about 4 μm, the width of which is relatively small, and the separation distance between the first metal layers spaced apart from each other is several μm or less, thereby improving the resistance to physical impact. Provides a gated shorting bar.

When the gate shorting bar according to the present invention is applied to an array substrate, it is possible to further minimize the chemical impact applied to the substrate, and thus, it is possible to implement a more reliable device.

Claims (5)

Providing a substrate; Forming a buffer layer on one surface of the substrate; Forming an island-like polycrystalline silicon layer on top of the buffer layer; Stacking a gate insulating film, a first metal layer including Al, and a second metal layer including Mo on top of the polycrystalline silicon layer and the buffer layer; Etching the first and second metal layers to form a gate electrode, a gate wiring, and a gate shorting bar; Forming an active region, a source and a drain region in the polycrystalline silicon layer using the gate electrode as a mask; Forming an interlayer insulating film over the gate electrode and the gate insulating film; First and second contact holes exposing portions of the source and drain regions by etching the interlayer passivation layer and the gate insulating layer thereunder, an opening hole exposing the upper gate shorting bar, and a lower layer first of the gate shorting bar. Forming metal layers spaced apart from each other; Stacking a third metal layer including Mo on the interlayer insulating film; Etching the third metal layer to remove the third metal layer and the lower second metal layer stacked above the gate shorting bar, and forming source and drain electrodes electrically connected to the source and drain regions, respectively. Method of manufacturing an array panel for a liquid crystal display device comprising a The method according to claim 1, The interlayer insulating film is a silicon nitride film having a thickness of 6500 to 7500 kPa, the first metal layer is AlNd having a thickness of 2500 to 3500 kPa, and the second and third metal layers are Mo having a thickness of 450 to 550 kPa. Manufacturing method of array panel for device The method according to claim 1, The upper gate shorting bar has a neck shape having a narrower width than other portions. The method according to claim 3, The neck-shaped upper gate shorting bar has a width of 4 μm or less, and an angle between the inclined surface connecting different widths and the neck-shaped gate shorting bar is 100 to 160 °, and the lower gate showing bar is formed around the upper gate shorting bar. Method of manufacturing an array panel for a liquid crystal display device having a separation distance of several μm or less Array panel for a liquid crystal display device comprising a gate shorting bar formed and removed by the method of claim 1