JP2008216940A - Manufacturing method of electro-optical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture an electro-optical device capable of displaying an image of high quality. <P>SOLUTION: The manufacturing method of the electro-optical device includes the steps of: forming a base insulating film 12 on a substrate 10; forming a semiconductor film 1aa on the base insulating film; forming a semiconductor layer 1a constituting a transistor 30 by etching the semiconductor film to pattern the semiconductor film in a predetermined pattern and also forming a recessed portion 810 on a top surface of the base insulating film by etching the base insulating film as well; and forming a gate electrode 3b constituting the transistor so that the gate electrode has a main body portion 3b1 overlapping a channel region 1a' on the semiconductor layer and an extension portion 3b2 extended from the main body portion to at least a portion in the recessed portion. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technical field of a method for manufacturing an electro-optical device such as a liquid crystal device.

  A liquid crystal device which is an example of this type of electro-optical device is frequently used not only as a direct-view display but also as a light modulation means (light valve) of, for example, a projection display device. In particular, in the case of a projection display device, strong light from a light source is incident on a liquid crystal light valve, and this thin film transistor (TFT: Thin Film Transistor) in the liquid crystal light valve does not cause an increase in leakage current or malfunction. As described above, a light shielding film as a light shielding means for blocking incident light is built in the liquid crystal light valve. Regarding such a light shielding means or a light shielding film, for example, Patent Document 1 discloses a technique for improving light shielding properties by forming a scanning line functioning as a gate electrode of a TFT in a groove formed beside a channel region. Has been.

JP 2004-170910 A

  The groove as described above is formed by performing an etching process on a predetermined position in a base insulating film that is a base of the semiconductor layer after the semiconductor layer constituting the TFT is formed in a predetermined pattern. For this reason, there is a technical problem that the number of manufacturing steps in the manufacturing process of the electro-optical device may increase by the number of steps for forming the grooves.

  The present invention has been made in view of the above-described problems, for example. An electro-optical device capable of reducing the generation of light leakage current in a TFT and displaying a high-quality image without increasing the number of manufacturing steps. It is an object to provide a method for manufacturing an electro-optical device to be manufactured.

  In order to solve the above problems, an electro-optical device manufacturing method according to the present invention is an electro-optical device for manufacturing an electro-optical device including a pixel electrode and a transistor electrically connected to the pixel electrode on a substrate. A method for manufacturing an apparatus, comprising: forming a base insulating film on the substrate; forming a semiconductor film on the base insulating film; and etching the semiconductor film to form the semiconductor film. Forming a semiconductor layer constituting the transistor by patterning and forming the recess on the upper surface of the base insulating film by performing the etching process on the base insulating film; and A gate electrode that constitutes a channel region in the semiconductor layer and an extending portion that extends from the main body portion to at least a part of the recess. Forming as the as the transistors electrically connected, and a step of forming the pixel electrode.

  During operation of the electro-optical device manufactured by the method of manufacturing an electro-optical device according to the present invention, for example, an image signal supplied from a data line to a pixel electrode is controlled by a transistor, and a pixel region in which a plurality of pixel electrodes are arranged Thus, image display by the so-called active matrix method can be performed. The image signal is supplied from the data line to the pixel electrode via the transistor at a predetermined timing when a transistor, which is a switching element electrically connected between the data line and the pixel electrode, is turned on / off.

  According to the method for manufacturing an electro-optical device according to the present invention, first, a base insulating film is formed from, for example, a silicon oxide film on a substrate such as a quartz substrate or a glass substrate. At this time, the base insulating film is typically formed on the entire surface of the substrate. Next, after forming a semiconductor film made of, for example, a polysilicon film over the entire surface of the substrate, for example, over the entire surface of the base insulating film, the semiconductor film is patterned by an etching process so that the semiconductor layer constituting the transistor is arranged for each pixel. To form. Next, a transistor is formed by forming a gate electrode included in the transistor so as to overlap with a channel region in the semiconductor layer, for example, with a gate insulating film interposed therebetween. The gate electrode is formed of a light-shielding conductive film such as a metal film, for example, and also functions as a built-in light-shielding film that shields light incident on the channel region of the transistor from the upper layer side. Therefore, generation of light leakage current in the transistor can be reduced. Note that a normal semiconductor integration technique can be used in the process of forming the transistor.

  In the present invention, in particular, a recess is formed on the upper surface of the base insulating film by performing an etching process applied to the semiconductor film also on the base insulating film. Further, in the step of forming the gate electrode, the gate electrode is formed so as to have a main body portion that overlaps the channel region and an extending portion that extends from the main body portion to at least a part of the recess.

  Therefore, the extending portion is formed as a wall-shaped light shielding body adjacent to the channel region in the semiconductor layer as viewed three-dimensionally. In other words, the extending portion is formed as a side wall light shield that covers the channel region in the semiconductor layer from the side surface side. Accordingly, light that is obliquely incident on the channel region in the semiconductor layer or light that is incident on the channel region from the side surface of the semiconductor layer (that is, light having a component along the substrate surface) is formed in the recess. It can be blocked by the extended part. That is, the gate electrode can be formed so as to have an extending portion as a wall-shaped light shielding body arranged in the vicinity of the semiconductor layer, and has a light shielding property that blocks light incident obliquely on the semiconductor layer (that is, The light shielding property of the side surface of the semiconductor layer can be enhanced. As a result, flicker and pixel unevenness in image display can be reduced.

  Further, the recess is subjected to etching treatment when patterning the semiconductor film also on the base insulating film (that is, for example, when etching processing is performed on the semiconductor film, overetching is performed on the base insulating film. The etching conditions are set so as to be applied), thereby forming an upper surface of the base insulating film. That is, the patterning of the semiconductor film and the formation of the recess in the base insulating film are performed at the same opportunity. In other words, the semiconductor layer constituting the transistor and the recess in the base insulating film are formed by a common etching process. Therefore, there is little or no increase in the number of manufacturing steps in the manufacturing process of the electro-optical device. In other words, the number of manufacturing steps can be reduced as compared with the case where the recess is formed in the vicinity of the semiconductor layer by an etching process different from the etching process for patterning the semiconductor film.

  In addition, if the recess is formed in the vicinity of the semiconductor layer by an etching process different from the etching process for patterning the semiconductor film, the etching process for forming the recess is performed at least from the semiconductor layer, for example. It is necessary to apply the difference by a difference (that is, a misalignment margin from a desired position). However, according to the present invention, since the concave portion is formed by performing the etching process for patterning the semiconductor film also on the base insulating film, the concave portion can be formed at a position closer to the semiconductor layer. Therefore, the extending portion as a wall-shaped light shielding body can be formed at a position closer to the semiconductor layer. Therefore, the light shielding property of the side surface of the semiconductor layer can be enhanced.

  As described above, according to the method for manufacturing an electro-optical device according to the present invention, the generation of light leakage current in the TFT can be reduced without causing an increase in the number of manufacturing steps, and an electric device capable of displaying a high-quality image. It is possible to manufacture an optical device.

  In one aspect of the method for manufacturing an electro-optical device according to the present invention, in the step of forming the gate electrode, the gate electrode is formed so as to include a light-shielding conductive material.

  According to this aspect, the gate electrode is formed so as to include a light-shielding conductive material such as a refractory metal material such as tungsten (W), titanium (Ti), or titanium nitride (TiN). Therefore, the gate electrode can reliably function as a light-shielding film that shields light incident on the transistor.

  In another aspect of the method for manufacturing an electro-optical device according to the present invention, the lower light-shielding film is provided on the lower layer side of the base insulating film so as to at least partially overlap the semiconductor layer and include a light-shielding material. Forming a step.

  According to this aspect, the lower light-shielding film causes back-surface reflection on the substrate, light emitted from another electro-optical device by a multi-plate projector, etc., and the like that penetrates the composite optical system, and the like from the substrate side into the device. The transistor can be shielded from incident return light. Therefore, generation of light leakage current in the transistor can be more reliably reduced.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, an embodiment of a method for manufacturing an electro-optical device according to the invention will be described with reference to the drawings. In this embodiment, as an example of the electro-optical device, a TFT active matrix driving type liquid crystal device with a built-in driving circuit is taken as an example.

<First Embodiment>
First, an overall configuration of the liquid crystal device according to the present embodiment manufactured using the method for manufacturing a liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of the liquid crystal device when the TFT array substrate is viewed from the side of the counter substrate together with the components formed thereon, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG. is there.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. The TFT array substrate 10 is a transparent substrate such as a quartz substrate, a glass substrate, or a silicon substrate. The counter substrate 20 is also a transparent substrate, like the TFT array substrate 10. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20. The TFT array substrate 10 and the counter substrate 20 are bonded to each other by a sealing material 52 provided in a sealing region located around the image display region 10a provided with a plurality of pixel electrodes.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. In the sealing material 52, a gap material such as glass fiber or glass bead is dispersed for setting the distance between the TFT array substrate 10 and the counter substrate 20 (that is, the inter-substrate gap) to a predetermined value. The liquid crystal device according to this embodiment is small and suitable for performing enlarged display for a light valve of a projector.

  A light-shielding frame light-shielding film 53 that defines the frame area of the image display area 10a is provided on the counter substrate 20 side in parallel with the inside of the seal area where the sealing material 52 is disposed. However, part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side.

  A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The scanning line driving circuit 104 is provided along two sides adjacent to the one side so as to be covered with the frame light shielding film 53. Further, in order to connect the two scanning line driving circuits 104 provided on both sides of the image display area 10 a in this way, a plurality of the pixel lines are covered along the remaining side of the TFT array substrate 10 and covered with the frame light shielding film 53. Wiring 105 is provided.

  Vertical conductive members 106 functioning as vertical conductive terminals between the two substrates are disposed at the four corners of the counter substrate 20. On the other hand, the TFT array substrate 10 is provided with vertical conduction terminals in a region facing these corner portions. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  In FIG. 2, on the TFT array substrate 10, an alignment film is formed on the pixel electrode 9a after the pixel switching TFT, the scanning line, the data line, and the like are formed. The pixel electrode 9a is made of a transparent conductive film such as an ITO film, and the alignment film is made of an organic film such as a polyimide film. On the other hand, on the counter substrate 20, a lattice-shaped or striped light-shielding film 23 is formed, and then a counter electrode 21 is provided over the entire surface, and an alignment film is formed on the uppermost layer portion. Yes. The counter electrode 21 is made of a transparent conductive film such as an ITO film, and the alignment film is made of an organic film such as a polyimide film. A liquid crystal layer 50 is formed between the TFT array substrate 10 and the counter substrate 20 that are configured as described above and are arranged so that the pixel electrode 9a and the counter electrode 21 face each other. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  1 and 2, on the TFT array substrate 10, in addition to the drive circuits such as the data line drive circuit 101 and the scanning line drive circuit 104, the image signal on the image signal line is sampled to obtain data. Sampling circuit that supplies lines, precharge circuit that supplies pre-charge signals of a predetermined voltage level to multiple data lines in advance of image signals, inspection of quality, defects, etc. of the electro-optical device during production or shipment An inspection circuit or the like may be formed.

  Next, an electrical configuration of the pixel portion of the liquid crystal device according to the present embodiment will be described with reference to FIG. FIG. 3 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming the image display area of the liquid crystal device according to this embodiment.

  In FIG. 3, a pixel electrode 9 a and a TFT 30 as an example of a “transistor” according to the present invention are formed in each of a plurality of pixels formed in a matrix form that constitutes the image display region 10 a. The TFT 30 is electrically connected to the pixel electrode 9a, and performs switching control of the pixel electrode 9a during the operation of the liquid crystal device according to the present embodiment. The data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. May be.

  The scanning line 3a is electrically connected to the gate of the TFT 30, and the liquid crystal device according to the present embodiment applies scanning signals G1, G2,..., Gm to the scanning line 3a in a pulsed manner at a predetermined timing. It is configured to apply line-sequentially in this order. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,... Supplied from the data line 6a is closed by closing the switch of the TFT 30 serving as a switching element for a certain period. Sn is written at a predetermined timing. A predetermined level of image signals S1, S2,..., Sn written in the liquid crystal as an example of the electro-optical material via the pixel electrode 9a is held for a certain period with the counter electrode formed on the counter substrate. The

  The liquid crystal constituting the liquid crystal layer 50 (see FIG. 2) modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The transmittance for light is increased, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device as a whole.

  In order to prevent the image signal held here from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode 21 (see FIG. 2). The storage capacitor 70 is a capacitive element that functions as a storage capacitor that temporarily holds the potential of each pixel electrode 9a in response to supply of an image signal. One electrode of the storage capacitor 70 is connected to the drain of the TFT 30 in parallel with the pixel electrode 9a, and the other electrode is connected to the capacitor line 300 with a fixed potential so as to have a constant potential. According to the storage capacitor 70, the potential holding characteristic in the pixel electrode 9a is improved, and display characteristics such as contrast improvement and flicker reduction can be improved.

  Next, a specific configuration of the pixel portion that realizes the above-described operation will be described with reference to FIGS. FIG. 4 is a plan view of a plurality of adjacent pixel portions. FIG. 5 is a cross-sectional view taken along the line A-A ′ of FIG. 4. In FIGS. 4 and 5, the scale of each layer / member is different for each layer / member to have a size that can be recognized on the drawing. In FIG. 4 and FIG. 5, for convenience of explanation, illustration of a portion located above the pixel electrode 9a is omitted.

  In FIG. 4, a plurality of pixel electrodes 9 a are provided in a matrix on the TFT array substrate 10. Data lines 6a and scanning lines 3a are provided along the vertical and horizontal boundaries of the pixel electrode 9a. That is, the scanning line 3a extends along the X direction, and the data line 6a extends along the Y direction so as to intersect the scanning line 3a. A pixel switching TFT 30 is provided at each of the locations where the scanning line 3a and the data line 6a intersect each other.

  The scanning line 3a, the data line 6a, the storage capacitor 70, the lower light-shielding film 11a, the relay layer 93, and the TFT 30 are viewed on the TFT array substrate 10 in plan view, that is, an opening area of each pixel corresponding to the pixel electrode 9a (that is, In each pixel, the pixel is disposed in a non-opening region surrounding a region where light that actually contributes to display is transmitted or reflected. That is, the scanning line 3a, the data line 6a, the storage capacitor 70, the relay layer 93, the lower light shielding film 11a, and the TFT 30 are not in the opening area of each pixel but in the non-opening area so as not to disturb the display. Has been placed.

  4 and 5, the TFT 30 includes a semiconductor layer 1a and a gate electrode 3b formed as a part of the scanning line 3a.

  The semiconductor layer 1a is made of, for example, polysilicon, and has a channel region 1a ′ having a channel length along the Y direction, a data line side LDD region 1b, a pixel electrode side LDD region 1c, a data line side source / drain region 1d, and a pixel electrode side. It consists of a source / drain region 1e. That is, the TFT 30 has an LDD structure.

  The data line side source / drain region 1d and the pixel electrode side source / drain region 1e are formed substantially in mirror symmetry along the Y direction with respect to the channel region 1a '. The data line side LDD region 1b is formed between the channel region 1a 'and the data line side source / drain region 1d. The pixel electrode side LDD region 1c is formed between the channel region 1a 'and the pixel electrode side source / drain region 1e. The data line side LDD region 1b, the pixel electrode side LDD region 1c, the data line side source / drain region 1d, and the pixel electrode side source / drain region 1e are impurities formed by implanting impurities into the semiconductor layer 1a by, for example, ion implantation. It is an area. The data line side LDD region 1b and the pixel electrode side LDD region 1c are formed as low concentration impurity regions with less impurities than the data line side source / drain region 1d and the pixel electrode side source / drain region 1e, respectively. According to such an impurity region, when the TFT 30 is not operating, the off-current flowing between the source region and the drain region can be reduced, and a decrease in the on-current flowing when the TFT 30 is operating can be suppressed. Although the TFT 30 preferably has an LDD structure, the TFT 30 may have an offset structure in which no impurity is implanted into the data line side LDD region 1b and the pixel electrode side LDD region 1c. A self-alignment type in which the data line side source / drain region and the pixel electrode side source / drain region are formed by implanting the concentration may be used.

  4 and 5, the gate electrode 3b is formed as a part of the scanning line 3a. The scanning line 3a is formed so as to extend along the X direction. A portion of the scanning line 3a that overlaps the channel region 1a 'functions as the gate electrode 3b. The gate electrode 3b and the semiconductor layer 1a are insulated by the gate insulating film 2.

  Particularly in the present embodiment, the scanning line 3a is formed of a tungsten silicide (WSi) film. Therefore, the scanning line 3 a can function reliably as a light shielding film that blocks light incident on the TFT 30. In particular, light incident on the channel region 1a 'from the upper layer side can be reliably blocked by the gate electrode 3b which is a portion of the scanning line 3a overlapping the channel region 1a'. Therefore, generation of light leakage current in the TFT 30 can be reduced.

  As will be described in detail later with reference to FIG. 6, a recess 810 that is recessed from the surface on which the semiconductor layer 1a is provided is formed in the base insulating film 12 that is the base of the semiconductor layer 1a that constitutes the TFT 30. The gate electrode 3b has an extended portion 3b2 that extends into the recess 810.

  4 and 5, a lower light shielding film 11a is provided in a lattice pattern on the lower layer side of the TFT 30 on the TFT array substrate 10 with the base insulating film 12 interposed therebetween. The lower light-shielding film 11a includes, for example, a metal simple substance, an alloy, a metal silicide, a polysilicide, or a laminate of at least one of refractory metals such as Ti, Cr, W, Ta, Mo, and Pd. It is made of a light shielding material such as. The lower light-shielding film 11a is reflected from the back surface of the TFT array substrate 10 or light emitted from another liquid crystal device by a multi-plate projector or the like and penetrates the combined optical system, and enters the device from the TFT array substrate 10 side. The channel region 1a ′ of the TFT 30 and its surroundings are shielded from incident return light.

  In FIG. 5, the base insulating film 12 is formed on the entire surface of the TFT array substrate 10 in addition to the function of interlayer insulating the TFT 30 from the lower light-shielding film 11 a, so that roughening during polishing of the surface of the TFT array substrate 10 can be achieved. The pixel switching TFT 30 has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to dirt remaining after cleaning.

  In FIG. 5, a storage capacitor 70 is provided on the upper layer side of the TFT 30 on the TFT array substrate 10 via the interlayer insulating film 41.

  The storage capacitor 70 is formed by disposing the lower capacitor electrode 71 and the upper capacitor electrode 300a so as to face each other with the dielectric film 75 interposed therebetween.

  The upper capacitor electrode 300 a is formed as a part of the capacitor line 300. The capacitance line 300 extends from the image display area 10a where the pixel electrode 9a is disposed to the periphery thereof. The upper capacitor electrode 300a is a fixed potential side capacitor electrode that is electrically connected to a constant potential source via the capacitor line 300 and maintained at a fixed potential. The upper capacitor electrode 300a is formed of a non-transparent metal film containing a metal or alloy such as Al (aluminum) or Ag (silver), for example, and also functions as an upper light shielding film (built-in light shielding film) that shields the TFT 30. To do. The upper capacitor electrode 300a is formed by laminating a single metal, an alloy, a metal silicide, a polysilicide, or the like including at least one of refractory metals such as Ti, Cr, W, Ta, Mo, and Pd. You may be comprised from things. In this case, the function of the upper capacitor electrode 300a as a built-in light shielding film can be enhanced.

  The lower capacitor electrode 71 is a pixel potential side capacitor electrode electrically connected to the pixel electrode side source / drain region 1e of the TFT 30 and the pixel electrode 9a. More specifically, the lower capacitor electrode 71 is electrically connected to the pixel electrode side source / drain region 1 e through the contact hole 83 and electrically connected to the relay layer 93 through the contact hole 84. Yes. Further, the relay layer 93 is electrically connected to the pixel electrode 9 a through the contact hole 85. That is, the lower capacitor electrode 71 relays the electrical connection between the pixel electrode side source / drain region 1e and the pixel electrode 9a together with the relay layer 93. The lower capacitor electrode 71 is made of conductive polysilicon. Therefore, the storage capacitor 70 has a so-called MIS structure. The lower capacitance electrode 71 has a function as a light absorption layer or a light shielding film disposed between the upper capacitance electrode 300a as the upper light shielding film and the TFT 30 in addition to the function as the pixel potential side capacitance electrode.

  The dielectric film 75 is, for example, a single layer structure or a multilayer structure formed of a silicon oxide (SiO 2) film such as an HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film, or a silicon nitride (SiN) film. have.

  The lower capacitor electrode 71 may be formed of a metal film in the same manner as the upper capacitor electrode 300a. That is, the storage capacitor 70 may be formed to have a so-called MIM structure having a three-layer structure of metal film-dielectric film (insulating film) -metal film. In this case, compared to the case where the lower capacitor electrode 71 is formed using conductive polysilicon or the like, the power consumption of the entire liquid crystal device can be reduced when the liquid crystal device is driven, and each pixel unit can be reduced. The device can be operated at high speed.

  In FIG. 5, a data line 6 a and a relay layer 93 are provided on the upper layer side of the storage capacitor 70 on the TFT array substrate 10 via the interlayer insulating film 42. An insulating film 61 is partially interposed between the interlayer insulating films 41 and 42.

  The data line 6a is electrically connected to the data line side source / drain region 1d of the semiconductor layer 1a through a contact hole 81 penetrating the interlayer insulating film 41, the insulating film 61, and the interlayer insulating film. The data line 6a and the inside of the contact hole 81 are made of, for example, an Al (aluminum) -containing material such as Al—Si—Cu or Al—Cu, Al alone, or a multilayer film including an Al layer and a TiN layer. The data line 6a also has a function of shielding the TFT 30 from light.

  The relay layer 93 is formed in the same layer as the data line 6 a on the interlayer insulating film 42. For the data line 6a and the relay layer 93, a thin film made of a conductive material such as a metal film is formed on the interlayer insulating film 42 using a thin film forming method, and the thin film is partially removed, that is, patterned. Thus, they are formed apart from each other. Therefore, since the data line 6a and the relay layer 93 can be formed in the same process, the manufacturing process of the device can be simplified.

  In FIG. 5, the pixel electrode 9a is formed on the upper layer side of the data line 6a via the interlayer insulating film 43. The pixel electrode 9a is electrically connected to the pixel electrode side source / drain region 1e of the semiconductor layer 1a through the lower capacitor electrode 71, the contact holes 83, 84 and 85, and the relay layer 93. The contact hole 85 is formed by depositing a conductive material constituting the pixel electrode 9a such as ITO on the inner wall of a hole formed so as to penetrate the interlayer insulating layer 43. An alignment film subjected to a predetermined alignment process such as a rubbing process is provided on the upper surface of the pixel electrode 9a.

  The configuration of the pixel portion described above is common to each pixel portion as shown in FIG. Such pixel portions are periodically formed in the image display area 10a (see FIG. 1).

  Next, a configuration related to the TFT in the pixel portion described above will be described in detail with reference to FIG. FIG. 6 is a sectional view taken along line B-B ′ in FIG. 4. In FIG. 6, the components on the upper layer side from the interlayer insulating film 42 are not shown.

  As shown in FIG. 6, a recess 810 is formed in the base insulating film 12. The recess 810 is formed such that a portion of the upper surface of the base insulating film 12 excluding the portion where the semiconductor layer 1a is formed is recessed from the portion where the semiconductor layer 1a is formed. As will be described in detail later with reference to FIG. 7, the recess 810 is also subjected to the etching process for patterning the semiconductor film 1aa which is the precursor film of the semiconductor layer 1a. Thus, an upper surface of the base insulating film 12 is formed.

  The gate electrode 3 b has a main body 3 b 1 that overlaps the channel region 1 a ′ of the semiconductor layer 1 a and an extension 3 b 2 that extends into the recess 810. The extending portion 3b2 is formed as a wall-shaped light shielding body adjacent to the channel region 1a 'in the semiconductor layer 1a when viewed three-dimensionally. In other words, the scanning line 3a functioning as a gate electrode is formed so as to cover the upper surface and side surfaces of the channel region 1a of the semiconductor layer 1a. Accordingly, light incident obliquely on the channel region 1a ′ in the semiconductor layer 1a (that is, light having a component along the X direction or Y direction, for example, along the direction indicated by the arrow P1 in FIG. 6). Light) can be blocked by the extension 3b2 formed in the recess 810. That is, the light shielding property of the side surface of the semiconductor layer 1a can be enhanced by the extending portion 3b2. As a result, light leakage current in the TFT 30 can be reduced, and flicker and pixel unevenness in image display can be reduced.

  Next, a manufacturing method of the liquid crystal device according to the above-described embodiment will be described with reference to FIG. 7 in addition to FIGS. FIG. 7 is a process diagram showing each step of the manufacturing process of the liquid crystal device according to this embodiment, and corresponds to the cross-sectional view shown in FIG. In the following, the process of forming the pixel switching TFT of the liquid crystal device according to the present embodiment will be mainly described.

  First, in the process shown in FIG. 7A, the image display region 10a on the TFT array substrate 10 contains a single metal containing at least one of refractory metals such as Ti, Cr, W, Ta, and Mo. Then, an alloy, a metal silicide, a polysilicide, or a laminate of these is laminated to form the lower light shielding film 11a of a predetermined pattern. At this time, the lower light-shielding film 11a is formed in a lattice shape so as to have a portion overlapping with the TFT 30 to be formed later as a predetermined pattern.

  Subsequently, a base insulating film 12 is formed on the entire surface of the TFT array substrate 10. The base insulating film 12 is formed by, for example, TEOS (tetraethylorthosilicate) gas, TEB (tetraethylboatrate) gas, TMOP (tetramethylmethylrate) by atmospheric pressure or low pressure CVD (Chemical Vapor Deposition) method or the like. It is formed from a silicate glass film such as NSG, PSG, or BSG, a nitride film, a silicon oxide film, or the like using an oxy-phosphorate gas or the like. Note that after the base insulating film 12 is formed, the surface thereof may be planarized by performing a planarization process such as a CMP process (Chemical Mechanical Polishing).

  Subsequently, a semiconductor film 1aa such as a polysilicon film is formed on the base insulating film 12.

  Next, in the step shown in FIG. 7B, after a resist film 510 having a predetermined pattern is formed on the semiconductor film 1aa, an etching process is performed on the semiconductor film 1aa via the resist film 510 (in the drawing, a downward arrow is used). Apply). Thereby, the semiconductor layer 1a constituting the TFT 30 is formed for each pixel. At this time, in this embodiment, in particular, the recess 810 is formed on the upper surface of the base insulating film 12 by performing the etching process performed on the semiconductor film 1aa also on the base insulating film 12. That is, when the etching process is performed on the semiconductor film 1aa, the base insulating film 12 is over-etched (that is, the etching process is performed below the broken line in the drawing). Etching conditions are set. For this reason, the patterning of the semiconductor film 1aa and the formation of the recess 810 in the base insulating film 12 are performed on the same occasion. Therefore, there is little or no increase in the number of manufacturing steps in the manufacturing process of the liquid crystal device. In other words, the number of manufacturing steps can be reduced as compared with the case where the recess 810 is formed in the base insulating film 12 by an etching process different from the etching process for patterning the semiconductor film 1aa.

  After performing such an etching process, the resist film 510 is removed.

  Next, in the step shown in FIG. 7C, the gate insulating film 2 is formed on the semiconductor layer 1a by thermally oxidizing the semiconductor layer 1a.

  Subsequently, the scanning line 3a including the gate electrode 3b is formed of a light-shielding conductive material such as tungsten silicide (WSi) so as to extend along the X direction in FIG. At this time, the gate electrode 3b is formed so as to have a main body 3b1 overlapping the channel region and an extending portion 3b2 extending from the main body 3b1 into the recess 810. As described above with reference to FIG. 6, the light shielding property of the side surface of the semiconductor layer 1a can be enhanced by the extending portion 3b2.

  Particularly in the present embodiment, as described above, the etching process performed on the semiconductor film 1aa is also performed on the base insulating film 12, thereby forming the recess 810 on the upper surface of the base insulating film 12. Therefore, the extending part 3b2 can be formed at a position closer to the semiconductor layer 1a. That is, if a recess is formed in the vicinity of the semiconductor layer 1a by an etching process different from the etching process for patterning the semiconductor film 1aa, the etching process for forming the recess is performed from the semiconductor layer 1a. For example, it is necessary to apply at least a tolerance. However, according to the present embodiment, the recess 810 is formed by performing the etching process when patterning the semiconductor film 1aa also on the base insulating film 12, and thus the recess 810 is formed at a position closer to the semiconductor layer 1a. Can do. Therefore, the extending portion 3b2 as a wall-shaped light shielding body with respect to the side surface of the semiconductor layer 1a can be formed at a position closer to the semiconductor layer 1a. Therefore, the light shielding property of the side surface of the semiconductor layer 1a can be further enhanced.

  Thereafter, in FIG. 5, by doping the semiconductor layer 1a with impurity ions, the data line side LDD region 1b, the pixel electrode side LDD region 1c, the data line side source / drain region 1d and the pixel electrode side are added to the semiconductor layer 1a. The source / drain region 1e is formed, and the TFT 30 is formed. Note that a normal semiconductor integration technique can be used in the process of forming the TFT 30. Subsequently, an interlayer insulating film 41 is formed on the entire surface of the TFT array substrate 10. The interlayer insulating film 41 is formed of, for example, a silicate glass film such as NSG, PSG, or BSG, a nitride film, a silicon oxide film, or the like using TEOS gas, TEB gas, TMOP gas, or the like by atmospheric pressure or low pressure CVD. The Note that after the formation of the interlayer insulating film 41, the surface thereof may be planarized by, for example, a CMP process. Subsequently, an etching process is performed at a predetermined position on the surface of the interlayer insulating film 41 to form a contact hole 83 having a depth reaching the pixel electrode side source / drain region 1e. Subsequently, a conductive polysilicon film is laminated to form a lower capacitor electrode 71 having a predetermined pattern. The lower capacitor electrode 71 is connected to the pixel electrode side source / drain region 1e through the contact hole 83. Subsequently, the insulating film 61 is stacked on the interlayer insulating film 41 and the lower capacitor electrode 71. Subsequently, a resist having a predetermined pattern is stacked on the insulating film 61 and etched to form an opening so that the lower capacitor electrode 71 is exposed. At this time, the insulating film 61 is formed so as to leave a portion that has run over the lower capacitor electrode 71. By forming such an insulating film 61, the interlayer distance between the end face of the lower capacitor electrode 71 and the end face of the upper capacitor electrode 300a to be formed later can be increased as compared with the case where the insulating film 61 is not formed. Therefore, it is possible to prevent unintended current leakage between the end face of the lower capacitor electrode 71 and the end face of the upper capacitor electrode 300a. Subsequently, a dielectric film 75 having a predetermined pattern is formed from, for example, a silicon nitride film. Subsequently, an Al film is stacked on the dielectric film 75 to form the upper capacitor electrode 300a (in other words, the capacitor line 300 (see FIG. 4)) having a predetermined pattern, thereby forming the storage capacitor 70. Subsequently, an interlayer insulating film 42 is laminated on the entire surface of the TFT array substrate 10. Subsequently, etching is performed at a predetermined position on the surface to open contact holes 81 and 84. Subsequently, the data line 6 a and the relay layer 93 are formed on the interlayer insulating film 42. The data line 6a is connected to the data line side source / drain region 1d through a contact hole 81 penetrating the insulating film 61 and the interlayer insulating films 41 and. The relay layer 93 is connected to the lower capacitor electrode 71 through a contact hole 84. Subsequently, an interlayer insulating film 43 is laminated on the entire surface of the TFT array substrate 10. Subsequently, etching is performed at a predetermined position on the surface to form a contact hole 85. Subsequently, the pixel electrode 9 a is formed at a predetermined position on the surface of the interlayer insulating film 43. The pixel electrode 9 a is connected to the relay layer 93 through a contact hole 85.

  According to the manufacturing method of the liquid crystal device described above, the above-described liquid crystal device can be manufactured. In particular, since the recess 810 is formed on the upper surface of the base insulating film 12 by performing the etching process performed on the semiconductor film 1aa also on the base insulating film 12, a process for forming the recess 810 is performed. There is no need to increase the number of steps such as providing them separately, and the gate electrode 3b can be formed to have the extended portion 3b2 extended in the concave portion 810. Such an extended portion 3b2 can improve the light shielding property of the side surface of the semiconductor layer 1a and reduce the occurrence of light leakage current in the TFT 30.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change. These manufacturing methods are also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is the H-H 'sectional view taken on the line of FIG. 3 is an equivalent circuit diagram of a plurality of pixel units of the liquid crystal device according to the first embodiment. FIG. 2 is a plan view of a plurality of pixel units of the liquid crystal device according to the first embodiment. FIG. FIG. 5 is a cross-sectional view taken along line A-A ′ of FIG. 4. FIG. 5 is a sectional view taken along line B-B ′ of FIG. 4. It is process drawing which shows each process of the manufacturing process of the liquid crystal device which concerns on 1st Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 1a '... Channel region, 1aa ... Semiconductor film, 3a ... Scan line, 3b, 3b1, 3b2 ... Gate electrode, 6a ... Data line, 9a ... Pixel electrode, 10 ... TFT array substrate, 10a ... Image display 11a ... lower light shielding film, 12 ... base insulating film, 20 ... counter substrate, 21 ... counter electrode, 23 ... light shielding film, 30 ... TFT, 50 ... liquid crystal layer, 52 ... sealing material, 53 ... frame light shielding film, 70 ... Storage capacitor, 71 ... Lower capacitance electrode, 75 ... Dielectric film, 101 ... Data line drive circuit, 102 ... External circuit connection terminal, 104 ... Scanning line drive circuit, 300a ... Upper capacitance electrode, 810 ... Recess

Claims (3)

An electro-optical device manufacturing method for manufacturing an electro-optical device including a pixel electrode and a transistor electrically connected to the pixel electrode on a substrate,
Forming a base insulating film on the substrate;
Forming a semiconductor film on the base insulating film;
By etching the semiconductor film and patterning the semiconductor film, a semiconductor layer constituting the transistor is formed, and the etching process is also performed on the base insulating film to thereby form the base layer. Forming a recess on the upper surface of the insulating film;
Forming a gate electrode constituting the transistor so as to have a main body portion that overlaps a channel region in the semiconductor layer and an extending portion that extends from the main body portion to at least a part of the recess;
And a step of forming the pixel electrode so as to be electrically connected to the transistor.   The method of manufacturing an electro-optical device according to claim 1, wherein the step of forming the gate electrode includes forming the gate electrode so as to include a light-shielding conductive material.   3. A step of forming a lower light-shielding film on a lower layer side than the base insulating film so as to at least partially overlap the semiconductor layer and to contain a light-shielding material. A method for manufacturing the electro-optical device according to claim 1.

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