JP2002156652A - Electro-optical device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve pattern accuracy in a semiconductor film pattern that constitutes pixel switching TFTs(Thin Film Transistors) and light resistance while making the laminate body surface on a substrate flat by digging grooves on the substrate for an electro-optical device such as a liquid crystal display or the like. SOLUTION: The electro-optical device is provided with, on a TFT array substrate (10), pixel electrodes (9a), TFTs (30) that are connected to the electrodes and wiring such as scanning lines (3a) that are connected to the TFTs. A semiconductor film pattern including the channel regions of the TFTs is arranged in the grooves that are dug on the substrate and dummy patterns (201) are formed from the same film of the TFTs beside the semiconductor film pattern in the grooves.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of an electro-optical device of an active matrix drive system, and particularly to a thin film transistor for pixel switching (Thin Film Tran).
(hereinafter, appropriately referred to as TFT) in a laminated structure on a substrate, and belongs to the technical field of an electro-optical device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In an electro-optical device of a TFT active matrix drive type, when incident light is applied to a channel region of a pixel switching TFT provided in each pixel, light leakage current is generated by excitation by light, and characteristics of the TFT are increased. Changes. In particular, in the case of an electro-optical device for a light valve of a projector, since the intensity of incident light is high, it is important to shield the TFT channel region and its peripheral region from incident light. Therefore, conventionally, a light shielding film that defines an opening area of each pixel provided on the opposite substrate or a TF
After passing over the TFT on the T array substrate, A
The channel region and its peripheral region are shielded from light by a data line made of a metal film such as l (aluminum). Further, a light-shielding film made of, for example, a refractory metal may be provided at a position on the TFT array substrate facing the lower side of the TFT. If a light-shielding film is provided below the TFT as described above, the reflected light from the back side of the TFT array substrate or a combination of a plurality of electro-optical devices via a prism or the like constitutes another optical system. Return light, such as projection light, which passes through a prism or the like from the electro-optical device described above, can be prevented from entering the TFT of the electro-optical device.

On the other hand, in this type of electro-optical device,
The flattening of the surface facing the electro-optical material such as a liquid crystal is an important factor for the electro-optical material to operate well. Therefore, conventionally, a technique has been developed in which a groove is formed in a substrate and a TFT and its wiring are buried in the groove to planarize the surface of a laminate finally formed on the substrate.

In this type of manufacturing method of an electro-optical device, a photolithography process and an etching process are used to form various conductive films and semiconductor films having a predetermined pattern on a substrate, thereby forming a pixel switching TFT.
In addition, techniques for forming scanning lines, data lines, and the like are generally employed.

[0005]

However, when both the technique of flattening a substrate by digging a groove as described above and the manufacturing technique using photolithography processing are adopted,
When a resist having a predetermined pattern is formed using a mask having a predetermined pattern during the photolithography process, halation due to a step or a slope of a groove occurs, and light for exposure wraps around to the side of the resist. Although the pattern becomes thin, there is a problem. Moreover, the degree of such halation changes three-dimensionally in accordance with the positional relationship between the step of the groove or the slope and the resist pattern to be formed. Therefore, the semiconductor film pattern and the conductive film pattern formed by the etching process through the resist pattern thus obtained are not only thin, but also thin.
Generally, irregularities are irregularly formed in three dimensions, and the unevenness of the narrowing is large. For this reason, it is not possible to cope with a simple technique of leaving the resist thicker on the assumption that the resist is thinned by halation.

Further, according to the above-described technique of flattening a groove by digging a groove in a substrate, particularly in a case where a strong incident light or a return light is incident such as a projector use, such a light is generated. The possibility of reaching the channel region of the TFT as internal reflected light or multiple reflected light is increased by reflection at the step or the slope of the groove. That is, when a groove is dug in the substrate in this way, even if the above-described various light-shielding films are used to cover the upper and lower sides of the TFT, it is necessary to prevent the internal reflection light or the multiple reflection light caused by the groove. This is not sufficient, and a light leak current occurs. In addition, as the electro-optical device has been improved in definition or the pixel pitch has been reduced to meet the general demand for higher quality of display images in recent years, the light intensity of incident light has been increased to display a brighter image. As a result, it becomes more difficult to provide sufficient light shielding, and eventually, a change in the transistor characteristics of the TFT causes flicker, crosstalk, display unevenness, and the like, resulting in a problem of deteriorating the quality of a displayed image. is there.

The present invention has been made in view of the above-mentioned problems, and has a structure in which a surface of a laminated body on a substrate is flattened by digging a groove in the substrate, and also constitutes a pixel switching TFT. An object of the present invention is to provide an electro-optical device having high pattern accuracy in a semiconductor film pattern and excellent light resistance, and a method for manufacturing the same.

[0008]

In order to solve the above-mentioned problems, an electro-optical device according to the present invention comprises, on a substrate, a pixel electrode, a thin film transistor connected to the pixel electrode, and a wiring connected to the thin film transistor. A semiconductor film pattern including a channel region of the thin film transistor is arranged in a groove dug in the substrate, and a dummy pattern is formed in the groove beside the semiconductor film pattern.

According to the electro-optical device of the present invention, the pixel electrode is switched by the thin film transistor connected thereto, so that the driving by the active matrix driving method can be performed. Further, since the semiconductor film pattern including the channel region of the thin film transistor is arranged in the trench dug in the substrate, the step caused by the thin film transistor and its wiring on the surface of the stacked body built on the substrate in the electro-optical device is reduced. Can be reduced. Then, a dummy pattern is formed in the groove beside the semiconductor film pattern. Therefore, when the semiconductor film pattern is patterned by the photolithography process and the etching process, the exposure light reflected on the step or the slope of the groove can be removed by the mask portion for forming the dummy pattern. That is, by reducing the halation effect caused by the step or the slope of the groove, the pattern accuracy of the resist for forming the semiconductor film pattern is improved, and the pattern accuracy of the semiconductor film pattern obtained by the subsequent etching is also improved. Therefore, it is possible to reduce the pixel pitch by reducing the size of the semiconductor film pattern including the channel region and reducing the variation of the semiconductor film pattern. In addition, in particular, since the dummy pattern is formed beside the semiconductor film pattern in the groove, at the time of operation after manufacturing, the internal reflection light or the multiple reflection light due to the step or the slope of the groove tends to reach the channel region. Can be effectively prevented by the dummy pattern at least partially by absorption or reflection.

In the present application, "the semiconductor film pattern is arranged in the groove dug in the substrate" means that the semiconductor film pattern may be directly arranged in the groove dug in the substrate.
This means that the semiconductor film pattern may be arranged in the trench dug in the substrate via one or more other films such as an interlayer insulating film. In short, there is a broad meaning that a groove is formed on the surface of the substrate as the base surface of the semiconductor film pattern or the surface of the interlayer insulating film or the like laminated thereon, and the semiconductor film pattern is arranged in the groove. Furthermore, in the present application, "a dummy pattern is formed beside a semiconductor film pattern in a groove" means that at least one of the dummy patterns is formed beside one or both of the semiconductor film patterns in a groove including a bottom portion and a side wall. It means that a part is formed.

As a result, according to the electro-optical device of the present invention, a situation in which the pattern accuracy of the semiconductor film pattern is reduced due to halation during the manufacturing process while adopting a structure in which a groove is formed in the substrate to flatten the groove. It is possible to effectively block and improve the light resistance after production. Therefore, the electro-optical material can be favorably operated by the flattening, and the pixel pitch can be reduced by a thin film transistor having a semiconductor film pattern having excellent pattern accuracy, and strong incident light and return light can be incident. Even under severe conditions such as those described above, the switching of the pixel electrode can be favorably controlled by the thin film transistor with reduced light leakage current, and finally, the present invention enables display of a bright, high-contrast, high-definition image. .

In one aspect of the electro-optical device according to the present invention, the dummy pattern is disposed on both sides of the semiconductor film pattern in the groove.

According to this aspect, since the dummy pattern is disposed on both sides of the semiconductor film pattern in the groove, when the semiconductor film pattern is patterned by photolithography and etching, the step of the groove is formed. Alternatively, the exposure light reflected on the slope can be removed by the dummy pattern forming mask portions arranged on both sides of the semiconductor film pattern, and the halation effect can be further reduced. Moreover, in particular, since dummy patterns are formed on both sides of the semiconductor film pattern, it is possible to prevent the internal reflected light or multiple reflected light from reaching the channel region due to the step or the slope of the groove during operation after manufacturing. In addition, the dummy pattern can more effectively prevent the dummy pattern.

In another aspect of the electro-optical device according to the present invention, the dummy pattern is disposed on a side wall of the groove.

According to this aspect, since the dummy pattern is arranged on the side wall of the groove, when the semiconductor film pattern is patterned by the photolithography process and the etching process, the exposure reflected on the step or the slope of the groove. Light can be removed by the dummy pattern forming mask portion disposed on the side wall of the groove, and the halation effect can be further reduced. Moreover, in particular, since the dummy pattern is formed on the side wall of the groove, during the operation after manufacturing, the internal reflection light or the multiple reflection light due to the step or the slope of the groove tries to reach the channel region. Dummy patterns can be more effectively prevented.

In another aspect of the electro-optical device according to the present invention, the dummy pattern is disposed on a bottom of the groove.

According to this aspect, since the dummy pattern is disposed on the bottom of the groove, when the semiconductor film pattern is patterned by photolithography and etching, the light is reflected by the step or the slope of the groove. Light can be removed by a dummy pattern forming mask portion disposed on the side wall of the groove. Moreover, in particular, since the dummy pattern is formed on the bottom of the groove, during the operation after manufacturing, the internal reflection light or the multiple reflection light due to the step or the slope of the groove tries to reach the channel region. It can be effectively prevented by the dummy pattern.

In another aspect of the electro-optical device according to the present invention, the dummy pattern is formed of the same film as the semiconductor film pattern.

According to this aspect, since the dummy pattern is formed of the same film as the semiconductor film pattern, no additional step is required to form the dummy pattern. In particular,
Light absorption characteristics (wavelength characteristics, etc.) in the channel region
Since it is the same as that of the dummy pattern, during operation after manufacturing, the frequency component that is easily absorbed in the channel region among the internally reflected light and the multiple reflected light caused by the step or the slope of the groove can be absorbed by the dummy pattern, It is very advantageous.

In another aspect of the electro-optical device according to the present invention, the dummy pattern is formed of a silicon film.

According to this aspect, light can be reduced beside the semiconductor film pattern by the dummy pattern made of a silicon film such as a polysilicon film or an amorphous silicon film.

In another aspect of the electro-optical device of the present invention, the dummy pattern has at least partially lower conductivity than the semiconductor film pattern.

According to this aspect, since the dummy pattern has low conductivity, the dummy pattern and a wiring such as a scanning line or another conductive film are opposed to each other in the laminate on the substrate with a reduced interlayer distance. However, the parasitic capacitance between the two is of little or no problem, which is advantageous.

In this aspect, the wiring includes a scanning line connected to a gate electrode arranged to face the channel region, and the dummy pattern has a low conductivity at least at a portion facing the scanning line. May be configured.

According to this structure, the dummy pattern and the scanning line are opposed to each other via the interlayer insulating film and the like.
Since the dummy pattern has low conductivity in the opposing portion, the parasitic capacitance between the scanning line and the dummy pattern causes little or no problem.

Alternatively, in another aspect of the electro-optical device of the present invention, the wiring includes a scanning line connected to a gate electrode arranged to face the channel region, and the dummy pattern faces the scanning line. They are arranged avoiding the plane area.

According to this aspect, since the dummy pattern is arranged so as to avoid the plane area facing the scanning line,
Even if the dummy pattern is conductive, the parasitic capacitance between the scanning line and the dummy pattern does not matter at all.
Further, by forming the dummy pattern from a conductive film, it can be conveniently used as another electrode, part of another element, wiring, or the like.

In another aspect of the electro-optical device according to the present invention, the dummy pattern also functions as one of a pair of capacitance electrodes forming a storage capacitor with respect to the pixel electrode, and the dummy pattern has a dielectric function. It further includes another electrode opposed to the body film.

According to this aspect, since the storage capacitance is constructed in the pixel electrode, the potential holding characteristic in the pixel electrode is remarkably enhanced. In addition, since one electrode of such a storage capacitor and the dummy pattern are also used, it is very advantageous in simplifying the laminated structure and the manufacturing process.

In the aspect having the storage capacitor, the dummy pattern may extend from a drain region of the semiconductor film pattern, and the one electrode may be a pixel potential side capacitor electrode.

According to this structure, a structure in which the dummy pattern extended from the semiconductor film pattern also functions as the pixel potential side capacitance electrode can be obtained relatively easily.

In the embodiment having the storage capacitor, the other electrode may be formed of a light-shielding film containing a metal or an alloy.

With this configuration, the light-shielding performance can be further improved by using both the other electrode formed of the light-shielding film containing a metal or an alloy and the dummy pattern. As a light-shielding film containing a metal or an alloy, for example, at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum), and Pb (lead) is used. Metal, an alloy, a metal silicide, a polysilicide, a laminate of these, and the like.

In the aspect having the storage capacitor, the wiring includes a scanning line connected to a gate electrode arranged to face the channel region, and the other electrode is formed on an upper layer of the one electrode on the substrate. And may be located below the scanning line.

According to this structure, since the other electrode exists at the lamination position between one of the dummy patterns and the scanning line, the parasitic capacitance between the dummy pattern and the scanning line is reduced. It can be reduced depending on the presence of the electrode.

In this case, the other electrode may be configured as a fixed potential side capacitance electrode.

According to this structure, since the fixed-potential-side capacitance electrode exists at the lamination position between one electrode formed of the dummy pattern and the scanning line, a configuration in which the dummy pattern is electromagnetically shielded from the scanning line is obtained. As a result, the parasitic capacitance between the dummy pattern and the scanning line can be significantly reduced.

In the aspect having the storage capacitor, the dielectric film may be formed of the same film as a gate insulating film interposed between the gate electrode of the thin film transistor and the channel region.

According to this structure, the gate insulating film of the thin film transistor and the dielectric film of the storage capacitor can be formed simultaneously from the same film, which is advantageous in simplifying the laminated structure and the manufacturing process.

In order to solve the above-mentioned problems, a method for manufacturing an electro-optical device according to the present invention is a method for manufacturing an electro-optical device (including various aspects thereof) according to the present invention. A step of digging a groove in the substrate; and a step of simultaneously forming the semiconductor film pattern and the dummy pattern in the groove by photolithography and etching using the same resist.

According to the method of manufacturing an electro-optical device of the present invention, first, a groove is dug in a substrate. Then, since the semiconductor film pattern and the dummy pattern are formed in the groove by photolithography and etching simultaneously using the same resist, the manufacturing process is compared with forming the semiconductor film pattern and the dummy pattern separately. This is advantageous in simplifying. In addition, in particular, the light for exposure reflected on the step or the slope of the groove can be removed by the mask portion for forming the dummy pattern, and the halation effect can be reduced. Therefore, the pattern accuracy of a resist for forming a semiconductor film pattern is improved, and the pattern accuracy of a semiconductor film pattern obtained by a subsequent etching process is also improved.

In order to solve the above-mentioned problems, another electro-optical device according to the present invention includes, on a substrate, a pixel electrode, a thin film transistor connected to the pixel electrode, and a wiring connected to the thin film transistor. A semiconductor film pattern including a channel region of the thin film transistor is arranged in a trench dug in the substrate, and a light-absorbing film is formed in the trench beside the semiconductor film pattern.

According to another electro-optical device of the present invention, a light-absorbing film is formed in the groove beside the semiconductor film pattern. For this reason, at the time of operation after manufacturing, the internal reflection light or the multiple reflection light caused by the step or the slope of the groove is likely to reach the channel region by the light absorbing film at least partially absorbing or reflecting the light. Can be effectively blocked. As a result, it is possible to improve the light resistance after manufacturing while adopting a structure in which a groove is formed in the substrate to flatten it, and finally, it is possible to display a bright, high-contrast, high-definition image by the present invention. Becomes

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0045]

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the electro-optical device according to the invention is applied to a liquid crystal device.

(Configuration of Pixel Portion of Electro-Optical Device) First, the configuration of the pixel portion of the electro-optical device according to the embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming an image display area of the electro-optical device. FIG. 2 is a plan view of a plurality of adjacent pixel groups on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. FIG. 3 is a sectional view taken along line AA ′ of FIG. In FIG. 3, the scale of each layer and each member is different so that each layer and each member have a size that can be recognized in the drawing.

In FIG. 1, a plurality of pixels formed in a matrix forming an image display area of the electro-optical device according to the present embodiment have a pixel electrode 9a and a TFT 30 for controlling switching of the pixel electrode 9a. Are formed, and the data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. good. The scanning line 3 is connected to the gate of the TFT 30.
a is electrically connected to the scanning line 3a at predetermined timings in a pulsed manner with the scanning signals G1, G2,.
Are applied in this order in a line-sequential manner.
The pixel electrode 9a is electrically connected to the drain of the TFT 30, and by closing the switch of the TFT 30 as a switching element for a certain period, the data line 6 is turned off.
The image signals S1, S2,..., Sn supplied from a are written at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal as an example of the electro-optical material via the pixel electrode 9a are held for a certain period between the image signals S1, S2,. You. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode, the transmittance for the incident light decreases according to the voltage applied in each pixel unit. In the normally black mode, the light enters according to the voltage applied in each pixel unit. Light transmittance is increased, and light having a contrast corresponding to an image signal is emitted from the electro-optical device as a whole. Here, in order to prevent the held image signal from leaking, the pixel electrode 9a
A storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the capacitor and the counter electrode.

In FIG. 2, a plurality of transparent pixel electrodes 9 are arranged in a matrix on a TFT array substrate of the electro-optical device.
a (the outline is indicated by a dotted line portion 9a '), and the data line 6a and the scanning line 3a are provided along the vertical and horizontal boundaries of the pixel electrode 9a, respectively.

Further, the scanning line 3a is arranged so as to face the channel region 1a 'indicated by the hatched region in the semiconductor layer 1a, which rises to the right in the figure, and the scanning line 3a functions as a gate electrode (particularly, In the present embodiment, the scanning line 3a
Is formed wide in a portion to be the gate electrode). In this manner, at the intersections of the scanning lines 3a and the data lines 6a, the scanning lines 3a and
A pixel switching TFT 30 is provided in which a is opposed to each other as a gate electrode.

As shown in FIGS. 2 and 3, in the present embodiment, the capacitance line 300 is composed of a first film 72 made of a conductive polysilicon film or the like and a second film 72 made of a metal silicide film containing a high melting point metal or the like. It has a multilayer structure in which the film 73 is laminated. The second film 73 has a function as an upper light-shielding film that shields the TFT 30 from incident light on the upper side of the TFT 30 in addition to the function as the fixed-potential-side capacitance electrode of the capacitor line 300 or the storage capacitor 70. Further, the first film 72 is formed of the capacitance line 300.
Alternatively, in addition to the function as the fixed potential side capacitor electrode of the storage capacitor 70, the storage capacitor 70 also has a function as a light absorbing layer disposed between the TFT 30 and the second film 73 as the upper light shielding film. On the other hand, the relay layer 71a disposed opposite to the capacitor line 300 via the dielectric film 75 has a function as a pixel potential side capacitor electrode of the storage capacitor 70 and a second film 73 as an upper light shielding film. It has a function as a light absorbing layer disposed between the TFT 30 and a function as an intermediate conductive layer for relay connection between the pixel electrode 9a and the high-concentration drain region 1e of the TFT 30.

In this embodiment, in particular, FIGS.
As shown in FIG.
The groove 10 is formed in a lattice-shaped plane area substantially corresponding to the gap area of FIG.
cv (shown by a hatched area in the lower right direction in FIG. 2) is dug, and the dummy pattern 201 shown by a bold line in FIG. 2 on both sides of the semiconductor layer 1a from the side wall to the bottom of the trench 10cv. Are formed. The configuration and operational effects of the dummy pattern 201 will be described later in detail with reference to FIGS.

In this embodiment, the storage capacitor 70 is a TFT
A relay layer 71a as a pixel potential side capacitance electrode connected to the high-concentration drain region 1e (and the pixel electrode 9a)
And a part of the capacitance line 300 as the fixed potential side capacitance electrode is formed by being opposed to each other with the dielectric film 75 interposed therebetween.

When viewed in plan, the capacitance line 300 has a scanning line 3a.
The portion overlapping the TFT 30 protrudes vertically in FIG. The data lines 6a extending in the vertical direction in FIG. 2 and the capacitance lines 300 extending in the horizontal direction in FIG. 2 are formed so as to intersect with each other. The upper light-shielding film is formed in a lattice shape when viewed, and defines an opening region of each pixel.

On the other hand, T on the TFT array substrate 10
Below the FT 30, a lower light-shielding film 11a is provided in a lattice shape.

The second layer constituting one example of these upper light shielding films
The film 73 and the lower light-shielding film 11a are made of, for example, Ti, C
a simple metal, an alloy, a metal silicide, including at least one of refractory metals such as r, W, Ta, Mo, and Pb;
It is made of polysilicide, a material obtained by laminating them, and the like. Further, the capacitance line 300 including such a second film 73
Has a multilayer structure, and since the first film 72 is a conductive polysilicon film, it is not necessary to form the second film 73 from a conductive material. If the second film 73 is also formed of a conductive film, the capacitance line 300
Can be further reduced.

In FIG. 3, a dielectric film 7 disposed between a relay layer 71a as a capacitor electrode and a capacitor line 300 is provided.
5 is a relatively thin HT having a thickness of, for example, about 5 to 200 nm.
It is composed of a silicon oxide film such as an O film, an LTO film, or a silicon nitride film. From the viewpoint of increasing the storage capacitance 70, as long as the reliability of the film is sufficiently obtained,
The thinner the dielectric film 75, the better.

The first film 72 which not only functions as a light absorbing layer but also forms a part of the capacitance line 300 has a thickness of, for example, 15 μm.
It is made of a polysilicon film of about 0 nm. In addition, the second film 73 not only functioning as a light shielding layer but also forming another part of the capacitance line 300 is made of, for example, a tungsten silicide film having a thickness of about 150 nm. Thus, the dielectric film 75
The first film 72 arranged on the side in contact with the dielectric film 75 is made of a polysilicon film, and the relay layer 71a in contact with the dielectric film 75 is made of a polysilicon film, so that the deterioration of the dielectric film 75 can be prevented. Further, when such a capacitor line 300 is formed on the dielectric film 75, the capacitor line 300 is continuously formed without performing a photoresist process after the formation of the dielectric film 75.
Is formed, the quality of the dielectric film 75 can be improved.
The dielectric film 75 can be formed thin, and the storage capacitance 70 can be finally increased.

As shown in FIGS. 2 and 3, the data line 6a
Is connected to a relay layer 71b for relay connection via a contact hole 81. The relay layer 71b is further connected via a contact hole 82 to the high-concentration source region 1d in the semiconductor layer 1a made of, for example, a polysilicon film. Is electrically connected to The relay layer 71b is formed simultaneously from the same film as the relay layer 71a having various functions described above.

The capacitance line 300 extends from the image display area where the pixel electrode 9a is arranged to the periphery thereof, is electrically connected to a constant potential source, and has a fixed potential. As such a constant potential source, a scanning line driving circuit (described later) for supplying a scanning signal for driving the TFT 30 to the scanning line 3a.
Or a constant potential source such as a positive power supply or a negative power supply supplied to a data line driving circuit (described later) for controlling a sampling circuit for supplying an image signal to the data line 6a, or supplied to a counter electrode 21 of a counter substrate 20. Constant potential. Furthermore,
The potential fluctuation of the lower light-shielding film 11a
In order to avoid having an adverse effect on 0, like the capacitor line 300, it is preferable to extend from the image display area to the periphery thereof and connect to a constant potential source.

The pixel electrode 9a is electrically connected to the high-concentration drain region 1e of the semiconductor layer 1a via the contact holes 83 and 85 by relaying the relay layer 71a. That is, in the present embodiment, the relay layer 71a
Indicates that, in addition to the function of the storage capacitor 70 as a pixel potential side capacitor electrode and the function as a light absorption layer, the pixel electrode 9a
It performs the function of relay connection to T30. When the relay layers 71a and 71b are used as the relay layers in this way, even if the interlayer distance is as long as about 2000 nm, for example, it is possible to avoid the technical difficulty of connecting them with one contact hole while avoiding the technical difficulty of connecting them with one contact hole. The two or more contact holes can be connected favorably to each other, so that the pixel aperture ratio can be increased, and it is also useful for preventing penetration of etching when the contact holes are opened.

In FIGS. 2 and 3, the electro-optical device comprises:
The device includes a transparent TFT array substrate 10 and a transparent opposing substrate 20 disposed opposite to the TFT array substrate 10. The TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.

The scanning lines 3a, the data lines 6a, and the TFTs 3 are provided in the lattice-shaped grooves 10cv dug in the TFT array substrate 10.
Wirings such as 0 and elements are buried. As a result, on the surface of the stacked body on the TFT array substrate 10 (that is, the surface of the third interlayer insulating film 43 serving as the base of the pixel electrode 9a), a step between the region where the wiring, the element, and the like are present and the region where it is not present is provided. , And finally, image defects such as liquid crystal alignment defects due to the steps can be reduced.

As shown in FIG. 3, the TFT array substrate 10
Is provided with a pixel electrode 9a, and above it,
Alignment film 16 that has been subjected to a predetermined alignment treatment such as a rubbing treatment
Is provided. The pixel electrode 9a is made of, for example, ITO (In
It is composed of a transparent conductive film such as a dium tin oxide film. The alignment film 16 is made of, for example, an organic film such as a polyimide film.

On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode 21. I have. The counter electrode 21 is made of, for example, a transparent conductive film such as an ITO film. The alignment film 22 is made of an organic film such as a polyimide film.

The opposing substrate 20 may be provided with a lattice-shaped or stripe-shaped light-shielding film. By adopting such a configuration, as described above, the light shielding film on the opposite substrate 20 together with the capacitance line 300 and the data line 6a constituting the upper light shielding film allows the incident light from the opposite substrate 20 side to be transmitted to the channel region 1a 'and the like. Intrusion into the low-concentration source region 1b and the low-concentration drain region 1c can be more reliably prevented. Furthermore,
Such a light-shielding film on the counter substrate 20 is formed by forming at least the surface irradiated with incident light with a highly reflective film.
It functions to prevent the temperature of the electro-optical device from rising. Note that the light-shielding film on the counter substrate 20 is preferably formed so as to be located inside the light-shielding layer including the capacitor lines 300 and the data lines 6a in plan view. Thereby, the opposing substrate 20
By the upper light shielding film, without lowering the aperture ratio of each pixel,
Such effects of light shielding and temperature rise prevention can be obtained.

The space between the TFT array substrate 10 and the opposing substrate 20 having the pixel electrode 9a and the opposing electrode 21 arranged in such a manner as to face each other is provided in a space surrounded by a sealing material described later. Liquid crystal, which is an example of an electro-optical material, is sealed, and a liquid crystal layer 50 is formed. The liquid crystal layer 50 holds the alignment film 1 in a state where no electric field is applied from the pixel electrode 9a.
A predetermined orientation state is taken by 6 and 22. Liquid crystal layer 50
Is composed of, for example, a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is used for bonding the TFT array substrate 10 and the opposing substrate 20 around them.
For example, it is an adhesive made of a photo-curing resin or a thermosetting resin, and a gap material such as glass fiber or glass beads for mixing the two substrates at a predetermined distance is mixed.

Further, under the pixel switching TFT 30, a base insulating film 12 is provided. Base insulating film 1
2 has a function of interlayer insulating the TFT 30 from the lower light-shielding film 11a, and is formed on the entire surface of the TFT array substrate 10 so that the surface of the TFT array substrate 10 can be roughened during polishing or stains remaining after cleaning. T for pixel switching
It has a function of preventing deterioration of the characteristics of the FT 30.

In FIG. 3, the pixel switching TFT
Reference numeral 30 denotes an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a and a channel region 1 of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a.
a ', an insulating film 2 including a gate insulating film for insulating the scanning line 3a from the semiconductor layer 1a, a low-concentration source region 1b and a low-concentration drain region 1c of the semiconductor layer 1a, a high-concentration source region 1d of the semiconductor layer 1a, and a high-concentration source region. It has a concentration drain region 1e.

On the scanning line 3a, a high concentration source region 1d
A first interlayer insulating film 41 is formed in which a contact hole 82 leading to the contact hole 83 and a contact hole 83 leading to the high concentration drain region 1e are opened.

The relay layers 71a and 71b and the capacitor line 300 are formed on the first interlayer insulating film 41, and a contact hole 81 and a contact hole 85 respectively leading to the relay layers 71a and 71b are formed thereon. An apertured second interlayer insulating film 42 is formed.

In this embodiment, the first interlayer insulating film 41
By sintering at 1000 ° C., the ions implanted into the polysilicon film forming the semiconductor layer 1a and the scanning line 3a may be activated. On the other hand, by not performing such sintering on the second interlayer insulating film 42, stress generated near the interface of the capacitance line 300 may be reduced.

The data lines 6a are formed on the second interlayer insulating film 42, and the third interlayer insulating film 4 on which a contact hole 85 leading to the relay layer 71a is formed.
3 are formed. The pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 43 configured as described above.

(Configuration and Operation and Effect of Dummy Pattern) Next, referring to FIGS. 4 to 8, in the above-described embodiment of the electro-optical device, the groove 10cv of the TFT array substrate 10 will be described.
The structure, operation and effect of the dummy pattern 201 provided therein will be described in detail. FIG. 4 is a plan view showing the dummy pattern 201 of FIG. 2 together with the semiconductor layer 1a and the scanning line 3a (indicated by a dotted line in FIG. 2).
6 is a cross-sectional view taken along the line CC ′ in FIG. 4, and FIG. 6 is a cross-sectional view taken along the line CC ′ in the comparative example. FIG. 7 shows the dummy pattern 2
01 is a process drawing showing a patterning step on a section corresponding to a CC ′ section, and FIG. 8 is a process drawing showing a patterning step in a comparative example on a section corresponding to a CC ′ section.

As shown in FIGS. 4 and 5, in the trench 10cv dug in the TFT array substrate 10, the underlying insulating film 12 is formed.
The semiconductor layer 1a including the channel region 1a 'of the TFT 30 is disposed through the semiconductor layer 1a, and the light-absorbing dummy patterns 201 are formed on both sides of the semiconductor layer 1a except for the scanning line 3a region. The dummy pattern 201 is formed from the edge of the groove 10cv of the base insulating film 12 to the bottom. Therefore, as shown in FIG. 5, during the operation of the electro-optical device, the light L1 (that is, a part of the incident light or the return light or the internal reflected light or the multiple reflected light resulting therefrom) is applied to the step or the slope of the groove.
Is reached, the light L1 is at least partially removed by absorption or reflection by the dummy pattern 201.
For this reason, the semiconductor layer 1 is formed by using the step or the slope of the groove as an optical path.
The light L2 reaching a is attenuated by the presence of the dummy pattern 201 as compared with the light L1.

Here, the comparative example shown in FIG. 6 is obtained by removing the dummy pattern 201 from the configuration of the present embodiment shown in FIG. As shown in FIG. 6, in the case of the comparative example, during the operation of the electro-optical device, even if the light L1 reaches the step or the slope of the groove, there is no absorption or reflection by the dummy pattern 201. Therefore, the light L2 reaching the semiconductor layer 1a is hardly attenuated as compared with the light L1 by using the step or the slope of the groove as an optical path. That is, in this comparative example, the groove 10
Due to the existence of cv, a light leakage current occurs in the TFT including the semiconductor layer 1a during operation.

As can be seen from FIGS. 5 and 6, according to the present embodiment, it is possible to improve the light resistance while adopting a structure in which the trench 10cv is dug and flattened in the TFT array substrate 10. Accordingly, the liquid crystal can be favorably operated by the flattening, and the pixel electrode 9a can be favorably formed by the TFT 30 in which the light leakage current is reduced even under severe conditions where strong incident light and return light enter. Switching control.

Here, in the present embodiment, as shown in FIGS. 2 and 3, the light shielding of the TFT 30 is performed from above and below by various light shielding films. That is, for the incident light incident from the upper side (that is, the incident light incident side) in the electro-optical device, the capacitance line 300 and the data line 6a function as an upper light shielding film. On the other hand, for return light that enters from the lower side (that is, the exit side of the incident light) in the electro-optical device,
The lower light-shielding film 11a literally functions as a lower light-shielding film. Therefore, it is considered that the light L1 shown in FIG. 5 does not actually exist. However, the incident light is
Includes oblique light that enters obliquely with respect to 0.
For example, about 10% of a component whose incident angle deviates from vertical by about 10 to 15 degrees is included. Similarly, the return light also includes oblique light. For this reason, the oblique light is reflected on the upper surface of the substrate 10, the upper surface of the lower light-shielding film 11a, or the like, or is reflected on the lower surface of the upper light-shielding film, and the like, and is reflected at another interface in the electro-optical device. The light is reflected to generate internally reflected light / multiple reflected light. Therefore, the light L1 shown in FIG.
Even if various light-shielding films are provided above and below 30, the light-shielding films may be present. Therefore, it can be said that the effect of the dummy pattern 201 that performs light-shielding beside the semiconductor layer 1 a as in this embodiment is large.

In addition, in the present embodiment, as shown in FIG. 4, the dummy pattern 201 is arranged so as to avoid a plane region facing the scanning line 3a. For this reason, even if the dummy pattern 201 is conductive or low conductive, the parasitic capacitance between the scanning line 3a and the dummy pattern 201 causes little or no practical problem.

Further, in this embodiment, since the dummy patterns 201 are formed on both sides of the semiconductor layer 1a as shown in FIGS. 4 and 5, the semiconductor layer 1a and the dummy pattern 201 are formed as shown in FIG. When patterning the semiconductor layer 1 by photolithography and etching, light for exposure reflected on a step or a slope of a groove can be removed by a mask portion for forming a dummy pattern.

That is, as shown in FIG. 7, when forming the semiconductor layer 1a and the dummy pattern 201 of this embodiment,
First, as shown in the upper part of FIG. 7, a semiconductor layer 1 is formed on the entire surface of a base insulating film 12, and a photoresist 6 is further formed thereon.
00 is formed. Then, the photoresist 600 is passed through a mask (reticle) 601 having a light shielding pattern 602 corresponding to the semiconductor layer 1a and the dummy pattern 201.
Is exposed with light Le for exposure. Next, as shown in the lower part of FIG. 7, the uncured portion of the photoresist 600 is removed to form a photoresist 600a having a pattern corresponding to the semiconductor layer 1a and the dummy pattern 201. Then, after baking this photoresist 600a, the semiconductor layer 1 is etched through this to form the semiconductor layer 1a and the dummy pattern 201 as shown in FIGS.

Accordingly, in the exposure step shown in the upper part of FIG. 7, the light Le for exposure is emitted from the step or the slope above the groove.
The light is removed by the light shielding pattern 602 for forming the dummy pattern. Therefore, the light Le for exposure is hardly reflected by the step or the slope of the groove. Therefore, as shown in the lower part of FIG.
In No. 0a, the halation effect due to the reflection of the light for exposure at the step or the slope of the groove does not appear, and it can be said that the patterning accuracy is extremely high. As a result, the pattern accuracy of the semiconductor layer 1a obtained by etching the photoresist 600a is very high.

Here, the comparative example shown in FIG. 8 is obtained by removing the dummy pattern 201 from the configuration of the present embodiment shown in FIG. In the exposure step shown in the upper part of FIG. 8, of the exposure light Le, the exposure light Le1 directed to the step or the slope of the groove is formed on the semiconductor layer 1a (there is no light shielding pattern portion for forming a dummy pattern). Light-shielding pattern 6
The light transmitted through the mask 601 'having the 02' is reflected by the step or the slope of the groove, and reaches the portion for forming the semiconductor layer 1a in the photoresist 600 as the reflected light Le2 from the side. That is, in the case of the comparative example, the halation effect due to the reflection of the exposure light Le1 on the step or the slope of the groove is remarkable. Therefore, as shown in the lower part of FIG. 8, the photoresist 600a ′ after patterning is formed.
Has low patterning accuracy. As a result, the pattern accuracy of the semiconductor layer obtained by etching the photoresist 600a 'also decreases.

As can be seen from FIGS. 7 and 8, according to the present embodiment, the pixel pitch can be reduced by miniaturizing the semiconductor layer 1a including the channel region 1a 'and reducing the variation in the shape of the semiconductor layer 1a. Can be miniaturized.

As described above with reference to FIGS. 4 to 8, according to the present embodiment, the structure in which the dummy pattern 201 is formed and the trench 10cv is dug in the TFT array substrate 10 to make it flat. While adopting, effectively preventing the pattern accuracy of the semiconductor film pattern 1a from deteriorating due to halation during the manufacturing process (see FIGS. 7 and 8), and improving the light resistance of the electro-optical device after manufacturing. (See FIGS. 5 and 6).

In this embodiment, in particular, the dummy pattern 20
1 is made of the same film as the semiconductor layer 1a such as a polysilicon film or an amorphous silicon film, so that an additional step is not required to form the dummy pattern 201. In addition, since the light absorption characteristics of the channel region 1a 'are the same as those of the dummy pattern 201, light of a frequency component that is easily absorbed by the channel region 1a' can be absorbed by the dummy pattern 201 during operation after manufacturing. This is very advantageous from the viewpoint of reducing the light leakage current generated in the channel region 1a '.

In the present embodiment described above, the dummy patterns 201 are arranged on both sides of the semiconductor layer 1a. However, even if the dummy patterns 201 are arranged only on one side of the semiconductor layer 1a, some similarity can be obtained. The effect is obtained. For example, in the case where it is difficult to arrange the dummy patterns 201 on both sides of the semiconductor layer 1a in view of the arrangement of the wirings and elements around the semiconductor layer 1a, the layout is not forced and added to one side. Need only be provided with the dummy pattern 201. In the present embodiment, the dummy pattern 201
Are arranged so as to extend over the top of the groove, on the side wall and the bottom of the groove. However, the dummy pattern 201
May be arranged so as to straddle only on the side wall and the bottom of the groove, or may be arranged only on the side wall of the groove or only on the bottom. In any case, the dummy pattern 201
Can be obtained as long as is disposed beside the semiconductor layer 1a in the groove.

In the embodiment described above, a large number of conductive layers are laminated as shown in FIG.
The occurrence of a step in a region along the data line 6a and the scanning line 3a on the lower ground (ie, the surface of the third interlayer insulating film 43) is alleviated by digging the groove 10cv in the TFT array substrate 10. However, in addition to this, trenches are dug in the base insulating film 12, the first interlayer insulating film 41, the second interlayer insulating film 42, and the third interlayer insulating film 43, and the wiring such as the data line 6a and the TFT 3 are formed.
A planarization process may be performed by embedding 0 or the like, or a step on the upper surface of the third interlayer insulating film 43 or the second interlayer insulating film 42 may be polished by a CMP (Chemical Mechanical Polishing) process or the like, or an organic layer may be formed. SOG (Spin On G
The flattening process may be performed by forming a flat surface using lass).

In the embodiment described above, the pixel switching TFT 30 preferably has the LDD structure as shown in FIG. 3, but does not implant impurities into the low-concentration source region 1b and the low-concentration drain region 1c. An impurity may be implanted at a high concentration using an offset structure, or using a gate electrode composed of a part of the scanning line 3a as a mask.
A self-aligned TFT that forms high-concentration source and drain regions in a self-aligned manner may be used. In the present embodiment, the gate switching TFT 30 has a single gate structure in which only one gate electrode is disposed between the high-concentration source region 1d and the high-concentration drain region 1e, but two or more gate electrodes are provided between them. It may be arranged. In this way, the TF is more than dual gate or triple gate.
When T is formed, a leak current at a junction between the channel and the source / drain region can be prevented, and a current at the time of off can be reduced.

(Various Types of Dummy Pattern) Next, FIG.
13 to FIG. 13, dummy pattern 2 shown in FIG.
Various modes that can be adopted as dummy patterns instead of 01 will be described. 9 to 13 respectively.
FIG. 5 is a plan view showing a dummy pattern extracted together with a semiconductor layer 1a and a scanning line 3a (indicated by a dotted line in the figure) as in FIG.

In the embodiment shown in FIG.
No. 2 is formed to have a large width corresponding to the narrow width of the semiconductor layer 1a. Other configurations are shown in FIG.
4 is the same as that of the embodiment shown in FIG. According to this structure, the light shielding function can be enhanced by an amount corresponding to the area where the dummy pattern 202 is formed.

In the embodiment shown in FIG. 10, the dummy pattern 2
Numeral 03 extends across the scanning line 3a. Other configurations are the same as those of the embodiment shown in FIGS. With this configuration, the dummy pattern 20
The light-shielding function can be enhanced as much as the formation area of the second is large.

However, in the embodiment shown in FIG. 10, preferably, the dummy pattern 203 has low conductivity at least in a portion facing the scanning line 3a. With this configuration, the parasitic capacitance between the dummy pattern 203 and the scanning line 3a causes little or no problem.

In the embodiment shown in FIG. 11, the dummy pattern 2
04 is formed to have a large width corresponding to the narrow width of the semiconductor layer 1a. Other configurations are the same as those of the embodiment shown in FIG. According to this structure, the light shielding function can be enhanced by an amount corresponding to the area where the dummy pattern 204 is formed.

In the embodiment shown in FIG.
Reference numeral 05 includes a dummy pattern 205a extending from the drain region of the semiconductor layer 1a and a dummy pattern 205b separated from the semiconductor layer 1a. The dummy pattern 205a preferably functions also as a pixel-potential-side capacitance electrode of a pair of capacitance electrodes forming a storage capacitance with respect to the pixel electrode (liquid crystal capacitance). With this configuration, the storage capacitor is used alone (ie, instead of the storage capacitor 70 shown in FIGS. 2 and 3) or additionally (ie, as shown in FIGS. 2 and 3) using the dummy pattern 205a. (In addition to the storage capacity 70 shown). In addition, since the fixed-potential-side capacitor electrode and the dummy pattern 205a are also used, the laminated structure and the manufacturing process can be simplified. Other configurations are the same as those of the embodiment shown in FIGS.

The dummy pattern 205 shown in FIG.
Will be described in detail later in (First Embodiment of Manufacturing Process) and (Second Embodiment of Manufacturing Process).

In the embodiment shown in FIG.
Reference numeral 06 extends from the drain region of the semiconductor layer 1a. The dummy pattern 206 preferably functions also as a fixed-potential-side capacitance electrode of a pair of capacitance electrodes that form a storage capacitance with respect to the pixel electrode (liquid crystal capacitance). With this configuration, the storage capacity is used independently (ie, instead of the storage capacity 70 shown in FIGS. 2 and 3) or additionally (ie, the storage capacity shown in FIGS. 2 and 3) using the dummy pattern 206. (In addition to the storage capacity 70 shown). In addition, since the capacitance electrode of the storage capacitor and the dummy pattern 206 are also used, the laminated structure and the manufacturing process can be simplified. In addition, the dummy pattern 206 has the scanning line 3
a, the light-shielding function can be enhanced and, at the same time, the plane area in which the storage capacitor is formed can be increased.
Other configurations are the same as those of the embodiment shown in FIGS.

The dummy pattern 206 shown in FIG.
Will be described in detail later (third embodiment of the manufacturing process).

(First Embodiment of Manufacturing Process) Next, a first embodiment of the manufacturing process of the electro-optical device according to the present invention will be described with reference to FIGS. Here, FIG. 14 is a process diagram sequentially showing, in a plan view, the vicinity of the semiconductor layer 1a of the electro-optical device in each step of the first embodiment of the manufacturing process, and FIG. FIG. 14 is a process diagram sequentially showing a state near the semiconductor layer 1a of the electro-optical device in each step of the embodiment in a cross-sectional view taken along the line DD ′ of FIG. 14, and FIG. 16 is a view illustrating each step of the first embodiment of the manufacturing process. FIG. 15 is a process diagram sequentially illustrating states near the semiconductor layer 1a of the electro-optical device in the EE ′ cross-sectional view of FIG. 14.

A dummy pattern formed in the first embodiment of the present manufacturing process is the same as that shown in FIG.
That is, here, the dummy pattern 205 is the semiconductor layer 1a.
Pattern 205a functioning also as a pixel potential side capacitor electrode extended from the drain region of FIG.
And a dummy pattern 205b separated from the dummy pattern 205b.

First, as shown in step (1) of FIGS. 14 to 16, T substrate such as quartz substrate, hard glass, silicon substrate, etc.
An FT array substrate 10 is prepared and subjected to photolithography and dry and wet etching, for example, at a depth of 8
Groove 10 having a lattice shape of about 70 nm and a planar shape
Dig cv. Here, the TFT is preferably annealed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and is used in a high-temperature process to be performed later
The pre-processing is performed so that distortion generated in the array substrate 10 is reduced.

Subsequently, a metal such as Ti, Cr, W, Ta, Mo and Pd or a metal alloy film such as a metal silicide is formed on the entire surface of the TFT array substrate 10 thus processed by sputtering to a thickness of 100 to 500 nm. A light-shielding film having a thickness of about 200 nm, preferably about 200 nm is formed. Then, the lower light-shielding film 11a having a lattice-like planar shape is formed by photolithography and etching.

Next, in step (2) of FIGS. 14 to 16,
On the lower light-shielding film 11a, for example, TEOS (tetra-ethyl-ortho-silicate) gas, TEB (tetra-ethyl-borate) gas, or TMOP (tetra-methyl-oxy-phos) by a normal pressure or reduced pressure CVD method or the like. NSG, PSG, BSG, BPS
A base insulating film 12 made of a silicate glass film such as G, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the base insulating film 12 is, for example, about 500 to 2000 nm.
Degree.

Subsequently, on the underlying insulating film 12, about 450 to
In a relatively low-temperature environment of 550 ° C., preferably about 500 ° C., an amorphous silicon film is formed by low-pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using a monosilane gas, a disilane gas, or the like at a flow rate of about 400 to 600 cc / min. Form. Then, in a nitrogen atmosphere, about 600
By performing an annealing treatment at a temperature of about 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, the polysilicon film 1 has a particle size of about 50 to 200 nm, preferably about 100 n.
Solid phase growth is performed until the particle size becomes m. As a method for solid phase growth, annealing treatment using RTA (Rapid Thermal Anneal) or laser annealing using an excimer laser or the like may be used. At this time, depending on whether the pixel switching TFT 30 is of an n-channel type or a p-channel type, a dopant of a group V element or a group III element may be slightly doped by ion implantation or the like. Then, by photolithography and etching, the semiconductor layer 1a having the predetermined pattern and the dummy pattern 205 having the predetermined pattern (that is, the dummy pattern 205a
And 205b).

In the present embodiment, in particular, since the halation effect is reduced when patterning the semiconductor layer 1a and the dummy pattern 205 as described above (see FIG. 7), the semiconductor layer 1a and the dummy pattern 205 Pattern accuracy can be improved.

Subsequently, the semiconductor layer 1 forming the TFT 30
a at a temperature of about 900-1300 ° C., preferably about 100
A lower gate insulating film is formed by thermal oxidation at a temperature of 0 ° C., and subsequently, an upper gate insulating film is formed by a low pressure CVD method or the like, or by performing both of them continuously. An insulating film 2 (including a gate insulating film) made of a film (HTO film) or a silicon nitride film is formed. As a result, each of the semiconductor layer 1a and the dummy pattern 205 has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating film 2 has a thickness of about 20 to 150 nm, preferably. About 30-100n
m.

Subsequently, in a state where the semiconductor layer 1a is covered with the photoresist 610, the dummy pattern 601 is doped with a dopant DP such as boron by a predetermined amount by ion implantation or the like. To give any conductivity. However, in this embodiment, since the dummy pattern 605 is not used as a capacitor electrode or the like, the dummy pattern 605 may not have conductivity. Conversely, as shown in FIGS. 10 and 11, when the dummy pattern is also formed in the plane region overlapping the scanning line 3a, a mask is provided at least for the portion overlapping the scanning line 3a, and the dopant DP is ion-implanted. By not doing so, it is preferable that the conductivity be low (that is, the parasitic capacitance between the scanning line 3a and the dummy pattern can be reduced).

Further, simultaneously with or separately from such ion implantation of the dopant DP, a pixel switching TF is used.
In order to control the threshold voltage Vth of T30, the N channel region or the P channel region in the semiconductor layer 1a is doped with a predetermined amount of a dopant such as boron by ion implantation or the like.

Next, in step (3) of FIGS. 14 to 16,
A polysilicon film is deposited by a low pressure CVD method or the like, and phosphorus (P) is thermally diffused to make the polysilicon film conductive. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The thickness of the polysilicon film is about 100 to 500 nm,
Preferably, it is about 350 nm. Then, a scanning line 3a having a predetermined pattern including the gate electrode of the TFT 30 is formed by photolithography and etching.

For example, when the TFT 30 is formed of n having an LDD structure,
In the case of a channel type TFT, a dopant of a group V element such as P is used with the scanning line 3a (gate electrode) as a mask in order to first form the low concentration source region 1b and the low concentration drain region 1c in the semiconductor layer 1a. At a low concentration (for example, P ions at a dose of 1 to 3 × 10 ¹³ / cm ² ). Thereby, the semiconductor layer 1 under the scanning line 3a
a becomes the channel region 1a '. Further, in order to form the high-concentration source region 1d and the high-concentration drain region 1e that constitute the pixel switching TFT 30, a resist layer having a plane pattern wider than the scanning line 3a is formed on the scanning line 3a. After that, a dopant of a group V element such as P is doped at a high concentration (for example, P ions are added at 1 to 3 × 10 ¹⁵ /
(dose at a dose of cm ² ). Note that, for example, a TFT having an offset structure may be used without doping at a low concentration, or a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like using the scanning line 3a as a mask. The resistance of the scanning line 3a is further reduced by the impurity doping.

Next, in step (4) in FIGS. 14 to 16,
A silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed on the scanning line 3a using, for example, a TEOS gas, a TEB gas, a TMOP gas, or the like by a normal pressure or reduced pressure CVD method. The first interlayer insulating film 41 made of is formed. The thickness of the first interlayer insulating film 12 is, for example, about 500 to 2000 nm. Here, preferably, annealing is performed at a high temperature of about 800 ° C. to improve the film quality of the interlayer insulating film 41.

Subsequently, the contact holes 82 (not shown) are formed by dry etching such as reactive ion etching and reactive ion beam etching on the interlayer insulating film 41.
And 83 (see FIGS. 2 and 3).

Subsequently, a polysilicon film is deposited by a low pressure CVD method or the like, and phosphorus (P) is thermally diffused to make the polysilicon film conductive. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The thickness of the polysilicon film is about 100 to
It has a thickness of 500 nm, preferably about 150 nm. Then, a pixel electrode relay layer 71a and a data line relay layer 71b (see FIGS. 2 and 3) (not shown) are formed by photolithography and etching.

Subsequently, the reduced pressure C is applied on the pixel electrode relay layer 71a also serving as the pixel potential side capacitor electrode and the first interlayer insulating film 41.
A dielectric film 75 made of a high-temperature silicon oxide film (HTO film) or a silicon nitride film is deposited to a relatively small thickness of about 50 nm by a VD method, a plasma CVD method, or the like. However,
As in the case of the insulating film 2, the dielectric film 75 may be formed of either a single-layer film or a multilayer film, and can be formed by various known techniques generally used for forming a gate insulating film of a TFT. It is. Since the storage capacitance 70 increases as the thickness of the dielectric film 75 decreases, the dielectric film becomes an extremely thin insulating film having a film thickness of 50 nm or less, provided that no defect such as film breakage occurs. It is advantageous to form 75.

Subsequently, a polysilicon film is deposited on the dielectric film 75 by a low pressure CVD method or the like, and furthermore, phosphorus (P) is thermally diffused, and the polysilicon film is made conductive to form a first film 72 (not shown). 2 and 3) are formed. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The thickness of the polysilicon film is about 100 to 500 nm, preferably about 150 nm.
nm. On top of this, Ti, Cr, W, T
A second film 73 having a thickness of about 100 to 500 nm is formed by sputtering a metal such as a, Mo, and Pd, or a metal alloy film such as a metal silicide. Then, a first pattern having a predetermined pattern is formed by photolithography and etching.
The capacitance line 300 including the film 72 and the second film 73 is completed.

Subsequently, for example, NSG, PSG, BSG, BSG
A second interlayer insulating film made of a silicate glass film such as PSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the first interlayer insulating film 42 is, for example, 500 to 15
It is about 00 nm.

Subsequently, a contact hole 81 (not shown) (see FIGS. 2 and 3) is formed by dry etching such as reactive ion etching or reactive ion beam etching on the second interlayer insulating film.

Subsequently, on the entire surface of the second interlayer insulating film 42,
By sputtering or the like, a low-resistance metal such as Al or a metal silicide having a light shielding property is used as a metal film to form a metal film of about 100 to 500.
Deposit to a thickness of nm, preferably about 300 nm. Then, a data line 6a having a predetermined pattern is formed by photolithography and etching.

Next, in step (5) of FIGS. 14 to 16,
For example, at normal pressure or reduced pressure C so as to cover the data line 6a.
NSG, PSG, B using VD method or TEOS gas
A third interlayer insulating film 43 made of a silicate glass film such as SG or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the third interlayer insulating film 43 is, for example, 500
〜1500 nm.

Then, a contact hole 85 (not shown) (see FIGS. 2 and 3) is formed by dry etching such as reactive ion etching or reactive ion beam etching on the third interlayer insulating film 43.

Subsequently, a transparent conductive film such as an ITO film is formed on the third interlayer insulating film 43 by sputtering or the like to a thickness of about 50 nm.
Deposit to a thickness of ~ 200 nm. Then, the pixel electrode 9a is formed by photolithography and etching. When the liquid crystal device is used for a reflection type liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

Subsequently, a coating liquid for a polyimide-based alignment film is applied onto the pixel electrode 9a, and then rubbed in a predetermined direction so as to have a predetermined pretilt angle, and the like. 3) is formed.

On the other hand, for the counter substrate 20 shown in FIG. 3, a glass substrate or the like is first prepared, and a light-shielding film as a frame is formed by, for example, sputtering metal chromium and then performing photolithography and etching. Note that these light-shielding films do not need to be conductive, and may be Cr, Ni, Al.
In addition to the above metal materials, the material may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist.

Thereafter, a transparent conductive film such as ITO is formed on the entire surface of the opposing substrate 20 by sputtering or the like to a thickness of about 50 to 20.
The counter electrode 21 is formed by depositing it to a thickness of 0 nm. Furthermore, after applying a coating liquid for a polyimide-based alignment film to the entire surface of the counter electrode 21, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction, so that the alignment film 22 (see FIG. 3) is formed. It is formed.

Finally, the T on which each layer is formed as described above
The FT array substrate 10 and the counter substrate 20 are bonded together with a sealing material (see FIGS. 22 and 23) so that the alignment films 16 and 22 face each other. The liquid crystal formed by mixing the above nematic liquid crystals is sucked to form a liquid crystal layer 50 having a predetermined thickness.

As described above, according to the first embodiment of the manufacturing process of the present invention, the above-described electro-optical device of the present invention can be manufactured. Then, the TFT array substrate 1
After the trench 10cv is dug in the trench 10cv, the semiconductor layer 1
Since a and the dummy pattern 205 are simultaneously formed from the same film by photolithography and etching (see step (2) in FIGS. 14 to 16), the semiconductor film pattern and the dummy pattern are compared with separately formed dummy patterns. Thus, the manufacturing process can be simplified. Moreover, as described with reference to FIGS. 7 and 8, in particular, these semiconductor layers 1a
When patterning the dummy pattern 205 and the dummy pattern 205 at the same time, the exposure light reflected on the step or the slope of the groove 10cv can be removed by the mask portion for forming the dummy pattern 205, and the halation effect can be reduced. Therefore, the pattern accuracy in the semiconductor layer 1a can be improved.

(Second Embodiment of Manufacturing Process) Next, a second embodiment of the manufacturing process of the electro-optical device according to the present invention will be described with reference to FIGS. 17 and 18 (and FIG. 16). FIG. 17 is a process diagram sequentially showing, in a plan view, the vicinity of the semiconductor layer 1a of the electro-optical device in each step of the second embodiment of the manufacturing process.
FIG. 17 shows a state in the vicinity of the semiconductor layer 1a of the electro-optical device in each step of the second embodiment of the manufacturing process by DD ′ in FIG.
It is a process drawing shown in order in a sectional view. And FIG.
FIG. 17 is a process diagram showing the state of the vicinity of the semiconductor layer 1a of the electro-optical device in each step of the second embodiment as well as the first embodiment of the manufacturing process described above in order along the EE ′ cross-sectional view of FIG. This is also the case (that is, the process diagram in the EE ′ section is the same as that of the first embodiment of the manufacturing process described with reference to FIGS. 14 to 16). FIG.
In FIG. 18 and FIG. 18, the same components as those in the first embodiment shown in FIGS. 14 to 16 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

A dummy pattern formed in the second embodiment of the present manufacturing process is the same as that shown in FIG.
That is, here, the dummy pattern 205 is the semiconductor layer 1a.
Pattern 205a functioning also as a pixel potential side capacitor electrode extended from the drain region of FIG.
And a dummy pattern 205b separated from the dummy pattern 205b.

First, in steps (1) to (2) of FIGS. 17 and 18 (and FIG. 16), steps (1) to (2) of the first embodiment of the manufacturing process shown in FIGS. The same steps as in ()) are performed. However, in the present embodiment, the dummy pattern 205a functions as a pixel potential side capacitor electrode. For this reason, in the step (2), the dummy pattern 205a is sufficiently doped so as to have appropriate conductivity as a pixel potential side capacitor electrode. Such doping may be performed simultaneously with the doping of the semiconductor layer 1a, or may be performed separately.

Next, in the step (3 ') of FIGS. 17 and 18 (and FIG. 16), when forming the scanning line 3a, the scanning is performed on the plane area facing the dummy pattern 205a as the pixel potential side capacitor electrode. The fixed potential side capacitance electrode 215 is formed from the same polysilicon film as the line 3a. Therefore, the insulating film 2
From the dummy pattern 205a and the fixed-potential-side capacitance electrode 215 opposed to each other, the storage capacitor 70 'is used alone (that is, instead of the storage capacitor 70 shown in FIGS. 2 and 3).
Or additionally (ie, the storage capacitor 7 shown in FIGS. 2 and 3).
(In addition to 0). Otherwise, steps similar to step (3) of the first embodiment of the manufacturing process shown in FIGS. 14 to 16 are performed.

Next, FIGS. 17 and 18 (and FIG. 16)
In steps (4) to (5), the same steps as steps (4) to (5) of the first embodiment of the manufacturing process shown in FIGS. 14 to 16 are performed. However, in the present embodiment, the contact for lowering the fixed potential side capacitor electrode 215 to a constant potential is formed simultaneously with or separately from the formation of other contacts.

As described above, according to the second embodiment of the manufacturing process of the present invention, in particular,
Reference numeral 5 also functions as a pixel-potential-side capacitance electrode, and an electro-optical device can be manufactured in which a storage capacitor 70 'is incorporated alone or additionally (see step (5) in FIG. 18). Then, as in the case of the first embodiment, the grooves 10 are formed in the TFT array substrate 10.
After digging cv, the semiconductor layer 1a and the dummy pattern 205 are simultaneously formed in the trench 10cv from the same film by a photolithography process and an etching process, so that the semiconductor film pattern and the dummy pattern are formed separately. Thus, the manufacturing process can be simplified. Moreover, the pattern accuracy in the semiconductor layer 1a can be increased by reducing the halation effect.

In addition, according to the second embodiment of the present manufacturing process, the dielectric film of the storage capacitor 70 ′ and the gate insulating film of the TFT can be formed simultaneously from the same insulating film 2. Forming one quality insulating film 2 is advantageous because the capacitance value and reliability of the storage capacitor 70 ′ and the performance and reliability of the TFT 30 can be simultaneously increased.

(Third Embodiment of Manufacturing Process) Next, a third embodiment of the manufacturing process of the electro-optical device according to the present invention will be described with reference to FIGS. Here, FIG. 19 is a process diagram sequentially showing, in a plan view, the vicinity of the semiconductor layer 1a of the electro-optical device in each step of the third embodiment of the manufacturing process, and FIG. FIG. 19 is a process diagram sequentially showing a state near the semiconductor layer 1a of the electro-optical device in each step of the embodiment in a DD ′ cross-sectional view of FIG. 19, and FIG. 21 is a view illustrating each step of the third embodiment of the manufacturing process. FIG. 20 is a process diagram sequentially illustrating the state near the semiconductor layer 1a of the electro-optical device in the EE ′ cross-sectional view of FIG. 19. In FIGS. 19 to 21, the same components as those of the first embodiment shown in FIGS. 14 to 16 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

The dummy pattern formed in the third embodiment of the present manufacturing process is the same as that shown in FIG.
That is, here, the dummy pattern 206 is the semiconductor layer 1a
And functions also as a pixel potential side capacitor electrode.

First, in step (1) of FIGS. 19 to 21,
Steps similar to step (1) of the first embodiment of the manufacturing process shown in FIGS. 14 to 16 are performed.

Next, in the step (2a) shown in FIGS. 19 to 21, when forming the semiconductor layer 1a, the dummy pattern 206 having the planar shape shown in FIG. 13 is formed simultaneously from the same film as the semiconductor layer 1a. . For others, see FIG.
To the step (2) of the first embodiment of the manufacturing process shown in FIG.

Next, in the step (2b) of FIGS. 19 to 21, Ti, Cr, W, Ta, Mo and P
A metal such as d or a metal alloy film such as a metal silicide is deposited by sputtering to a thickness of about 100 to 500 nm, and then, by photolithography and etching, in a region facing the dummy pattern 206 as a pixel potential side capacitor electrode. The fixed potential side capacitor electrode 216 is formed. Therefore, the dummy patterns 2 opposed to each other via the insulating film 2
06 and the fixed potential side capacitor electrode 216, the storage capacitor 7
0 "alone (that is, the storage capacitor 7 shown in FIGS. 2 and 3).
It can be constructed in place of (instead of 0) or additionally (ie, in addition to the storage capacitor 70 shown in FIGS. 2 and 3). Immediately before and after the formation of the fixed potential side capacitor electrode 216, a portion of the insulating film 2 facing the channel region of the semiconductor layer 1a is removed by etching, and an insulating film 220 is formed thereon. This insulating film may be formed by, for example, a low pressure CVD method or the like, and has a thickness of about 20 to 150 nm, preferably about 3 to 150 nm.
The thickness is set to 0 to 100 nm. Incidentally, as described above, the insulating film 2
If the portion of the semiconductor layer 1a facing the channel region is removed by etching, the gate insulating film of the TFT 30 can be thinned. However, if there is no problem with the film thickness, the gate insulating film is formed of the insulating film 2 and the insulating film 220. Alternatively, the gate insulating film may be formed from the insulating film 2 instead of the insulating film 220.

Next, steps (3) to (5) of FIGS. 19 to 21 are the same as steps (3) to (5) of the first embodiment of the manufacturing process shown in FIGS. Is performed. However, in the present embodiment, the contact formation for lowering the fixed potential side capacitor electrode 216 to a constant potential is performed simultaneously or separately with other contact formation.

As described above, according to the third embodiment of the manufacturing process of the present invention, in particular, the dummy pattern 20 is formed.
6 also functions as a pixel-potential-side capacitance electrode, and an electro-optical device can be manufactured in which a storage capacitor 70 ″ is incorporated alone or additionally (see step (5) in FIGS. 20 and 21). As in the case of the embodiment, the TFT array substrate 1
After the trench 10cv is dug in the trench 10cv, the semiconductor layer 1
Since a and the dummy pattern 206 are simultaneously formed from the same film by photolithography and etching, the manufacturing process can be simplified as compared with the case where the semiconductor film pattern and the dummy pattern are separately formed. Moreover, by reducing the halation effect, the semiconductor layer 1
The pattern accuracy in a can be increased.

According to the third embodiment of the present manufacturing process, in particular, the fixed potential side capacitor electrode 216 is connected to the TFT array substrate 1.
0, a dummy pattern 2 which is a pixel potential side capacitance electrode
21 is located on the upper layer side of the electrode and on the lower layer side of the scanning line 3a (from step (3) to step (5) in FIG. 21).
reference). Therefore, since the fixed potential side capacitance electrode 216 of the fixed potential exists between the dummy pattern 206 and the scanning line 3a, the parasitic capacitance between them can be reduced. That is, as shown in FIG. 13, even if the conductive dummy pattern 206 is formed so as to overlap the plane region where the scanning line 3a is formed, the parasitic capacitance between the two does not matter. It is possible to increase the planar area in which the storage capacitor 70 "is formed without inviting.

Further, according to the third embodiment of the present manufacturing process, since the fixed potential side capacitor electrode 216 is formed from a light shielding film containing a metal or an alloy, the light shielding performance can be further enhanced in cooperation with the dummy pattern 206. . However, it is also possible to form the fixed potential side capacitor electrode 216 from a conductive polysilicon film or the like.

In the third embodiment of the present manufacturing process,
Although the fixed potential side capacitance electrode 216 is provided below the scanning line 3a, it is also possible to provide a fixed potential side capacitance electrode above the scanning line 3a. For example, the step (3) shown in FIGS. 19 to 21 is performed before the step (2b), and before the fixed potential side capacitance electrode 216 is formed in the step (2b) in that case, the dummy pattern as the pixel potential side capacitance electrode is formed. 2
If the portion of the insulating film 2 or 220 on the substrate 06 is removed by etching, the dummy pattern 206 and the fixed-potential-side capacitance electrode 216 opposed to each other are disposed with the remaining insulating film as a dielectric film.
Thereby, a storage capacity can be constructed. However, in this case,
Although it is possible to dispose the fixed potential side capacitance electrode or the capacitance line over the scanning line 3a via the interlayer insulating film, the region where the storage capacitance can be formed is the region excluding the scanning line 3a (that is, the region itself). Slightly narrower).

In each of the embodiments described above, the grooves 10cv
Is a lattice shape, but may be a stripe shape along the data line 6a or a stripe shape along the scanning line 3a. In any case, by forming the dummy pattern, the effect of increasing the patterning accuracy of the semiconductor layer 1a and the effect of increasing the light shielding performance of the semiconductor layer 1a can be obtained.

(Overall Configuration of Electro-Optical Device) The overall configuration of the electro-optical device in each embodiment configured as described above will be described with reference to FIGS. 22 and 23. Incidentally, FIG.
FIG. 23 is a plan view of the TFT array substrate 10 together with the components formed thereon as viewed from the counter substrate 20, and FIG. 23 is a cross-sectional view taken along the line HH ′ of FIG.

In FIG. 22, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and in parallel with the inside of the sealing material 52, a light shielding as a frame defining the periphery of the image display area 10a is provided. A film 53 is provided. In a region outside the sealing material 52, a data line driving circuit 101 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10. A scanning line driving circuit 1 for driving a scanning line 3a by supplying a scanning signal to the scanning line 3a at a predetermined timing.
04 are provided along two sides adjacent to this one side. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. In addition, the data line driving circuit 10
1 may be arranged on both sides along the side of the image display area 10a. Further, on one remaining side of the TFT array substrate 10, the scanning line driving circuits 10 provided on both sides of the image display area 10a are provided.
A plurality of wirings 105 are provided to connect the four wirings. In at least one of the corners of the counter substrate 20, a conductive material 106 for electrically connecting the TFT array substrate 10 and the counter substrate 20 is provided. Then, as shown in FIG. 23, the opposing substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 22 is fixed to the TFT array substrate 10 by the sealing material 52.

It should be noted that, on the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, etc., a sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing, a plurality of Data line 6a
A precharge circuit for supplying a precharge signal of a predetermined voltage level prior to the image signal, an inspection circuit for inspecting the quality, defects, and the like of the electro-optical device during manufacturing or shipping. Good.

In the embodiment described above with reference to FIGS. 1 to 23, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, a TAB (Tape Automated bonding) substrate The driving LSI mounted thereon may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. For example, TN (Twisted) is provided on each of the side of the opposite substrate 20 where the projection light is incident and the side where the emission light of the TFT array substrate 10 is emitted.
Nematic) mode, VA (Vertically Aligned) mode, PDLC (Polymer Dispersed Liquid Crystal) mode and other operation modes, and normally white mode / normally black mode. They are arranged in a predetermined direction.

Since the electro-optical device in the above-described embodiment is applied to a projector, three electro-optical devices are used as light valves for RGB, and each light valve has a dichroic for RGB color separation. The light of each color decomposed via the mirror is respectively incident as projection light. Therefore, in each embodiment, the opposing substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the counter substrate 20 in a predetermined region facing the pixel electrode 9a together with the protective film. In this way, the electro-optical device in each embodiment can be applied to a direct-view or reflective color electro-optical device other than the projector. Further, a micro lens may be formed on the counter substrate 20 so as to correspond to one pixel. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrode 9a facing the RGB on the TFT array substrate 10. With this configuration, a bright electro-optical device can be realized by improving the efficiency of collecting incident light. Furthermore, the counter substrate 2
A dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the zero. According to the counter substrate with the dichroic filter, a brighter color electro-optical device can be realized.

The present invention is not limited to the above-described embodiments, but can be appropriately modified without departing from the spirit and spirit of the invention which can be read from the claims and the entire specification. The electro-optical device and the manufacturing method thereof are also included in the technical scope of the present invention.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wiring, and the like provided in a plurality of pixels in a matrix forming an image display area in an electro-optical device according to an embodiment of the present invention.

FIG. 2 is a plan view of a plurality of adjacent pixel groups on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device according to the embodiment.

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is a plan view showing a dummy pattern extracted from FIG. 2 together with a semiconductor layer and a scanning line.

FIG. 5 is a sectional view taken along line C-C 'of FIG.

FIG. 6 is a sectional view taken along line C-C ′ of FIG. 4 in a comparative example.

FIG. 7 is a process diagram showing a patterning step of a dummy pattern according to the embodiment on a cross section corresponding to a CC ′ cross section;

FIG. 8 is a process diagram showing a patterning step in a comparative example on a cross section corresponding to a CC ′ cross section;

FIG. 9 is a plan view showing another dummy pattern that can be adopted in the present embodiment together with the semiconductor layers and the scanning lines, similarly to FIG. 4;

FIG. 10 is a plan view showing another dummy pattern that can be adopted in the present embodiment together with the semiconductor layers and the scanning lines, similarly to FIG. 4;

FIG. 11 is a plan view showing another dummy pattern that can be adopted in the present embodiment together with the semiconductor layers and the scanning lines, similarly to FIG. 4;

FIG. 12 is a plan view showing another dummy pattern that can be adopted in the present embodiment together with the semiconductor layers and the scanning lines, similarly to FIG. 4;

13 is a plan view showing another dummy pattern that can be adopted in the present embodiment, together with the semiconductor layers and the scanning lines, similarly to FIG.

FIG. 14 is a process diagram sequentially showing, in a plan view, a state near a semiconductor layer of the electro-optical device in each step of the first embodiment of the manufacturing process according to the present invention.

FIG. 15 is a process diagram sequentially showing the state near the semiconductor layer of the electro-optical device in each step of the first embodiment of the manufacturing process according to the present invention in a DD ′ cross-sectional view of FIG. 14;

FIG. 16 is a process diagram sequentially showing the state near the semiconductor layer of the electro-optical device in each step of the first embodiment of the manufacturing process according to the present invention in the EE ′ cross-sectional view of FIG. 14;

FIG. 17 is a process diagram sequentially showing, in a plan view, the state near the semiconductor layer of the electro-optical device in each step of the second embodiment of the manufacturing process according to the present invention.

FIG. 18 is a process diagram sequentially showing the state near the semiconductor layer of the electro-optical device in each step of the second embodiment of the manufacturing process according to the present invention in the DD ′ cross-sectional view of FIG. 17;

FIG. 19 is a process diagram sequentially showing, in a plan view, the state near the semiconductor layer of the electro-optical device in each step of the third embodiment of the manufacturing process according to the present invention.

FIG. 20 is a process diagram sequentially showing the state near the semiconductor layer of the electro-optical device in each step of the third embodiment of the manufacturing process according to the present invention in the DD ′ cross-sectional view of FIG. 19;

FIG. 21 is a process chart sequentially showing the state near the semiconductor layer of the electro-optical device in each step of the third embodiment of the manufacturing process according to the present invention in the EE ′ cross-sectional view of FIG. 19;

FIG. 22 is a plan view of the TFT array substrate in the electro-optical device according to the embodiment together with the components formed thereon as viewed from the counter substrate side.

FIG. 23 is a sectional view taken along line H-H ′ of FIG. 22;

[Explanation of symbols]

 1a Semiconductor layer 1a 'Channel region 1b Low-concentration source region 1c Low-concentration drain region 1d High-concentration source region 1e High-concentration drain region 2 Insulating film 3a Scanning line 6a Data line 9a Pixel electrode 10 ... TFT array substrate 10cv Groove 11a Lower light-shielding film 12 Base insulating film 16 Alignment film 20 Counter substrate 21 Counter electrode 22 Alignment film 30 TFT 50 Liquid crystal layer 70 Storage capacitor 71a Relay layer 71b ... Relay layer 72. First film of capacitance line 73... Second film of capacitance line 75. Dielectric film 81, 82, 83, 85. Contact holes 201 to 206... Dummy patterns 215 and 216. ... insulating film 300 ... capacitance line 600 ... photoresist 601 ... mask (reticle) 602 ... light shielding pattern

Continuation of the front page F term (reference) 2H090 JA02 JB02 JC03 JD14 LA04 LA05 2H092 JA26 JB51 KB13 KB21 KB25 MA07 MA27 NA01 NA19 NA24 PA01 PA09 RA05 5C094 AA03 AA31 BA03 BA43 CA19 CA24 DA14 DA15 EA01 EA04 EA07 AFB EB07 BB01 CC02 DD02 DD03 DD05 DD12 DD13 DD14 DD21 DD25 EE09 EE28 EE45 FF02 FF03 FF09 FF23 FF32 GG02 GG13 GG32 GG47 GG52 GG60 HJ01 HJ04 HJ13 HL08 HL24 HM14 HM15 NN03 NN04 NN40 NN22 NN23 QQ09 QQ11 QQ19

Claims (17)

[Claims] 1. A substrate, comprising: a pixel electrode; a thin film transistor connected to the pixel electrode; and a wiring connected to the thin film transistor; and a channel region of the thin film transistor in a groove dug in the substrate. An electro-optical device, comprising: a semiconductor film pattern including: a dummy pattern is formed in the groove beside the semiconductor film pattern. 2. The electro-optical device according to claim 1, wherein the dummy pattern is disposed on both sides of the semiconductor film pattern in the groove. 3. The electro-optical device according to claim 1, wherein the dummy pattern is disposed on a side wall of the groove. 4. The electro-optical device according to claim 1, wherein the dummy pattern is disposed on a bottom of the groove. 5. The electro-optical device according to claim 1, wherein the dummy pattern is formed of the same film as the semiconductor film pattern. 6. The electro-optical device according to claim 1, wherein the dummy pattern is made of a silicon film. 7. The electro-optical device according to claim 1, wherein the dummy pattern has at least partially lower conductivity than the semiconductor film pattern. 8. The wiring includes a scanning line connected to a gate electrode disposed to face the channel region, and the dummy pattern has a low conductivity at least at a portion facing the scanning line. The electro-optical device according to claim 7, wherein 9. The semiconductor device according to claim 9, wherein the wiring includes a scanning line connected to a gate electrode arranged to face the channel region, and the dummy pattern is arranged so as to avoid a plane region facing the scanning line. The electro-optical device according to any one of claims 1 to 7, wherein: 10. The dummy pattern also functions as one electrode of a pair of capacitance electrodes forming a storage capacitor with respect to the pixel electrode, and the other is disposed to face the dummy pattern via a dielectric film. The electro-optical device according to any one of claims 1 to 9, further comprising: 11. The electro-optical device according to claim 10, wherein the dummy pattern extends from a drain region of the semiconductor film pattern, and the one electrode is a pixel potential side capacitance electrode. . 12. The device according to claim 10, wherein the other electrode is made of a light-shielding film containing a metal or an alloy.
An electro-optical device according to claim 1. 13. The wiring includes a scanning line connected to a gate electrode disposed to face the channel region, and the other electrode is located on an upper layer side of the one electrode on the substrate, and The electro-optical device according to any one of claims 10 to 12, wherein the electro-optical device is located below a scanning line. 14. The electro-optical device according to claim 13, wherein the other electrode is a fixed potential side capacitance electrode. 15. The semiconductor device according to claim 1, wherein the dielectric film is formed of the same film as a gate insulating film interposed between a gate electrode of the thin film transistor and the channel region.
15. The electro-optical device according to any one of 0 to 14. 16. A method for manufacturing an electro-optical device for manufacturing the electro-optical device according to claim 1, wherein a step of digging a groove in the substrate, and the step of forming the semiconductor film in the groove are performed. Forming a pattern and the dummy pattern simultaneously by photolithography and etching using the same resist. 17. A substrate, comprising: a pixel electrode; a thin film transistor connected to the pixel electrode; and a wiring connected to the thin film transistor; and a channel region of the thin film transistor in a groove dug in the substrate. An electro-optical device, comprising: a semiconductor film pattern including: a light-absorbing film formed in the trench beside the semiconductor film pattern.