JP3969439B2 - Electro-optic device - Google Patents

Description

  The present invention belongs to the technical field of an active matrix drive type electro-optical device, and in particular, a storage capacitor for holding a potential written in a pixel electrode, a thin film transistor for pixel switching (hereinafter referred to as a TFT as appropriate). Belongs to the technical field of an electro-optical device of a type provided in a laminated structure on a substrate and a manufacturing method thereof.

  In an electro-optical device of the TFT active matrix driving type, when incident light is irradiated to a channel region of a pixel switching TFT provided in each pixel, a current is generated by excitation by light, and the characteristics of the TFT change. In particular, in the case of an electro-optical device for a projector light valve, since the intensity of incident light is high, it is important to shield incident light from the TFT channel region and its peripheral region. Therefore, conventionally, the channel region and its peripheral region are shielded by a light shielding film that defines the opening region of each pixel provided on the counter substrate, or by a data line that passes over the TFT and is made of a metal film such as Al. Is configured to do. Japanese Patent Laid-Open No. 9-33944 discloses a technique for reducing light incident on a channel region with a light shielding film formed of a-Si (amorphous silicon) having a large refractive index. Furthermore, a light shielding film made of, for example, a refractory metal may be provided at a position facing the pixel switching TFT on the TFT array substrate (that is, below the TFT). If a light-shielding film is also provided on the lower side of the TFT in this way, the back surface reflection from the TFT array substrate side, or when combining a plurality of electro-optical devices via a prism or the like, Projection light penetrating through the prism or the like from the electro-optical device can be prevented from entering the TFT of the electro-optical device.

  On the other hand, generally in this type of electro-optical device, when a scanning signal is supplied to the gate electrode of the TFT via the scanning line, the TFT is turned on and supplied to the source region of the semiconductor layer via the data line. An image signal is supplied to the pixel electrode through the source and drain of the TFT. Since such an image signal is supplied only for a very short time for each pixel electrode through each TFT, the voltage of the image signal supplied through the TFT is set to be much longer than the time in which it is turned on. In general, a storage capacitor is added to each pixel electrode (in parallel with a liquid crystal capacitor or the like) so that the pixel electrode can be held for a long time. Such a storage capacitor generally has a capacitor electrode extending from a conductive polysilicon film or the like constituting a drain region of a TFT connected to the pixel electrode and having a pixel electrode potential, and a dielectric material on the capacitor electrode. A capacitor line including an electrode portion arranged opposite to each other through a film and having a fixed potential is configured.

  However, the various light shielding techniques described above have the following problems. That is, according to the technique of forming a light shielding film on the counter substrate or the TFT array substrate, the space between the light shielding film and the channel region is, for example, through a liquid crystal layer, an electrode, an interlayer insulating film, etc. in three dimensions. The light is obliquely separated from each other, and the light is not sufficiently shielded. In addition, after the light that has entered the electro-optical device from the region without the light shielding film is reflected by the inner surface of the light shielding film or the data line (that is, the surface facing the channel region), the reflected light or In some cases, the multiple reflected light reflected from the inner surface of the light shielding film or the data line finally reaches the channel region of the TFT. In addition, according to the technology for shielding light by the data line, the data line is formed in a stripe shape extending in a direction perpendicular to the scanning line when seen in a plan view, and the adverse effect of capacitive coupling between the data line and the channel region is negligible. Since it is necessary to dispose a thick interlayer insulating film between the two, it is basically difficult to sufficiently shield the light. Further, according to the technique described in Japanese Patent Application Laid-Open No. 9-33944, an a-Si film is formed on the gate line, so that the adverse effect of capacitive coupling between the gate electrode and the a-Si film is reduced. It is necessary to stack a relatively thick interlayer insulating film. As a result, the a-Si film, the interlayer insulating film, and the like that are additionally formed increase the complexity of the laminated structure, and it is also difficult to sufficiently shield oblique incident light and inner surface reflected light. In particular, according to various conventional light-shielding techniques described above, sufficient light shielding can be achieved as the electro-optical device is refined or the pixel pitch is made finer in order to meet the general demand for high-quality display images in recent years. It becomes more difficult to apply, and there is a problem that the flicker or the like occurs due to a change in the transistor characteristics of the TFT and the quality of the display image is lowered.

  On the other hand, the above-described technology for adding a storage capacity has the following problems. In other words, in this type of electro-optical device, the pixel aperture ratio is increased while reducing the pixel pitch in order to improve the display image quality (that is, in each pixel, in the non-aperture region in each pixel through which display light is not transmitted). On the other hand, it is important to widen the opening area through which the display light is transmitted), but the non-opening area of each pixel to which the scanning line and the capacitor line can be routed as the aperture ratio of the fine pitch pixel increases as described above. Narrow. For this reason, as the pixel pitch becomes finer, it becomes more difficult to create a sufficiently large storage capacitor and to provide sufficient conductivity to the scanning line and the capacitor line. If sufficient storage capacity cannot be obtained or sufficient conductivity is not obtained for the scanning lines and the capacity lines, eventually, crosstalk and ghosts in the display image increase and image quality deteriorates. Problems arise.

The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an electro-optical device in which a sufficiently large storage capacitor is formed and the pixel pitch can be reduced.

In order to solve the above-described problem, an electro-optical device according to an aspect of the invention includes a scanning line extending in a certain direction on a substrate, a data line extending in a direction intersecting the scanning line, and an intersection of the scanning line and the data line. A thin film transistor provided corresponding to the region, a pixel electrode provided in a matrix-like arrangement corresponding to the thin film transistor, and a storage capacitor, and the scanning line and one capacitor electrode of the storage capacitor; Are formed in the same layer, and the scanning line has a wide portion as a gate electrode in a portion facing the channel region of the thin film transistor and a narrow portion in another portion, and the width of the wide portion is The channel length of the channel region extending in the data line extending direction is defined.
In the present invention, by narrowing the width of the scanning line except for the portion facing the channel region of the thin film transistor, it is possible to cope with the finer pixel pitch and the capacity electrode formed in the same layer as the scanning line. The size can be made larger.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, the electro-optical device of the invention is applied to a liquid crystal device.

(First embodiment)
The configuration of the electro-optical device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms an image display region of an electro-optical device. FIG. 2 is a plan view of a plurality of adjacent pixel groups on the TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed. 3 is a cross-sectional view taken along the line AA ′ of FIG. 2, and FIG. 4 is a cross-sectional view taken along the line BB ′ of FIG. In FIGS. 3 and 4, the scales of the layers and members are different for each layer and each member so that each layer and each member can be recognized on the drawings.

  In FIG. 1, a plurality of pixels formed in a matrix that forms an image display area of the electro-optical device according to the present embodiment includes a pixel electrode 9 a and a TFT 30 for switching control of the pixel electrode 9 a. A data line 6 a to which an image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. good. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing. Image signals S1, S2,..., Sn written in a liquid crystal as an example of an electro-optical material via the pixel electrode 9a are transmitted to a counter electrode (described later) formed on a counter substrate (described later). Held for a certain period of time. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signal is emitted from the electro-optical device as a whole. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode.

  Particularly in this embodiment, the storage capacitor 70 is connected to a pixel potential side capacitor electrode 71 connected to the drain (and the pixel electrode 9a) of the TFT 30 and a capacitor line 300 as an example of a fixed potential wiring made of a light shielding film as will be described later. The fixed potential side capacitor electrode 72 is formed so as to be opposed to each other through a dielectric film. One of the pixel potential side capacitor electrode 71 and the fixed potential side capacitor electrode 72 is formed of the same silicon layer as the cover layer covering the channel region of the semiconductor layer constituting the TFT 30 as described later.

  In FIG. 2, on the TFT array substrate of the electro-optical device, a plurality of transparent pixel electrodes 9a (outlined by dotted line portions 9a ') are provided in a matrix, and the vertical and horizontal directions of the pixel electrodes 9a are provided. A data line 6a and a scanning line 3a are provided along each boundary.

  In addition, the scanning line 3a is disposed so as to face the channel region 1a 'indicated by the hatched region rising to the right in the drawing in the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode (particularly in the present embodiment). Then, the scanning line 3a is formed to be wide in the portion that becomes the gate electrode). As described above, the pixel switching TFT 30 in which the scanning line 3a is opposed to the channel region 1a ′ as the gate electrode is provided at each of the intersections of the scanning line 3a and the data line 6a. In FIG. 2, only the upper right pixel of the four pixels is shown in detail for the TFT 30, the storage capacitor 70, etc., but in reality, each pixel has the TFT 30, the storage capacitor 70, etc. It is built.

  In the present embodiment, the conductive upper light shielding film 90 constituting the capacitor line 300 shown in FIG. 1 is provided in a grid pattern along the gap between the pixel electrodes (on the upper layer side of the TFT 30 on the substrate as will be described later). Similarly, the lower-layer light-shielding film 11a is also provided in a lattice pattern (on the lower layer side of the TFT 30 on the substrate as will be described later). These upper-layer light-shielding film 90 and lower-layer light-shielding film 11a are refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum), and Pb (lead), respectively. These include at least one of them, simple metals, alloys, metal silicides, polysilicides, and laminates of these. In the present embodiment, since the upper light shielding film 90 also serves as the capacitor line 300 in particular, it is necessary to form at least the upper light shielding film 90 of the light shielding film from a conductive material. If it is configured to serve as the function 300, at least the lower layer light-shielding film 11a needs to be formed of a conductive material.

  As shown in FIGS. 2 to 4, in this embodiment, in particular, a cover layer 80 made of a silicon layer is provided on the upper layer side in the vicinity of the gate electrode of the TFT 30 to cover the channel region 1 a ′ from the upper side. Further, a pixel potential side capacitor electrode 71 of the storage capacitor 70 is formed from the same layer as the scanning line 3a, and a fixed potential side capacitor electrode 72 of the storage capacitor 70 is formed from the same silicon layer as the cover layer 80. The pixel potential side capacitance electrode 71 and the fixed potential side capacitance electrode 72 are arranged to face each other via the dielectric film 74, so that the pixel potential side capacitance electrode 71 and the fixed potential side capacitance electrode 72 mainly overlap the data line 6a and the scanning line 3a in plan view. A substantially L-shaped storage capacitor 70 including a portion extending along the data line 6a and the scanning line 3a is constructed in the region. The dielectric film 74 is made of a relatively thin HTO film having a thickness of about 5 to 200 nm, a silicon oxide film such as an LTO film, a silicon nitride film, or the like. From the viewpoint of increasing the storage capacitor 70, the thinner the dielectric film 74 is, the better, as long as sufficient film thickness reliability is obtained.

  In the present embodiment, in particular, the silicon layer portion forming the fixed potential side capacitor electrode 72 is electrically conductive by being doped with impurities, and the silicon layer portion forming the cover layer 80 made of the same silicon layer as the impurity is doped with impurities. Is not conductive because it is not doped. The cover layer 80 made of the same silicon layer and the fixed potential side capacitor electrode 72 are not separated in a pattern.

  As shown in FIGS. 2 and 3, the data line 6a is electrically connected to the high concentration source region 1d in the semiconductor layer 1a made of, for example, a polysilicon film through the contact hole 81.

As shown in FIGS. 2 and 4, the fixed potential side capacitor electrode 72 is connected to the upper light shielding film 90 constituting the capacitor line 300 of FIG. 1 via the contact hole 84.
The upper light shielding film 90 functioning as the capacitor line 300 extends around the image display area where the pixel electrode 9a is disposed, and is electrically connected to a constant potential source to have a fixed potential. As a constant potential source, a data line driving circuit for controlling a scanning line driving circuit (described later) for supplying a scanning signal for driving the TFT 30 to the scanning line 3a and a sampling circuit for supplying an image signal to the data line 6a. A constant potential source of a positive power source or a negative power source (described later) may be used, or a constant potential supplied to the counter electrode of the counter substrate may be used.

  Note that the lower-layer light-shielding film 11 a provided below the TFT 30 also extends from the image display area to the periphery thereof in the same manner as the upper-layer light-shielding film 90 in order to avoid the potential fluctuation from adversely affecting the TFT 30. Then, it may be connected to a constant potential source.

  Further, as shown in FIGS. 2 to 4, the pixel electrode 9a is electrically connected to the high concentration drain region 1e in the semiconductor layer 1a through the contact holes 83 and 85 by relaying the pixel potential side capacitor electrode 71. It is connected.

  In FIG. 3, the contact hole 81 has a relatively deep depth, so that another conductive layer in the middle (for example, the same layer as the pixel potential side capacitor electrode 71, the same layer as the fixed potential side capacitor electrode 72, and the upper layer light shielding). The same layer as the film 90) may be used as a relay layer and may be composed of two or more serial contact holes. Similarly, since the contact hole 85 in FIG. 4 has a relatively deep depth, another conductive layer in the middle (for example, the same layer as the fixed potential side capacitor electrode 72, the same layer as the upper light shielding film 90, the data line 6a) The same layer) may be used as a relay layer and may be composed of two or more serial contact holes. Thus, if another intermediate conductive layer is used as a relay layer, for example, even if the interlayer distance is as long as, for example, about 1000 nm, the technical difficulty of connecting the two with a single contact hole is relatively avoided. Two or more series contact holes having a small diameter can be connected to each other well, the pixel aperture ratio can be increased, and it is useful for preventing etching through when the contact hole is opened. In addition, for the contact holes 81 and 85 having such a deep depth, in consideration of the difficulty in controlling the etching depth, a film for preventing etching through is formed below the semiconductor layer 1a (in the case of the contact hole 81) and the pixel potential. It may be provided in an island shape below the side capacitor electrode 71 (in the case of the contact hole 85).

  As shown in FIGS. 3 and 4, the electro-optical device includes a transparent TFT array substrate 10 and a transparent counter substrate 20 disposed to face the TFT array substrate 10. The TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive thin film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is made of an organic thin film such as a polyimide thin film.

  On the other hand, a counter electrode 21 is provided over the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. The counter electrode 21 is made of a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.

  As shown in FIGS. 3 and 4, the counter substrate 20 may be further provided with a second light shielding film 23 having a lattice shape or a stripe shape. By adopting such a configuration, it is possible to reliably prevent the incident light from entering the channel region 1a ′, the low concentration source region 1b, and the low concentration drain region 1c from the counter substrate 20 side together with the upper light shielding film 90. Further, the second light-shielding film 23 functions to prevent an increase in temperature of the electro-optical device by forming at least a surface irradiated with incident light with a highly reflective film. In addition, in the present embodiment, a light shielding data line 6a made of an Al film or the like may shield light from the light shielding region of each pixel along the data line 6a.

  Between the TFT array substrate 10 and the counter substrate 20, which are arranged in such a manner so that the pixel electrode 9 a and the counter electrode 21 face each other, an electro-optical material is placed in a space surrounded by a seal material described later. A liquid crystal layer 50 is formed by encapsulating liquid crystal as an example. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the counter substrate 20 around them, and the distance between the two substrates is set to a predetermined value. Gap materials such as glass fibers or glass beads are mixed.

  Further, a base insulating film 12 is provided under the pixel switching TFT 30. The base insulating film 12 is formed on the entire surface of the TFT array substrate 10, thereby preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughness during polishing of the surface of the TFT array substrate 10 or dirt remaining after cleaning. Have

  In FIG. 3, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a, a channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, and scanning. Insulating thin film 2 including a gate insulating film that insulates line 3a from semiconductor layer 1a, low concentration source region 1b and low concentration drain region 1c of semiconductor layer 1a, high concentration source region 1d and high concentration drain region 1e of semiconductor layer 1a It has.

  On the fixed potential side capacitance electrode 72, a contact hole 81 leading to the high concentration source region 1d, a contact hole 84 leading to the fixed potential side capacitance electrode 72, and a contact hole 85 leading to the pixel potential side capacitance electrode 71 are opened. A first interlayer insulating film 41 is formed.

  An upper light shielding film 90 is formed on the first interlayer insulating film 41, and a contact hole 81 leading to the high-concentration source region 1d and a contact hole 85 leading to the pixel potential side capacitor electrode 71 are opened on these. A holed second interlayer insulating film 42 is formed.

  A data line 6 a is formed on the second interlayer insulating film 42, and a third interlayer insulating film 43 in which a contact hole 85 leading to the pixel potential side capacitor electrode 71 is formed is formed thereon. . The pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 43 thus configured.

  According to the present embodiment configured as described above, when incident light enters the channel region 1a ′ of the TFT 30 and its vicinity from the counter substrate 20 side, the second light shielding film 23, the data line 6a, and the upper layer light shielding film. The light is shielded at 90. On the other hand, when returning light enters the channel region 1a ′ of the TFT 30 and the vicinity thereof from the TFT array substrate 10 side, the lower light shielding film 11a shields the light (especially, a plurality of projectors for color display, etc.) When an electro-optical device is combined through a prism or the like to form one optical system, the return light consisting of the projection light portion that penetrates the prism or the like from another electro-optical device is strong and effective. .) Then, when light is shielded from the TFT 30 such as oblique incident light, inner surface reflected light, and multiple reflected light at a distance from each other, the light component having a light shielding effect is absorbed by the cover layer 80 laminated close to the TFT 30. To do. As a result, the characteristics of the TFT 30 are hardly deteriorated by light leakage, and the electro-optical device can obtain very high light resistance. That is, in this embodiment, the cover layer 80 can be disposed close to the TFT 30 without causing problems related to stress and capacitive coupling, and thus the light resistance can be sufficiently enhanced by the cover layer 80.

  Moreover, in this embodiment, in particular, as described above, the silicon layer portion that forms the fixed potential side capacitor electrode 72 is made of doped silicon that is conductive by being doped with impurities, and the silicon layer portion that forms the cover layer 80 is It is made of non-doped silicon that is not electrically conductive because it is not doped with impurities. For this reason, even if the cover layer 80 is disposed close to the TFT 30, the capacitive coupling does not become a problem, which is very advantageous because the cover layer 80 can be disposed closer to the channel region 1 a ′.

  By setting the film thickness of such a cover layer to about 100 nm to 300 nm, preferably about 200 nm, the light absorption rate can be sufficiently increased practically. At the same time, the stress generated by the presence of the cover layer 80 is hardly a problem in practical use, and the step on the lower ground (the surface of the third interlayer insulating film 43) generated due to the presence of the cover layer 80 is also practical. Almost no problem. Further, there is no problem if the fixed potential side capacitor electrode 72 has such a film thickness. A more specific film thickness may be set by comprehensively considering the influence of transmittance (light absorption rate), steps, stress, and the like required according to the apparatus specifications.

  Furthermore, according to the present embodiment, the potential written to the pixel electrode 9a via the data line 6a and the TFT 30 is relatively reduced by the storage capacitor 70 in which the fixed potential side capacitor electrode 72 is formed from the same silicon layer as the cover layer 80. It can be held for a long time. In other words, it efficiently accumulates in a limited area on the TFT array substrate 10 while avoiding complication or enlargement of the laminated structure by additionally laminating conductive layers used exclusively as electrodes of the storage capacitor 70. Capacity 70 can be made.

  In particular, in the present embodiment, the fixed potential side capacitor electrode 72 is dropped to a fixed potential by being connected to the upper light shielding film 90 laminated on the upper layer side of the TFT 30. Even where the semiconductor layer 1a exists, contact between the upper light-shielding film 90 and the fixed potential side capacitor electrode 72 can be made (that is, the semiconductor layer 1a can be bundled in plan view to avoid the contact hole 84). There is no need to make it smaller. Further, by using the upper light shielding film 90 laminated on the upper layer side of the TFT 30 in this way as the capacitor line 300 (see FIG. 1), in the electro-optical device manufacturing process described later, the dielectric film 74 of the storage capacitor 70 is obtained. Immediately after forming (that is, without interposing the operation of opening a contact hole for connecting to the fixed potential wiring on the lower side), the benefit of stacking the cover layer 80 and the silicon layer serving as the fixed potential side capacitor electrode 72 Can also be obtained.

  In addition, in this embodiment, in particular, the cover layer 80 made of the same silicon layer and the fixed potential side capacitor electrode 72 are not separated in a pattern. Therefore, the construction area of the storage capacitor 70 can be increased as compared with the case of separation, and the storage capacitor 70 can be increased.

  In the embodiment described above, by stacking a large number of conductive layers, a step is formed in the region along the data line 6a and the scanning line 3a on the lower ground of the pixel electrode 9a (that is, the surface of the third interlayer insulating film 43). However, a trench is dug in the TFT array substrate 10, the base insulating film 12, the first interlayer insulating film 41, the second interlayer insulating film 42, and the third interlayer insulating film 43 to embed wiring such as the data line 6 a and the TFT 30. The planarization process may be performed by polishing the upper surface of the third interlayer insulating film 43 and the second interlayer insulating film 42 by a CMP (Chemical Mechanical Polishing) process or the like, or using organic SOG. The flattening treatment may be performed by forming it flat.

  Further, in the embodiment described above, the pixel switching TFT 30 preferably has an LDD structure as shown in FIG. 3, but has an offset structure in which impurities are not implanted into the low concentration source region 1b and the low concentration drain region 1c. Alternatively, it may be a self-aligned TFT in which a high concentration source and drain regions are formed in a self-aligned manner by implanting impurities at a high concentration using a gate electrode formed of a part of the scanning line 3a as a mask. In this embodiment, only one gate electrode of the pixel switching TFT 30 is arranged between the high concentration source region 1d and the high concentration drain region 1e. However, two or more gate electrodes are provided between these gate electrodes. You may arrange. If the TFT is configured with dual gates or triple gates or more in this way, leakage current at the junction between the channel and the source and drain regions can be prevented, and the off-time current can be reduced.

(Manufacturing process)
Next, a manufacturing process of the electro-optical device according to the first embodiment having the above-described configuration will be described with reference to FIGS. FIG. 5 and FIG. 6 show the layers on the TFT array substrate side in each step in the manufacturing process of the electro-optical device according to the first embodiment, as in FIG. 4 and FIG. It is process drawing shown corresponding to a -B 'cross section.

First, as shown in step (1) of FIG. 5, a TFT array substrate 10 such as a quartz substrate, hard glass, or silicon substrate is prepared. Here, annealing is preferably performed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and pretreatment is performed so as to reduce distortion generated in the TFT array substrate 10 in a high-temperature process to be performed later. Keep it. Then, a metal alloy film such as a metal such as Ti, Cr, W, Ta, Mo, and Pd or a metal silicide is formed on the entire surface of the TFT array substrate 10 thus processed by sputtering to a thickness of about 100 to 500 nm. Preferably, a light shielding film having a thickness of about 200 nm is formed. Then, a lower-layer light-shielding film 11a having a predetermined pattern as shown in FIG. 2 is formed by photolithography and etching.

  Subsequently, TEOS (tetraethyl orthosilicate) gas, TEB (tetraethyl boatate) gas, TMOP (tetramethyloxy) are formed on the lower light shielding film 11a by, for example, atmospheric pressure or reduced pressure CVD. A base insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed using a phosphite gas or the like. The film thickness of the base insulating film 12 is, for example, about 500 to 2000 nm.

  Subsequently, low pressure CVD (for example, pressure) using monosilane gas, disilane gas or the like at a flow rate of about 400 to 600 cc / min on the base insulating film 12 in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C. An amorphous silicon film is formed by CVD of about 20 to 40 Pa. Thereafter, an annealing process is performed in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, so that the polysilicon film 1 has a thickness of about 50 to 200 nm, preferably Is solid-phase grown to a thickness of about 100 nm. As a method for solid phase growth, annealing using RTA (Rapid Thermal Anneal) may be used, or laser annealing using an excimer laser or the like may be used. At this time, depending on whether the TFT 30 for pixel switching is an n-channel type or a p-channel type, a dopant of a group V element or a group III element may be slightly doped by ion implantation or the like. Then, a semiconductor layer 1a having a predetermined pattern as shown in FIG. 2 is formed by photolithography and etching.

  Next, as shown in step (2), the semiconductor layer 1a constituting the TFT 30 is thermally oxidized at a temperature of about 900 to 1300 ° C., preferably about 1000 ° C., or by a low pressure CVD method, or both. The insulating thin film 2 (including the gate insulating film) made of a single-layer or multilayer high-temperature silicon oxide film (HTO film) or silicon nitride film is formed. As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating thin film 2 has a thickness of about 20 to 150 nm, preferably about 30. The thickness is ˜100 nm.

  Subsequently, the contact hole 83 is opened by dry etching such as reactive ion etching or reactive ion beam etching on the insulating thin film 2. Further, a polysilicon film is deposited by a low pressure CVD method or the like, and phosphorus (P) is further thermally diffused to make the polysilicon film conductive. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The polysilicon film has a thickness of about 100 to 500 nm, preferably about 300 nm. Then, the scanning line 3a having a predetermined pattern and the pixel potential side capacitor electrode 71 as shown in FIG. 2 are simultaneously formed by photolithography and etching.

Subsequently, when the TFT 30 is an n-channel TFT having an LDD structure, the scanning line 3a (gate electrode) is used as a mask to form the low concentration source region 1b and the low concentration drain region 1c in the semiconductor layer 1a. A dopant of a group V element such as P is doped at a low concentration (for example, P ions are doped at a dose of 1 to 3 × 10 ¹³ / cm ² ). Thereby, the semiconductor layer 1a under the scanning line 3a becomes the channel region 1a ′. This impurity doping also reduces the resistance of the pixel potential side capacitor electrode 71 and the scanning line 3a. Further, in order to form the high concentration source region 1d and the high concentration drain region 1e constituting the pixel switching TFT 30, a resist layer 600 is formed on the scanning line 3a with a mask wider than the scanning line 3a. A dopant of a group V element such as P is doped at a high concentration (for example, P ions are doped at a dose of 1 to 3 × 10 ¹⁵ / cm ² ). When the pixel switching TFT 30 is a p-channel type, B or the like is used to form the low concentration source region 1b and the low concentration drain region 1c, the high concentration source region 1d and the high concentration drain region 1e in the semiconductor layer 1a. Doping is performed using a group III element dopant. For example, an TFT having an offset structure may be used without doping at a low concentration, or a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like using the scanning line 3a as a mask. This impurity doping further reduces the resistance of the pixel potential side capacitor electrode 71 and the scanning line 3a.

  In parallel with the element forming process of these TFTs 30, peripheral circuits such as a data line driving circuit and a scanning line driving circuit having a complementary structure composed of an n-channel TFT and a p-channel TFT are arranged on the TFT array substrate 10. You may form in the upper peripheral part.

  Next, as shown in step (3), a high-temperature silicon oxide film (HTO film) or silicon nitride film is formed on the pixel potential side capacitor electrode 71, the scanning line 3a, and the insulating thin film 2 by a low pressure CVD method, a plasma CVD method or the like. A dielectric film 74 is deposited to a relatively thin thickness of 25 nm or more and 50 nm or less. However, the dielectric film 74 may be composed of either a single layer film or a multilayer film as in the case of the insulating thin film 2 and is generally formed by various known techniques used to form a gate insulating film of a TFT. It can be formed. The thinner the dielectric film 74 is, the larger the storage capacitor 70 is. Therefore, the dielectric film is formed so as to be an extremely thin insulating film having a film thickness of 50 nm or less on the condition that no film breakage or other defects occur. If 74 is formed, the effect of this embodiment can be increased.

  Subsequently, after depositing a non-conductive polysilicon layer on the dielectric film 74 by a low pressure CVD method or the like, the cover layer 80 and the fixed potential side capacitor electrode 72 ′ (see FIG. 2) are formed by photolithography and etching. A silicon layer having a predetermined pattern including an electrode before conductivity is imparted). In this case, the film thickness of the silicon layer is preferably about 100 nm to 300 nm, but comprehensively considers the influence of transmittance (light absorption rate), step, stress, etc. required according to the device specifications as described above. To set.

  Next, in step (4), after forming a resist 601 that masks the silicon layer portion that will become the cover layer 80 by photolithography and etching, ion implantation is performed from the direction indicated by the arrow 600 to obtain a fixed potential side capacitance. The resistance of the electrode 72 'is reduced. That is, the fixed potential side capacitor electrode 72 made of doped silicon is completed. At this time, the cover layer 80 is not doped. That is, the cover layer 80 is made of non-doped silicon.

  Next, as shown in step (5) of FIG. 6, after removing the resist 500, a silicate glass film such as NSG, PSG, BSG, BPSG, etc., using, for example, atmospheric pressure or reduced pressure CVD method or TEOS gas. Then, a first interlayer insulating film 41 made of a silicon nitride film, a silicon oxide film or the like is formed. The film thickness of the first interlayer insulating film 41 is, for example, about 500 to 1500 nm.

  Further, the contact hole 84 is opened by dry etching such as reactive ion etching or reactive ion beam etching for the first interlayer insulating film 41. Thereafter, a metal alloy film such as a metal such as Ti, Cr, W, Ta, Mo, and Pd or a metal silicide is formed on the entire surface of the first interlayer insulating film 41 to a thickness of, for example, about 100 to 500 nm. Thereafter, photolithography and etching are performed to form an upper light shielding film 90 having a predetermined pattern as shown in FIG.

  Next, in step (6), a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, an oxide film, or the like is formed on the upper light shielding film 90 by using, for example, atmospheric pressure or reduced pressure CVD or TEOS gas. A second interlayer insulating film 42 made of a silicon film or the like is formed. The film thickness of the second interlayer insulating film 42 is, for example, about 500 to 1500 nm.

  Subsequently, the contact hole 81 is opened by dry etching such as reactive ion etching or reactive ion beam etching for the second interlayer insulating film 42. At this time, a contact hole for connecting the scanning line 3 a and the upper light shielding film 90 to a wiring (not shown) in the peripheral region of the substrate can be formed in the second interlayer insulating film 42 by the same process as the contact hole 81. Thereafter, a light-shielding low-resistance metal such as Al or metal silicide is deposited as a metal film on the entire surface of the first interlayer insulating film 41 to a thickness of about 100 to 500 nm, preferably about 300 nm, by sputtering or the like. . Then, the data line 6a having a predetermined pattern as shown in FIG. 2 is formed by photolithography and etching.

  Next, as shown in step (7), a silicate glass film such as NSG, PSG, BSG, BPSG, or the like is nitrided using, for example, atmospheric pressure or reduced pressure CVD method or TEOS gas so as to cover the data line 6a. A third interlayer insulating film 43 made of a silicon film, a silicon oxide film or the like is formed. The film thickness of the third interlayer insulating film 43 is, for example, about 500 to 1500 nm.

  Subsequently, the contact hole 85 is opened by dry etching such as reactive ion etching or reactive ion beam etching for the third interlayer insulating film 43.

  Subsequently, a transparent conductive thin film such as an ITO film is deposited on the third interlayer insulating film 43 to a thickness of about 50 to 200 nm by sputtering or the like. Then, a pixel electrode 9a having a predetermined pattern as shown in FIG. 2 is formed by photolithography and etching. When the liquid crystal device is used for a reflective liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

  Subsequently, after applying a polyimide-based alignment film coating solution on the pixel electrode 9a, the alignment film 16 (FIGS. 3 and FIG. 3) is formed by performing a rubbing process so as to have a predetermined pretilt angle and in a predetermined direction. 4) is formed.

  On the other hand, for the counter substrate 20 shown in FIGS. 3 and 4, a glass substrate or the like is first prepared, and the second light shielding film 23 and the light shielding film as a frame (see FIGS. 14 and 15) are sputtered with, for example, metal chromium. Then, it is formed through photolithography and etching. These light shielding films do not need to be conductive, and may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist in addition to a metal material such as Cr, Ni, or Al. If the light shielding region is defined on the TFT array substrate 10 by the data line 6a, the cover layer 80, the lower light shielding film 11a, etc., the second light shielding film 23 on the counter substrate 20 can be omitted.

  Then, the counter electrode 21 is formed by depositing a transparent conductive thin film such as ITO to a thickness of about 50 to 200 nm by sputtering or the like on the entire surface of the counter substrate 20. Further, after a polyimide alignment film coating solution is applied to the entire surface of the counter electrode 21, a rubbing process is performed in a predetermined direction so as to have a predetermined pretilt angle, and the alignment film 22 (FIGS. 3 and 4). Reference) is formed.

  Finally, the TFT array substrate 10 and the counter substrate 20 on which the respective layers are formed as described above are bonded together with a sealing material (see FIGS. 14 and 15) so that the alignment films 16 and 22 face each other, and vacuum suction or the like is performed. Thus, for example, liquid crystal formed by mixing a plurality of types of nematic liquid crystals is sucked into the space between the two substrates to form a liquid crystal layer 50 having a predetermined layer thickness.

  As described above, in this manufacturing process, the cover layer 80 and the fixed potential side capacitance electrode 72 are formed from the same silicon layer in the steps (3) and (4) of FIG. An electro-optical device can be manufactured relatively easily. In particular, in step (4), the silicon layer portion forming the cover layer 80 is ion-implanted while masking, and the cover layer 80 is not made conductive, and only the silicon layer portion forming the fixed potential side capacitor electrode 72 is conductive. Can give sex. As a result, the cover layer 80 that is not pattern-separated and that does not cause a problem of capacitive coupling with the TFT 30 even when arranged close to the TFT 30 can be manufactured relatively easily.

(Second Embodiment)
Next, a second embodiment of the electro-optical device according to the invention will be described with reference to FIGS. FIG. 7 is a plan view of a pixel of the TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed, and FIG. 8 shows a main laminated structure centering on the cover layer in FIG. FIG. 9 is an AA ′ sectional view, and FIG. 9 is an AA ′ sectional view of the modification. In FIGS. 8 and 9, the scales of the respective layers and members are appropriately changed in order to make each layer and each member large enough to be recognized on the drawings. Also, in FIGS. 7 to 9, the same components as those in FIGS. 1 to 3 (first embodiment) are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 7 and FIG. 8, in the second embodiment, unlike the first embodiment, the upper light shielding film 90 does not exist (and accordingly, the second interlayer insulating film 42 and the contact hole 84). Instead, the fixed potential side capacitor electrode 172 made of the same silicon layer as the cover layer 80 is connected to the lower light-shielding film 11a through the contact hole 86 and dropped to the fixed potential. . Further, the pixel potential side capacitor electrode 171 is formed not from the same layer as the scanning line 3a but from a conductive polysilicon film portion extending from the high concentration drain region 1a of the semiconductor layer 1a. The storage capacitor 170 is constructed by disposing the capacitor electrode 171 and the fixed potential side capacitor electrode 172 so as to face each other through the dielectric film 174. Further, the planar shape of the semiconductor layer 1a is slightly shortened in the vicinity of the upper end in FIG. 8 so that the contact hole 86 can be opened, and a portion forming the pixel potential side capacitor electrode 171 so as to increase the storage capacitor 170 is formed. The region extending along the scanning line is also extended (on the right side in FIG. 8). Further, a contact hole 85 from the pixel electrode 9a is formed near the right end of the semiconductor layer 1a in FIG. On the other hand, the insulating thin film 2 including the gate insulating film 2 in this region is removed by etching so that the dielectric film of the storage capacitor 170 is not thickened. Other configurations are the same as those in the first embodiment shown in FIGS. 2 to 4 including the configuration of the pixel electrode 9a, the counter substrate 20 and the like omitted in FIG.

  Therefore, according to the second embodiment, the lower light shielding film 11a that at least partially defines the non-opening region of each pixel has not only a light shielding function but also a function as the capacitance line 300 shown in FIG. Such a lower light-shielding film 11a is preferably extended from the image display region in which the pixel electrode 9a is disposed to a constant potential source, as in the case of the upper light-shielding film 90 in the first embodiment. Electrically connected.

  In addition, as shown in FIG. 9, the storage capacitor 170 may be formed only in the region overlapping the data line 6a (in a rectangular shape) without forming it in the region overlapping the scanning line 3a (in an L shape). . In this case, in order not to unnecessarily widen the pixel non-opening region along the scanning line 3a, a corner portion extending from the high concentration drain region 1e of the semiconductor layer 1a is protruded below the pixel electrode 9a. A contact hole 185 from the pixel electrode 9a is opened in the portion.

(Third embodiment)
Next, a third embodiment of the electro-optical device of the invention will be described with reference to FIGS. FIG. 10 is a plan view of a pixel of the TFT array substrate on which data lines, scanning lines, pixel electrodes, etc. are formed, and FIG. 11 shows a main laminated structure centering on the cover layer in FIG. FIG. 12 is an AA ′ sectional view, and FIG. 12 is an AA ′ sectional view of the modification. In FIGS. 11 and 12, the scale of each layer and each member is appropriately changed so that each layer and each member has a size that can be recognized on the drawings. 10 to 13, the same reference numerals are given to the same components as those in FIGS. 1 to 3 (first embodiment) or the drawings, and the description thereof will be omitted.

  As shown in FIGS. 10 and 11, in the third embodiment, the cover layer 80 ′ made of the same silicon layer and the fixed potential side capacitor electrode 172 ′ are separated in a pattern as compared with the second embodiment. Yes. About another structure, it is the same as that of the case of 2nd Embodiment.

  Therefore, according to the third embodiment, the lower light shielding film 11a that at least partially defines the non-opening region of each pixel has not only a light shielding function but also a function as the capacitor line 300 shown in FIG. In particular, since the cover layer 80 ′ and the fixed potential side capacitor electrode 172 ′ are separated, it is possible to alleviate the stress caused by additionally forming them in the laminated structure. Furthermore, it is possible to prevent a situation in which a slight potential fluctuation at the fixed potential side capacitor electrode 72 adversely affects the TFT 30 via the cover layer 80.

  As shown in FIG. 12, the storage capacitor 170 may be formed only in the region overlapping the data line 6a (in a rectangle) without forming the storage capacitor 170 up to the region overlapping the scanning line 3a (in an L shape). . In this case, in order not to unnecessarily widen the pixel non-opening region along the scanning line 3a, a corner portion extending from the high concentration drain region 1e of the semiconductor layer 1a is protruded below the pixel electrode 9a. A contact hole 185 from the pixel electrode 9a is opened in the portion.

  Unlike the case of the first embodiment, the second and third embodiments described above do not have a function as the capacitor line 300 because the lower-layer light-shielding film 11a has a function as the capacitor line 300 in FIG. Although the upper light shielding film is omitted, in the second and third embodiments, a light shielding film such as the upper light shielding film 90 of the first embodiment may be provided exclusively for light shielding. That is, in order to improve the light resistance, it is more preferable that the upper light shielding film and the lower light shielding film are respectively disposed above and below the TFT 30.

  Here, with reference to FIG. 13, a description will be given of a preferable relationship between the shapes of the lower light shielding film and the upper light shielding film in the electro-optical device according to each embodiment of the present invention. Here, FIG. 13 is a plan view of a pixel of the TFT array substrate in which only the lower light shielding film and the upper light shielding film are extracted and shown.

  As shown in FIG. 13, in each embodiment, the lower light shielding film 11a and the upper light shielding film 90 are both formed in a lattice shape, and the lower light shielding film 11a protrudes from the formation region of the upper light shielding film 90 in plan view. It is configured so that it does not (that is, one size smaller). Accordingly, the upper light shielding film 90 defines the outline of the opening area of each pixel. Further, scanning lines, data lines, TFTs, and the like (not shown) between them are configured not to protrude from the formation region of the lower light-shielding film 11a in plan view.

  Accordingly, the incident light from the counter substrate 20 side is reflected by the lower light shielding film 11a (further, the scanning line, the data line, etc.) that protrudes from the formation region of the upper light shielding film 90, thereby reflecting the inner surface inside the electro-optical device. Generation of light and multiple reflected light can be effectively prevented. The return light from the TFT array substrate 10 is reflected by the upper light shielding film 90 portion that protrudes from the formation region of the lower light shielding film 11a, so that some internal reflection light and multiple reflected light are generated inside the electro-optical device. To do. However, since the return light has a much lower light intensity than the incident light, the adverse effect of the internal reflection and the multiple reflected light due to the return light is less than that of the incident light. Then, such a slight internal reflection light or multiple reflection light can be sufficiently absorbed by the cover layer 80 made of a silicon layer disposed in the vicinity of the TFT 30. Therefore, the configuration of this embodiment is advantageous.

(Other variations)
In each of the embodiments described above, the silicon layer portion forming the cover layer 80 is made of non-doped silicon and has no conductivity. However, the cover layer 80 is also the same as the fixed potential side capacitor electrode 72 formed from the same silicon layer. Alternatively, it may be formed of doped silicon that is conductive by being doped with impurities. In this case, capacitive coupling is hardly a problem even if the cover layer 80 is placed close to the TFT 30 by dropping the cover layer 80 to a fixed potential. Thus, when the cover layer 80 is composed of conductive doped silicon, from the viewpoint of reliably suppressing parasitic capacitance with the TFT 30, the cover layer 80 and the TFT 30 (that is, the scanning line 3a constituting the gate electrode). It is preferable that the thickness of the interlayer insulating film (dielectric film) interposed therebetween is 400 nm or more. Therefore, it is not desirable to use such a relatively thick interlayer insulating film as it is as the dielectric film of the storage capacitor (that is, the capacity is reduced in inverse proportion to the film thickness of the dielectric film). The insulating film may be locally etched at a portion to be a dielectric film to form a thin dielectric film of 25 nm to 50 nm. In such an electro-optical device, for example, in step (4) of FIG. 5, the cover layer 80 and the silicon layer forming the fixed potential side capacitor electrode 72 are ionized without masking the portion that becomes the cover layer 80. Implantation may be performed to form a low resistance doped silicon layer. Further, when the cover layer 80 is made conductive in this way, it is separated from the electrode made of the same silicon layer in a pattern, and further separated from the upper light shielding film, the lower light shielding film, etc. via a separate contact hole. Even when connected to the fixed potential wiring, the conductive cover layer 80 can be lowered to a fixed potential. In particular, when an electrode made of the same silicon layer as the cover layer 80 is used as the pixel potential electrode, such a configuration is preferably adopted.

  In each of the embodiments described above, the fixed potential side capacitor electrode 72 is formed from the same silicon film as the cover layer 80, but the pixel potential side capacitor electrode 71 may be formed from the same silicon film as the cover layer 80. . In each of the embodiments described above, the electrode that is not formed from the same silicon layer as the cover layer 80 is formed from the same layer as the scanning line 3a or the semiconductor layer 1a made of a conductive polysilicon film. For example, it may be formed of the same layer as the pixel electrode 9a made of an ITO film, the same layer as the upper or lower light shielding film, the same layer as the data line, or the like. Further, the fixed potential side capacitance electrode may be stacked on the upper side of the TFT 30 (for example, between the scanning line 3a and the pixel potential side capacitance electrode 71 or between the data line 6a and the pixel potential side capacitance electrode 71). Further, it may be laminated on the lower side of the TFT 30. However, the shorter the interlayer distance between the light-shielding film functioning as the capacitor line 300 and the fixed potential side capacitor electrode, the easier it is to connect the two through contact holes and the like, so that the laminated structure does not become complicated and the device reliability is improved. Rise.

  In addition, each of the above-described embodiments is constructed as a transmissive electro-optical device in which the pixel electrode is transparent and transmits incident light. However, the pixel electrode is a reflective film or the reflective film is below the pixel electrode. It may be constructed as a reflection type electro-optical device that is disposed in the reflection type and reflects incident light.

(Overall configuration of electro-optical device)
The overall configuration of the electro-optical device according to each embodiment configured as described above will be described with reference to FIGS. 14 and 15. FIG. 14 is a plan view of the TFT array substrate 10 as viewed from the counter substrate 20 side together with the components formed thereon, and FIG. 15 is a cross-sectional view taken along line HH ′ of FIG.

  In FIG. 15, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and an image display region made of the same or different material as the second light-shielding film 23, for example, in parallel with the inner side. A third light-shielding film 53 is provided as a frame that defines the periphery of 10a. In a region outside the sealing material 52, a data line driving circuit 101 and an external circuit connection terminal 102 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing along one side of the TFT array substrate 10. A scanning line driving circuit 104 that drives the scanning line 3a by supplying a scanning signal to the scanning line 3a at a predetermined timing is provided along two sides adjacent to the one side. Needless to say, if the delay of the scanning signal supplied to the scanning line 3a is not a problem, the scanning line driving circuit 104 may be provided on only one side. The data line driving circuit 101 may be arranged on both sides along the side of the image display area 10a. Further, on the remaining side of the TFT array substrate 10, a plurality of wirings 105 are provided for connecting between the scanning line driving circuits 104 provided on both sides of the image display region 10a. Further, at least one corner of the counter substrate 20 is provided with a conductive material 106 for electrical connection between the TFT array substrate 10 and the counter substrate 20. As shown in FIG. 15, the counter substrate 20 having substantially the same outline as the sealing material 52 shown in FIG. 14 is fixed to the TFT array substrate 10 by the sealing material 52.

  On the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104 and the like, a sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing, and a plurality of data lines A precharge circuit for supplying a precharge signal of a predetermined voltage level in advance to the image signal to 6a, an inspection circuit for inspecting quality, defects, etc. of the electro-optical device during manufacture or at the time of shipment are formed. Also good.

  In each embodiment described above with reference to FIGS. 1 to 15, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, on a TAB (Tape Automated Bonding) substrate. The mounted LSI for driving may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. Further, for example, a TN mode, a VA (Vertically Aligned) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, and the like are respectively provided on the side on which the projection light of the counter substrate 20 enters and the side on which the emission light of the TFT array substrate 10 exits. A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to the operation mode and the normally white mode / normally black mode.

  Since the electro-optical device in each embodiment described above is applied to a projector, three electro-optical devices are respectively used as RGB light valves, and each light valve has a dichroic mirror for RGB color separation. The light of each color resolved through the light enters as projection light. Therefore, in each embodiment, the counter substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the counter substrate 20 together with the protective film in a predetermined region facing the pixel electrode 9a where the second light shielding film 23 is not formed. In this way, the electro-optical device in each embodiment can be applied to a direct-view type or reflective type color electro-optical device other than the projector. Further, a microlens may be formed on the counter substrate 20 so as to correspond to one pixel. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrodes 9 a facing RGB on the TFT array substrate 10. In this way, a bright electro-optical device can be realized by improving the collection efficiency of incident light. Furthermore, a dichroic filter that creates RGB colors using light interference may be formed by depositing multiple layers of interference layers having different refractive indexes on the counter substrate 20. According to this counter substrate with a dichroic filter, a brighter color electro-optical device can be realized.

  The present invention is not limited to each of the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. An optical device and a manufacturing method thereof are also included in the technical scope of the present invention.

3 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of pixels in a matrix form constituting an image display region in the electro-optical device according to the first embodiment of the present invention. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed in the electro-optical device of the first embodiment. FIG. It is AA 'sectional drawing of FIG. It is BB 'sectional drawing of FIG. Each layer on the TFT array substrate side in each step in the manufacturing process of the electro-optical device according to the first embodiment is shown corresponding to the AA ′ cross section and the BB ′ cross section in FIG. 2 as in FIGS. 4 and 5. It is process drawing (the 1). Each layer on the TFT array substrate side in each step in the manufacturing process of the electro-optical device according to the first embodiment is shown corresponding to the AA ′ cross section and the BB ′ cross section in FIG. 2 as in FIGS. 4 and 5. It is process drawing (the 2). FIG. 6 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in an electro-optical device according to a second embodiment. It is AA 'sectional drawing of FIG. 7 which shows the main laminated structures centering on the cover layer in 2nd Embodiment. It is AA 'sectional drawing of FIG. 7 in the modification of 2nd Embodiment. FIG. 10 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed in an electro-optical device according to a third embodiment. It is AA 'sectional drawing of FIG. 10 which shows the main laminated structures centering on the cover layer in 3rd Embodiment. It is AA 'sectional drawing of FIG. 10 in the modification of 3rd Embodiment. It is a top view of the pixel of the TFT array substrate which extracts and shows the upper layer light shielding film and lower layer light shielding film in each embodiment. FIG. 5 is a plan view of a TFT array substrate in the electro-optical device according to each embodiment, as viewed from the counter substrate side, together with each component formed thereon. It is HH 'sectional drawing of FIG.

Explanation of symbols

1a ... Semiconductor layer 1a '... Channel region 1b ... Low concentration source region 1c ... Low concentration drain region 1d ... High concentration source region 1e ... High concentration drain region 2 ... Insulating thin film 3a ... Scan line 6a Data line 9a Pixel electrode 10 TFT array substrate 11a Lower light shielding film 12 Base insulating film 16 Orientation film 20 Counter substrate 21 Counter electrode 22 Orientation film 23 Second light shielding film 30 ... TFT
50 ... Liquid crystal layer 70 ... Storage capacitor 71 ... Pixel potential side capacitor electrode 72 ... Fixed potential side capacitor electrode 74 ... Dielectric film 80 ... Cover layer 90 ... Upper light shielding films 81, 83, 85 ... Contact hole 300 ··· Capacitance line

Claims (1)

A scanning line extending in a certain direction on the substrate, a data line extending in a direction crossing the scanning line, a thin film transistor provided corresponding to an intersection region of the scanning line and the data line, and a thin film transistor corresponding to the thin film transistor A pixel electrode provided in a matrix arrangement and a storage capacitor,
The scanning line and one capacitor electrode of the storage capacitor are formed in the same layer,
The scanning line has a wide portion as a gate electrode in a portion facing the channel region of the thin film transistor and a narrow portion in another portion,
2. The electro-optical device according to claim 1, wherein a width of the wide portion is provided so as to define a channel length of the channel region extending in a direction in which the data line extends.

Images