JP4144183B2 - Electro-optical device, manufacturing method thereof, and projection display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of an active matrix driving type electro-optical device, a method for manufacturing the same, and an electronic apparatus including such an electro-optical device. An electro-optical device of a type having a transistor such as a film transistor (hereinafter referred to as TFT as appropriate) and a storage capacitor, and having a peripheral circuit such as a drive circuit in a peripheral region on the substrate, and a method for manufacturing the same And belongs to the technical field of electronic equipment including such an electro-optical device.
[0002]
[Background]
In an electro-optical device such as a TFT active matrix driving type liquid crystal device, a TFT is formed for each of a large number of pixel electrodes arranged in a plane in an image display area, and a scanning line and a data line are connected to each TFT. Is common. In operation, when the scanning signal is supplied to the gate electrode of the TFT via the scanning line, the TFT is turned on, and the image signal supplied to the source region of the semiconductor layer via the data line is the source of the TFT. -It is supplied to the pixel electrode through the drain. Since such an image signal is supplied only for a very short time for each pixel electrode through each TFT, the voltage of the image signal supplied through the TFT is set to be much longer than the time in which it is turned on. In general, a storage capacitor is added to each pixel electrode (in parallel with a liquid crystal capacitor or the like) so that the pixel electrode can be held for a long time. That is, in the laminated structure in the image display region, a TFT and a storage capacitor are generally formed for each pixel.
[0003]
On the other hand, in this type of electro-optical device, peripheral circuits such as a data line driving circuit for driving data lines, a scanning line driving circuit for driving scanning lines, and a sampling circuit for sampling image signals on the image signal lines are connected to the substrate. In addition to the so-called external type externally attached, the so-called peripheral circuit built-in type or drive circuit built-in type in which such a peripheral circuit is built in a laminated structure in the peripheral region on the substrate is also generalized.
[0004]
[Problems to be solved by the invention]
In this type of electro-optical device, there is a strong general demand for high-quality display images. For this purpose, each pixel has a non-aperture area that does not transmit display light while miniaturizing the pixel pitch. On the other hand, it is important to widen the opening area through which the display light is transmitted and increase the pixel aperture ratio. In addition, how to expand the image display area on the same size substrate is also important. Furthermore, there is a strong general demand for simplifying the device configuration and manufacturing process.
[0005]
However, if a TFT or a storage capacitor is formed for each pixel in the image display area, the area occupied by these increases, resulting in an increase in the non-opening area in each pixel, making it difficult to increase the pixel aperture ratio. There is a problem.
[0006]
Furthermore, the complex sophistication of peripheral circuits generally leads to an increase in the number of electronic elements constituting the peripheral circuits, and as a result, there is a problem that the peripheral area on a limited substrate widens and the image display area becomes narrow. is there.
[0007]
In addition, on the same substrate, TFTs and storage capacitors are created in the image display area, and peripheral circuits are created in the peripheral area. The number of conductive films, the number of semiconductor films, the number of insulating films, etc. on the substrate increases. There is a problem that the structure is complicated and the manufacturing process is complicated at the same time.
[0008]
The present invention has been made in view of the above-described problems, and can improve the pixel aperture ratio, simplify the device configuration and the manufacturing process, and can produce a high-definition image display and the manufacturing thereof. It is an object to provide a method and an electronic apparatus including such an electro-optical device.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the electro-optical device of the present invention has an image display area on a substrate. Wirings arranged in a matrix, thin film transistors and pixel electrodes arranged corresponding to the intersections of the wirings, A storage capacitor connected to the pixel electrode and stacked on the transistor;
A first electronic element including a portion formed based on the same film as at least one of a semiconductor film and an insulating film constituting the transistor in a peripheral region on the substrate, and a stacked formation with respect to the first electronic element And a second electronic element including a portion formed based on the same film as at least one of the conductive film and the insulating film constituting the storage capacitor, and through the wiring and the transistor, A peripheral circuit for operating the pixel electrode is provided.
[0010]
According to the electro-optical device of the present invention, driving by an active matrix driving method can be performed by performing switching control of the pixel electrode with a transistor connected thereto under driving control by a peripheral circuit provided in the peripheral region. At this time, good potential holding characteristics in the pixel electrode can be obtained by the storage capacitor. Here, in particular, in the image display area, the storage capacitor is stacked with respect to the transistor, and in the peripheral area, the second electronic element is stacked with respect to the first electronic element. Accordingly, since the three-dimensional arrangement requires a small area for forming the storage capacitor and the transistor in the image display region, the pixel aperture ratio can be increased while ensuring a sufficient storage capacitor. On the other hand, in the peripheral region, since the area for forming the first and second electronic elements can be small, the peripheral region occupying a limited region on the substrate can be narrowed, and at the same time, the pixel pitch can be made finer. Thus, it is possible to reduce the circuit pitch of the electronic elements in the peripheral circuit. In addition, the first electronic element includes a portion formed based on the same film as at least one of the semiconductor film and the insulating film constituting the transistor in the image display area, and the second electronic element has a storage capacitor in the image display area. Therefore, the number of semiconductor films, the number of insulating films, and the number of conductive films required as a whole can be reduced. In the image display area and the peripheral area, the transistor and the first electronic element can be formed at least partially simultaneously, and the storage capacitor and the second electronic element can be formed at least partially simultaneously. As a result, the laminated structure on the substrate and the manufacturing process can be simplified.
[0011]
As a result, according to the electro-optical device of the present invention, the device configuration and the manufacturing process can be simplified while increasing the pixel aperture ratio, and high-quality image display is possible.
[0012]
The transistor in the present invention may be a thin film transistor formed on a glass substrate or a silicon substrate. In the case of a glass substrate, since the substrate can be made transparent, a transmissive or reflective electro-optical device can be constructed. On the other hand, in the case of a silicon substrate, since the substrate is opaque, a reflection type electro-optical device is obtained.
[0013]
Alternatively, the transistor in the present invention may be formed on a semiconductor substrate. That is, a transistor may be formed near the surface of a single crystal silicon substrate by providing a P-layer or N-layer island or a buried layer on a single crystal silicon substrate or an N-type or P-type single crystal silicon substrate. In this case, the substrate is opaque and a reflective electro-optical device can be constructed.
[0014]
Further, the transistor in the present invention may be formed on a substrate by using so-called SOI (Silicon On Insulator) technology, SOS (Silicon On Sapphire) technology, or the like. More specifically, a silicon single crystal film is grown on an insulating substrate such as a sapphire substrate, or a single crystal silicon substrate is bonded to an insulating substrate such as a sapphire substrate and then separated after annealing. Thus, the transistor may be constructed from the single crystal silicon film by leaving the single crystal silicon film on the insulating substrate.
[0015]
Furthermore, the transistor in the present invention may be formed on a so-called Silicon Implanted Oxide substrate in which single-crystal silicon is formed on a silicon substrate through an oxide film by performing oxygen ion implantation or heat treatment on the silicon substrate.
[0016]
In one aspect of the electro-optical device of the present invention, the wiring includes a scanning line and a data line that intersect each other, and the peripheral circuit includes a scanning line driving circuit that drives the scanning line and a data line that drives the data line. Includes a drive circuit.
[0017]
According to this aspect, the driving by the active matrix driving method can be performed while driving the scanning line and the data line by the scanning line driving circuit and the data line driving circuit provided in the peripheral region, respectively. Here, the first and second electronic elements such as a shift register, a DAC (Digital to Analog Converter), a level shifter, an inverter, and the like that constitute the scanning line driving circuit and the data line driving circuit are arranged three-dimensionally. In particular, it is possible to reduce the circuit pitch of the first and second electronic elements in accordance with the reduction in pixel pitch.
[0018]
In another aspect of the electro-optical device according to the aspect of the invention, the wiring includes a scanning line and a data line that intersect each other, and the peripheral circuit samples an image signal on the image signal line and supplies the image signal to the data line including.
[0019]
According to this aspect, it is possible to drive by the active matrix driving method while sampling the image signal by the sampling circuit provided in the peripheral region. Here, since the first and second electronic elements such as TFTs constituting the sampling circuit are arranged three-dimensionally, the circuit pitch of the sampling circuit is made finer especially in response to the finer pixel pitch. It is also possible.
[0020]
In another aspect of the electro-optical device of the present invention, at least one of the first electronic element and the second electronic element includes a transistor.
[0021]
According to this aspect, the first electronic element and the second electronic element made of a transistor have the same or similar laminated structure as the transistor and the storage capacitor in the image display region, so that the laminated structure on the substrate and the manufacturing process can be simplified. Can be planned.
[0022]
Note that the transistor constituting at least one of the first electronic element and the second electronic element may be a polysilicon thin film transistor, an SOI thin film transistor, or a silicon substrate as in the case of the transistor in the pixel portion. The thin film transistor may be used. Furthermore, a top gate type, a bottom gate type, an n channel type, or a p channel type may be used. In particular, in the case of a transistor located on the lower side, a transistor built on a silicon substrate may be used.
[0023]
In another aspect of the electro-optical device of the present invention, the first electronic element and the second electronic element are configured as CMOS transistors.
[0024]
According to this aspect, the first electronic element and the second electronic element configured as CMOS transistors can form a peripheral circuit with a small area, and the leakage current and the consumption current in the peripheral circuit can be reduced. be able to.
[0025]
In another aspect of the electro-optical device of the present invention, at least one of the first electronic element and the second electronic element includes a capacitor.
[0026]
According to this aspect, since the first electronic element and the second electronic element made of the capacitor have the same or similar stacked structure as the transistor and the storage capacitor in the image display region, the stacked structure on the substrate and the simplification of the manufacturing process Can be planned. Moreover, it is advantageous when a high density integration and a large area are required, such as a switched capacitor type DAC.
[0027]
In another aspect of the electro-optical device according to the aspect of the invention, at least one of the first electronic element and the second electronic element includes a resistor.
[0028]
According to this aspect, the first electronic element and the second electronic element made of the resistor are formed based on the same layer as a part of the transistor and the storage capacitor in the image display region. Can be simplified. For example, the wiring resistance of a semiconductor layer or a conductor layer is used. In particular, if the resistance value is controlled by ion implantation after the intrinsic polysilicon film is formed, a resistor having a desired resistance value can be constructed. Such a resistor is very advantageous from the viewpoint of suppressing an increase in the area due to a three-dimensional structure when, for example, a resistance division type DAC that generally requires a large area is formed.
[0029]
In another aspect of the electro-optical device of the present invention, the first electronic element and the second electronic element are electrically connected to each other through a refractory metal plug.
[0030]
According to this aspect, since the first electronic element and the second electronic element are electrically connected to each other via the refractory metal plug, the electronic elements stacked on each other are highly reliable. An electrically connected configuration is obtained in the peripheral circuit.
[0031]
Alternatively, in another aspect of the electro-optical device according to the aspect of the invention, the first electronic element and the second electronic element may be further above one of the first electronic element and the second electronic element stacked on the upper side. They are electrically connected to each other through other stacked conductive films.
[0032]
According to this aspect, the first electronic element and the second electronic element are electrically connected to each other via the other conductive film stacked on the upper side thereof, so that these electrons stacked on each other A configuration in which the elements are electrically connected with high reliability and relatively easily can be obtained in the peripheral circuit.
[0033]
In this aspect, the other conductive film and the lower one of the first electronic element and the second electronic element may be electrically connected to each other via the relay layer.
[0034]
If comprised in this way, even if the interlayer distance of the electronic element located below and the other electrically conductive film laminated | stacked on the upper side is long, both will be connected by one long and large diameter contact hole, for example While avoiding technical difficulties and disadvantages, the two can be connected to each other through two contact holes that are relatively short and have a small diameter through the relay layer.
[0035]
In another aspect of the electro-optical device of the invention, one or more electronic elements are further stacked on the first electronic element and the second electronic element.
[0036]
According to this aspect, since one or more electronic elements are further stacked on the first electronic element and the second electronic element stacked on each other, the three electronic elements are arranged three-dimensionally. The structure is obtained. For this reason, a more complex or large-scale peripheral circuit can be created using many electronic elements while reducing the area occupied by the electronic elements on the substrate.
[0037]
In another aspect of the electro-optical device of the present invention, a conductive film dropped to a fixed potential is further stacked at a stacking position between the first electronic element and the second electronic element.
[0038]
According to this aspect, the conductive film lowered to a fixed potential is interposed between the first electronic element and the second electronic element that are stacked on each other, and functions as an electromagnetic shield. For this reason, it is possible to effectively prevent one potential fluctuation between the two from adversely affecting the other potential. Note that the conductive film dropped to such a fixed potential can be used for other purposes as a fixed potential wiring in a peripheral circuit or an image display region.
[0039]
In this aspect, the conductive film dropped to the fixed potential may be configured to function as a built-in light shielding film.
[0040]
With this configuration, the conductive film functions not only as an electromagnetic shield or a fixed potential wiring, but also as a built-in light shielding film. Therefore, when a laminated structure that requires the built-in light shielding film is adopted, the conductive film is laminated as a whole. The structure and manufacturing process can be simplified. For example, such a built-in light shielding film is formed for the purpose of shielding light that enters the TFT channel region and changes the transistor characteristics of the TFT due to the photoelectric effect.
[0041]
In another aspect of the electro-optical device of the present invention, the image display region further includes another transistor stacked on the transistor instead of or in addition to the storage capacitor.
[0042]
According to this aspect, in the image display region, other transistors are stacked on the pixel switching transistor, so that the pixel opening is formed by the two transistors and the storage capacitors arranged three-dimensionally in each pixel. It is possible to increase the functionality of each pixel without reducing the rate.
[0043]
In this aspect, in the image display region, the transistor and the other transistor may be configured as a CMOS transistor.
[0044]
With this configuration, it is possible to reduce leakage current and consumption current in each pixel by using a CMOS transistor.
[0045]
In order to solve the above-described problem, a method for manufacturing an electro-optical device according to the present invention is a method for manufacturing the electro-optical device according to the present invention described above (including various aspects thereof). Performing the step of forming the first electronic element in the peripheral region in parallel with the step of forming the transistor in the display region; and in the peripheral region in parallel with the step of forming the storage capacitor in the image display region. A step of forming a second electronic element is performed.
[0046]
According to the method of manufacturing the electro-optical device of the present invention, the transistor and the first electronic element are at least partially formed simultaneously in the image display area and the peripheral area, and the storage capacitor and the second electronic element are at least partially formed. Since these are formed simultaneously, the manufacturing process can be simplified.
[0047]
In an aspect of the method for manufacturing an electro-optical device according to the aspect of the invention, the same film is formed of a polysilicon film, and impurities are implanted into the polysilicon film while masking one of the image display area and the peripheral area. Thus, the method includes the step of using the polysilicon film in the non-masked region as the conductive film while maintaining the polysilicon film in the masked region as the semiconductor film.
[0048]
According to this aspect, by selectively implanting impurities into the same polysilicon film with or without a mask, one of the image display region and the peripheral region uses the polysilicon film as a semiconductor film, and on the other hand, It can be used as a conductive film. That is, based on the same film, it is finally used as a film with different electrical properties, so that the number of layers in the multilayer structure on the substrate can be reduced as a whole, and from the viewpoint of avoiding the complexity of the multilayer structure It is very advantageous. Such impurity implantation is performed using a known technique such as ion implantation or ion doping.
[0049]
In one aspect of the method of manufacturing the electro-optical device according to the aspect of the invention, the polarities of the transistors configured based on the same film are unified in the image display region and the peripheral region.
[0050]
According to this aspect, since transistors having the same polarity are manufactured based on the same film in the image display region and the peripheral region, a P-channel type transistor or an N-channel type transistor is relatively easily formed in both regions by the same process. I can make it.
[0051]
In order to solve the above-described problems, an electronic apparatus according to the present invention includes a light valve including any one of the electro-optical devices according to the present invention described above (including various aspects thereof), and projection light to the light valve. An illuminating light source; and an optical system that projects the projection light emitted from the light valve.
[0052]
According to the electronic device of the present invention, the light beam is projected onto the light valve from the light source, and the projection light emitted from the light valve is projected onto the screen or the like by the optical system. At this time, since the light valve is composed of the above-described electro-optical device of the present invention, a bright and high-quality image can finally be displayed.
[0053]
Such an operation and other advantages of the present invention will become apparent from the embodiments described below.
[0054]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the electro-optical device of the invention is applied to a liquid crystal device.
[0055]
(Overall configuration of electro-optical device)
First, the overall configuration of an electro-optical device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. Here, a TFT active matrix driving type liquid crystal device with a built-in driving circuit, which is an example of an electro-optical device, is taken as an example.
[0056]
FIG. 1 is a plan view of a TFT array substrate as viewed from the counter substrate side together with the components formed thereon, and FIG. 2 is a cross-sectional view taken along line HH ′ of FIG.
[0057]
1 and 2, in the electro-optical device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are disposed to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region positioned around the image display region 10a. Are bonded to each other. The sealing material 52 is made of, for example, a thermosetting resin, heat and photo-curing resin, photo-curing resin, UV-curing resin, or the like in order to bond the two substrates, and after being applied on the TFT array substrate 10 in the manufacturing process, It is cured by heating, light irradiation, light irradiation, ultraviolet irradiation and the like.
[0058]
In such a sealing material 52, a gap material such as glass fiber or glass beads for mixing the distance between the two substrates (inter-substrate gap) to a predetermined value is mixed. In other words, the electro-optical device according to the present embodiment is small and suitable for performing enlarged display for a projector light valve. However, such a gap material may be included in the liquid crystal layer 50 if the electro-optical device is a large-sized liquid crystal device such as a liquid crystal display or a liquid crystal television that performs the same size display.
[0059]
Vertical conduction members 106 are provided at the four corners of the counter substrate 20, and electrical conduction is established between the vertical conduction terminals provided on the TFT array substrate 10 and the counter electrode 21 provided on the counter substrate 20. Take.
[0060]
1 and 2, a light-shielding frame 53 that defines the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the seal material 52 is disposed. It goes without saying that the frame 53 may be provided on the TFT array substrate 10 side. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in an outer portion extending around the image display area and outside the seal area where the seal material 52 is disposed. The scanning line driving circuit 104 is provided along two sides adjacent to the one side. Further, on the remaining side of the TFT array substrate 10, a plurality of wirings 105 are provided for connecting between the scanning line driving circuits 104 provided on both sides of the image display region 10a.
[0061]
In FIG. 2, on the TFT array substrate 10, an alignment film is formed on the pixel electrode 9a after the pixel switching TFT, the scanning line, the data line and the like are formed. On the other hand, an alignment film is formed on the counter substrate 20 in the uppermost layer portion in addition to the counter electrode 21. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.
[0062]
In the present embodiment, a sampling circuit 118 is provided in a region on the TFT array substrate 10 below the frame 53. The sampling circuit 118 is configured to sample the image signal on the image signal line in accordance with the sampling circuit drive signal supplied from the data line drive circuit 101 and supply it to the data line.
[0063]
(Circuit configuration and operation of electro-optical device)
Next, the circuit configuration and operation of the electro-optical device configured as described above will be described with reference to FIG. FIG. 3 is a block diagram showing equivalent circuits such as various elements and wirings and peripheral circuits in a plurality of pixels formed in a matrix that constitutes an image display area of the electro-optical device.
[0064]
In FIG. 3, a pixel electrode 9 a and a TFT 30 for switching control of the pixel electrode 9 a are formed in each of a plurality of pixels formed in a matrix that forms the image display region of the electro-optical device according to the present embodiment. The data line 6 a to which the image signal is supplied is electrically connected to the source of the TFT 30.
[0065]
In the peripheral area outside the image display area 10a, one end (the lower end in FIG. 3) of the data line 6a is connected to the drain of each switching element made of, for example, a TFT of the sampling circuit 118. On the other hand, the image signal line 115 is connected to the TFT source of the sampling circuit 118 via the lead-out wiring 116. The sampling circuit drive signal line 114 connected to the data line drive circuit 101 is connected to the gate of the TFT of the sampling circuit 118. The image signals S1, S2,..., Sn on the image signal line 115 are sampled in response to the sampling circuit drive signal supplied from the data line drive circuit 101 via the sampling circuit drive signal line 114. And is supplied to each data line 6a.
[0066]
In this way, the image signals S1, S2,..., Sn written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. Anyway.
[0067]
The scanning line 3a is electrically connected to the gate of the pixel switching TFT 30, and the scanning signals G1, G2,..., Gm are pulsed to the scanning line 3a at a predetermined timing. Thus, it is configured to apply the lines sequentially in this order. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing. Image signals S1, S2,..., Sn written in a liquid crystal as an example of an electro-optical material via the pixel electrode 9a are held for a certain period with the counter electrode 21 formed on the counter substrate. . The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied potential level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signal is emitted from the electro-optical device as a whole. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 a and the counter electrode 21. The storage capacitor 70 is formed between a high-concentration drain region 1e of a pixel switching TFT 30 to be described later and a constant potential capacitor line 300 via an insulating film 301 which is a dielectric film.
[0068]
On the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, the sampling circuit 118, and the like, a precharge signal having a predetermined voltage level is preceded by an image signal on a plurality of data lines 6a. In addition, a precharge circuit to be supplied, an inspection circuit for inspecting the quality, defects, and the like of the electro-optical device during manufacture or at the time of shipment may be formed.
[0069]
(First embodiment)
The configurations of the pixel unit and the peripheral circuit unit of the electro-optical device according to the first embodiment of the present invention will be described with reference to FIGS. 4 is a plan view of a plurality of adjacent pixel groups on the TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed, and FIG. 5 is a cross-sectional view taken along line AA ′ of FIG. FIG. 6 is a cross-sectional view of a CMOS TFT constituting peripheral circuits such as a scanning line driving circuit, a data line driving circuit, and a sampling circuit. In FIGS. 5 and 6, the scale of each layer and each member is different in order to make each layer and each member recognizable on the drawing.
[0070]
In FIG. 4, on the TFT array substrate of the electro-optical device, a plurality of transparent pixel electrodes 9a (outlined by dotted line portions 9a ′) are provided in a matrix, and the vertical and horizontal directions of the pixel electrodes 9a are provided. A data line 6a and a scanning line 3a are provided along each boundary.
[0071]
In addition, the scanning line 3a is disposed so as to face the channel region 1a ′ indicated by the hatched region in the lower right portion of the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode. As described above, the pixel switching TFT 30 in which the scanning line 3a is opposed to the channel region 1a ′ as a gate electrode is provided at each intersection of the scanning line 3a and the data line 6a.
[0072]
In the present embodiment, the capacitor line 300 is formed so as to overlap the formation region of the scanning line 3a as indicated by the bold line in the drawing. More specifically, the capacitor line 300 includes a main line portion extending along the scanning line 3a, a protruding portion protruding upward along the data line 6a from each portion intersecting the data line 6a in FIG. A portion corresponding to the hole 84 is provided with a constricted portion slightly constricted. The capacitor line 300 includes at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum), and Pb (lead). It consists of a single metal, an alloy, a metal silicide, polycide, or a laminate of these.
[0073]
As shown in FIGS. 4 and 5, the data line 6a relays through the relay layer 303, so that the semiconductor layer made of, for example, a polysilicon film through the contact hole 81 and the contact hole 82 plugged with a refractory metal or the like. 1a is electrically connected to the high concentration source region 1d. On the other hand, the pixel electrode 9a is connected to the semiconductor layer via the contact hole 83 and the contact hole 84 plugged with a refractory metal or the like by relaying using the capacitor electrode 302 made of the same film as the relay layer 303 as a relay layer. 1a is electrically connected to the high concentration drain region 1e.
[0074]
The semiconductor layer 1a may be made of, for example, a polysilicon film or an amorphous silicon film formed on a glass substrate or a silicon substrate as the TFT array substrate 10. The TFT array substrate 10 may be made of a silicon single crystal film grown on an insulating substrate such as a sapphire substrate. Alternatively, the TFT array substrate 10 may be composed of a single crystal silicon film left on the insulating substrate by bonding a single crystal silicon substrate on an insulating substrate such as a sapphire substrate and performing an annealing treatment, followed by separation. .
[0075]
By using the capacitor electrode 302 as a relay layer in this way, even if the interlayer distance between the pixel electrode 9a and the semiconductor layer 1a constituting the TFT 30 is as long as about 1000 nm, for example, they are connected by a single contact hole. While avoiding technical difficulties, the two serial contact holes 83 and 84 having a relatively small diameter can be connected to each other satisfactorily, and the pixel aperture ratio can be increased. In particular, the use of such a relay layer is useful for preventing etching through when a contact hole is opened. Similarly, by using the relay layer 303, even if the interlayer distance between the data line 6a and the semiconductor layer 1a constituting the TFT 30 is long, the technical difficulty of connecting the two with a single contact hole is avoided. However, the two series contact holes 81 and 82 having a relatively small diameter can be connected to each other satisfactorily. Such a capacitor electrode 302 and the relay layer 303 are made of a conductive polysilicon film. The film thickness of the capacitor electrode 302 and the relay layer 303 is, for example, about 50 to 500 nm.
[0076]
As shown in FIGS. 4 and 5, the capacitor electrode 302 and the capacitor line 300 are arranged to face each other via the dielectric film 301, so that the region overlaps the scanning line 3a and the data line 6a when viewed in plan. In the area, a storage capacitor 70-1 as an example of the storage capacitor 70 (see FIG. 3) is constructed.
[0077]
That is, the capacitor line 300 extends so as to cover the scanning line 3a, and has a protruding portion protruding so as to cover the capacitor electrode 302 below the region of the data line 6a. The capacitive electrode 302 extends from the intersection of the scanning line 3a and the data line 6a along one protruding portion of the capacitive line 300 below the area of the data line 6a, and the other is a capacitive line on the area of the scanning line 3a. An L-shaped island-shaped capacitive electrode extending along the line 300 to the vicinity of the adjacent data line 6a is formed. A storage capacitor 70-1 is formed in a region where the L-shaped capacitor electrode 302 overlaps the capacitor line 300 via the dielectric film 301.
[0078]
The capacitor electrode 302, which is one of the capacitor electrodes of the storage capacitor 70-1, is connected to the pixel electrode 9a through the contact hole 84 and is connected to the high-concentration drain region 1e through the contact hole 83, and is set to the pixel electrode potential. The
[0079]
The capacitor line 300 including the other capacitor electrode of the storage capacitor 70-1 extends from the image display region in which the pixel electrode 9a is disposed, and is electrically connected to a constant potential source to be a fixed potential. The The constant potential source is supplied to a scanning line driving circuit for supplying a scanning signal for driving the TFT 30 to the scanning line 3a and a data line driving circuit for controlling a sampling circuit for supplying an image signal to the data line 6a. A constant potential source such as a positive power source or a negative power source may be used, or a constant potential supplied to the counter substrate may be used.
[0080]
The dielectric film 301 of the storage capacitor 70-1 is made of, for example, a relatively thin HTO film (high temperature oxide film) having a film thickness of about 5 to 200 nm, a silicon oxide film such as an LTO film (low temperature oxide film), or a silicon nitride film. Composed. The dielectric film 301 may be a thermal oxide film obtained by oxidizing the surface of the capacitor electrode 302. From the viewpoint of increasing the storage capacitor 70-1, it is better that the dielectric film 301 is thinner as long as sufficient film thickness reliability is obtained.
[0081]
As shown in FIG. 5, the electro-optical device includes a transparent TFT array substrate 10 and a transparent counter substrate 20 disposed to face the TFT array substrate 10. The TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is made of an organic film such as a polyimide film.
[0082]
On the other hand, a counter electrode 21 is provided over the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. The counter electrode 21 is made of a transparent conductive film such as an ITO film. The alignment film 22 is made of an organic film such as a polyimide film.
[0083]
The TFT array substrate 10 is provided with a pixel switching TFT 30 that controls switching of each pixel electrode 9a at a position adjacent to each pixel electrode 9a.
[0084]
The counter substrate 20 may be further provided with a second light shielding film 23 as shown in FIG. By adopting such a configuration, it is possible to suppress incident light from entering the channel region 1a ′, the low concentration source region 1b, and the low concentration drain region 1c of the semiconductor layer 1a of the pixel switching TFT 30 from the counter substrate 20 side. Further, the second light-shielding film 23 functions to prevent a temperature increase of the electro-optical device by forming a surface irradiated with incident light with a highly reflective film.
[0085]
In the present embodiment, the light-shielding data line 6a made of an Al film or the like may shield a portion along the data line 6a in the light-shielding region of each pixel, or the capacitor line 300 may be shielded from the light-shielding film. As a result, the light can be shielded under the data line 6a excluding the region where the contact holes 81 and 82 are formed.
[0086]
As an example of an electro-optical material, the space between the TFT array substrate 10 and the counter substrate 20, which are configured in this manner and arranged so that the pixel electrode 9 a and the counter electrode 21 face each other, is surrounded by a sealing material. A certain liquid crystal is enclosed, and the liquid crystal layer 50 is formed. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed.
[0087]
Further, a base insulating film 12 is provided under the pixel switching TFT 30. The base insulating film 12 is formed on the entire surface of the TFT array substrate 10, thereby preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughness during polishing of the surface of the TFT array substrate 10 or dirt remaining after cleaning. Have If the TFT array substrate 10 is a silicon substrate and the semiconductor layer 1a is SOI, the base insulating film 12 becomes a buried oxide film.
[0088]
In FIG. 5, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a, a channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, and scanning. Insulating film 2 including a gate insulating film that insulates line 3a from semiconductor layer 1a, data line 6a, low concentration source region 1b and low concentration drain region 1c of semiconductor layer 1a, high concentration source region 1d of semiconductor layer 1a and high concentration A concentration drain region 1e is provided. A corresponding one of the plurality of pixel electrodes 9 a is relay-connected to the high-concentration drain region 1 e by a capacitor electrode 302 through contact holes 83 and 84. Further, a contact hole 82 passing through the high-concentration source region 1d and the relay layer 303 and a contact hole 83 passing through the high-concentration drain region 1e and the capacitor electrode 302 are respectively formed on the scanning line 3a. A film 311 is formed.
[0089]
A second interlayer insulating film 312 is formed on the capacitor line 300. The contact hole 81 passes through the relay layer 303 and the data line 6a, and the contact hole 84 passes through the capacitor electrode 302 and the pixel electrode 9a. .
[0090]
A data line 6 a is formed on the second interlayer insulating film 312, and a third interlayer insulating film 7 in which a contact hole 84 to the capacitor electrode 302 is further formed is formed thereon. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 thus configured.
[0091]
Next, as shown in FIG. 6, the CMOS TFT in the peripheral circuit portion is configured by stacking a TFT 131 and a TFT 141 each having an LDD structure. Such TFT 131 and TFT 141 constitute a part of, for example, a shift register, a DAC, an inverter, and a level shifter in peripheral circuits such as a scanning line driving circuit, a data line driving circuit, and a sampling circuit.
[0092]
More specifically, the TFT 131 is the same as the semiconductor layer 132 made of the same film as the semiconductor layer 1a in the pixel portion, the gate insulating film 133 made of the same film as the insulating film 2 in the pixel portion, and the scanning line 3a in the pixel portion. The gate electrode 134 is made of a film and connected to, for example, an input wiring.
[0093]
On the other hand, the TFT 141 includes a semiconductor layer 142 based on the same film as the capacitor electrode 302 in the pixel portion, a gate insulating film 143 made of the same film as the insulating film 301 in the pixel portion, and the same film as the capacitor line 300 in the pixel portion. And a gate electrode 144 connected to, for example, an input wiring.
[0094]
The TFT 141 extends from the semiconductor layer 142 and is connected to, for example, a wiring 147 that is an output wiring. The TFT 131 is opened through a contact hole 135 that is opened in the first interlayer insulating film 311 and is metal-plugged. Similarly, it is connected to the wiring 147.
[0095]
The TFT 141 is made of the same film as the data line 6a in the pixel portion and is connected to, for example, a high-potential wiring 146 through a contact hole 145 opened in the second interlayer insulating film 312. The TFT 131 is formed of the same film as the data line 6a in the pixel portion through the contact hole 136 opened in the first interlayer insulating film 311 and metal-plugged and the contact hole 137 opened in the second interlayer insulating film 312. In addition, for example, it is connected to a wiring 138 which is a low potential wiring.
[0096]
As described above, in the first embodiment, the TFT 131 as an example of the first electronic element constituting the peripheral circuit is configured based on the same film as the TFT 30 in the pixel portion, and an example of the second electronic element constituting the peripheral circuit. The TFT 141 is configured based on the same film as the storage capacitor 70-1 in the pixel portion. Therefore, the number of semiconductor layers, insulating films, and conductive layers required for the entire device can be reduced. In addition, since the TFT and the storage capacitor can be simultaneously formed in the image display region and the peripheral region, the laminated structure on the substrate and the manufacturing process can be simplified.
[0097]
In addition, since the TFT 30 and the storage capacitor 70-1 are stacked in the pixel portion, the area for forming these electronic elements can be reduced by a three-dimensional arrangement, so that a sufficient storage capacitor can be provided. The pixel aperture ratio can be increased while ensuring. On the other hand, since the TFT 131 and the TFT 141 are laminated in the peripheral region, an area for forming these electronic elements can be reduced, and the peripheral region occupying a limited region on the substrate can be narrowed. . Then, the circuit pitch of the electronic elements in the peripheral circuit can be miniaturized corresponding to the miniaturization of the pixel pitch.
[0098]
The thin film transistor constituting at least one of the first electronic element and the second electronic element may be a polysilicon thin film transistor, an SOI thin film transistor, or a thin film transistor on a silicon substrate. Furthermore, a top gate type, a bottom gate type, an n channel type, or a p channel type may be used.
[0099]
Further, instead of one or both of the TFT 131 and the TFT 141 constituting the peripheral circuit, other electrons such as a capacitor, a thin film diode, and a resistor are at least partially based on the same film as the TFT 30 and the storage capacitor 70-1 in the pixel portion. It is also possible to form elements.
[0100]
In this embodiment, although omitted, the lower light-shielding film including a portion covering the TFT 30 from the TFT array substrate 10 side (lower side in FIG. 5) is striped along the scanning line 3a or the scanning line 3a. Alternatively, it may be formed in a matrix along the data line 6a. Such a lower-layer light-shielding film shields the return light from the back surface of the TFT array substrate and the projection optical system, and is effective in changing the characteristics of the TFT 30 due to the leakage current when the TFT 30 is turned off by light excitation based on this light. To prevent. Such a lower light shielding layer is made of, for example, a single metal, an alloy, a metal silicide, or a polysilicon film containing at least one of refractory metals such as Ti, Cr, W, Ta, Mo, and Pb. In particular, when a single optical system is configured by combining a plurality of electro-optical devices via a prism or the like in a multi-plate type color display projector or the like, projection light that penetrates the prism or the like from another electro-optical device Since the return light composed of the portion is strong, it is very effective to provide the lower light-shielding film on the lower side of the TFT 30 in this way. Such a lower-layer light-shielding film is also preferably extended from the image display region to the periphery thereof and connected to a constant potential source, similarly to the capacitor line 300. Further, such a lower light shielding film may be formed below the TFT 131 in the peripheral circuit portion.
[0101]
In the embodiment described above, by stacking a large number of conductive layers, steps are generated in regions along the data lines 6a and the scanning lines 3a. However, the TFT array substrate 10, the base insulating film 12, and the first interlayer insulating film 311 are formed. The planarization process may be performed by digging a groove in the second interlayer insulating film 312 and embedding the wiring such as the data line 6a or the TFT 30 or the like, or the third interlayer insulating film 7 or the second interlayer insulating film 312 The planarization process may be performed by polishing a step on the upper surface by a CMP (Chemical Mechanical Polishing) process or the like, or by flattening using an organic SOG.
[0102]
Further, in the embodiment described above, the pixel switching TFT 30 preferably has an LDD structure as shown in FIG. 5, but has an offset structure that does not implant impurities into the low concentration source region 1b and the low concentration drain region 1c. Alternatively, it may be a self-aligned TFT in which a high concentration source and drain regions are formed in a self-aligned manner by implanting impurities at a high concentration using a gate electrode formed of a part of the scanning line 3a as a mask. In this embodiment, only one gate electrode of the pixel switching TFT 30 is arranged between the high concentration source region 1d and the high concentration drain region 1e. However, two or more gate electrodes are provided between these gate electrodes. You may arrange. If the TFT is configured with dual gates or triple gates or more in this way, leakage current at the junction between the channel and the source and drain regions can be prevented, and the off-time current can be reduced. The TFT 131 formed based on the same film as the TFT 30 and constituting the peripheral circuit can be similarly constructed as various TFTs, and the TFT 141 can be constructed as various TFTs.
[0103]
(Manufacturing method of the first embodiment)
Next, regarding the manufacturing method of the electro-optical device according to the first embodiment having the above-described configuration, particularly on the TFT array substrate 10 side, the TFT 30 and the storage capacitor 70-1 in the pixel portion and the TFT 131 and the TFT 141 in the peripheral circuit portion are arranged in parallel. With reference to FIG. 7 corresponds to FIG. 5 related to the pixel portion and FIG. 6 related to the peripheral circuit portion in each layer on the TFT array substrate 10 side in the process of forming these electronic elements in the manufacturing process of the first embodiment. It is process drawing shown in the cross section to do.
[0104]
First, in step (1) of FIG. 7, in the pixel portion, a TFT array substrate 10 such as a quartz substrate, hard glass, or silicon substrate is prepared, and predetermined patterns are formed thereon by sputtering, vapor deposition, photolithography, etching, or the like. The semiconductor layer 1a, the scanning line 3a, the capacitor electrode 302, and the relay layer 303 are sequentially formed, and the base insulating film 12, the insulating film 2, the first interlayer insulating film 311, and the insulating film 301 are sequentially formed therebetween. At the same time, in the peripheral circuit portion, the semiconductor layer 132 is formed from the same film as the semiconductor layer 1a, the gate electrode 134 is formed from the same film as the scanning line 3a, and the semiconductor layer 142 is formed based on the same film as the capacitor electrode 302. In addition, the base insulating film 12, the insulating film 133, the first interlayer insulating film 311 and the insulating film 143 are sequentially formed therebetween.
[0105]
More specifically, for the semiconductor layer 1a and the semiconductor layer 132, for example, a monosilane gas or a disilane gas having a flow rate of about 400 to 600 cc / min is used in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C. An amorphous silicon film is formed by low pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa), and heat treatment is performed at about 600 to 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours in a nitrogen atmosphere. The solid phase growth of the polysilicon film to a particle size of about 50 to 200 nm, preferably about 100 nm is performed, followed by patterning.
[0106]
As for the insulating film 2 of the TFT 30 and the insulating film 133 of the TFT 131, for example, the semiconductor layer is thermally oxidized at a temperature of about 700 to 1300 ° C., preferably about 1000 ° C., to form a lower gate insulating film, and then the low pressure CVD. An HTO film or a silicon oxide film is formed by a method or the like. Thus, the insulating film 2 and the insulating film 133 made of a multilayer high-temperature silicon oxide film (HTO film) or a silicon nitride film are formed. As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating film 2 has a thickness of about 20 to 150 nm, preferably about 30. The thickness is ˜100 nm.
[0107]
For the scanning line 3a and the gate electrode 134, for example, a polysilicon film is deposited by a low pressure CVD method or the like, and phosphorous (P) is thermally diffused. The film thickness is about 100 to 500 nm, preferably about 350 nm.
[0108]
For the semiconductor layer 1a, after forming the scanning line 3a and the gate electrode 134 to construct the LDD structure, the lightly doped source region 1b and the lightly doped drain region 1c, and the heavily doped source region 1d and the heavily doped drain region 1e are formed. In contrast, a predetermined amount of P ions or the like is doped according to the specifications of the TFT 30. The semiconductor layer 132 is similarly doped to construct an LDD structure.
[0109]
In this case, in particular, it is preferable to manufacture the semiconductor layer 1a and the semiconductor layer 131 as thin-film transistors having the same polarity, that is, both p-channel or n-channel thin-film transistors in order to simplify the manufacturing process.
[0110]
For the base insulating film 12 and the first interlayer insulating film 311, for example, TEOS (tetra-ethyl ortho-silicate) gas, TEB (tetra-ethyl boat rate) by atmospheric pressure, low pressure CVD method, plasma CVD method, etc. Using gas, TMOP (tetramethyloxyphosphate) gas, etc., NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron silicate glass) (Phosphorus / silicate / glass) or a single-layer silicate glass film, a silicon nitride film, a silicon oxide film, or the like. Each of these film thicknesses is, for example, about 500 to 2000 nm.
[0111]
After the first interlayer insulating film 311 is formed, contact holes 82 and 83 and contact holes 135 and 136 are opened by dry etching such as reactive ion etching and reactive ion beam etching, and refractory metal is formed. Form a plug.
[0112]
The capacitor electrode 302, the relay layer 303, and the semiconductor layer 142 are formed by depositing a polysilicon film by, for example, a low pressure CVD method and then patterning. These film thicknesses are about 50 to 500 nm, preferably about 150 nm.
[0113]
As for the insulating film 301 and the insulating film 143, for example, a high-temperature silicon oxide film (HTO film) or a silicon nitride film is deposited to a relatively thin thickness of about 50 nm by a low pressure CVD method, a plasma CVD method, or the like. Alternatively, it may be formed in the same manner as the insulating film 2 described above.
[0114]
Next, in step (2) of FIG. 7, while masking the semiconductor layer 142 in the peripheral circuit portion with the mask 900, the capacitor electrode 302 and the relay layer 303 in the pixel portion are formed by ion implantation or ion doping in the direction indicated by the arrow. Make it conductive.
[0115]
Next, in step (3) of FIG. 7, the capacitor line 300 in the pixel portion and the gate electrode 144 in the peripheral circuit portion are formed simultaneously. These include, for example, a conductive polysilicon film formed by sputtering Ti, Cr, W, Ta, Mo, Pb or the like to form a metal film having a thickness of about 100 to 500 nm, or by CVD, ion doping, or the like. After forming the film, or after forming a film in which the polysilicon film and the metal film are stacked, patterning is performed.
[0116]
Next, in step (4) of FIG. 7, the semiconductor layer 142 in the peripheral circuit portion is first subjected to low concentration ion implantation or ion doping in a self-aligning manner using the gate electrode 144 as a mask to reduce the semiconductor layer 142 to a low level. A concentration source region and a low concentration drain region are formed. Thereafter, a high concentration source region and a high concentration drain region are formed in the semiconductor layer 142 by ion implantation or ion doping in a direction indicated by an arrow while masking the low concentration region and the gate electrode 144 with a mask 901. As a result, the TFT 141 having the LDD structure is constructed in the peripheral circuit portion. In parallel with the manufacturing process of the TFT 141, in the pixel portion, the storage capacitor 70-1 and the like are masked by the mask 901, and each film constituting the storage capacitor 70-1 by ion implantation or ion doping in the direction indicated by the arrow. The resistance value at is not changed. However, in the pixel portion, a predetermined resistance value in each film constituting the storage capacitor 70-1 is obtained by performing ion implantation or ion doping in the direction indicated by the arrow without masking with the mask 901. It is also possible to manufacture.
[0117]
Thereafter, a second interlayer insulating film 312 made of a silicon oxide film or the like is formed by a normal pressure or low pressure CVD method or the like, and a data line 6a having a predetermined pattern is formed by sputtering, photolithography, etching, or the like. A third interlayer insulating film 7 made of a silicon oxide film or the like is formed by CVD or the like (see FIGS. 5 and 6). Then, a pixel electrode 9 a made of a transparent conductive film such as an ITO film is formed on the third interlayer insulating film 7 by sputtering, photolithography, etching, or the like. When the liquid crystal device is used for a reflective liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al. Subsequently, after applying a polyimide-based alignment film coating solution on the pixel electrode 9a, the alignment film 16 is formed by performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle.
[0118]
As a result, the TFT array substrate 10 side of the electro-optical device of the first embodiment is manufactured.
[0119]
According to the present embodiment, in particular, in the steps (2) to (4) of FIG. 7, the same polysilicon film is selectively subjected to ion implantation or ion doping. Simultaneously with the formation of the electrode 302, the semiconductor layer 143 can be formed in the peripheral circuit portion.
[0120]
As described above, the manufacturing method of the present embodiment is very advantageous in simplifying the manufacturing process, and based on the same film, it is finally used as a film having different electrical properties. It is also possible to reduce the number of layers in the stacked structure on the substrate.
[0121]
(Second Embodiment)
Next, a second embodiment of the electro-optical device of the invention will be described with reference to FIGS. FIG. 8 is a plan view of a pixel of the TFT array substrate on which data lines, scanning lines, pixel electrodes, etc. are formed, and FIG. 9 is a schematic diagram showing a connection relationship and a stacked state of each layer in FIG. It is sectional drawing. FIG. 10 is a schematic cross-sectional view showing the connection relationship and the stacked state of each layer in a CMOS type TFT constituting a part of the peripheral circuit. In FIGS. 9 and 10, the scale of each layer and each member is reduced in order to make each layer and each member recognizable on the drawing and to facilitate understanding of the connection relationship and the laminated state by contact holes. In addition, the relative planar arrangement is appropriately changed. 9 and 10, the same reference numerals are given to the same components as those in FIGS. 5 and 6 according to the first embodiment, and the description thereof is omitted.
[0122]
As shown in FIGS. 8 and 9, in the second embodiment, compared to the first embodiment, instead of the storage capacitor 70-1 being constructed on the upper side of the TFT 30, the capacitive electrode is provided on the lower side of the TFT 30. 502, a storage capacitor 70-2 composed of an insulating film 501 functioning as a dielectric film and a capacitor electrode 11a is generally different. More specifically, in the second embodiment, the data line 6a is formed on the interlayer insulating film 511, and is connected to the high concentration source region 1d of the TFT 30 through the contact hole 551 opened therein. Yes. The storage capacitor 70-2 is connected to the relay layer 510 through a contact hole 555 opened in the first interlayer insulating film 12, and the high-concentration drain region 1e of the TFT 30 is opened in the insulating film 2. It is connected to the relay layer 510 through a contact hole 554. The pixel electrode 9 a is connected to the relay layer 510 through a contact hole 553 opened in the interlayer insulating film 7 and the interlayer insulating film 511.
[0123]
The capacitor electrode 11a extends, for example, to the outside of the image display area and is connected to a constant potential line or the like in the peripheral circuit, and is set to a fixed potential. That is, the capacitor electrode 11a is a fixed potential side capacitor electrode in the storage capacitor 70-2. On the other hand, the capacitor electrode 502 is connected to the pixel electrode 9a through the contact hole 555, and has a pixel potential. That is, the capacitor electrode 502 is a pixel potential side capacitor electrode in the storage capacitor 70-2.
[0124]
The capacitor electrode 11a may be composed of a light shielding film. By doing so, it is possible to effectively prevent the return light from the TFT array substrate 10 side from entering the channel region of the TFT 30.
[0125]
On the other hand, as shown in FIG. 10, in the peripheral circuit, a CMOS type TFT composed of TFT 151 and TFT 161 is constructed. More specifically, the TFT 151 includes a semiconductor layer 152 formed based on the same film as the capacitor electrode 502 in the pixel portion, an insulating film 501 functioning as a gate insulating film, and the same film as the capacitor electrode 11a in the pixel portion. Gate electrode 154. The TFT 161 includes a semiconductor layer 162 formed based on the same film as the semiconductor layer 1a in the pixel portion, an insulating film 2 functioning as a gate insulating film, and a gate electrode 164 made of the same film as the scanning line 3a in the pixel portion. It is configured. The TFT 161 is connected to a wiring 167, which is an output wiring, for example, formed from the same film as the data line 6a in the pixel portion through a contact hole 165 on the drain side. The TFT 151 is connected to the wiring 167 via a contact hole 155 and a contact hole 166 plugged with metal or the like on the drain side. The TFT 161 is connected to a wiring 169 which is a high potential wiring, for example, formed from the same film as the data line 6a in the pixel portion through a contact hole 168 on the source side. The TFT 151 is connected to a wiring 158 that is formed of the same film as the data line 6a in the pixel portion, for example, a low potential wiring through a contact hole 156 and a contact hole 157 plugged with metal or the like on the source side. ing.
[0126]
Therefore, according to the second embodiment, the TFT 161 as an example of the first electronic element constituting the peripheral circuit is configured based on the same film as the TFT 30 in the pixel portion, and the second electronic element constituting the peripheral circuit An example TFT 151 is configured based on the same film as the storage capacitor 70-2 in the pixel portion. Therefore, the number of semiconductor layers, insulating films, and conductive layers required for the entire device can be reduced. In addition, since the TFT and the storage capacitor can be simultaneously formed in the image display region and the peripheral region, the laminated structure on the substrate and the manufacturing process can be simplified.
[0127]
In addition, since the TFT 30 and the storage capacitor 70-2 are stacked in the pixel portion, a three-dimensional arrangement requires a small area for manufacturing these electronic elements, and ensures a sufficient storage capacitor. In addition, the pixel aperture ratio can be increased. On the other hand, since the TFT 151 and the TFT 161 are stacked in the peripheral region, an area for forming these electronic elements is small, and the peripheral region occupying a limited region on the substrate can be narrowed. Then, the circuit pitch of the electronic elements in the peripheral circuit can be miniaturized corresponding to the miniaturization of the pixel pitch.
[0128]
Further, in this embodiment, in particular, the TFT 151 and the TFT 161 are phase-connected via the wiring 167 stacked on the upper side of the upper TFT 161, and therefore in the manufacturing process, compared with the case of the first embodiment. The step of opening a contact hole and plugging it under the semiconductor layer of the upper TFT can be omitted. Therefore, a configuration in which both TFTs are electrically connected with high reliability and relatively easily can be obtained in the peripheral circuit.
[0129]
(Third embodiment)
Next, a third embodiment of the electro-optical device of the invention will be described with reference to FIGS. FIG. 11 is a schematic cross-sectional view showing the connection relationship and the lamination state of each layer. FIG. 12 is a schematic cross-sectional view showing a connection relationship and a stacked state of each layer in a CMOS type TFT constituting a part of the peripheral circuit. In FIGS. 11 and 12, the scale of each layer and each member is reduced in order to make each layer and each member recognizable on the drawing and to facilitate understanding of the connection relationship and the stacked state by contact holes. In addition, the relative planar arrangement is appropriately changed. In FIGS. 11 and 12, the same components as those in FIGS. 5 and 6 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
[0130]
As shown in FIG. 11, in the third embodiment, compared to the first embodiment, the interlayer insulating film 311 is divided into two interlayer insulating films 311a and 311b, and the pixel portion drops to a constant potential during this period. The conductive film 650 is disposed, and the peripheral circuit portion is different in that a conductive film 660 dropped to a constant potential is disposed therebetween.
[0131]
Therefore, according to the third embodiment, in particular, in the pixel portion, it is possible to effectively prevent the potential fluctuation of the capacitor electrode 302 from adversely affecting the TFT 30 by electromagnetically shielding the conductive film 650. In the peripheral circuit portion, it is possible to effectively prevent the potential fluctuation between the TFT 174 and the TFT 184 from adversely affecting each other by electromagnetically shielding the conductive film 660.
[0132]
In addition, the conductive films 650 and 660 may be formed of a light shielding film having conductivity such as a refractory metal. Thereby, it can comprise so that it may have both functions as an electromagnetic shield and a built-in light shielding film.
[0133]
In the first to third embodiments described above, two electronic elements are stacked in each of the pixel portion and the peripheral circuit portion. However, three or more electronic elements may be stacked in the pixel portion and the peripheral circuit portion. Good. Furthermore, although the example in which the TFT and the storage capacitor are stacked in the pixel portion has been described, two TFTs may be stacked in the pixel portion. For example, a CMOS type TFT may be provided in each pixel.
[0134]
In each of the embodiments described above with reference to FIGS. 1 to 12, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, on a TAB (Tape Automated Bonding) substrate. The mounted LSI for driving may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. Further, for example, a TN (Twisted Nematic) mode, a VA (Vertically Aligned) mode, and a PDLC (Polymer Dispersed Liquid Crystal) are respectively provided on the side on which the projection light of the counter substrate 20 enters and the side on which the outgoing light of the TFT array substrate 10 exits. ) Mode or the like, or a normally white mode / normally black mode, a polarizing film, a retardation film, a polarizing plate and the like are arranged in a predetermined direction.
[0135]
Since the electro-optical device in each embodiment described above is applied to a projector, three electro-optical devices are respectively used as RGB light valves, and each light valve has a dichroic mirror for RGB color separation. The light of each color resolved through the light enters as projection light. Therefore, in each embodiment, the counter substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the counter substrate 20 together with the protective film in a predetermined region facing the pixel electrode 9a where the second light shielding film 23 is not formed. In this way, the electro-optical device in each embodiment can be applied to a direct-view type or reflective type color electro-optical device other than the projector. Further, a microlens may be formed on the counter substrate 20 so as to correspond to one pixel. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrodes 9 a facing RGB on the TFT array substrate 10. In this way, a bright electro-optical device can be realized by improving the collection efficiency of incident light. Furthermore, a dichroic filter that creates RGB colors using light interference may be formed by depositing multiple layers of interference layers having different refractive indexes on the counter substrate 20. According to this counter substrate with a dichroic filter, a brighter color electro-optical device can be realized.
[0136]
(Embodiment of electronic device)
Next, an embodiment of a projection color display device as an example of an electronic apparatus using the liquid crystal device described in detail above as a light valve will be described with reference to FIGS.
[0137]
First, the circuit configuration of the projection type color display device of this embodiment will be described with reference to the block diagram of FIG. FIG. 13 shows a circuit configuration relating to one of the three light valves in the projection type color display device. Since all of these three light valves have basically the same configuration, only a part related to the circuit configuration will be described here. Strictly speaking, however, the input signals of the three light valves are different (that is, driven by signals for R, G, and B, respectively). Compared with the case of B and B, the order of the image signals is reversed within each field or frame so that the image is reversed and displayed, or the horizontal or vertical scanning direction is reversed.
[0138]
In FIG. 13, the projection color display device includes a display information output source 1000, a display information processing circuit 1002, a drive circuit 1004, a liquid crystal device 100, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs an image signal, and the like. Based on this, display information such as an image signal in a predetermined format is output to the display information processing circuit 1002. The display information processing circuit 1002 is configured to include various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and a display input based on a clock signal. A digital signal is sequentially generated from the information and is output to the drive circuit 1004 together with the clock signal CLK. The drive circuit 1004 drives the liquid crystal device 100. The power supply circuit 1010 supplies predetermined power to the above-described circuits. Note that the drive circuit 1004 may be mounted on the TFT array substrate constituting the liquid crystal device 100, and in addition to this, the display information processing circuit 1002 may be mounted.
[0139]
Next, with reference to FIG. 14, the overall configuration, particularly the optical configuration, of the projection type color display device of the present embodiment will be described. FIG. 14 is a schematic cross-sectional view of the projection type color display device.
[0140]
In FIG. 14, a liquid crystal projector 1100 as an example of a projection type color display device according to the present embodiment prepares three liquid crystal modules including the liquid crystal device 100 in which the drive circuit 1004 described above is mounted on a TFT array substrate. It is configured as a projector used as the light valve 100R, 100G, and 100B for use. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, light components R, G, and R corresponding to the three primary colors of RGB are obtained by three mirrors 1106 and two dichroic mirrors 1108. B is divided into the light valves 100R, 100G and 100B corresponding to the respective colors. At this time, in particular, the B light is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are synthesized again by the dichroic prism 1112 and then projected as a color image on the screen 1120 via the projection lens 1114.
[0141]
The present invention is not limited to each of the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. An optical device and a manufacturing method thereof are also included in the technical scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a plan view of a TFT array substrate in an electro-optical device according to an embodiment of the present invention, viewed from the side of a counter substrate together with each component formed thereon.
FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.
FIG. 3 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of matrix pixels that form an image display region in the electro-optical device according to the embodiment of the invention.
4 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed in the electro-optical device according to the first embodiment. FIG.
5 is a cross-sectional view taken along line AA ′ of FIG.
FIG. 6 is a schematic cross-sectional view of a CMOS TFT in the peripheral circuit portion of the first embodiment.
FIG. 7 is a process diagram showing the manufacturing process of the first embodiment.
FIG. 8 is a plan view of a pixel of a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed in an electro-optical device according to a second embodiment of the invention.
9 is a schematic cross-sectional view showing a connection relation and a laminated state of each layer in FIG. 8. FIG.
FIG. 10 is a schematic cross-sectional view of a CMOS type TFT in the peripheral circuit portion of the second embodiment.
FIG. 11 is a schematic cross-sectional view illustrating a connection relationship and a stacked state of layers in an electro-optical device according to a third embodiment of the invention.
FIG. 12 is a schematic cross-sectional view of a CMOS type TFT in the peripheral circuit portion of the third embodiment.
FIG. 13 is a block diagram showing a circuit configuration relating to a light valve in a projection type color display device which is an embodiment of the electronic apparatus of the invention.
FIG. 14 is a schematic cross-sectional view showing a color liquid crystal projector as an example of a projection type color display device which is an embodiment of the electronic apparatus of the invention.
[Explanation of symbols]
1a ... Semiconductor layer
1a '... channel region
1b ... low concentration source region
1c: low concentration drain region
1d ... High concentration source region
1e ... High concentration drain region
2… Insulating thin film
3a ... scan line
6a ... Data line
9a: Pixel electrode
10 ... TFT array substrate
12 ... Underlying insulating film
16 ... Alignment film
20 ... Counter substrate
21 ... Counter electrode
22 ... Alignment film
23. Second light shielding film
30 ... TFT
50 ... Liquid crystal layer
70 ... Storage capacity
70-1 to 70-2 ... Storage capacity
81, 82, 83, 84 ... contact holes
300 ... capacity line
301: Insulating film
302 ... Capacitance electrode
131, 141, 151, 161, 171, 181 ... TFT

Claims (5)

In the image display area on the substrate, wirings arranged in a matrix, transistors and pixel electrodes arranged corresponding to intersections of the wirings, and provided corresponding to the pixel electrodes and with respect to the transistors Storage capacity formed in layers,
A first electronic element including a portion formed based on the same film as at least one of a semiconductor film and an insulating film constituting the transistor in a peripheral region on the substrate, and stacked on the first electronic element And a second electronic element including a portion formed on the basis of the same film as at least one of the conductive film and the insulating film constituting the storage capacitor, and through the wiring and the transistor, A peripheral circuit for controlling the pixel electrode is provided.
An electro-optical device, wherein a conductive film having a fixed potential is further laminated at a lamination position between the first electronic element and the second electronic element. The electro-optical device according to claim 1, further comprising another transistor stacked on the transistor instead of or in addition to the storage capacitor in the image display region. An electro-optical device manufacturing method for manufacturing the electro-optical device according to claim 1,
Performing the step of forming the first electronic element in the peripheral region in parallel with the step of forming the transistor in the image display region;
A method of manufacturing an electro-optical device, comprising performing a step of forming the second electronic element in the peripheral region in parallel with the step of forming the storage capacitor in the image display region. The same film is made of a polysilicon film, and the polysilicon film in the masked region is implanted by implanting impurities into the polysilicon film while masking either the image display region or the peripheral region. 4. The method of manufacturing an electro-optical device according to claim 3, further comprising a step of using the polysilicon film in a region not masked while being maintained as a semiconductor film as a conductive film. A light valve comprising the electro-optical device according to claim 1 or 2,
A light source for projecting light onto the light valve;
An optical display system for projecting projection light emitted from the light valve.

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