JP4872197B2 - Thin film transistor panel and manufacturing method thereof - Google Patents

Description

  The present invention relates to a thin film transistor panel and a method for manufacturing the same, and more particularly to a thin film transistor panel including a polysilicon thin film transistor and an amorphous silicon thin film transistor and a method for manufacturing the same.

  In the image reading apparatus, for example, a plurality of photosensors are arranged in an image reading area in a substantially central portion on a glass substrate, and a semiconductor chip for driving the photosensors is arranged outside the image reading area on the glass substrate. (For example, refer to Patent Document 1).

  However, in such an image reading device, since the semiconductor chip arranged outside the image reading region protrudes upward, for example, when used as a fingerprint reading device, a finger as a subject touches the semiconductor chip. If contact is made, the finger cannot be brought into close contact with the image reading area as expected, and an appropriate fingerprint reading operation is not performed, which causes a malfunction such as a malfunction.

  Therefore, in order to avoid such a problem due to the upward protrusion of the semiconductor chip, it may be possible to adopt a configuration in which the semiconductor chip is arranged at a position somewhat away from the image reading area. Is not preferable when the entire apparatus becomes large and is considered to be mounted on a portable device or the like.

  On the other hand, in an active matrix type liquid crystal display device, for example, an amorphous silicon thin film is formed on a glass substrate, and only the polysilicon thin film transistor forming region is selectively crystallized to selectively form a polysilicon thin film. There is one in which an amorphous silicon thin film transistor is formed in an amorphous silicon thin film formation region and a polysilicon thin film transistor is formed in a polysilicon thin film formation region (see, for example, Patent Document 2).

  In such a liquid crystal display device, an amorphous silicon thin film transistor is formed as a switching element in an image display region in a substantially central portion on the glass substrate, and the amorphous silicon thin film transistor is driven outside the image display region on the glass substrate. When a polysilicon thin film transistor is formed as a drive circuit section for the purpose, the uppermost surface becomes substantially flat. Therefore, when such a structure is adopted in the fingerprint reading apparatus, it is not necessary to separate the drive circuit unit from the image reading area more than necessary, and the entire apparatus can be downsized.

JP-A-8-8414 (FIG. 3) Japanese Patent Publication No. 5-9794

  However, in the liquid crystal display device described in Patent Document 2, only the polysilicon thin film transistor formation region (drive circuit portion formation region) is selectively crystallized out of the amorphous silicon thin film formed on the glass substrate. Therefore, a step of partially forming a polysilicon thin film is required.

  For this reason, when crystallization of an amorphous silicon thin film is performed by laser irradiation, for example, it is necessary to control the laser irradiation position with high accuracy and to selectively crystallize the amorphous silicon thin film by scanning a thin laser beam. As a result, it is necessary to increase the precision of the manufacturing apparatus, and it takes a relatively long time for the crystallization process, resulting in an increase in manufacturing cost.

  In addition, since the amorphous silicon thin film is crystallized by heating the amorphous silicon thin film to about 600 ° C., it is difficult to clearly separate the crystallized region from the non-crystallized region. There has been a problem that it is difficult to dispose the image display region made of the amorphous silicon thin film transistor and the drive circuit portion made of the polysilicon thin film transistor sufficiently close to each other on the substrate, and there is a limit to downsizing of the entire device.

  Accordingly, an object of the present invention is to provide a thin film transistor panel and a method for manufacturing the same that can reduce the manufacturing cost and can further reduce the size of the entire apparatus.

In order to achieve the above object, the present invention provides a polysilicon thin film transistor having a semiconductor thin film made of polysilicon and a plurality of electrodes on a substrate, and an amorphous silicon thin film transistor having a semiconductor thin film made of amorphous silicon and a plurality of electrodes. In the thin film transistor panel provided, the first wiring connected to any of the plurality of electrodes of the polysilicon thin film transistor, provided in the same layer with the same conductive material as the electrode, and having a connection pad; A semiconductor thin film made of amorphous silicon provided on a first wiring via an insulating film, and opposed to the first wiring via an insulating film, the same as any of the plurality of electrodes of the amorphous silicon thin film transistor Conductive material, provided in the same layer, before the insulating film Via a contact hole provided in a portion corresponding to the connection pads of the first wiring, a second wiring that is electrically connected to the first wiring, any of the plurality of electrodes of the amorphous silicon thin film transistor Are connected to each other and provided in the same layer with the same conductive material as the electrode, and a third wiring having a connection pad, and an insulating film above the third wiring, the amorphous silicon thin film transistor The same conductive material as any of the plurality of electrodes, provided in the same layer, and through the contact hole provided at a position corresponding to the connection pad of the third wiring of the insulating film, And a fourth wiring electrically connected to the wiring .

  According to this invention, since the semiconductor thin film of the amorphous silicon thin film transistor is provided on the upper layer side of the semiconductor thin film of the polysilicon thin film transistor, the semiconductor thin film of the amorphous silicon thin film transistor is formed on the upper layer after the semiconductor thin film of the polysilicon thin film transistor is formed. Therefore, the entire amorphous silicon thin film formed may be crystallized to form a polysilicon thin film. As in the prior art, a specific region of the formed amorphous silicon thin film is selected. Therefore, a process for crystallization is unnecessary, the process can be simplified, and the manufacturing cost can be reduced.

  In addition, since the semiconductor thin film of the amorphous silicon thin film transistor is provided on the upper layer side of the semiconductor thin film of the polysilicon thin film transistor, the polysilicon thin film transistor and the amorphous silicon thin film transistor are separately formed in different layers. Can be arranged close enough to each other, and further downsizing of the entire apparatus can be achieved.

  Furthermore, it is connected to one of the plurality of electrodes of the polysilicon thin film transistor and the plurality of electrodes of the amorphous silicon thin film transistor, and is electrically connected through the contact hole to connect the electrodes of the polysilicon thin film transistor and the amorphous silicon thin film transistor to each other. And forming each wiring simultaneously with the electrodes by the same conductor layer as any of the plurality of electrodes of the polysilicon thin film transistor and the amorphous silicon thin film transistor. There is no need to form it, and the manufacturing process can be simplified and the manufacturing cost can be reduced.

(First embodiment)
FIG. 1 shows an equivalent circuit plan view of a main part of a thin film transistor panel constituting an image reading apparatus as a first embodiment of the present invention. The thin film transistor panel includes a glass substrate 1. A plurality of photoelectric conversion type thin film transistors 3 as photosensors are arranged in a matrix in the image reading region 2 in the substantially central portion on the glass substrate 1.

  On the glass substrate 1, first to third drive circuit units 4 to 6 to be described later for driving the thin film transistor 3 are provided in the adjacent regions on the right side, the left side, and the lower side of the image reading region 2. . A plurality of external connection terminals 7 are provided at the lower end portion on the glass substrate 1. As will be described later, the external connection terminal 7 is connected to the first to third drive circuit units 4 to 6 through an upper layer connection wiring and a lower layer connection wiring provided on the glass substrate 1.

  The thin film transistor 3 includes a top gate electrode 8, a bottom gate electrode 9, and source / drain electrodes 10 and 10, which will be described in detail later. The top gate electrode 8 is connected to the first drive circuit unit (top gate driver) 4 via the top gate line 11 arranged in the row direction in the image reading region 2. The bottom gate electrode 9 is connected to a second drive circuit unit (bottom gate driver) 5 via a bottom gate line 12 arranged in the row direction in the image reading region 2.

  One source / drain electrode 10 is connected to a third drive circuit section (drain driver) 6 via a drain line 13 arranged in the column direction in the image reading region 2. The other source / drain electrode 10 is connected to a grounding external connection terminal of the external connection terminals 7 via a ground line (not shown) arranged in the image reading region 2 or the like.

  Next, an example of a specific structure of a part of the thin film transistor panel will be described with reference to FIG. In this case, from the left side to the right side in FIG. 2, a cross-sectional view of the portion of the external connection terminal 7, and portions of the CMOS thin film transistors 21 and 22 constituting each part of the first to third drive circuit portions 4 to 6. Sectional drawing, sectional drawing of the part of the 1st-4th interlayer contact, sectional drawing of the part of the photoelectric conversion type thin-film transistor 3 are shown.

  First, the portions of the CMOS thin film transistors 21 and 22 that constitute each part of the first to third drive circuit units 4 to 6 will be described. In the drive circuit portion forming region on the glass substrate 1, a CMOS thin film transistor including an NMOS thin film transistor 21 and a PMOS thin film transistor 22 made of, for example, a polysilicon thin film transistor is provided.

  Each of the thin film transistors 21 and 22 includes semiconductor thin films 25 and 26 made of polysilicon provided on the upper surfaces of the first and second base insulating films 23 and 24 provided on the upper surface of the glass substrate 1. In this case, the first base insulating film 23 is made of silicon nitride, and the second base insulating film 24 is made of silicon oxide.

  The NMOS thin film transistor 21 has, for example, an LDD (Lightly Doped Drain) structure. That is, the central portion of the semiconductor thin film 25 of the NMOS thin film transistor 21 is a channel region 25a made of an intrinsic region, both sides thereof are a source / drain region 25b made of an n-type impurity low concentration region, and both sides thereof are n-type impurity high The source / drain region 25c is formed of a concentration region. On the other hand, the central portion of the semiconductor thin film 26 of the PMOS thin film transistor 22 is a channel region 26a made of an intrinsic region, and both sides thereof are a source / drain region 26b made of a p-type impurity high concentration region.

  A gate insulating film 27 made of silicon oxide is provided on the upper surface of the second base insulating film 24 including the semiconductor thin films 25 and 26. Gate electrodes 28 and 29 made of molybdenum are provided on the upper surface of the gate insulating film 27 on the channel regions 25a and 26a. A first interlayer insulating film 30 made of silicon nitride is provided on the upper surface of the gate insulating film 27 including the gate electrodes 28 and 29. Contact holes 33 and 34 are provided in the first interlayer insulating film 30 and the gate insulating film 27 on the source / drain regions 25 c and 26 b of the semiconductor thin films 25 and 26.

  Conductive layers 35 and 36 made of molybdenum are connected to the source / drain regions 25c and 26b via the contact holes 33 and 34 on the upper surface of the first interlayer insulating film 30 in and near the contact holes 33 and 34, respectively. The source / drain electrodes and the wirings connected thereto are formed. Here, the conductor layers 35 and 36 include a portion formed on the first interlayer insulating film 30 and a portion filled in the contact holes 33 and 34. A second interlayer insulating film 37 made of silicon nitride, a bottom gate insulating film 38, a top gate insulating film 39, and an overcoat film 40 are provided on the upper surface of the first interlayer insulating film 30 including the conductor layers 35 and 36. ing.

  The NMOS thin film transistor 21 includes a semiconductor thin film 25, a gate insulating film 27, a gate electrode 28, and a conductor layer 35 including a source / drain electrode. The PMOS thin film transistor 22 includes a semiconductor thin film 26, a gate insulating film 27, a gate electrode 29, and a conductor layer 36 including source / drain electrodes. As a result, the CMOS thin film transistor composed of the NMOS thin film transistor 21 and the PMOS thin film transistor 22, that is, the first to third drive circuit units 4 to 6 are integrally formed on the glass substrate 1.

  Next, the photoelectric conversion type thin film transistor 3 will be described. A bottom gate electrode 9 made of chromium (light-shielding metal) is provided on the upper surface of the second interlayer insulating film 37 provided so as to cover the source / drain electrodes 35 and 36 of the thin film transistors 21 and 22 for the driving circuit section. ing. A bottom gate insulating film 38 is provided on the upper surface of the second interlayer insulating film 37 including the bottom gate electrode 9. A semiconductor thin film 41 made of intrinsic amorphous silicon is provided on the bottom gate insulating film 38 on the bottom gate electrode 9.

  A channel protective film 42 made of silicon nitride is provided at substantially the center of the upper surface of the semiconductor thin film 41. Ohmic contact layers 43 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 42 and on the upper surface of the semiconductor thin film 41 on both sides thereof. A source / drain electrode 10 made of chromium is provided on the upper surface of the ohmic contact layer 43 and the upper surface of the bottom gate insulating film 38 in the vicinity thereof.

  A top gate insulating film 39 is provided on the upper surface of the bottom gate insulating film 38 including the source / drain electrodes 10. A top gate electrode 8 made of ITO (translucent metal) is provided on the top surface of the top gate insulating film 39 on the semiconductor thin film 41. An overcoat film 40 is provided on the top surface of the top gate insulating film 39 including the top gate electrode 8.

  The photoelectric conversion type thin film transistor 3 is a bottom-gate type selection composed of the bottom gate electrode 9, the bottom gate insulating film 38, the semiconductor thin film 41, the channel protective film 42, the ohmic contact layer 43 and the source / drain electrode 10. The thin film transistor includes a top gate electrode 8, a top gate insulating film 39, a semiconductor thin film 41, a channel protective film 42, an ohmic contact layer 43, and a source / drain electrode 10. Yes. Thus, the photoelectric conversion type thin film transistor 3 is integrally formed on the glass substrate 1.

  Next, the external connection terminal 7 will be described. The external connection terminal 7 made of molybdenum is provided on the upper surface of the first interlayer insulating film 30, and is provided on the overcoat film 40, the top gate insulating film 39, the bottom gate insulating film 38, and the second interlayer insulating film 37. It is exposed through the opening 44.

  Next, the first to fourth interlayer contact portions will be described. In the first interlayer contact portion, the first upper-layer connection wiring 45 provided on the upper surface of the first interlayer insulating film 30 and provided in the same layer as the conductor layers 35 and 36, and made of the same molybdenum, Via the contact hole 46 provided in the first interlayer insulating film 30, the upper surface of the gate insulating film 27 is provided in the same layer as the gate electrodes 28 and 29 and is made of the same molybdenum and is connected to the gate electrodes 28 and 29. The first lower layer connection wiring 47 is connected to the connection pad portion. Here, the first upper layer connection wiring 45 includes a portion formed on the upper surface of the first interlayer insulating film 30 and a portion filled in the contact hole 46.

  In the second interlayer contact portion, the second upper layer connection wiring 48 made of chromium provided on the upper surface of the second interlayer insulating film 37 has a contact hole 49 provided in the second interlayer insulating film 37. Accordingly, the first interlayer insulating film 30 is provided on the upper surface of the same layer as the conductor layers 35 and 36 and is connected to the connection pad portion of the second lower layer connection wiring 50 made of the same molybdenum. Here, the second upper layer connection wiring 49 includes a portion formed on the upper surface of the second interlayer insulating film 37 and a portion filled in the contact hole 49.

In the third interlayer contact portion, the third upper layer connection wiring 51 made of the same chromium is provided on the upper surface of the bottom gate insulating film 38 in the same layer as the source / drain electrodes 10. A third lower layer made of the same molybdenum is provided on the upper surface of the first interlayer insulating film 30 in the same layer as the conductor layers 35 and 36 via a contact hole 52 provided in the second interlayer insulating film 37. The connection wiring 53 is connected to the connection pad portion. Here, the third upper layer connection wiring 51 includes a portion formed on the upper surface of the bottom gate insulating film 38 and a portion filled in the contact hole 52.

  In the fourth interlayer contact portion, the fourth upper layer connection wiring 54 made of the same ITO is provided on the upper surface of the top gate insulating film 39 in the same layer as the top gate electrode 8. Via the contact hole 55 provided in the gate insulating film 38 and the second interlayer insulating film 37, it is provided on the upper surface of the first interlayer insulating film 30 in the same layer as the conductor layers 35 and 36, and from the same molybdenum. The fourth lower layer connection wiring 56 is connected to the connection pad portion. Here, the fourth upper layer connection wiring 54 includes a portion formed on the upper surface of the top gate insulating film 40 and a portion filled in the contact hole 55.

  Next, the electrical connection of each part shown in FIG. 2 will be described. The bottom gate electrode 9 of the photoelectric conversion type thin film transistor 3 is connected to each of the conductor layers of the second upper layer connection wiring 48 and the second lower layer connection wiring 50, that is, through the bottom gate line 12 shown in FIG. The source / drain electrodes 35 and 36 of the thin film transistors 21 and 22 of the second drive circuit section (bottom gate driver) 5 are connected.

  One source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected to each of the conductor layers of the third upper layer connection wiring 51 and the third lower layer connection wiring 53, that is, through the drain line 13 shown in FIG. The third drive circuit section (drain driver) 6 is connected to the source / drain electrodes 35 and 36 of the thin film transistors 21 and 22.

  The other source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected to each of the conductor layers of the third upper layer connection wiring 51 and the third lower layer connection wiring 53, that is, through a ground line not shown in FIG. The external connection terminal 7 is connected to the grounding external connection terminal.

  The top gate electrode 8 of the photoelectric conversion type thin film transistor 3 is connected to each of the conductor layers of the fourth upper layer connection wiring 54 and the fourth lower layer connection wiring 56, that is, through the top gate line 11 shown in FIG. The first drive circuit section (top gate driver) 4 is connected to the source / drain electrodes 35 and 36 of the thin film transistors 21 and 22.

  The gate electrodes 28 and 29 of the thin film transistors 21 and 22 for the drive circuit section are connected to the external connection terminal 7 through the first lower layer connection wiring 47 and the first upper layer connection wiring 45. The source / drain electrodes 35 and 36 of the thin film transistors 21 and 22 for the drive circuit section are connected to the external connection terminal 7 through connection wiring (not shown) provided on the upper surface of the first interlayer insulating film 30. ing.

  Here, the connection for connecting the bottom gate electrode 8, the source / drain electrode 10 and the top gate electrode 8 of the photoelectric conversion type thin film transistor 3 to the source / drain electrodes 35 and 36 of the thin film transistors 21 and 22 for the drive circuit section. Among the wirings, the second to fourth lower layer connection wirings 50, 53, and 56 are provided on the first interlayer insulating film 30, and the source / drain electrodes 35 and 36 of the thin film transistors 21 and 22 for the drive circuit section In the same layer and made of the same conductive material, the second upper layer connection wiring 48 is provided on the second interlayer insulating film 37 and is the same layer as the bottom gate electrode 8 of the photoelectric conversion type thin film transistor 3. The third upper-layer connection wiring 51 made of the same conductive material is provided on the bottom gate insulating film 38, and the source / drain electrodes 1 of the photoelectric conversion type thin film transistor 3 are provided. The fourth upper layer connection wiring 54 is provided on the top gate insulating film 39 and is the same layer as the top gate electrode 8 of the photoelectric conversion type thin film transistor 3 and is the same. Made of a conductive material.

  Next, an example of a method for manufacturing the thin film transistor panel will be described. First, as shown in FIG. 3, a first base insulating film 23 (thickness of about 2000 mm) made of silicon nitride and a second base insulating film 24 made of silicon oxide are formed on the upper surface of the glass substrate 1 by plasma CVD. (A film thickness of about 1000 mm) and an amorphous silicon thin film 61 (film thickness of about 500 mm) are continuously formed. Here, the step of forming the amorphous silicon thin film 61 is performed under a temperature condition (second temperature condition) in which about 300 ° C. is the maximum temperature.

  Next, in order to remove the hydrogen contained in the amorphous silicon thin film 61 formed by plasma CVD with a high hydrogen content, a dehydrogenation process is performed for about 1 hour at a temperature of about 500 ° C. in a nitrogen gas atmosphere. This dehydrogenation treatment is performed in order to avoid the occurrence of defects due to bumping of hydrogen in the amorphous silicon thin film 61 when high energy is given to the amorphous silicon thin film 61 by excimer laser irradiation in a subsequent process. is there.

  Next, by irradiating the amorphous silicon thin film 61 with an excimer laser from the upper surface side, the amorphous silicon thin film 61 is crystallized to form a polysilicon thin film 62. Here, the step of crystallizing the amorphous silicon thin film 61 to form the polysilicon thin film 62 is performed under a temperature condition (first temperature condition) where the maximum temperature is approximately 600 ° C.

  Next, by patterning the polysilicon thin film 62 by photolithography, semiconductor thin films 25 and 26 are formed as shown in FIG. Next, as shown in FIG. 5, a gate insulating film 27 (thickness of about 1000 mm) made of silicon oxide is formed on the upper surface of the second base insulating film 24 including the semiconductor thin films 25 and 26 by plasma CVD. To do. Next, a conductor layer made of a molybdenum film (having a film thickness of about 3000 mm) formed by sputtering is patterned on the upper surface of the gate insulating film 27 by photolithography, whereby the gate electrodes 28 and 29 and the first electrode are formed. A lower layer connection wiring 47 is formed.

Next, as shown in FIG. 6, a p-type impurity is formed using a first resist pattern (not shown) formed by photolithography and having an opening in a portion corresponding to the source / drain region 26b as a mask. Inject at high concentration. As an example, boron ions are implanted under conditions of an acceleration energy of 30 keV and a dose of 3 × 10 ¹⁵ atm / cm ² . As a result, the semiconductor thin film 26 has a channel region 26a made of an intrinsic region under the gate electrode 29 and source / drain regions 26b made of p-type impurity high concentration regions on both sides thereof. Thereafter, the first resist pattern is peeled off.

Next, an n-type impurity is implanted at a high concentration using a second resist pattern (not shown) having an opening in a portion corresponding to the source / drain region 25c formed by photolithography. As an example, phosphorus ions are implanted under the conditions of an acceleration energy of 70 keV and a dose amount of 3 × 10 ¹⁵ atm / cm ² . Thereafter, the second resist pattern is peeled off.

Next, an n-type impurity is implanted at a low concentration using a third resist pattern (not shown) formed by photolithography and having an opening in a portion corresponding to the source / drain region 25b as a mask. As an example, phosphorus ions are implanted under the conditions of an acceleration energy of 70 keV and a dose of 3 × 10 ¹³ atm / cm ² . Thereafter, the third resist pattern is peeled off.

  As a result, the semiconductor thin film 25 includes a channel region 25a made of an intrinsic region under the gate electrode 28, source / drain regions 25b made of n-type impurity low concentration regions on both sides thereof, and n-type impurity high concentration regions on both sides thereof. And a source / drain region 25c.

  Next, implanted ion activation treatment is performed in a nitrogen gas atmosphere at a temperature of about 450 ° C. for about 1 hour. Here, the respective ion implantation steps using the first to third resist patterns as masks are not particularly limited to the above order, and may be performed in any order, and other methods such as gates are used. A method including an ion implantation process using the electrodes 28 and 29 as a mask may be used.

  Next, as shown in FIG. 7, on the upper surface of the gate insulating film 27 including the gate electrodes 28 and 29 and the first lower layer connection wiring 47, the first interlayer insulating film 30 ( A film thickness of about 3000 mm is formed. Next, contact holes 33 and 34 are continuously formed in the first interlayer insulating film 30 and the gate insulating film 27 on the source / drain regions 25c and 26b of the semiconductor thin films 25 and 26 by a photolithography method. A contact hole 46 is formed in the first interlayer insulating film 30 on the connection pad portion of the first lower layer connection wiring 47.

  Next, a conductor layer made of a molybdenum film (with a film thickness of about 5000 mm) is formed on the upper surface of the first interlayer insulating film 30 by sputtering, filling the contact holes 33, 34, and 46, and by photolithography. By patterning, the conductor layers 35 and 36 are formed to be connected to the source / drain regions 25c and 26b through the contact holes 33 and 34, thereby forming the source / drain electrodes and wirings connected thereto. Further, the first upper layer connection wiring 45 is formed to be connected to the connection pad portion of the first lower layer connection wiring 47 through the contact hole 46, and the external connection terminal 7, the first to third lower layer connection wirings 50, Connection wiring (not shown) for connecting 53 and 56 and the conductor layers 35 and 36 and the external connection terminal 7 is formed.

  Next, as shown in FIG. 8, the first interlayer including the external connection terminal 7, the conductor layers 35 and 36, the first upper layer connection wiring 45 and the second to fourth lower layer connection wirings 50, 53 and 56. A second interlayer insulating film 37 (thickness of about 3000 mm) made of silicon nitride is formed on the upper surface of the insulating film 30 by plasma CVD. Next, a contact hole 49 is formed in the second interlayer insulating film 37 on the connection pad portion of the second lower layer connection wiring 50 by photolithography.

  Next, a conductor layer made of a chromium film (with a film thickness of about 1000 mm) is formed on the upper surface of the second interlayer insulating film 37 by filling the contact hole 49 and patterned by photolithography. The second upper layer connection wiring 48 is formed to be connected to the connection pad portion of the second lower layer connection wiring 50 through the contact hole 49, and the bottom gate electrode 9 is formed.

  Next, as shown in FIG. 9, a bottom gate insulating film 38 (of silicon nitride) is formed on the upper surface of the second interlayer insulating film 37 including the bottom gate electrode 9 and the second upper layer connection wiring 48 by plasma CVD. A semiconductor thin film forming layer 41a (film thickness of about 500 mm) made of intrinsic amorphous silicon and a channel protective film forming layer 42a (film thickness of about 1000 mm) made of silicon nitride are successively formed. In this case, the semiconductor thin film forming layer 41a made of intrinsic amorphous silicon is formed under a temperature condition of about 300 ° C. as in the case of forming the amorphous silicon thin film 61 shown in FIG.

  Next, the channel protective film forming layer 42a is patterned by photolithography to form the channel protective film 42 as shown in FIG. Next, as shown in FIG. 11, an ohmic contact layer forming layer 43a (film thickness of about 250 mm) made of n-type amorphous silicon is formed on the upper surface of the semiconductor thin film forming layer 41a including the channel protective film 42 by plasma CVD. Is deposited. Also in this case, the ohmic contact layer forming layer 43a made of n-type amorphous silicon is formed under a temperature condition of about 300 ° C. as in the case of forming the amorphous silicon thin film 61 shown in FIG.

  Next, the ohmic contact layer 43 and the semiconductor thin film 41 are continuously patterned by photolithography to form the ohmic contact layer 43 and the semiconductor thin film 41 as shown in FIG.

  Next, as shown in FIG. 13, contact holes 52 are continuously formed on the bottom gate insulating film 38 and the second interlayer insulating film 37 on the connection pad portion of the third lower layer connection wiring 53 by photolithography. Form. Next, a conductor layer made of a chromium film (film thickness of about 500 mm) is formed by sputtering on the upper surface of the bottom gate insulating film 38 and the upper surface of the ohmic contact layer 43, and the contact hole 52 is filled, and photolithography is performed. Thus, the third upper layer connection wiring 51 is formed to be connected to the connection pad portion of the third lower layer connection wiring 53 through the contact hole 52, and the source / drain electrode 10 is formed.

  Next, as shown in FIG. 14, a top gate insulating film 39 (film) made of silicon nitride is formed on the upper surface of the bottom gate insulating film 38 including the source / drain electrodes 10 and the third upper layer connection wiring 51 by plasma CVD. A film having a thickness of about 3000 mm is formed. Next, contact holes 55 are continuously formed in the top gate insulating film 39, the bottom gate insulating film 38, and the second interlayer insulating film 37 on the connection pad portion of the fourth lower layer connection wiring 56 by photolithography. To do.

  Next, a conductor layer made of an ITO film (with a film thickness of about 500 mm) is formed on the upper surface of the top gate insulating film 39, filled in the contact hole 55, and patterned by a photolithography method. 4 upper layer connection wirings 54 are formed to be connected to the connection pad portions of the fourth lower layer connection wirings 56 through contact holes 55, and the top gate electrode 8 is formed.

  Next, as shown in FIG. 2, an overcoat film 40 (film thickness: 6000 mm) made of silicon nitride is formed on the upper surface of the top gate insulating film 39 including the top gate electrode 8 and the fourth upper layer connection wiring 54 by plasma CVD. Film). Next, the opening 44 is continuously formed in the overcoat film 40, the top gate insulating film 39, the bottom gate insulating film 38, and the second interlayer insulating film 37 on the external connection terminal 7 by photolithography. Thus, the thin film transistor panel shown in FIG. 2 is obtained.

  In the above manufacturing method, the semiconductor thin film 41 made of amorphous silicon of the photoelectric conversion type thin film transistor 3 is provided on the upper layer side of the semiconductor thin films 25 and 26 made of polysilicon of the thin film transistors 21 and 22 for the drive circuit section. After forming the semiconductor thin films 25 and 26 made of polysilicon of the thin film transistors 21 and 22 for the driving circuit section, the semiconductor thin film 41 made of amorphous silicon of the photoelectric conversion type thin film transistor 3 may be formed on the upper layer. The entire amorphous silicon thin film 61 formed may be crystallized to form the polysilicon thin film 62. As in the prior art, specific regions of the formed amorphous silicon thin film are selectively crystallized. This eliminates the need for such processes, simplifies the process, and reduces manufacturing costs. It is possible to reduce the.

  Further, in the above manufacturing method, the semiconductor thin film 41 of the photoelectric conversion type thin film transistor 3 is formed on the upper side of the semiconductor thin films 25 and 26 of the thin film transistors 21 and 22 for the drive circuit section, and the thin film transistors 21 and 22 for the drive circuit section Since the photoelectric conversion type thin film transistor 3 is formed separately in different layers, the thin film transistors 21 and 22 for the drive circuit section and the photoelectric conversion type thin film transistor 3 can be disposed sufficiently close to each other, and the entire apparatus Can be further reduced, and as a result, the entire apparatus can be further miniaturized.

  In the above manufacturing method, as shown in FIG. 3, the amorphous silicon thin film 61 is formed at a relatively low temperature condition (approximately about 300 ° C.), and then the amorphous silicon thin film 61 is crystallized to form a polysilicon thin film 62. Since the amorphous silicon thin film 41a is formed under a relatively low temperature condition (approximately 300 ° C.) as shown in FIG. 9, the process is performed under a relatively high temperature condition (approximately 600 ° C.). Each element characteristic of the thin film transistors 21 and 22 for the circuit portion and the photoelectric conversion type thin film transistor 3 can be maintained well.

  That is, contrary to the above, after the amorphous silicon thin film 41a is formed at a relatively low temperature condition (approximately 300 ° C.) and then the semiconductor thin film 41 is formed, the amorphous silicon thin film 61 is formed at a relatively low temperature condition (approximately When the step of forming the polysilicon thin film 62 by crystallizing the amorphous silicon thin film 61 and then forming the polysilicon thin film 62 at a relatively high temperature condition (approximately 600 ° C.) is performed first. Since dehydrogenation proceeds in the semiconductor thin film 41 made of amorphous silicon, sufficient electron mobility cannot be realized in the photoelectric conversion type thin film transistor 3, and there is a possibility that a phenomenon in which element characteristics are deteriorated may occur.

  On the other hand, in the above manufacturing method, the semiconductor thin film 41 made of amorphous silicon that can be formed at a relatively low temperature after the semiconductor thin films 25 and 26 made of polysilicon that require a relatively high temperature condition are formed. Since it is formed, the element characteristics of the photoelectric conversion type thin film transistor 3 can be maintained well while the element characteristics of the thin film transistors 21 and 22 for the drive circuit section are maintained well.

  Further, in the above manufacturing method, the bottom gate electrode 8, the source / drain electrode 10 of the photoelectric conversion type thin film transistor 3, and the top gate electrode 8 and the conductor connected to the source / drain electrode of the thin film transistors 21 and 22 for the driving circuit section. The second to fourth lower layer connection wirings 50, 53, 56 for connecting the layers 35, 36 are connected to the source / drain electrodes of the thin film transistors 21, 22 for the driving circuit section. The second upper layer connection wiring 48 is formed simultaneously with the formation of the bottom gate electrode 8 of the photoelectric conversion type thin film transistor 3, and the third upper layer connection wiring 51 is formed as the source / drain of the photoelectric conversion type thin film transistor 3. The fourth upper layer connection wiring 54 is formed simultaneously with the formation of the electrode 10, and the top gate electrode 8 of the photoelectric conversion type thin film transistor 3 is formed. Since formation to be formed at the same time, there is no need to form either a private its process of each lower connection wiring and the upper connection wiring, thereby to simplify the manufacturing process, it is possible to reduce the manufacturing cost.

(Second Embodiment)
FIG. 15 is a sectional view similar to FIG. 2 of a thin film transistor panel as a second embodiment of the present invention. In this thin film transistor panel, the difference from the case shown in FIG. 2 is that the third upper layer connection wiring 51 is formed on the upper surface of the second interlayer insulating film 37 through the contact hole 52 provided in the bottom gate insulating film 38. The fourth upper layer connection wiring 54 is connected to the connection pad portion of the third lower layer connection wiring 53 made of chromium, and the contact hole 55 provided in the top gate insulating film 39 and the bottom gate insulating film 38 is connected. In other words, it is connected to the connection pad portion of the fourth lower layer connection wiring 56 made of chromium provided on the upper surface of the second interlayer insulating film 37.

  In this case, the third and fourth lower layer connection wirings 53 and 56 made of chromium provided on the upper surface of the second interlayer insulating film 37 are connected to the bottom gate electrode 9 made of chromium on the upper surface of the second interlayer insulating film 37. Since the second upper-layer connection wiring 48 can be formed at the same time, it is not necessary to form any of the third and fourth lower-layer connection wirings 53 and 56 in a dedicated process.

  Next, the electrical connection between the photoelectric conversion type thin film transistor 3, the thin film transistors 21 and 22 for the drive circuit section, and the external connection terminal 7 in this thin film transistor panel will be described. The bottom gate electrode 9 of the photoelectric conversion type thin film transistor 3 includes a conductor layer 35 connected to the source / drain electrodes of the thin film transistors 21 and 22 through the second upper layer connection wiring 48 and the second lower layer connection wiring 50. 36.

  One source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected via a third upper layer connection wiring 51, a third lower layer connection wiring 53, a second upper layer connection wiring 48 and a second lower layer connection wiring 50. The conductive layers 35 and 36 are connected to the source and drain electrodes of the thin film transistors 21 and 22. The other source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected via a third upper layer connection wiring 51, a third lower layer connection wiring 53, a second upper layer connection wiring 48 and a second lower layer connection wiring 50. The external connection terminal 7 is connected to the grounding external connection terminal.

  The top gate electrode 8 of the photoelectric conversion type thin film transistor 3 is connected to the thin film transistor 21 via the fourth upper layer connection wiring 54, the fourth lower layer connection wiring 56, the second upper layer connection wiring 48, and the second lower layer connection wiring 50. , 22 are connected to conductor layers 35, 36 connected to the source / drain electrodes.

  In the thin film transistor panel, the contact hole 52 may be formed only in the bottom gate insulating film 38 in the third interlayer contact portion, and the contact hole 55 is formed in the top gate insulating film in the fourth interlayer contact portion. 39 and the bottom gate insulating film 38, the depth of the contact holes 52 and 55 can be reduced compared to the case shown in FIG. 2, and as a result, the third and fourth upper layer connection wirings can be formed. Connection reliability with respect to the third and fourth lower layer connection wirings 53 and 56 of 51 and 54 can be improved.

(Third embodiment)
FIG. 16 is a sectional view similar to FIG. 15 of a thin film transistor panel as a third embodiment of the present invention. In this thin film transistor panel, the difference from the case shown in FIG. 15 is that the fourth upper layer connection wiring 54 is provided on the upper surface of the bottom gate insulating film 38 through the contact hole 55 provided in the top gate insulating film 39. This is the point of connection to the connection pad portion of the fourth lower layer connection wiring 56 made of chrome.

  In this case, the third lower layer connection wiring 56 made of chromium provided on the upper surface of the bottom gate insulating film 38 has the source / drain electrode 10 made of chromium and the third lower connection wiring 56 made of chromium on the upper surface of the ohmic contact layer 43 and the bottom gate insulating film 38. Since the upper connection wiring 51 can be formed at the same time, it is not necessary to form the fourth lower connection wiring 56 in a dedicated process.

  Next, the electrical connection between the photoelectric conversion type thin film transistor 3, the thin film transistors 21 and 22 for the drive circuit section, and the external connection terminal 7 in this thin film transistor panel will be described. The bottom gate electrode 9 of the photoelectric conversion type thin film transistor 3 includes a conductor layer 35 connected to the source / drain electrodes of the thin film transistors 21 and 22 through the second upper layer connection wiring 48 and the second lower layer connection wiring 50. 36.

  One source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected via a third upper layer connection wiring 51, a third lower layer connection wiring 53, a second upper layer connection wiring 48 and a second lower layer connection wiring 50. The conductive layers 35 and 36 are connected to the source and drain electrodes of the thin film transistors 21 and 22. The other source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected via a third upper layer connection wiring 51, a third lower layer connection wiring 53, a second upper layer connection wiring 48 and a second lower layer connection wiring 50. The external connection terminal 7 is connected to the grounding external connection terminal.

  The top gate electrode 8 of the photoelectric conversion type thin film transistor 3 includes a fourth upper layer connection wiring 54, a fourth lower layer connection wiring 56, a third upper layer connection wiring 51, a third lower layer connection wiring 53, and a second upper layer connection. The wirings 48 and the second lower layer connection wiring 50 are connected to conductor layers 35 and 36 connected to the source / drain electrodes of the thin film transistors 21 and 22.

  By the way, in this thin film transistor panel, the contact hole 55 only needs to be formed only in the top gate insulating film 39 in the portion of the fourth interlayer contact, so that the depth of the contact hole 55 is reduced compared to the case shown in FIG. Thus, the connection reliability of the fourth upper layer connection wiring 54 to the fourth lower layer connection wiring 56 can be improved.

(Fourth embodiment)
FIG. 17 is a sectional view similar to FIG. 2 of a thin film transistor panel as a fourth embodiment of the present invention. The thin film transistor panel is greatly different from the case shown in FIG. 2 in that the thin film transistors 21 and 22 for the drive circuit shown in FIG. 2 have a top gate structure, but a bottom gate structure. In this case, only the base insulating film 23 made of silicon nitride is provided on the upper surface of the glass substrate 1 as the base insulating film.

  Next, an example of a method for manufacturing the thin film transistor panel will be described. First, as shown in FIG. 18, a base insulating film 23 (film thickness of about 2000 mm) made of silicon nitride is formed on the upper surface of the glass substrate 1 by plasma CVD. Next, a conductive layer made of a molybdenum film (having a film thickness of about 1000 mm) formed by sputtering is patterned on the upper surface of the base insulating film 23 by photolithography, whereby the gate electrodes 28 and 29 and the first electrode are formed. A lower layer connection wiring 47 is formed.

  Next, on the upper surface of the base insulating film 23 including the gate electrodes 28 and 29 and the first lower layer connection wiring 47, a gate insulating film 27 (about 1000 mm thick) made of silicon oxide and an amorphous silicon thin film 61 are formed by plasma CVD. (Film thickness of about 500 mm) is continuously formed. Also in this case, the step of forming the amorphous silicon thin film 61 is performed under a temperature condition where the maximum temperature is approximately 300 ° C. Next, dehydrogenation treatment is performed for about 1 hour at a temperature of about 500 ° C. in a nitrogen gas atmosphere.

  Next, by irradiating the amorphous silicon thin film 61 with an excimer laser from the upper surface side, the amorphous silicon thin film 61 is crystallized to form a polysilicon thin film 62. Also in this case, the process of crystallizing the amorphous silicon thin film 61 to form the polysilicon thin film 62 is performed under temperature conditions where the maximum temperature is approximately 600 ° C.

Next, a p-type impurity is implanted at a high concentration using a first resist pattern (not shown) formed by photolithography and having an opening in a portion corresponding to the source / drain region 26b. As an example, boron ions are implanted under the conditions of an acceleration energy of 10 keV and a dose of 1 × 10 ¹⁵ atm / cm ² . Thereafter, the first resist pattern is peeled off.

Next, an n-type impurity is implanted at a high concentration using a second resist pattern (not shown) having an opening in a portion corresponding to the source / drain region 25c formed by photolithography. As an example, phosphorus ions are implanted under the conditions of an acceleration energy of 10 keV and a dose of 1 × 10 ¹⁵ atm / cm ² . Thereafter, the second resist pattern is peeled off.

Next, an n-type impurity is implanted at a low concentration using a third resist pattern (not shown) formed by photolithography and having an opening in a portion corresponding to the source / drain region 25b as a mask. As an example, phosphorus ions are implanted under the conditions of an acceleration energy of 10 keV and a dose of 1 × 10 ¹³ atm / cm ² . Thereafter, the third resist pattern is peeled off. Next, implanted ion activation treatment is performed in a nitrogen gas atmosphere at a temperature of about 450 ° C. for about 1 hour.

  Next, by patterning the polysilicon thin film 62 by photolithography, semiconductor thin films 25 and 26 are formed as shown in FIG. In this state, the semiconductor thin film 25 includes a channel region 25a composed of an intrinsic region on the gate electrode 28, a source / drain region 25b composed of n-type impurity low concentration regions on both sides thereof, and a high n-type impurity concentration on both sides thereof. It has a source / drain region 25c composed of a region. The semiconductor thin film 26 has a channel region 26a made of an intrinsic region on the gate electrode 29 and source / drain regions 26b made of p-type impurity high concentration regions on both sides thereof.

  Next, as shown in FIG. 20, a first interlayer insulating film 30 (thickness of about 3000 mm) made of silicon oxide is formed on the upper surface of the gate insulating film 27 including the semiconductor thin films 25 and 26 by plasma CVD. To do. Next, contact holes 33 and 34 are formed in the first interlayer insulating film 30 on the source / drain regions 25c and 26b of the semiconductor thin films 25 and 26 by photolithography, and the connection of the first lower layer connection wiring 47 is performed. Contact holes 46 are continuously formed in the first interlayer insulating film 30 and the gate insulating film 27 on the pad portion.

  Next, a conductor layer made of an aluminum film (having a thickness of about 5000 mm) is formed on the upper surface of the first interlayer insulating film 30 by sputtering, filling the contact holes 33, 34, and 46, and by photolithography. By patterning, the conductor layers 35 and 36 are formed to be connected to the source / drain regions 25c and 26b through the contact holes 33 and 34, and the first upper layer connection wiring 45 is formed through the contact hole 46. 1 and connected to the connection pad portion of the lower layer connection wiring 47, and the external connection terminal 7, the second to fourth lower layer connection wirings 50, 53 and 56, the conductor layers 35 and 36, and the external connection terminal 7 A connection wiring (not shown) for connecting the two is formed. Since the following steps are the same as those in the first embodiment, a description thereof will be omitted.

  In the above manufacturing method, as shown in FIG. 18, since boron ions and phosphorus ions are directly implanted into the polysilicon semiconductor thin film 62, it is inexpensive without using an expensive high acceleration (up to 80 keV) ion implantation apparatus. Boron ions and phosphorus ions can be implanted using a low-acceleration (-10 keV) ion implantation apparatus.

  The ion implantation and activation treatment may be performed after the device area is formed as shown in FIG. Here, also in the first embodiment, the ion implantation and activation treatment may be performed after forming the polysilicon thin film 62 as shown in FIG. 3, and as shown in FIG. You may carry out after forming.

(Other embodiments)
In each of the above-described embodiments, the case where the drive circuit unit is configured by a CMOS thin film transistor made of a polysilicon thin film transistor has been described. However, the present invention is not limited thereto, and may be configured by only an NMOS thin film transistor. You may make it comprise by a combination with a thin-film transistor.

  In each of the above embodiments, the external connection terminal 7 has a single-layer structure made of molybdenum simultaneously with the formation of 35 and 36 connected to the source / drain electrodes made of molybdenum of the thin film transistors 21 and 22 for the drive circuit section. Although the case where it is formed is not limited to this, it may be formed simultaneously with the formation of an electrode on another layer (for example, the bottom gate electrode 9), or may be formed simultaneously with the formation of an electrode on a plurality of layers. It is good also as a structure.

  Further, for example, in the first embodiment (see FIG. 2), the first and second interlayer insulating films 30 and 37 may be a single layer of a silicon oxide film instead of a single layer of a silicon nitride film, Also, a plurality of types of laminated structures may be used. Further, for example, in the fourth embodiment (see FIG. 17), the gate insulating film 27 is not a single layer of a silicon oxide film, but may be a two-layer structure of a lower silicon nitride film and an upper silicon oxide film. In addition, the first interlayer insulating film 30 may not be a single layer of a silicon oxide film, but may have a two-layer structure of a lower silicon oxide film and an upper silicon nitride film, and the second interlayer insulating film 37. May be a single layer of a silicon oxide film instead of a single layer of a silicon nitride film, or may be a plurality of types of laminated structures.

  Further, in each of the above embodiments, the case where the thin film transistor panel of the present invention is applied to an image reading apparatus has been described. However, the present invention is not limited to this. In short, a thin film transistor panel having a structure in which amorphous silicon thin film transistors are arranged in a matrix in a predetermined region on a substrate and a polysilicon thin film transistor for driving the amorphous silicon thin film transistor is disposed in a peripheral region adjacent to the predetermined region. I just need it.

  For example, a well-known display pixel including a light emitting element such as a liquid crystal capacitor or an organic EL element in a predetermined region on a substrate (specifically, a liquid crystal pixel composed of a liquid crystal capacitor and a pixel transistor, an organic EL element and a pixel driving circuit) Are arranged in a matrix, and each display pixel is set in a selected state in a peripheral region adjacent to the predetermined region, and a predetermined gradation signal is supplied to the display pixel. The present invention can also be applied to a known image display device provided with a driver (scanning driver, data driver, power supply driver, etc.) that controls to display the image information.

The equivalent circuit top view of the principal part of the thin-film transistor panel as 1st Embodiment of this invention. FIG. 2 is a cross-sectional view illustrating a specific structure of part of the thin film transistor panel illustrated in FIG. 1. FIG. 3 is a cross-sectional view of an initial process in manufacturing the thin film transistor panel shown in FIG. 2. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing similar to FIG. 2 of the thin-film transistor panel as 2nd Embodiment of this invention. Sectional drawing similar to FIG. 15 of the thin-film transistor panel as 3rd Embodiment of this invention. Sectional drawing similar to FIG. 2 of the thin-film transistor panel as 4th Embodiment of this invention. FIG. 18 is a cross-sectional view of an initial process in manufacturing the thin film transistor panel shown in FIG. 17. FIG. 19 is a cross-sectional view of the process following FIG. 18. FIG. 20 is a cross-sectional view of the process following FIG. 19.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Image reading area 3 Photoelectric conversion type thin-film transistor 4-6 Drive circuit part 7 External connection terminal 8 Top gate electrode 9 Bottom gate electrode 10 Source / drain electrode 11 Top gate line 12 Bottom gate line 13 Drain line 21, 22 Thin film transistors 25 and 26 for driving circuits 25 and 26 Semiconductor thin films 28 and 29 Gate electrodes 33 and 34 Contact holes 35 and 36 Conductor layers including source / drain electrodes 41 Semiconductor thin films 42 Channel protective films 43 Ohmic contact layers 44 Openings 45 and 48 , 51, 54 First to fourth upper layer connection wiring 46, 49, 52, 55 Contact hole 47, 50, 53, 56 First to fourth lower layer connection wiring

Claims (8)

On a substrate, a thin film transistor panel provided with a polysilicon thin film transistor having a semiconductor thin film made of polysilicon and a plurality of electrodes, and an amorphous silicon thin film transistor having a semiconductor thin film made of amorphous silicon and a plurality of electrodes,
A first wiring connected to any of the plurality of electrodes of the polysilicon thin film transistor, provided in the same layer with the same conductive material as the electrode, and having a connection pad;
A semiconductor thin film made of amorphous silicon provided above the first wiring via an insulating film;
Opposite the first wiring through an insulating film, provided in the same layer with the same conductive material as any of the plurality of electrodes of the amorphous silicon thin film transistor, and the first wiring of the insulating film A second wiring electrically connected to the first wiring through a contact hole provided at a location corresponding to the connection pad;
A third wiring connected to any of the plurality of electrodes of the amorphous silicon thin film transistor, provided in the same layer with the same conductive material as the electrode, and having a connection pad;
Provided in the same layer with the same conductive material as any of the plurality of electrodes of the amorphous silicon thin film transistor via an insulating film above the third wiring, and the third wiring of the insulating film A fourth wiring electrically connected to the third wiring through a contact hole provided at a location corresponding to the connection pad;
A thin film transistor panel comprising: In the invention of claim 1 ,
The amorphous silicon thin film transistor is a double gate type thin film transistor having a top gate electrode and a bottom gate electrode provided above and below the semiconductor thin film via an insulating film, respectively.
The second wiring, the third wiring, and the fourth wiring are provided in the same layer with the same conductive material as any of the bottom gate electrode, source / drain electrode, and top gate electrode of the amorphous silicon thin film transistor. A thin film transistor panel, wherein In the invention according to claim 1 or 2 ,
The thin film transistor panel, wherein the polysilicon thin film transistor is a top gate type. In the invention according to claim 1 or 2 ,
The thin film transistor panel, wherein the polysilicon thin film transistor is a bottom gate type. In the invention according to any one of claims 1 to 4 ,
The amorphous silicon thin film transistors are arranged in a matrix in a predetermined region on the substrate,
The thin film transistor panel, wherein the polysilicon thin film transistor is disposed in a peripheral region adjacent to the predetermined region on the substrate to constitute a drive circuit unit for driving the amorphous silicon thin film transistor. In a method of manufacturing a thin film transistor panel in which a semiconductor thin film made of polysilicon and a polysilicon thin film transistor having a plurality of electrodes and an amorphous silicon thin film transistor having a semiconductor thin film made of amorphous silicon and a plurality of electrodes are provided on a substrate,
Forming a semiconductor thin film made of polysilicon on the substrate;
Forming the polysilicon thin film transistor using the semiconductor thin film made of polysilicon;
Forming a first wiring connected to any of the plurality of electrodes of the polysilicon thin film transistor and made of the same conductive material as the electrode and having a connection pad simultaneously with the electrode;
Forming a semiconductor thin film made of amorphous silicon via an insulating film on the first wiring;
Forming the amorphous silicon thin film transistor using a semiconductor thin film made of the amorphous silicon ;
Forming an insulating film on top of the first wiring, and forming a contact hole provided at a location corresponding to the connection pad of the first wiring of the insulating film;
On the insulating film corresponding to the contact hole, a second wiring made of the same conductive material as that of any of the plurality of electrodes of the amorphous silicon thin film transistor is formed at the same time as the electrode, Electrically connecting a second wiring and the first wiring;
Forming a third wiring connected to any of the plurality of electrodes of the amorphous silicon thin film transistor and made of the same conductive material as the electrode and having a connection pad simultaneously with the electrode;
Forming an insulating film on top of the third wiring, and forming a contact hole provided at a location corresponding to the connection pad of the third wiring of the insulating film;
On the insulating film corresponding to the contact hole, a fourth wiring made of the same conductive material as any of the plurality of electrodes of the amorphous silicon thin film transistor is formed simultaneously with the electrode, Electrically connecting a fourth wiring and the third wiring;
A method for producing a thin film transistor panel, comprising: In the invention of claim 6 ,
The step of forming the semiconductor thin film made of polysilicon is performed under a first temperature condition,
The method of manufacturing a thin film transistor panel, wherein the step of forming the semiconductor thin film made of amorphous silicon is performed under a second temperature condition where a maximum temperature is lower than the first temperature condition. In the invention according to claim 6 or 7 ,
The amorphous silicon thin film transistor is a double gate type thin film transistor having a top gate electrode and a bottom gate electrode provided above and below the semiconductor thin film via an insulating film, respectively.
The second wiring, the third wiring, and the fourth wiring are made of the same conductive material as any of the bottom gate electrode, the source / drain electrode, and the top gate electrode of the amorphous silicon thin film transistor, and simultaneously with the electrodes. A method for manufacturing a thin film transistor panel, comprising: forming a thin film transistor panel.

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