JP4997692B2 - Thin film transistor panel and manufacturing method thereof - Google Patents

Description

  The present invention relates to a thin film transistor panel and a method for manufacturing the same, and more particularly to a thin film transistor panel including a polysilicon thin film transistor and an amorphous silicon thin film transistor and a method for manufacturing the same.

  In the image reading apparatus, for example, a plurality of photosensors are arranged in an image reading area in a substantially central portion on a glass substrate, and a semiconductor chip for driving the photosensors is arranged outside the image reading area on the glass substrate. (For example, refer to Patent Document 1).

  However, in such an image reading device, since the semiconductor chip arranged outside the image reading region protrudes upward, for example, when used as a fingerprint reading device, a finger as a subject touches the semiconductor chip. If contact is made, the finger cannot be brought into close contact with the image reading area as expected, and an appropriate fingerprint reading operation is not performed, which causes a malfunction such as a malfunction.

  Therefore, in order to avoid such a problem due to the upward protrusion of the semiconductor chip, it may be possible to adopt a configuration in which the semiconductor chip is arranged at a position somewhat away from the image reading area. Is not preferable when the entire apparatus becomes large and is considered to be mounted on a portable device or the like.

  On the other hand, in an active matrix type liquid crystal display device, for example, an amorphous silicon thin film is formed on a glass substrate, and only the polysilicon thin film transistor forming region is selectively crystallized to selectively form a polysilicon thin film. There is one in which an amorphous silicon thin film transistor is formed in an amorphous silicon thin film formation region and a polysilicon thin film transistor is formed in a polysilicon thin film formation region (see, for example, Patent Document 2).

  In such a liquid crystal display device, an amorphous silicon thin film transistor is formed as a switching element in an image display region in a substantially central portion on the glass substrate, and the amorphous silicon thin film transistor is driven outside the image display region on the glass substrate. When a polysilicon thin film transistor is formed as a drive circuit section for the purpose, the uppermost surface becomes substantially flat. Therefore, when such a structure is adopted in the fingerprint reading apparatus, it is not necessary to separate the drive circuit unit from the image reading area more than necessary, and the entire apparatus can be downsized.

JP-A-8-8414 (FIG. 3) Japanese Patent Publication No. 5-9794

  However, in the liquid crystal display device described in Patent Document 2, only the polysilicon thin film transistor formation region (drive circuit portion formation region) is selectively crystallized out of the amorphous silicon thin film formed on the glass substrate. Therefore, a step of partially forming a polysilicon thin film is required.

  For this reason, when crystallization of an amorphous silicon thin film is performed by laser irradiation, for example, it is necessary to control the laser irradiation position with high accuracy and to selectively crystallize the amorphous silicon thin film by scanning a thin laser beam. As a result, it is necessary to increase the precision of the manufacturing apparatus, and it takes a relatively long time for the crystallization process, resulting in an increase in manufacturing cost.

  In addition, since the amorphous silicon thin film is crystallized by heating the amorphous silicon thin film to about 600 ° C., it is difficult to clearly separate the crystallized region from the non-crystallized region. There has been a problem that it is difficult to dispose the image display region made of the amorphous silicon thin film transistor and the drive circuit portion made of the polysilicon thin film transistor sufficiently close to each other on the substrate, and there is a limit to downsizing of the entire device.

  Accordingly, an object of the present invention is to provide a thin film transistor panel and a method for manufacturing the same that can reduce the manufacturing cost and can further reduce the size of the entire apparatus.

In order to achieve the above object, the present invention provides a polysilicon thin film transistor having a semiconductor thin film made of polysilicon and a plurality of electrodes on a substrate, and an amorphous silicon thin film transistor having a semiconductor thin film made of amorphous silicon and a plurality of electrodes. In the thin film transistor panel provided, the first wiring connected to any of the plurality of electrodes of the polysilicon thin film transistor, provided in the same layer with the same conductive material as the electrode, and having a connection pad; a semiconductor thin film made of the amorphous silicon which is provided via an insulating film on the first wiring, and a plurality of second lines having a connection pad, and a plurality of third wiring provided in the same layer from each other the provided one of the second wiring of said plurality of second lines, the Amorufu A plurality of second wirings connected to one of the plurality of electrodes of the silicon thin film transistor, provided in the same layer as the one electrode with the same conductive material as the one electrode; The other second wiring different from the first second wiring is connected to another electrode formed in a layer different from the first electrode among the plurality of electrodes of the amorphous silicon thin film transistor. The plurality of third wirings are provided in the same layer as the other electrodes with the same conductive material as the other electrodes, and the plurality of third wirings include the plurality of third wirings and the plurality of second second electrodes. A portion corresponding to each connection pad of the second wiring of the insulating film, which is provided so that at least one insulating film is interposed between the wiring and is made of a different conductive material from each electrode of the amorphous silicon thin film transistor Provided in Via a plurality of contact holes, it is characterized in that it is electrically connected to the plurality of second wirings.

  According to the present invention, since the semiconductor thin film of the amorphous silicon thin film transistor is provided on the semiconductor thin film of the polysilicon thin film transistor via the insulating film, the semiconductor thin film of the polysilicon thin film transistor is formed and the insulating film is formed thereon. After that, it is sufficient to form a semiconductor thin film of an amorphous silicon thin film transistor. Therefore, the entire amorphous silicon thin film thus formed may be crystallized to form a polysilicon thin film, which is formed as in the prior art. In addition, a process for selectively crystallizing a specific region of the amorphous silicon thin film becomes unnecessary, and the manufacturing process can be reduced by simplifying the process.

In addition, since the semiconductor thin film of the amorphous silicon thin film transistor is provided on the upper layer side of the semiconductor thin film of the polysilicon thin film transistor, the polysilicon thin film transistor and the amorphous silicon thin film transistor are separately formed in different layers. Can be arranged close enough to each other, and further downsizing of the entire apparatus can be achieved.

  Furthermore, it is connected to one of the plurality of electrodes of the polysilicon thin film transistor and the plurality of electrodes of the amorphous silicon thin film transistor, and is electrically connected through the contact hole to connect the electrodes of the polysilicon thin film transistor and the amorphous silicon thin film transistor to each other. A material and a film used for the wiring by forming a part of each wiring with a conductive material different from each electrode separately from the step of forming the plurality of electrodes of the polysilicon thin film transistor and the amorphous silicon thin film transistor. The thickness can be arbitrarily selected, and the degree of freedom of wiring can be increased to increase the density.

(First embodiment)
FIG. 1 shows an equivalent circuit plan view of a main part of a thin film transistor panel constituting an image reading apparatus as a first embodiment of the present invention. The thin film transistor panel includes a glass substrate 1. A plurality of photoelectric conversion type thin film transistors 3 as photosensors are arranged in a matrix in the image reading region 2 in the substantially central portion on the glass substrate 1.

  On the glass substrate 1, first to third drive circuit units 4 to 6 to be described later for driving the thin film transistor 3 are provided in the adjacent regions on the right side, the left side, and the lower side of the image reading region 2. . A plurality of external connection terminals 7 are provided at the lower end portion on the glass substrate 1. As will be described later, the external connection terminal 7 is connected to the first to third drive circuit units 4 to 6 through an upper layer connection wiring and a lower layer connection wiring provided on the glass substrate 1.

  The thin film transistor 3 includes a top gate electrode 8, a bottom gate electrode 9, and source / drain electrodes 10 and 10, which will be described in detail later. The top gate electrode 8 is connected to the first drive circuit unit (top gate driver) 4 via the top gate line 11 arranged in the row direction in the image reading region 2. The bottom gate electrode 9 is connected to a second drive circuit unit (bottom gate driver) 5 via a bottom gate line 12 arranged in the row direction in the image reading region 2.

  One source / drain electrode 10 is connected to a third drive circuit section (drain driver) 6 via a drain line 13 arranged in the column direction in the image reading region 2. The other source / drain electrode 10 is connected to a grounding external connection terminal of the external connection terminals 7 via a ground line (not shown) arranged in the image reading region 2 or the like.

  Next, an example of a specific structure of a part of the thin film transistor panel will be described with reference to FIG. In this case, from the left side to the right side in FIG. 2, a cross-sectional view of the portion of the external connection terminal 7, and portions of the CMOS thin film transistors 21 and 22 constituting each part of the first to third drive circuit portions 4 to 6. Sectional drawing, sectional drawing of the part of the 1st-5th interlayer contact, sectional drawing of the part of the photoelectric conversion type thin-film transistor 3 are shown.

  First, the portions of the CMOS thin film transistors 21 and 22 that constitute each part of the first to third drive circuit units 4 to 6 will be described. In the drive circuit portion forming region on the glass substrate 1, a CMOS thin film transistor including an NMOS thin film transistor 21 and a PMOS thin film transistor 22 made of, for example, a polysilicon thin film transistor is provided.

  Each of the thin film transistors 21 and 22 includes semiconductor thin films 25 and 26 made of polysilicon provided on the upper surfaces of the first and second base insulating films 23 and 24 provided on the upper surface of the glass substrate 1. In this case, the first base insulating film 23 is made of silicon nitride, and the second base insulating film 24 is made of silicon oxide.

  The NMOS thin film transistor 21 has, for example, an LDD (Lightly Doped Drain) structure. That is, the central portion of the semiconductor thin film 25 of the NMOS thin film transistor 21 is a channel region 25a made of an intrinsic region, both sides thereof are a source / drain region 25b made of an n-type impurity low concentration region, and both sides thereof are n-type impurity high The source / drain region 25c is formed of a concentration region. On the other hand, the central portion of the semiconductor thin film 26 of the PMOS thin film transistor 22 is a channel region 26a made of an intrinsic region, and both sides thereof are a source / drain region 26b made of a p-type impurity high concentration region.

  A gate insulating film 27 made of silicon oxide is provided on the upper surface of the second base insulating film 24 including the semiconductor thin films 25 and 26. Gate electrodes 28 and 29 made of molybdenum are provided on the upper surface of the gate insulating film 27 on the channel regions 25a and 26a. A first interlayer insulating film 30 made of silicon nitride is provided on the upper surface of the gate insulating film 27 including the gate electrodes 28 and 29. Contact holes 33 and 34 are provided in the first interlayer insulating film 30 and the gate insulating film 27 on the source / drain regions 25 c and 26 b of the semiconductor thin films 25 and 26.

  Conductive layers 35 and 36 made of aluminum are connected to the source / drain regions 25c and 26b through the contact holes 33 and 34 on the upper surface of the first interlayer insulating film 30 in and near the contact holes 33 and 34, respectively. The source / drain electrodes and the wirings connected thereto are formed. Here, the conductor layers 35 and 36 include a portion formed on the first interlayer insulating film 30 and a portion filled in the contact holes 33 and 34. On the upper surface of the first interlayer insulating film 30 including the conductor layers 35 and 36, a second interlayer insulating film 37 made of silicon nitride, a bottom gate insulating film 38, a top gate insulating film 39, and a third interlayer insulating film 40 are formed. In addition, an overcoat film 41 is provided.

  The NMOS thin film transistor 21 includes a semiconductor thin film 25, a gate insulating film 27, a gate electrode 28, and a conductor layer electrode 35 including a source / drain. The PMOS thin film transistor 22 includes a semiconductor thin film 26, a gate insulating film 27, a gate electrode 29, and a conductor layer 36 including source / drain electrodes. As a result, the CMOS thin film transistor composed of the NMOS thin film transistor 21 and the PMOS thin film transistor 22, that is, the first to third drive circuit units 4 to 6 are integrally formed on the glass substrate 1.

  Next, the photoelectric conversion type thin film transistor 3 will be described. A bottom gate electrode 9 made of chromium (light-shielding metal) is provided on the upper surface of the second interlayer insulating film 37 provided so as to cover the source / drain electrodes 35 and 36 of the thin film transistors 21 and 22 for the driving circuit section. ing. A bottom gate insulating film 38 is provided on the upper surface of the second interlayer insulating film 37 including the bottom gate electrode 9. A semiconductor thin film 42 made of intrinsic amorphous silicon is provided on the bottom gate insulating film 38 on the bottom gate electrode 9.

  A channel protective film 43 made of silicon nitride is provided at substantially the center of the upper surface of the semiconductor thin film 42. Ohmic contact layers 44 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 43 and on the upper surface of the semiconductor thin film 42 on both sides thereof. Source / drain electrodes 10 made of chromium are provided on the upper surface of the ohmic contact layer 44 and the upper surface of the bottom gate insulating film 38 in the vicinity thereof.

  A top gate insulating film 39 is provided on the upper surface of the bottom gate insulating film 38 including the source / drain electrodes 10. A top gate electrode 8 made of ITO (translucent metal) is provided on the top surface of the top gate insulating film 39 on the semiconductor thin film 42. A third interlayer insulating film 40 and an overcoat film 41 are provided on the top surface of the top gate insulating film 39 including the top gate electrode 8.

  The photoelectric conversion type thin film transistor 3 is a bottom gate type selection circuit constituted by the bottom gate electrode 9, the bottom gate insulating film 38, the semiconductor thin film 42, the channel protective film 43, the ohmic contact layer 44, and the source / drain electrodes 10. The thin film transistor includes a top gate electrode 8, a top gate insulating film 39, a semiconductor thin film 42, a channel protective film 43, an ohmic contact layer 44, and a source / drain electrode 10. Yes. Thus, the photoelectric conversion type thin film transistor 3 is integrally formed on the glass substrate 1.

  Next, the external connection terminal 7 will be described. The external connection terminal 7 made of aluminum is provided on the upper surface of the first interlayer insulating film 30, and has an overcoat film 41, a third interlayer insulating film 40, a top gate insulating film 39, a bottom gate insulating film 38, and a second gate insulating film 38. It is exposed through an opening 45 provided in the interlayer insulating film 37.

  Next, the first to fifth interlayer contact portions will be described. In the first interlayer contact portion, the first upper layer connection wiring 46 provided on the upper surface of the first interlayer insulating film 30 and provided in the same layer as the conductor layers 35 and 36, and made of the same aluminum, Via the contact hole 47 provided in the first interlayer insulating film 30, the upper surface of the gate insulating film 27 is provided in the same layer as the gate electrodes 28 and 29 and is made of the same molybdenum and is connected to the gate electrodes 28 and 29. The first lower layer connection wiring 48 is connected to the connection pad portion.

  In the second interlayer contact portion, the second upper layer connection wiring 49 made of molybdenum provided on the upper surface of the third interlayer insulating film 40 includes the third interlayer insulating film 40, the top gate insulating film 39, and the bottom. Via the contact hole 50 provided in the gate insulating film 38 and the second interlayer insulating film 37, it is provided in the same layer as the conductor layers 35 and 36 on the upper surface of the first interlayer insulating film 30, and is made of the same aluminum. The second lower layer connection wiring 51 is connected to the connection pad portion. Here, the second upper layer connection wiring 49 includes a portion formed on the upper surface of the third interlayer insulating film 40 and a portion filled in the contact hole 50.

  In the third interlayer contact portion, the third upper layer connection wiring 52 made of molybdenum provided on the upper surface of the third interlayer insulating film 40 includes the third interlayer insulating film 40, the top gate insulating film 39, and the bottom. Connection of a third lower layer connection wiring 54 made of the same chromium and provided in the same layer as the bottom gate electrode 9 on the upper surface of the second interlayer insulating film 37 through a contact hole 53 provided in the gate insulating film 38. Connected to the pad section. Here, the third upper layer connection wiring 52 includes a portion formed on the upper surface of the third interlayer insulating film 40 and a portion filled in the contact hole 53.

  In the fourth interlayer contact portion, the fourth upper layer connection wiring 55 made of molybdenum provided on the upper surface of the third interlayer insulating film 40 is provided in the third interlayer insulating film 40 and the top gate insulating film 39. The contact hole 56 is provided on the upper surface of the bottom gate insulating film 38 in the same layer as the source / drain electrode 10 and connected to the connection pad portion of the fourth lower layer connection wiring 57 made of the same chromium. . That is, the fourth upper layer connection wiring 55 includes a portion formed on the upper surface of the third interlayer insulating film 40 and a portion filled in the contact hole 56.

  In the fifth interlayer contact portion, the fifth upper layer connection wiring 58 made of molybdenum provided on the upper surface of the third interlayer insulating film 40 has a contact hole 59 provided in the third interlayer insulating film 40. Accordingly, the upper gate insulating film 39 is provided in the same layer as the top gate electrode 8 on the upper surface, and is connected to the connection pad portion of the fifth lower layer connection wiring 60 made of the same ITO. Here, the fifth upper layer connection wiring 58 includes a portion formed on the upper surface of the third interlayer insulating film 40 and a portion filled in the contact hole 59.

  Next, the electrical connection of each part shown in FIG. 2 will be described. The bottom gate electrode 9 of the photoelectric conversion type thin film transistor 3 is formed by connecting the conductor layers of the third lower layer connection wiring 54, the third upper layer connection wiring 52, the second upper layer connection wiring 49 and the second lower layer connection wiring 51. Through the bottom gate line 12 shown in FIG. 1, the source / drain electrodes 35 and 36 of the thin film transistors 21 and 22 of the second drive circuit section (bottom gate driver) 5 are connected.

  One source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected to the fourth lower layer connection wiring 57, the fourth upper layer connection wiring 55, the second upper layer connection wiring 49, and the second lower layer connection wiring 51. It is connected to the source / drain electrodes 35 and 36 of the thin film transistors 21 and 22 of the third drive circuit section (drain driver) 6 through the body layer, that is, through the drain line 13 shown in FIG.

  The other source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected to the fourth lower layer connection wiring 57, the fourth upper layer connection wiring 55, the second upper layer connection wiring 49, and the second lower layer connection wiring 51. It is connected to the grounding external connection terminal among the external connection terminals 7 via the body layer, that is, via a ground line (not shown in FIG. 1).

  The top gate electrode 8 of the photoelectric conversion type thin film transistor 3 includes the conductor layers of the fifth lower layer connection wiring 60, the fifth upper layer connection wiring 58, the second upper layer connection wiring 49 and the second lower layer connection wiring 51. Through the top gate line 11 shown in FIG. 1, the source / drain electrodes 35 and 36 of the thin film transistors 21 and 22 of the first drive circuit section (top gate driver) 4 are connected.

  The gate electrodes 28 and 29 of the thin film transistors 21 and 22 for the drive circuit section are connected to the external connection terminal 7 via the first lower layer connection wiring 48 and the first upper layer connection wiring 46. The source / drain electrodes 35 and 36 of the thin film transistors 21 and 22 for the drive circuit section are connected to the external connection terminal 7 through connection wiring (not shown) provided on the upper surface of the first interlayer insulating film 30. ing.

  Here, the conductor layers forming the second to fifth upper layer connection wirings 49, 52, 55, and 58 in the present embodiment are provided to cover the top gate electrode 8 of the photoelectric conversion type thin film transistor 3. The upper surface of the interlayer insulating film 40 is provided. The second to fifth upper layer connection wirings 49, 52, 55, and 58 are the bottom gate electrode 9, the source / drain electrode 10, the top gate electrode 8 of the photoelectric conversion type thin film transistor 3, and the thin film transistor for the driving circuit section. The conductive layers 35 and 36 including the source / drain electrodes 21 and 22 are formed of a different conductive layer.

  Next, an example of a method for manufacturing the thin film transistor panel will be described. First, as shown in FIG. 3, a first base insulating film 23 (thickness of about 2000 mm) made of silicon nitride and a second base insulating film 24 made of silicon oxide are formed on the upper surface of the glass substrate 1 by plasma CVD. (A film thickness of about 1000 mm) and an amorphous silicon thin film 61 (film thickness of about 500 mm) are continuously formed. Here, the step of forming the amorphous silicon thin film 61 is performed under a temperature condition (second temperature condition) in which about 300 ° C. is the maximum temperature.

  Next, in order to remove the hydrogen contained in the amorphous silicon thin film 61 formed by plasma CVD with a high hydrogen content, a dehydrogenation process is performed for about 1 hour at a temperature of about 500 ° C. in a nitrogen gas atmosphere. This dehydrogenation treatment is performed in order to avoid the occurrence of defects due to bumping of hydrogen in the amorphous silicon thin film 61 when high energy is given to the amorphous silicon thin film 61 by excimer laser irradiation in a subsequent process. is there.

  Next, by irradiating the amorphous silicon thin film 61 with an excimer laser from the upper surface side, the amorphous silicon thin film 61 is crystallized to form a polysilicon thin film 62. Here, the step of crystallizing the amorphous silicon thin film 61 to form the polysilicon thin film 62 is performed under a temperature condition (first temperature condition) where the maximum temperature is approximately 600 ° C.

  Next, by patterning the polysilicon thin film 62 by photolithography, semiconductor thin films 25 and 26 are formed as shown in FIG. Next, as shown in FIG. 5, a gate insulating film 27 (thickness of about 1000 mm) made of silicon oxide is formed on the upper surface of the second base insulating film 24 including the semiconductor thin films 25 and 26 by plasma CVD. To do. Next, a conductor layer made of a molybdenum film (having a film thickness of about 3000 mm) formed by sputtering is patterned on the upper surface of the gate insulating film 27 by photolithography, whereby the gate electrodes 28 and 29 and the first electrode are formed. A lower layer connection wiring 48 is formed.

Next, as shown in FIG. 6, a p-type impurity is formed using a first resist pattern (not shown) formed by photolithography and having an opening in a portion corresponding to the source / drain region 26b as a mask. Inject at high concentration. As an example, boron ions are implanted under conditions of an acceleration energy of 30 keV and a dose of 3 × 10 ¹⁵ atm / cm ² . As a result, the semiconductor thin film 26 has a channel region 26a made of an intrinsic region under the gate electrode 29 and source / drain regions 26b made of p-type impurity high concentration regions on both sides thereof. Thereafter, the first resist pattern is peeled off.

Next, an n-type impurity is implanted at a high concentration using a second resist pattern (not shown) having an opening in a portion corresponding to the source / drain region 25c formed by photolithography. As an example, phosphorus ions are implanted under the conditions of an acceleration energy of 70 keV and a dose amount of 3 × 10 ¹⁵ atm / cm ² . Thereafter, the second resist pattern is peeled off.

Next, an n-type impurity is implanted at a low concentration using a third resist pattern (not shown) formed by photolithography and having an opening in a portion corresponding to the source / drain region 25b as a mask. As an example, phosphorus ions are implanted under the conditions of an acceleration energy of 70 keV and a dose of 3 × 10 ¹³ atm / cm ² . Thereafter, the third resist pattern is peeled off.

  As a result, the semiconductor thin film 25 includes a channel region 25a made of an intrinsic region under the gate electrode 28, source / drain regions 25b made of n-type impurity low concentration regions on both sides thereof, and n-type impurity high concentration regions on both sides thereof. And a source / drain region 25c.

  Next, implanted ion activation treatment is performed in a nitrogen gas atmosphere at a temperature of about 450 ° C. for about 1 hour. Here, the respective ion implantation steps using the first to third resist patterns as masks are not particularly limited to the above order, and may be performed in any order, and other methods such as gates are used. A method including an ion implantation process using the electrodes 28 and 29 as a mask may be used.

  Next, as shown in FIG. 7, on the upper surface of the gate insulating film 27 including the gate electrodes 28 and 29 and the first lower layer connection wiring 48, the first interlayer insulating film 30 ( A film thickness of about 3000 mm is formed. Next, contact holes 33 and 34 are continuously formed in the first interlayer insulating film 30 and the gate insulating film 27 on the source / drain regions 25c and 26b of the semiconductor thin films 25 and 26 by a photolithography method. A contact hole 47 is formed in the first interlayer insulating film 30 on the connection pad portion of the first lower layer connection wiring 48.

  Next, a conductor layer made of an aluminum film (with a film thickness of about 5000 mm) is formed on the upper surface of the first interlayer insulating film 30 by sputtering, filling the contact holes 33, 34, and 47, and by photolithography. By patterning, the conductor layers 35 and 36 are formed to be connected to the source / drain regions 25c and 26b through the contact holes 33 and 34, thereby forming the source / drain electrodes and wirings connected thereto. Further, the first upper layer connection wiring 46 is formed to be connected to the connection pad portion of the first lower layer connection wiring 48 through the contact hole 47, and the external connection terminal 7, the second lower layer connection wiring 51, and the conductor layer. Connection wiring (not shown) for connecting 35 and 36 and the external connection terminal 7 is formed.

  Next, as shown in FIG. 8, on the upper surface of the first interlayer insulating film 30 including the external connection terminal 7, the conductor layers 35 and 36, the first upper layer connection wiring 46, and the second lower layer connection wiring 51, A second interlayer insulating film 37 (thickness of about 3000 mm) made of silicon nitride is formed by plasma CVD. Next, a conductive layer made of a chromium film (having a film thickness of about 1000 mm) formed by sputtering is patterned on the upper surface of the second interlayer insulating film 37 by photolithography, so that the bottom gate electrode 9 and the second gate electrode 9 and the second interlayer insulating film 37 are patterned. 3 lower connection wirings 54 are formed.

  Next, as shown in FIG. 9, a bottom gate insulating film 38 (made of silicon nitride) is formed on the upper surface of the second interlayer insulating film 37 including the bottom gate electrode 9 and the third lower layer connection wiring 54 by plasma CVD. The semiconductor thin film forming layer 42a (thickness of about 500 mm) made of intrinsic amorphous silicon and the channel protective film forming layer 43a (thickness of about 1000 mm) made of silicon nitride are successively formed. In this case, the semiconductor thin film forming layer 42a made of intrinsic amorphous silicon is formed under a temperature condition of about 300 ° C. as in the case of forming the amorphous silicon thin film 61 shown in FIG.

  Next, the channel protective film formation layer 43a is patterned by photolithography, thereby forming the channel protective film 43 as shown in FIG. Next, as shown in FIG. 11, an ohmic contact layer forming layer 44a (film thickness of about 250 mm) made of n-type amorphous silicon is formed on the upper surface of the semiconductor thin film forming layer 42a including the channel protective film 43 by plasma CVD. Is deposited. Also in this case, the ohmic contact layer forming layer 44a made of n-type amorphous silicon is formed under a temperature condition of about 300 ° C. as in the case of forming the amorphous silicon thin film 61 shown in FIG.

  Next, the ohmic contact layer forming layer 44a and the semiconductor thin film forming layer 42a are successively patterned by a photolithography method to form the ohmic contact layer 44 and the semiconductor thin film 42 as shown in FIG. Next, as shown in FIG. 13, a conductor layer made of a chromium film (having a thickness of about 500 mm) formed by sputtering is formed on the upper surfaces of the ohmic contact layer 44 and the bottom gate insulating film 38 by photolithography. Thus, the source / drain electrodes 10 and the fourth lower layer connection wiring 57 are formed.

  Next, as shown in FIG. 14, a top gate insulating film 39 (film) made of silicon nitride is formed on the upper surface of the bottom gate insulating film 38 including the source / drain electrodes 10 and the fourth lower layer connection wiring 57 by plasma CVD. A film having a thickness of about 3000 mm is formed. Next, a conductive layer made of an ITO film (having a thickness of about 500 mm) formed by sputtering is patterned on the top surface of the top gate insulating film 39 by photolithography, whereby the top gate electrode 8 and the fifth gate A lower layer connection wiring 60 is formed.

  Next, as shown in FIG. 15, a third interlayer insulating film 40 (made of silicon nitride) is formed on the upper surface of the top gate insulating film 39 including the top gate electrode 8 and the fifth lower layer connection wiring 60 by plasma CVD. A film thickness of about 2000 mm) is formed.

  Next, the third interlayer insulating film 40, the top gate insulating film 39, the bottom gate insulating film 38, and the second interlayer insulating film 37 on the connection pad portion of the second lower layer connection wiring 51 are contacted by photolithography. The hole 50 is formed continuously, and the contact hole 53 is continuously formed in the third interlayer insulating film 40, the top gate insulating film 39, and the bottom gate insulating film 38 on the connection pad portion of the third lower layer connection wiring 54. The contact hole 56 is continuously formed in the third interlayer insulating film 40 and the top gate insulating film 39 on the connection pad portion of the fourth lower layer connection wiring 57, and the fifth lower connection wiring 60 is further formed. A contact hole 59 is formed in the third interlayer insulating film 40 on the connection pad portion.

  Next, a conductor layer made of a molybdenum film (thickness of about 5000 mm) is formed on the upper surface of the third interlayer insulating film 40 by sputtering, and the contact holes 50, 53, 56, 59 are filled, and photolithography is performed. By patterning by the method, the second upper layer connection wiring 49 is formed to be connected to the connection pad portion of the second lower layer connection wiring 51 through the contact hole 50, and the third upper layer connection wiring 52 is formed in the contact hole. 53 and connected to the connection pad portion of the third lower layer connection wiring 54, and the fourth upper layer connection wiring 55 is connected to the connection pad portion of the fourth lower layer connection wiring 57 through the contact hole 56. Further, the fifth upper layer connection wiring 58 is connected to the connection pad portion of the fifth lower layer connection wiring 60 through the contact hole 59.

  Next, as shown in FIG. 2, an overcoat made of silicon nitride is formed on the upper surface of the third interlayer insulating film 40 including the second to fifth upper layer connection wirings 49, 52, 55, 58 by plasma CVD. A film 41 (film thickness of about 6000 mm) is formed. Next, an opening is formed in the overcoat film 41, the third interlayer insulating film 40, the top gate insulating film 39, the bottom gate insulating film 38, and the second interlayer insulating film 37 on the external connection terminal 7 by photolithography. 45 is formed continuously. Thus, the thin film transistor panel shown in FIG. 2 is obtained.

  In the above manufacturing method, the semiconductor thin film 42 made of amorphous silicon of the photoelectric conversion type thin film transistor 3 is provided on the upper layer side of the semiconductor thin films 25 and 26 made of polysilicon of the thin film transistors 21 and 22 for the drive circuit section. After forming the semiconductor thin films 25 and 26 made of polysilicon of the thin film transistors 21 and 22 for the driving circuit section, the semiconductor thin film 42 made of amorphous silicon of the photoelectric conversion type thin film transistor 3 may be formed on the upper layer, and thus the formation is completed. The entire amorphous silicon thin film 61 formed may be crystallized to form the polysilicon thin film 62. As in the prior art, specific regions of the formed amorphous silicon thin film are selectively crystallized. This eliminates the need for such processes, simplifies the process, and reduces manufacturing costs. It is possible to reduce the.

  Further, in the above manufacturing method, the semiconductor thin film 42 of the photoelectric conversion type thin film transistor 3 is formed on the upper side of the semiconductor thin films 25 and 26 of the thin film transistors 21 and 22 for the driving circuit section, and the thin film transistors 21 and 22 for the driving circuit section are formed. Since the photoelectric conversion type thin film transistor 3 is formed separately in different layers, the thin film transistors 21 and 22 for the drive circuit section and the photoelectric conversion type thin film transistor 3 can be disposed sufficiently close to each other, and the entire apparatus Can be further reduced, and as a result, the entire apparatus can be further miniaturized.

  In the above manufacturing method, as shown in FIG. 3, the amorphous silicon thin film 61 is formed at a relatively low temperature condition (approximately about 300 ° C.), and then the amorphous silicon thin film 61 is crystallized to form a polysilicon thin film 62. This step is performed under a relatively high temperature condition (approximately 600 ° C.), and as shown in FIG. 9, the amorphous silicon thin film 42a is formed under a relatively low temperature condition (approximately 300 ° C.). Each element characteristic of the thin film transistors 21 and 22 for the circuit portion and the photoelectric conversion type thin film transistor 3 can be maintained well.

  That is, contrary to the above, after the amorphous silicon thin film 42a is formed at a relatively low temperature condition (approximately 300 ° C.) and then the semiconductor thin film 42 is formed, the amorphous silicon thin film 61 is formed at a relatively low temperature condition (approximately When the step of forming the polysilicon thin film 62 by crystallizing the amorphous silicon thin film 61 and then forming the polysilicon thin film 62 at a relatively high temperature condition (approximately 600 ° C.) is performed first. Since dehydrogenation proceeds in the semiconductor thin film 42 made of amorphous silicon, sufficient electron mobility cannot be realized in the photoelectric conversion type thin film transistor 3, and there is a possibility that the element characteristics deteriorate.

  On the other hand, in the above manufacturing method, the semiconductor thin film 42 made of amorphous silicon that can be formed at a relatively low temperature after the semiconductor thin films 25 and 26 made of polysilicon that require a relatively high temperature condition are formed. Since it is formed, the element characteristics of the photoelectric conversion type thin film transistor 3 can be maintained well while the element characteristics of the thin film transistors 21 and 22 for the drive circuit section are maintained well.

  Further, in the above-described manufacturing method, as shown in FIG. 15, the bottom gate electrode 9, the source / drain electrode 10 and the top gate electrode 8 of the photoelectric conversion type thin film transistor 3, and the source / drain of the thin film transistors 21 and 22 for the driving circuit section. The second to fifth upper layer connection wirings 49, 52, 55, 58 for connecting the conductor layers 35, 36 connected to the electrodes are connected to any one of the steps of forming each electrode of the thin film transistor 3 and the thin film transistors 21, 22. In both cases, since the layers are formed in different layers, the degree of freedom in routing the upper layer connection wiring is increased, and the density can be increased. In addition, it is possible to arbitrarily select a material (in the above case, molybdenum) and a film thickness (in the above case, about 5000 mm) used for the upper layer connection wiring.

(Second Embodiment)
FIG. 16 is a sectional view similar to FIG. 2 of a thin film transistor panel as a second embodiment of the present invention. In this thin film transistor panel, the difference from the case shown in FIG. 2 is that a second upper layer connection wiring 49 made of chromium is formed on the upper surface of the second interlayer insulating film 37 in the second interlayer contact portion. This is that the contact hole 50 provided in the insulating film 37 is connected to the connection pad portion of the second lower layer connection wiring 51 made of aluminum provided on the upper surface of the first interlayer insulating film 30. .

  In the case of manufacturing this thin film transistor panel, after forming the second interlayer insulating film 37 in the step shown in FIG. 8, as shown in FIG. 17, the second lower layer connection wiring 51 on the connection pad portion is formed. A contact hole 50 is formed in the second interlayer insulating film 37 by photolithography. Next, a conductor layer made of a chromium film is formed on the upper surface of the second interlayer insulating film 37 by filling the contact hole 50 and patterned by photolithography to form a second upper layer connection wiring. 49 is connected to the connection pad portion of the second lower layer connection wiring 51 through the contact hole 50, and the bottom gate electrode 9 and the third lower layer connection wiring 54 are formed. Since the following steps are substantially the same as those in the first embodiment, a description thereof will be omitted.

  In the second embodiment, as described above, the contact hole 50 is formed in the second interlayer insulating film 37 on the connection pad portion of the second lower layer connection wiring 51, and the second interlayer insulating film 37 is formed on the upper surface of the second interlayer insulating film 37. 2 is formed by connecting the upper layer connection wiring 49 to the connection pad portion of the second lower layer connection wiring 51 through the contact hole 50, so that the contact hole 50 is formed in the second region compared with the case shown in FIG. Therefore, the connection reliability of the second upper layer connection wiring 49 to the second lower layer connection wiring 51 can be improved.

(Third embodiment)
FIG. 18 is a sectional view similar to FIG. 2 of a thin film transistor panel as a third embodiment of the present invention. In this thin film transistor panel, the difference from the case shown in FIG. 2 is that a fifth upper layer connection wiring 58 made of ITO is formed on the top gate insulating film 39 on the top gate insulating film 39 in the fifth interlayer contact portion. This is that the contact hole 59 is provided to be connected to the connection pad portion of the fifth lower layer connection wiring 60 made of chromium provided on the upper surface of the bottom gate insulating film 38.

  In the case of manufacturing this thin film transistor panel, after the step shown in FIG. 12, as shown in FIG. 19, a conductive film made of a chromium film formed by sputtering on the ohmic contact layer 44 and the bottom gate insulating film 38 is formed. By patterning the body layer by photolithography, the source / drain electrodes 10 and the fourth and fifth lower layer connection wirings 57 and 60 are formed.

  Next, as shown in FIG. 20, the top gate made of silicon nitride is formed on the upper surface of the bottom gate insulating film 38 including the source / drain electrode 10 and the fourth and fifth lower layer connection wirings 57 and 60 by plasma CVD. An insulating film 39 is formed. Next, a contact hole 59 is formed in the top gate insulating film 39 on the connection pad portion of the fifth lower layer connection wiring 60 by photolithography.

  Next, a conductor layer made of an ITO film is formed on the upper surface of the top gate insulating film 39 by sputtering, the contact hole 59 is filled, and patterning is performed by photolithography, whereby a fifth upper layer connection wiring 58 is formed. Is connected to the connection pad portion of the fifth lower layer connection wiring 60 through the contact hole 59, and the top gate electrode 8 is formed. Since the following steps are substantially the same as those in the first embodiment, a description thereof will be omitted.

  By the way, in the thin film transistor panel shown in FIG. 18, the top gate electrode 8 of the photoelectric conversion type thin film transistor 3 includes the fifth upper layer connection wiring 58, the fifth lower layer connection wiring 60, the fourth lower layer connection wiring 57, and the fourth lower layer connection wiring 57. It is connected to the source / drain electrodes 35, 36 of the thin film transistors 21, 22 for the drive circuit section via the upper layer connection wiring 55, the second upper layer connection wiring 49, and the second lower layer connection wiring 51.

  In this case, since the fifth upper-layer connection wiring 58 made of ITO is connected to the connection pad portion of the fifth lower-layer connection wiring 60 made of chrome, in the step shown in FIG. When the fifth upper layer connection wiring 58 and the top gate electrode 8 are formed by patterning using an etching solution for the above, the fifth upper layer connection wiring 58 and the top gate electrode 8 made of ITO are oxidized by the battery reaction, The fifth lower layer connection wiring 60 made of chromium is reduced.

  However, since the ITO film is originally an oxide, even if the fifth upper layer connection wiring 58 and the top gate electrode 8 made of ITO are placed in an oxidized state, they are not substantially changed. Further, the fifth lower layer connection wiring 60 made of chromium is reduced, but does not change substantially. On the other hand, since the second to fourth upper layer connection wirings 49, 52, and 55 shown in FIG. 18 are not directly connected to the fifth upper layer connection wiring 58 made of ITO and the top gate electrode 8, the battery is connected to the second upper connection wirings. Corrosion due to reaction does not occur.

  That is, when it is necessary to prevent corrosion due to the battery reaction due to the connection with the ITO film, a relatively expensive single-layer structure of a refractory metal such as Mo, Cr, W, Ta, Ti or the like and Al and Although it was necessary to have a laminated structure, according to the configuration of the present embodiment, since it is not necessary to prevent corrosion due to battery reaction, the second to fourth upper layer connection wirings 49, 52, 55 are inexpensive and low. A single layer structure of Al with low resistance due to stress may be used. Thereby, the manufacturing cost can be reduced.

(Fourth embodiment)
FIG. 21 is a sectional view similar to FIG. 2 of a thin film transistor panel as a fourth embodiment of the present invention. The thin film transistor panel is different from the case shown in FIG. 2 in that it does not have the third interlayer insulating film 40 and is made of molybdenum on the upper surface of the top gate insulating film 39 in the second to fifth interlayer contact portions. The second to fifth upper layer connection wirings 49, 52, 55, 58 are provided, and the fifth upper layer connection wiring 68 among them is formed of the fifth lower layer connection wiring 60 made of ITO provided on the same surface. It is a point connected on the connection pad part. In this case, since the third interlayer insulating film 40 is not provided, the number of steps can be reduced accordingly.

(Fifth embodiment)
FIG. 22 is a sectional view similar to FIG. 2, of a thin film transistor panel as a fifth embodiment of the present invention. The thin film transistor panel is greatly different from the case shown in FIG. 2 in that the thin film transistors 21 and 22 for the drive circuit shown in FIG. 2 have a top gate structure, but a bottom gate structure. In this case, only the base insulating film 23 made of silicon nitride is provided on the upper surface of the glass substrate 1 as the base insulating film.

  Next, an example of a method for manufacturing the thin film transistor panel will be described. First, as shown in FIG. 23, a base insulating film 23 (film thickness of about 2000 mm) made of silicon nitride is formed on the upper surface of the glass substrate 1 by plasma CVD. Next, a conductive layer made of a molybdenum film (having a film thickness of about 1000 mm) formed by sputtering is patterned on the upper surface of the base insulating film 23 by photolithography, whereby the gate electrodes 28 and 29 and the first electrode are formed. A lower layer connection wiring 48 is formed.

  Next, on the upper surface of the base insulating film 23 including the gate electrodes 28 and 29 and the first lower layer connection wiring 48, a gate insulating film 27 (thickness of about 1000 mm) made of silicon oxide and an amorphous silicon thin film 61 are formed by plasma CVD. (Film thickness of about 500 mm) is continuously formed. Also in this case, the step of forming the amorphous silicon thin film 61 is performed under a temperature condition where the maximum temperature is approximately 300 ° C. Next, dehydrogenation treatment is performed for about 1 hour at a temperature of about 500 ° C. in a nitrogen gas atmosphere.

  Next, by irradiating the amorphous silicon thin film 61 with an excimer laser from the upper surface side, the amorphous silicon thin film 61 is crystallized to form a polysilicon thin film 62. Also in this case, the process of crystallizing the amorphous silicon thin film 61 to form the polysilicon thin film 62 is performed under temperature conditions where the maximum temperature is approximately 600 ° C.

Next, a p-type impurity is implanted at a high concentration using a first resist pattern (not shown) formed by photolithography and having an opening in a portion corresponding to the source / drain region 26b. As an example, boron ions are implanted under the conditions of an acceleration energy of 10 keV and a dose of 1 × 10 ¹⁵ atm / cm ² . Thereafter, the first resist pattern is peeled off.

Next, an n-type impurity is implanted at a high concentration using a second resist pattern (not shown) having an opening in a portion corresponding to the source / drain region 25c formed by photolithography. As an example, phosphorus ions are implanted under the conditions of an acceleration energy of 10 keV and a dose of 1 × 10 ¹⁵ atm / cm ² . Thereafter, the second resist pattern is peeled off.

Next, an n-type impurity is implanted at a low concentration using a third resist pattern (not shown) formed by photolithography and having an opening in a portion corresponding to the source / drain region 25b as a mask. As an example, phosphorus ions are implanted under the conditions of an acceleration energy of 10 keV and a dose of 1 × 10 ¹³ atm / cm ² . Thereafter, the third resist pattern is peeled off. Next, implanted ion activation treatment is performed in a nitrogen gas atmosphere at a temperature of about 450 ° C. for about 1 hour.

  Next, as shown in FIG. 24, semiconductor thin films 25 and 26 are formed by patterning the polysilicon thin film 62 by photolithography. In this state, the semiconductor thin film 25 includes a channel region 25a composed of an intrinsic region on the gate electrode 28, a source / drain region 25b composed of n-type impurity low concentration regions on both sides thereof, and a high n-type impurity concentration on both sides thereof. It has a source / drain region 25c composed of a region. The semiconductor thin film 26 has a channel region 26a made of an intrinsic region on the gate electrode 29 and source / drain regions 26b made of p-type impurity high concentration regions on both sides thereof.

  Next, as shown in FIG. 25, on the upper surface of the gate insulating film 27 including the semiconductor thin films 25 and 26, a first interlayer insulating film 30 (thickness of about 3000 mm) made of silicon oxide is formed by plasma CVD. To do. Next, contact holes 33 and 34 are formed in the first interlayer insulating film 30 on the source / drain regions 25c and 26b of the semiconductor thin films 25 and 26 by photolithography, and the connection of the first lower layer connection wiring 48 is performed. Contact holes 47 are continuously formed in the first interlayer insulating film 30 and the gate insulating film 27 on the pad portion.

  Next, a conductor layer made of an aluminum film (with a film thickness of about 5000 mm) is formed on the upper surface of the first interlayer insulating film 30 by sputtering, filling the contact holes 33, 34, and 47, and by photolithography. By patterning, the conductor layers 35 and 36 are formed to be connected to the source / drain regions 25c and 26b through the contact holes 33 and 34, and the first upper layer connection wiring 46 is formed through the contact hole 47. 1 is formed by connecting to the connection pad portion of the first lower layer connection wiring 48, and further, the external connection terminal 7, the second lower layer connection wiring 51 and the connection wiring for connecting the source / drain electrodes 35, 36 and the external connection terminal 7 ( (Not shown). Since the following steps are the same as those in the first embodiment, a description thereof will be omitted.

  In the above manufacturing method, as shown in FIG. 23, boron ions and phosphorus ions are directly implanted into the polysilicon semiconductor thin film 62, so that it is inexpensive without using an expensive high acceleration (up to 80 keV) ion implantation apparatus. Boron ions and phosphorus ions can be implanted using a low-acceleration (-10 keV) ion implantation apparatus.

  The ion implantation and activation treatment may be performed after the device area is formed as shown in FIG. Here, also in the first embodiment, the ion implantation and activation treatment may be performed after forming the polysilicon thin film 62 as shown in FIG. 3, and as shown in FIG. You may carry out after forming.

(Other embodiments)
In each of the above-described embodiments, the case where the drive circuit unit is configured by a CMOS thin film transistor made of a polysilicon thin film transistor has been described. However, the present invention is not limited thereto, and may be configured by only an NMOS thin film transistor. You may make it comprise by a combination with a thin-film transistor.

  In each of the above embodiments, the external connection terminal 7 has a single-layer structure made of aluminum at the same time as the formation of 35 and 36 connected to the source / drain electrodes made of aluminum of the thin film transistors 21 and 22 for the drive circuit section. Although the case where it is formed is not limited to this, it may be formed simultaneously with the formation of an electrode on another layer (for example, the bottom gate electrode 9), or may be formed simultaneously with the formation of an electrode on a plurality of layers. It is good also as a structure.

  Further, for example, in the first embodiment (see FIG. 2), the first to third interlayer insulating films 30, 37, and 40 may be a single layer of a silicon oxide film instead of a single layer of a silicon nitride film. In addition, a multi-layered structure may be used. Further, for example, in the fifth embodiment (see FIG. 22), the gate insulating film 27 is not a single layer of a silicon oxide film, but may have a two-layer structure of a lower silicon nitride film and an upper silicon oxide film. In addition, the first interlayer insulating film 30 may not be a single layer of a silicon oxide film but may have a two-layer structure of a lower silicon oxide film and an upper silicon nitride film, and the second and third layers. The interlayer insulating films 37 and 40 may be a single layer of a silicon oxide film instead of a single layer of a silicon nitride film, or may have a plurality of types of laminated structures.

  Further, in each of the above embodiments, the case where the thin film transistor panel of the present invention is applied to an image reading apparatus has been described. However, the present invention is not limited to this. In short, a thin film transistor panel having a structure in which amorphous silicon thin film transistors are arranged in a matrix in a predetermined region on a substrate and a polysilicon thin film transistor for driving the amorphous silicon thin film transistor is disposed in a peripheral region adjacent to the predetermined region. I just need it.

  For example, a well-known display pixel including a light emitting element such as a liquid crystal capacitor or an organic EL element in a predetermined region on a substrate (specifically, a liquid crystal pixel composed of a liquid crystal capacitor and a pixel transistor, an organic EL element and a pixel driving circuit) Are arranged in a matrix, and each display pixel is set in a selected state in a peripheral region adjacent to the predetermined region, and a predetermined gradation signal is supplied to the display pixel. The present invention can also be applied to a known image display device provided with a driver (scanning driver, data driver, power supply driver, etc.) that controls to display the image information.

The equivalent circuit top view of the principal part of the thin-film transistor panel as 1st Embodiment of this invention. FIG. 2 is a cross-sectional view illustrating a specific structure of part of the thin film transistor panel illustrated in FIG. 1. FIG. 3 is a cross-sectional view of an initial process in manufacturing the thin film transistor panel shown in FIG. 2. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 15 is a sectional view of a step following FIG. 14. Sectional drawing similar to FIG. 2 of the thin-film transistor panel as 2nd Embodiment of this invention. FIG. 17 is a cross-sectional view of a predetermined process in manufacturing the thin film transistor panel shown in FIG. 16. Sectional drawing similar to FIG. 2 of the thin-film transistor panel as 3rd Embodiment of this invention. FIG. 19 is a cross-sectional view of a predetermined process in manufacturing the thin film transistor panel shown in FIG. 18. FIG. 20 is a cross-sectional view of the process following FIG. 19. Sectional drawing similar to FIG. 2 of the thin-film transistor panel as 4th Embodiment of this invention. Sectional drawing similar to FIG. 2 of the thin-film transistor panel as 5th Embodiment of this invention. FIG. 23 is a cross-sectional view of an initial process in manufacturing the thin film transistor panel shown in FIG. 22. FIG. 24 is a sectional view of a step following FIG. 23. FIG. 25 is a sectional view of a step following FIG. 24.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Image reading area 3 Photoelectric conversion type thin-film transistor 4-6 Drive circuit part 7 External connection terminal 8 Top gate electrode 9 Bottom gate electrode 10 Source / drain electrode 11 Top gate line 12 Bottom gate line 13 Drain line 21, 22 Thin film transistor for driving circuit 25, 26 Semiconductor thin film 28, 29 Gate electrode 35, 36 Conductor layer including source / drain electrodes 42 Semiconductor thin film 43 Channel protective film 44 Ohmic contact layer 46, 49, 52, 55, 58 First -Fifth upper layer connection wiring 48, 51, 54, 57, 60 First to fifth lower layer connection wiring

Claims (15)

On a substrate, a thin film transistor panel provided with a polysilicon thin film transistor having a semiconductor thin film made of polysilicon and a plurality of electrodes, and an amorphous silicon thin film transistor having a semiconductor thin film made of amorphous silicon and a plurality of electrodes,
A first wiring connected to any of the plurality of electrodes of the polysilicon thin film transistor, provided in the same layer with the same conductive material as the electrode, and having a connection pad;
A semiconductor thin film made of amorphous silicon provided above the first wiring via an insulating film;
A plurality of second wires having connection pads;
A plurality of third wirings provided in the same layer;
With
One second wiring of the plurality of second wirings is connected to one electrode of the plurality of electrodes of the amorphous silicon thin film transistor, and the one conductive material is the same as the one electrode. In the same layer as the electrode of
Another second wiring different from the one second wiring among the plurality of second wirings is formed in a layer different from the one electrode among the plurality of electrodes of the amorphous silicon thin film transistor. Connected to the other electrode, provided in the same layer as the other electrode with the same conductive material as the other electrode,
The plurality of third wirings are provided such that at least one insulating film is interposed between the plurality of third wirings and the plurality of second wirings, and each electrode of the amorphous silicon thin film transistor is It is made of a different conductive material, and is electrically connected to the plurality of second wirings via a plurality of contact holes provided at locations corresponding to the connection pads of the second wiring of the insulating film. A thin film transistor panel. In the invention of claim 1,
The amorphous silicon thin film transistor has a gate electrode provided via an insulating film at least above the semiconductor thin film made of amorphous silicon,
The thin film transistor panel, wherein the third wiring is provided on an insulating film provided to cover the gate electrode. In the invention of claim 1,
An upper portion of the first wiring is provided via an insulating film, and the second wiring or the second wiring is provided via a contact hole provided at a location corresponding to the connection pad of the first wiring of the insulating film. A thin film transistor panel, comprising: a fourth wiring electrically connected to any one of the three wirings. In the invention of claim 1,
The amorphous silicon thin film transistor is a double gate type thin film transistor having a top gate electrode and a bottom gate electrode provided above and below the semiconductor thin film via an insulating film, respectively. In the invention of claim 4 ,
The thin film transistor panel, wherein the second wiring is provided in the same layer with the same conductive material as any of the top gate electrode, the bottom gate electrode, and the source / drain electrode of the amorphous silicon thin film transistor. In the invention of claim 4 ,
The thin film transistor panel, wherein the third wiring is provided on an insulating film provided so as to cover a top gate electrode of the amorphous silicon thin film transistor. In the invention of claim 1,
The thin film transistor panel, wherein the polysilicon thin film transistor is a top gate type. In the invention of claim 1,
The thin film transistor panel, wherein the polysilicon thin film transistor is a bottom gate type. In the invention of claim 1,
The amorphous silicon thin film transistors are arranged in a matrix in a predetermined region on the substrate,
The thin film transistor panel, wherein the polysilicon thin film transistor is disposed in a peripheral region adjacent to the predetermined region on the substrate to constitute a drive circuit unit for driving the amorphous silicon thin film transistor. In a method of manufacturing a thin film transistor panel in which a semiconductor thin film made of polysilicon and a polysilicon thin film transistor having a plurality of electrodes and an amorphous silicon thin film transistor having a semiconductor thin film made of amorphous silicon and a plurality of electrodes are provided on a substrate,
Forming a semiconductor thin film made of polysilicon on the substrate;
Forming the polysilicon thin film transistor using the semiconductor thin film made of polysilicon;
Forming a first wiring connected to any of the plurality of electrodes of the polysilicon thin film transistor and made of the same conductive material as the electrode and having a connection pad simultaneously with the electrode;
Forming a semiconductor thin film made of amorphous silicon over an insulating film above the first wiring;
Forming the amorphous silicon thin film transistor using a semiconductor thin film made of the amorphous silicon;
Forming a plurality of second wirings having connection pads;
Forming an insulating film on top of the second wiring, and forming a contact hole provided at a location corresponding to each connection pad of the second wiring of the insulating film;
A third wiring is formed on the insulating film corresponding to the contact hole with a conductive material different from that of each electrode of the amorphous silicon thin film transistor, and the third wiring and the second wiring are formed through the contact hole. Electrically connecting
Including
Forming the plurality of second wirings includes:
One second wiring of the plurality of second wirings is connected to one electrode of the plurality of electrodes of the amorphous silicon thin film transistor, and the same conductive material as the one electrode is used to Forming simultaneously with one electrode,
Another second wiring different from the one second wiring among the plurality of second wirings is connected to another electrode different from the one electrode among the plurality of electrodes of the amorphous silicon thin film transistor. A method of manufacturing a thin film transistor panel, comprising: forming the same electrode simultaneously with the other electrode by using the same conductive material as the other electrode. In the invention of claim 10 ,
The step of forming the semiconductor thin film made of polysilicon is performed under a first temperature condition,
The method of manufacturing a thin film transistor panel, wherein the step of forming the semiconductor thin film made of amorphous silicon is performed under a second temperature condition where a maximum temperature is lower than the first temperature condition. In the invention of claim 10 ,
The amorphous silicon thin film transistor has a gate electrode provided via an insulating film at least above the semiconductor thin film made of amorphous silicon,
A method of manufacturing a thin film transistor panel, comprising: forming the third wiring on an insulating film formed so as to cover the gate electrode. In the invention of claim 10 ,
Forming an insulating film on top of the first wiring, and forming a contact hole provided at a location corresponding to the connection pad of the first wiring of the insulating film;
A fourth wiring electrically connected to either the second wiring or the third wiring is formed on the insulating film corresponding to the contact hole, and the first wiring is formed through the contact hole. Electrically connecting a wiring and the second wiring or the third wiring;
A method for producing a thin film transistor panel, comprising: In the invention of claim 10 ,
The method of manufacturing a thin film transistor panel, wherein the amorphous silicon thin film transistor comprises a double gate type thin film transistor having a top gate electrode and a bottom gate electrode provided above and below the semiconductor thin film via an insulating film, respectively. . In the invention of claim 14 ,
A method of manufacturing a thin film transistor panel, wherein the third wiring is formed on an insulating film provided so as to cover the top gate electrode.

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