JP2742747B2 - Multilayer semiconductor integrated circuit having thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multilayer semiconductor integrated circuit (also referred to as a three-dimensional semiconductor integrated circuit or a three-dimensional semiconductor integrated circuit).

[0002]

2. Description of the Related Art In recent years, in order to improve the degree of integration of a semiconductor integrated circuit, a multilayer integrated circuit having a multilayer structure of an integrated circuit has been proposed. As such a multi-layer integrated circuit, it is simple to form a single semiconductor element layer on a single crystal substrate such as a silicon wafer and bond a large number of wafers with an adhesive or the like. Is difficult to form wiring between layers. For example, it is suitable for those having few bus lines between layers, such as using the first layer as a microprocessor and the second and third layers as a memory. It is not suitable for a unit having a very large number of wirings between units such as a so-called neuron circuit. In addition, it is difficult to cool the layer sandwiched between the substrates in terms of removing heat generated by the element.

[0003]

Therefore, a method of forming a multi-layered semiconductor integrated circuit on one substrate has been considered, but it has not been put to practical use due to a problem in fabrication. In other words, even when an attempt is made to form such a multilayer integrated circuit with the aid of the conventional integrated circuit technology, it is necessary to suppress the heat generation of the integrated circuit. However, since the normally used silicon gate wiring has a high resistance, not only the signal delay time is increased, but also a large amount of heat is generated. Moreover, in the conventional process, the activation of the semiconductor layer requires 600
Since a high temperature of １1100 ° C. was required, in a normal single-layer integrated circuit, it was necessary to use heat-resistant alloy wiring such as silicon or tungsten even in a portion where metal wiring was used.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has been made to use a low-resistance metal wiring mainly composed of aluminum for the gate wiring and other wirings. To the gist. The use of such a low-resistance material not only suppresses the heat generation of the integrated circuit, but also cools aluminum by conducting heat generated inside to the outside because aluminum has relatively good thermal conductivity. The effect is expected.

However, if it is necessary to go through a process of activating a semiconductor at a high temperature as in the conventional method, a material such as aluminum is not suitable. Therefore, in the present invention, an instantaneous annealing method such as pulse laser annealing or flash lamp annealing is adopted as a new low-temperature process. In these annealing methods, the semiconductor is instantaneously heated to a high temperature by irradiating a laser or an intense light equivalent thereto to activate the semiconductor, and the gate wiring and the lower layer are less thermally damaged. In particular, the inventors of the present invention disclosed in Japanese Patent Application Nos. 3-237100 and 3-238.
As indicated by reference numeral 713, when the periphery of the aluminum gate electrode is covered with an aluminum oxide film by anodization, the resistance to the impact of laser irradiation increases. Further, the purity of the aluminum film may be increased to suppress grain growth and increase the reflectivity of the surface of the aluminum wiring. The anodic oxide film is also important in forming an offset region for the source / drain, which performs the same function as the conventional LDD.

There are other advantages when using a method such as laser annealing. In such a multilayer integrated circuit, the flatness of the interlayer insulator is important. That is, when the interlayer insulator is rich in undulations, a defect such as disconnection is likely to occur in an integrated circuit thereon. In ordinary integrated circuit technology, phosphorus glass or phosphorus boron glass deposited by the CVD method is reflowed, but flattening is still insufficient, and a high temperature of 1000 ° C. or more is required. On the other hand, for example, an organic material such as polyimide can be easily formed by a spin coating method, and therefore, is preferably flat. However, from the viewpoint of heat resistance, polyimide cannot be used in an activation process requiring a high temperature as in the past. Therefore, when polyimide is used as an interlayer insulating material, a low-temperature activation technique such as laser annealing is required. Conversely, if the laser annealing technique is used, sufficient planarization can be performed at a low temperature by using a material such as polyimide.

[0007] Such a multilayer integrated circuit may be formed on a single crystal semiconductor wafer, or may be formed on an insulating substrate. On an insulating substrate, there is no capacity loss between the substrate and the wiring, signal propagation is good, and high-speed operation is possible.

[0008] In such a multilayer integrated circuit, the biggest problem is the formation of contacts between layers. In particular, since the interlayer insulator needs to be formed sufficiently thick so that the semiconductor element in the upper layer does not malfunction due to the signal of the wiring in the lower layer, the contact hole tends to be deeper. To this end, a metal wiring (second wiring) of the first integrated circuit layer is formed as shown in FIG. 1 and a circuit is formed such that the metal wiring (fourth wiring) of the second integrated circuit is in contact therewith. Should be designed.

FIG. 1 shows a conceptual diagram of the present invention. The first wiring is a gate wiring of a first integrated circuit layer, and the second wiring is a wiring crossing it, that is, a wiring connected to a source / drain. . Although an anodic oxide film is formed around the first wiring, an interlayer insulator may be formed as shown in the figure to further complete the interlayer insulation. The first integrated circuit layer is formed by these two (three or more, if necessary) wirings. And, covering the second wiring,
A second interlayer insulator is formed, and a semiconductor layer of a second integrated circuit layer is formed thereon. Above that is the same as the first integrated circuit layer.

In forming such a multilayer integrated circuit, it is effective to share the role of each layer. For example,
When forming an integrated circuit on a single crystal wafer,
An arithmetic unit and an ultra-high-speed memory unit may be formed in the first layer (single crystal), and a memory unit may be formed in the second layer or more that is a thin film transistor (TFT) region. Further, it is also possible to form an NMOS element in the first layer and a PMOS element in the second layer, and also to form a CMOS element. In this case, the elements can be arranged at a higher density than in the conventional case where the NMOS and the PMOS are formed in one layer. In FIG. 1, the first
The layer and the third layer are PMOS, and the second layer is NMOS.

[0011]

[Embodiment 1] An embodiment of manufacturing a multilayer integrated circuit on an insulating substrate using the present invention will be described with reference to FIG.
In this embodiment, a Corning 7059 glass substrate was used as the substrate 1. The substrate is a 2 inch diameter circle,
Its thickness was 1.1 mm. Various other types of substrates can be used, but it is necessary to take measures according to the substrate so that mobile ions such as sodium do not enter the semiconductor film. An ideal substrate is a synthetic quartz substrate having a low alkali concentration, but if it is difficult to use it cost-effectively, commercially available low alkali glass or non-alkali glass will be used. In the present embodiment, a thickness of 20 to
A silicon oxide film 2 having a thickness of 1000 nm, for example, 50 nm was formed. The thickness of the coating 2 is designed according to the degree of penetration of mobile ions or the degree of influence on the active layer.

These films may be formed not only by the sputtering method as described above, but also by a method such as a plasma CVD method. In particular, TEOS may be used. The selection of this means may be determined in consideration of investment scale, mass productivity, and the like.

Thereafter, a monosilane is used as a raw material to a thickness of 20 to 200 nm, for example, 100
A nm-thick amorphous silicon film was formed. The substrate temperature was set to 520 to 560 ° C, for example, 550 ° C. The amorphous silicon film obtained in this way is heated at 600 ° C. for 2 hours.
Thermal annealing was performed for 4 hours. As a result, crystalline silicon called semi-amorphous silicon was obtained.

After the amorphous silicon film was converted into a crystalline silicon film by thermal annealing, the amorphous silicon film was etched into an appropriate pattern to form an island-shaped semiconductor region 3. Thereafter, a gate insulating film (silicon oxide) is formed by a sputtering method using silicon oxide as a target in an oxygen atmosphere.
4 was formed with a thickness of 50 to 300 nm, for example, 100 nm. This thickness is determined by the operating conditions of the TFT and the like.

Next, an aluminum film was formed to a thickness of 500 nm by a sputtering method, and this was patterned with a mixed acid (a phosphoric acid solution to which 5% nitric acid was added) to form a gate electrode / wiring 5. The etching rate was 225 nm / min when the etching temperature was 40 ° C. Thus, the outer shape of the TFT was adjusted. At this time, the size of each channel is 8 μm in length and 20 μm in width.
μm.

Further, aluminum oxide was formed on the surface of the aluminum wiring by anodic oxidation. The method of anodic oxidation is described in Japanese Patent Application No. Hei.
1188 or the method described in Japanese Patent Application No. 3-238713. A detailed embodiment may be changed depending on the characteristics of the target device, process conditions, investment scale, and the like. In this example, an aluminum oxide film having a thickness of 250 nm was formed by anodic oxidation.

Thereafter, N-type source / drain regions 6 were formed by ion implantation through a gate oxide film.
The impurity concentration was set to 8 × 10 ¹⁹ cm ⁻³ . Phosphorus ions are used as the ion source, and the acceleration voltage is 110 ke.
V injected. The acceleration voltage is set in consideration of the thickness of the gate oxide film and the thickness of the semiconductor region 3. Instead of the ion implantation method, an ion doping method may be used. In the ion implantation method, unnecessary ions are not implanted because ions to be implanted are separated by mass, but the size of a substrate that can be processed by the ion implantation apparatus is limited. On the other hand, in the ion doping method, although a relatively large substrate (for example, a diagonal of 30 inches or more) is capable of being processed, hydrogen ions and other unnecessary ions are simultaneously accelerated and implanted, so that the substrate is easily heated. .

Thus, a TFT having an offset region was manufactured. Furthermore, the source / drain regions were recrystallized by laser annealing using the gate electrode as a mask. The conditions of laser annealing are described in, for example, Japanese Patent Application Nos. 3-231188 and 3-23871.
The method described in No. 3 was used. Then, silicon oxide was formed as an interlayer insulator 7 by an RF plasma CVD method. This state is shown in FIG.

Thereafter, contact holes are formed in the interlayer insulator 7 and the gate insulating film 4, and an aluminum film is formed to a thickness of 250 to 1000 nm, for example, 500 nm by sputtering, and is patterned to form a first integrated circuit layer. The wiring (corresponding to the second wiring in FIG. 1) 8 was formed. Then, a polyimide material (for example, Semico Fine manufactured by Toray Co., Ltd.) is applied by a spin coating method, and this is applied to 450-55.
Condensed at 0 ° C. to form a polyimide film 9 having a thickness of 0.5 to 5 μm.
m, for example, 3 μm. The flatness was adjusted to be within 0.1 μm in a 2-inch wafer. The state up to this point is shown in FIG.

Thereafter, an amorphous silicon film is deposited at a substrate temperature of 300 to 400.degree. C., for example, 320.degree. C. by a plasma CVD method, and is patterned into an island shape. Thus, a silicon oxide film 11 was formed. Further, an excimer laser beam was irradiated in this state to activate the island-shaped semiconductor region 10. This state is shown in FIG. The laser annealing conditions at this time were as follows. Laser: KrF laser, wavelength 248nm,
Pulse width 10 ns Irradiation energy: 200 mJ Irradiation pulse number: 20 shots

When irradiating the laser, the substrate is
When heated to 400 ° C., for example, 350 ° C., a silicon film having high reproducibility and high mobility was obtained. For example, when the substrate is heated to 350 ° C. and irradiated with a laser, the average electron mobility of the silicon film is 80 cm ² / Vs.
In the range of 70 to 90 cm ² / Vs, 80% was present. On the other hand, when the substrate temperature was set to room temperature and the laser irradiation was performed, the average value was 60 cm ² / Vs and the average was 50 to 70 cm ²
Only 40% was present in the ² / Vs range. Thus, the reliability could be improved by maintaining the substrate temperature at an appropriate temperature.

In the present embodiment, when irradiating the laser, the source / drain 6 is activated and the semiconductor region 1 is activated.
In the activation of 0, a 2-inch wafer was divided into 32 as shown in FIG. 3, and substantially square laser beams (hatched portions in the figure) were sequentially irradiated in the order of the numbers. Although laser annealing may seem to have lower productivity than thermal annealing, the repetition frequency of the excimer laser used in this example is 200 Hz, and the time required for processing one place on the wafer is as follows. , 0.1 second. Therefore, even if the time required for the wafer to move is taken into consideration, the processing time for one wafer is less than 10 seconds, and if the wafer is automatically transported, 200 or more wafers can be processed in one hour. .

Increasing the wafer or increasing the output of the laser eliminates the need for replacement of the wafer, increases the area of the laser beam, and further reduces the processing time.

Thereafter, as in the first integrated circuit layer,
After forming a gate wiring / electrode 12 with aluminum (covered with an anodic oxide film), a source / drain 13 is formed by implanting boron ions and laser annealing, and a silicon oxide film 14 is deposited by a sputtering method. This was used as an interlayer insulator. This state is shown in FIG.

Next, a contact hole 15 was formed through the interlayer insulator (silicon oxide) 14, the gate insulating film (silicon oxide) 11, and the interlayer insulator (polyimide) 9 (FIG. 2E). The diameter of the contact hole was 6 μm, twice the thickness of the polyimide interlayer insulator. Then, an aluminum film is formed to a thickness of 250 to 30 by sputtering.
After the contact hole was completely formed by forming the contact hole to a thickness of 00 nm, for example, 1500 nm, the contact hole was etched by 1000 nm by anisotropic etching. Thereafter, the aluminum film is patterned to form a wiring (fourth in FIG. 1).
(Corresponding to wiring) 16 was formed. At this time, if the film thickness of aluminum is small, disconnection occurs in the contact hole, so care must be taken.

Thus, a two-layer integrated circuit as shown in FIG. 2 (F) was formed. To form a multi-layer integrated circuit, the above operation may be repeated.

[0027]

According to the present invention, a multilayer integrated circuit can be surely formed. According to the present invention, not only can a multi-layer integrated circuit be formed on a conventional single crystal wafer, but also a multi-layer integrated circuit can be formed on an insulating substrate. Especially on an insulating substrate,
Since there is no capacitance between the wiring and the substrate, sufficiently high-speed operation is possible even when the mobility of the semiconductor is small. For example, the mobility of electrons is about 50 cm ² / Vs (for a single crystal, 500
(cm ² / Vs or more), the circuit can be driven with a clock of 100 MHz. Furthermore, in the present invention, since a low-resistance and high-thermal-conductivity material such as aluminum is used as a material of wiring such as a gate wiring, heat generation is small and cooling efficiency is good. Since pure aluminum is weak against mechanical stress such as electromigration, the same effect can be obtained even if an aluminum alloy to which a small amount of silicon or the like is added is used. Thus, the present invention is considered to be an industrially extremely useful invention.

[Brief description of the drawings]

FIG. 1 shows a conceptual diagram of an integrated circuit of the present invention.

FIG. 2 shows an embodiment of the present invention.

FIG. 3 shows an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Base oxide film 3, 10 ... Island-shaped semiconductor region 4, 11 ... Gate oxide film 5, 12 ... Gate electrode / wiring 6, 13 ... Source / drain 7, 14 ... interlayer insulator (silicon oxide) 8, 16 ... metal wiring 9 ... interlayer insulator (polyimide) 15 ... contact hole

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 617W

Claims (2)

(57) [Claims] 1. A first layer including a semiconductor or thin film transistor formed on an insulating substrate, a second layer having a thin film transistor formed with an interlayer insulator on the first layer, gate lines And a wiring connected to the source / drain, wherein the gate wiring and the wiring connected to the source / drain are provided.
Line is made of metal mainly composed of aluminum, from the thin <br/> film transistor capacitor of the first thin film transistor layer and the second layer is a metal mainly composed of coated aluminum oxide aluminum The gate electrode and the front
The half formed through the gate insulating film under the gate electrode
A conductor layer, and offset to the semiconductor layer below the aluminum oxide
A semiconductor integrated circuit, wherein a region is formed . 2. The semiconductor device according to claim 1, wherein the interlayer insulator has
The semiconductor integrated circuit characterized by comprising from equipment cost.