JPS63237520A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To perform a scale fixing for exposure even after levelling a layer insulation film sufficiently by forming the interlayer insulating film after the first semiconductor element has been prepared with the first scale fixing reference for exposure and by preparing the second semiconductor element with the second scale fixing reference for exposure. CONSTITUTION:In the case of preparation of the first semiconductor element 3 comprising a structure of the semiconductor element where its active layers have a laminated multilayer configuration, the first scale fixing reference 5 for exposure is prepared and the first semiconductor element 3 is prepared with the above reference. And then, when the second semiconductor element 7 laminated on the first semiconductor element 3 is prepared, an interlayer insulation film 11, first of all, is formed and after that, the second scale fixing reference 6 for exposure is prepared and the second semiconductor element 7 is prepared with the above reference 6. In this way, each time the active layer is increased one by one, such a reference for each layer is remaded and more than two semiconductor element layers are laminated and, formed one after another. Since the reference is remodelled with each layer, the scale fixing for exposure is performed easily and then the semiconductor element of good quality is manufactured.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

In recent years, when manufacturing semiconductor devices, the active layer of the semiconductor device is separated by an interlayer insulating film and stacked into multiple layers, and new LSIs with higher density, higher speed, and multifunctional performance than current LSIs have been developed. There are many attempts to do so. As an example, there is a paper published on pages 269 to 279 of the 4th Symposium on Functional Element Technology by Art Materials. As shown in the same paper, when increasing the number of active layers in a device, it is necessary that the surface of the interlayer insulating film that electrically isolates the active layers be sufficiently planarized.
If this is not sufficiently planarized, the crystallinity of the semiconductor thin film (in which elements are fabricated) formed on the interlayer insulating film by laser annealing or the like will deteriorate.

[Problem that the invention seeks to solve]

However, on the other hand, if the surface of the interlayer insulating film is sufficiently flattened, it becomes difficult to see the shape of the elements that exist under the interlayer insulating film, which naturally makes it difficult to see the shape of the elements that exist under the interlayer insulating film. It also becomes difficult to see the necessary alignment standards. This means that it will be difficult to perform subsequent exposure adjustments.
In the worst case, exposure may become impossible.

The purpose of the present invention is to
The object of the present invention is to provide a method that enables subsequent exposure combinations.

[Means for solving problems]

The present invention provides a method for manufacturing a semiconductor device having a structure in which semiconductor device active layers are laminated or multilayered, in which a first exposure alignment standard is created when manufacturing a first semiconductor device, and the first alignment standard for exposure is used. After producing the first semiconductor element, when producing the second semiconductor element to be laminated on the first semiconductor element, first an interlayer isolation M film is formed, and then a second exposure eye is formed. This method of manufacturing a semiconductor device is characterized in that a step of preparing an alignment standard and manufacturing the second semiconductor device using the second exposure alignment standard is performed.

〔Example〕

A detailed description will be given below with reference to the embodiment shown in FIG.

In FIG. 1(a), 1im SiO2 is placed on the Si substrate 1.
An interlayer insulating film 2 was grown by the LPCVD method.

0.5Ifmpoly-5 by LPCVD method
i grew up.

An alignment base 11!5 and an element region 3 were formed in the poly-Si by a photoresist process and a dry etching process. After that, formation of gate insulating film and vT
After performing ion implantation for adjustment, 0,5-poly-3i, which will be the gate electrode material, is formed using the PCVI method, and using the alignment reference 5 as a position reference, the patterning of the gate electrode 4 is performed using a photoresist process. Next, in FIG. 1(b), 1.5p SiO2 was grown as the interlayer insulating film 11 by the LPCVD method, and then the surface of the first interlayer insulating film 3 was planarized by applying an organic film and dry etching. After that, 0.51 by the LPCVII method
mpoly-5i was grown, and alignment standards 6 and device regions 7 were formed therein by a photoresist process and a dry etching process. In this photoresist process, alignment reference 5 was used as a position reference for exposure alignment.

Next, ion implantation was performed to form a gate insulating film and adjust the voltage, and the gate electrode material, 0°5
was formed by the LPCVI) method, and patterning of the gate electrode 8 was performed by a photoresist process using the alignment reference 6 as a position reference.

In this way, each time the number of active layers is increased, the alignment reference is remade for each layer, and two or more semiconductor element layers are successively stacked. In the example, the alignment reference was made in poly-5L for forming the element region, but alternatively, as shown in FIG. It may be made inside.

Although the above embodiments have been described using MOSFET as an example, bipolar elements may also be used. In addition, as a semiconductor thin film, pol
y-Si was used, but other materials (G
e, GaAs, etc.). Further, the number of active layers may be increased.

〔Effect of the invention〕

As described above, when the present invention is used to manufacture a semiconductor device having a multi-layered active layer structure, the alignment standard is re-created for each layer, making it easy to adjust the exposure, which in turn improves product quality.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are sectional views showing an embodiment of the present invention in the order of steps, and FIG. 1(c) is a sectional view showing another embodiment.

Claims (1)

[Claims] (1) In a method for manufacturing a semiconductor device having a structure in which semiconductor device active layers are laminated or multilayered, a first exposure alignment standard is created when manufacturing a first semiconductor device, and the first exposure alignment standard is used to create a first exposure alignment standard. After manufacturing the first semiconductor element, when manufacturing a second semiconductor element to be stacked on the first semiconductor element, an interlayer insulating film is first formed, and then a second semiconductor element is formed.
1. A method for manufacturing a semiconductor device, comprising: manufacturing an alignment standard for exposure, and then manufacturing the second semiconductor device using the second alignment standard for exposure.