JP3431653B2 - Method for manufacturing MIS type semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a metal (M) -insulator (I) -semiconductor (S) type semiconductor device, a so-called MIS type semiconductor device (also called an insulating gate type semiconductor device). For the MIS type semiconductor device, for example, MO
An S transistor, a thin film transistor, etc. are included.

[0002]

2. Description of the Related Art Conventionally, MIS type semiconductor devices have been manufactured by using a self-alignment method (self-alignment method). In this method, a gate electrode is formed on a semiconductor substrate or a semiconductor film via a gate insulating film, and impurities are introduced into the semiconductor substrate or the semiconductor film by using the gate electrode as a mask. As means for introducing impurities,
A thermal diffusion method, an ion implantation method, a plasma doping method, or a laser doping method is used. By such means, the end portion with the gate electrode and the end portion of the impurity region (source, drain) are substantially aligned with each other, and the gate electrode and the impurity region are overlapped with each other (the cause of the parasitic capacitance) or the gate electrode. It was possible to eliminate the offset state in which the impurity regions were separated (the cause of reduction in effective mobility).

However, in the conventional process, an impurity region,
The spatial variation of the carrier concentration in the active region (channel forming region) under the gate electrode, which is adjacent to it, is so large that a remarkably large electric field is generated, especially when a reverse bias voltage is applied to the gate electrode. There is a problem that (OFF current) increases.

The present inventors have found that the present invention can be improved by slightly offsetting the gate electrode and the impurity region, and further, in order to realize this offset state, the gate electrode is realized. It has been found that an offset state of 300 nm or less can be obtained with good reproducibility by forming impurities with a material that can be anodized and introducing impurities using the anodized film produced as a result of anodization as a mask.

Further, in the method of introducing impurities by irradiating the semiconductor substrate or the semiconductor film with high-speed ions such as the ion implantation method and the plasma doping method, the crystallinity of the semiconductor substrate or the semiconductor film at the portion where the ions have penetrated is It was necessary to improve the crystallinity (activation) because it would be impaired. Conventionally, the crystallinity was thermally improved mainly at a temperature of 600 ° C. or higher, but in recent years, there has been a tendency to lower the temperature of the process. Therefore, the inventors of the present invention used a laser or strong light equivalent thereto. It was also shown that activation can be performed by irradiation, and that its mass productivity is excellent.

FIG. 2 shows a process of manufacturing a thin film transistor based on the above idea. First, a base insulating film 202 is deposited on a substrate 201, an island-shaped crystalline semiconductor region 203 is further formed, and an insulating film 204 functioning as a gate insulating film is formed by covering the crystalline semiconductor region 203. Then, the gate wiring 205 is formed using an anodizable material.
(Fig. 2 (A))

Next, the gate wiring is anodized to have a thickness of 300 nm or less, preferably 250 nm on the surface of the gate wiring.
The following anodic oxide 206 is formed. Then, using this anodic oxide as a mask, impurities such as ion implantation and ion doping are self-aligned by means such as ion doping.
Irradiation with phosphorus (P) is performed to form an impurity region 207.
(Fig. 2 (B))

After that, the region in which the impurities are introduced is activated by irradiating the upper surface with strong light such as laser light. (FIG. 2C) Finally, an interlayer insulator 208 is deposited, a contact hole is formed in the impurity region, an electrode 209 connected to the contact hole is formed, and the thin film transistor is completed. (Fig. 2
(D))

[0009]

However, in the method described above, the boundary between the impurity region and the active region (which is sandwiched between the impurity regions by the semiconductor region immediately below the gate electrode) (X in FIG. 2C) is used. Is unstable, and problems such as an increase in leak current occur during long-term use, resulting in reduced reliability. That is, as is clear from the process, the active region is substantially
Crystallinity does not change from the beginning. On the other hand, the impurity region adjacent to the active region initially has the same crystallinity as the active region, but the crystallinity is destroyed in the process of introducing the impurity. The impurity region will be recovered by the laser irradiation process later,
It is difficult to reproduce the same state as the original crystallinity, and it is clear that the part of the impurity region that is in contact with the active region is likely to be shaded during laser irradiation, and sufficient activation cannot be performed. became. That is, the crystallinity of the impurity region and the active region is discontinuous, and therefore trap levels and the like are likely to occur. In particular, when a method of irradiating fast ions is adopted as a method of introducing impurities, the impurity ions are scattered to go under the gate electrode portion and destroy the crystallinity of the portion. Then, in the region under such a gate electrode portion, the gate electrode portion becomes a shadow and cannot be activated by a laser or the like.

One method of solving this problem is to irradiate light such as a laser from the back surface to activate it. In this method, since the gate wiring does not have a shadow, the boundary between the active region and the impurity region is sufficiently activated. However, in this case, the substrate material needs to transmit light, which cannot be naturally used when a silicon wafer or the like is used. Moreover, since it is difficult for many glass substrates to transmit ultraviolet light having a wavelength of 300 nm or less, for example, a KrF excimer laser (wavelength 248 nm) excellent in mass productivity cannot be used.

The present invention has been made in consideration of the above problems, and achieves a highly reliable MIS type semiconductor device, such as a MOS transistor, by achieving continuity of crystallinity between an active region and an impurity region. An object is to obtain a thin film transistor.

[0012]

According to the present invention, when the impurity region is irradiated with light energy emitted from a powerful light source such as a laser or a flash lamp to activate the impurity region, not only the impurity region but also the impurity region is activated. Light energy is also applied to a part of the adjacent active region, particularly the boundary part between the impurity region and the active region, and it is necessary to remove a part of the material forming the gate electrode part for the purpose. Characterize.

According to a first aspect of the present invention, after a material functioning as a mask for forming an impurity region is formed on a crystalline semiconductor substrate or semiconductor film, impurities are used as a mask for the semiconductor substrate or semiconductor film. A step of introducing into the inside, a step of removing the mask material so that both the impurity region and the active region can be irradiated with light energy, and then irradiating light energy in this state to perform activation, and thereafter, And a step of forming a gate electrode (gate wiring) on the active region. When such a method is adopted, if the offset region is not formed, the pattern of the mask material for forming the impurity region needs to be wider than the pattern of the gate electrode. if,
This is because the impurity region and the gate electrode overlap (overlap) if the pattern of the gate electrode is larger than the pattern of the mask material for impurity implantation.

Further, it is difficult to exactly overlap similar patterns by using different photomasks. In particular, it is almost impossible to mass-produce an offset state of 1 μm or less as required by the present invention. On the other hand, it is relatively easy to overlap using the same photomask. However, for example, a wiring of a certain pattern is formed using a certain photomask, an impurity region is formed using this as a mask material, this wiring is removed, and wiring is further formed using the same photomask. In that case, the offset state is hardly formed. But,
Thereafter, if the surface of the wiring them anodization conductive surface is offset state is realized by retracting.

Further, when the wiring formed first is anodized, the surface of the anodic oxide advances, so if the impurity region is formed using this as a mask, the impurity region is formed outside the pattern of the first wiring. . Then, if the wiring is anodized a second time, the offset state is further expanded due to the receding of the conductive surface.

In this way, the gate electrode is made of a material capable of anodizing, and the offset state can be realized relatively easily by anodizing this. Needless to say, the anodic oxide also has the effect of preventing a short circuit between layers. Also, the gate electrode (wiring)
It is needless to say that the structure may be covered with anodic oxide and further provided with an interlayer insulator or the like to reduce the capacitive coupling with the upper wiring.

According to a second aspect of the present invention, after an insulating film which functions as a gate insulating film is formed on a crystalline semiconductor substrate or a semiconductor film, impurities are self-aligned with the insulating film as a mask. By introducing the step of introducing into the inside and the end portion of the gate electrode selectively, the impurity region and the gate electrode are made to be in an offset state, and the boundary between the impurity region and the active region can be irradiated with light energy. And irradiating light energy in this state to perform activation.

If necessary, the gate electrode is made of a material capable of anodizing, is irradiated with light energy, and is then anodized to coat the surface thereof with an anodic oxide having a high insulating property. It goes without saying that a structure may be provided to reduce capacitive coupling with the upper wiring.

Preferred anodizable materials to be used when anodizing is performed in the present invention are aluminum, titanium, tantalum, silicon, tungsten and molybdenum. It is preferable to use a simple substance or an alloy of these materials as a single layer or a multi-layer structure for the gate electrode. It goes without saying that trace amounts of other elements may be added to these materials. Further, the anodic oxidation is usually carried out electrochemically in an electrolytic solution, but it goes without saying that it may be carried out in a reduced pressure plasma atmosphere as in the known plasma anodic oxidation method.

The source of the light energy used in the present invention is a KrF laser (wavelength 248).
nm), XeCl laser (308 nm), ArF laser (193 nm), XeF laser (353 nm) and other excimer lasers, and Nd: YAG laser (10
64 nm) and its second, third, and fourth harmonics, coherent light sources such as carbon dioxide lasers, argon ion lasers, copper vapor lasers, and non-coherent light sources such as xenon flash lamps and krypton arc lamps.

[0021]

[Embodiment] [Embodiment 1] FIG. 1 shows the present embodiment. In this embodiment, a thin film transistor is formed on an insulating substrate. The substrate 101 is a glass substrate, and for example, a non-alkali glass substrate such as Corning 7059 or a quartz substrate can be used. Considering cost, here is Corning 70
59 substrates were used. A silicon oxide film 102 was deposited on this as an underlying oxide film. As a method for depositing the silicon oxide film, for example, a sputtering method or a chemical vapor deposition method (CVD method) can be used. Here, film formation was performed by a plasma CVD method using TEOS (tetra-ethoxy-silane) and oxygen as material gases. Substrate temperature is 200-400
℃ was made. The thickness of the underlying silicon oxide film is 500 to 20.
It was set to 00Å.

Next, an amorphous silicon film was deposited and patterned into an island shape. As a method for depositing the amorphous silicon film, plasma CVD method or low pressure CV is used.
Method D is used. Here, monosilane (SiH ₄ )
An amorphous silicon film was deposited by the plasma CVD method using as a material gas. The thickness of this amorphous silicon film was 200 to 700 Å. Then, this was irradiated with laser light (KrF laser, wavelength 248 nm, pulse width 20 nsec). Prior to laser irradiation, the substrate was heated in vacuum at 300 to 550 ° C. for 0.1 to 3 hours to release hydrogen contained in the amorphous silicon film. Laser energy density is 250-450
It was set to mJ / cm ² . The substrate was heated to 250 to 550 ° C. during laser irradiation. As a result, the amorphous silicon film was crystallized to become the crystalline silicon film 103.

Next, a silicon oxide film 104 functioning as a gate insulating film was formed to a thickness of 800 to 1200Å. Here, the manufacturing method is the same as that of the base silicon oxide film 102. In addition, organic materials such as polyimide and many conductors
Conductive material, for example, formed of aluminum, tantalum, titanium, or other metal, a semiconductor such as silicon, tantalum nitride, the mask material 105 using a conductive metal nitride such as titanium nitride. Here, photosensitive polyimide is used, and its thickness is 2
000 to 10,000 Å. (Fig. 1 (A))
By a plasma doping method, boron (B) or phosphorus (P) ions are irradiated to form the impurity regions 106. The acceleration energy of ions varies depending on the thickness of the gate insulating film 104, but typically the gate insulating film is 1
In the case of 000Å, 50 to 65 keV for boron and 60 to 80 keV for phosphorus were suitable. Further, the dose amount of 2 × 10 ¹⁴ cm ^{−2 to} 6 × 10 ¹⁵ cm ⁻² was suitable, but it became clear that the lower the dose amount, the more reliable the device can be obtained. It is needless to say that the range of the impurity region shown in the figure is a nominal one, and actually, there is wraparound due to ion scattering and the like. (Fig. 1
(B))

After the impurity doping is completed, the polyimide mask material 105 is etched. The etching was performed in an oxygen plasma atmosphere. As a result, as shown in FIG. 1C, the impurity region 106 and the active region sandwiched by the impurity region 106 appeared. Then, in such a state, the impurity regions were activated by laser irradiation. The laser is a KrF excimer laser (wavelength 248
nm, pulse width 20 nsec) was used, and the energy density of the laser was 250 to 450 mJ / cm ² . Moreover, when the substrate was heated to 250 to 550 ° C. during laser irradiation, the activation could be more effectively performed. Typically, phosphorus is doped, the dose is 1 × 10 ¹⁵ cm ^-2 , the substrate temperature is 250 ° C., and the laser energy is 300 mJ / cm 2.
500~1000Ω / □ sheet resistance were obtained in ^2.
Further, in the present embodiment, the boundary between the impurity region and the active region is also irradiated by the laser, so that the deterioration of reliability due to the deterioration of the boundary portion, which has been a problem in the conventional manufacturing process, is significantly reduced. (Fig. 1 (C))

After that, 0.2 is larger than the mask material 105.
A tantalum gate electrode (wiring) having a narrow width of μm was patterned, and anodization was applied to the gate electrode to form an anodic oxide having a thickness of 1000 to 2500Å. The anodic oxidation is performed by immersing the substrate in an ethylene glycol solution of 1 to 5% citric acid, integrating all gate wirings, and using this as a positive electrode, while platinum is used as a negative electrode and the applied voltage is 1 to 1.
It was performed by increasing the pressure at 5 V / min. The gate electrode portion 107 thus formed was clearly offset from the impurity region. The anodic oxide of the gate electrode portion not only determines the size of the offset of the thin film transistor but also prevents a short circuit with the upper wiring, so that an appropriate thickness may be selected for that purpose. In some cases, such an anodic oxide may not be formed. (Fig. 1 (D))

Finally, a silicon oxide film 108 is formed as an interlayer insulator.
To a thickness of 2000 to 1000 Å, for example, by a plasma CVD method using TEOS as a material gas, and a contact hole is formed in this to form a material such as a metal, for example, a thickness of 200
The thin film transistor was completed by connecting the electrode 109 composed of a multilayer film of Å titanium nitride and 5000 Å thick aluminum to the impurity region. (Fig. 1 (E))

[Second Embodiment] FIGS. 3 and 4 show the present embodiment. FIG. 3 is a cross-sectional view taken along one-dot chain line in FIG. 4 (top view). First, a base silicon oxide film was formed on a substrate (Corning 7059) 301, and further an amorphous silicon film was formed to a thickness of 1000 to 1500Å. And
24 at 600 ° C in a nitrogen or argon atmosphere
By annealing for about 48 hours, the amorphous silicon was crystallized and patterned. In this way, crystalline island-shaped silicon 302 was formed. Further, a 1000 Å-thick silicon oxide film 303 which functions as a gate insulating film is deposited, and tantalum wiring (thickness 5000) is deposited.
Å) 304, 305 and 306 were formed. (Fig. 3
(A))

Then, an electric current is passed through these wirings 304 to 306, and a first layer having a thickness of 2000 to 2500Å is formed on the surface thereof.
Anodic oxides 307, 308, and 309 were formed. Then, using the wiring thus treated as a mask, impurities are introduced into the silicon film 302 by a plasma doping method to form an impurity region 310. (Fig. 3
(B) and FIG. 4 (A))

Next, the tantalum wiring and the anodic oxide which have been subjected to the above treatment are removed to expose the active region surface,
In this state, activation was performed by irradiating with KrF excimer laser light. (FIG. 3C) After that, again, the same patterns (wirings 311, 312, 313) as the previous wirings 304 to 306 were formed with tantalum. A polyimide coating film 314 having a thickness of 1 to 5 μm was provided only on a portion of the wiring 313 where a contact hole was formed. As the polyimide, it is easy to use a photosensitive polyimide because it is easily patterned. (FIG. 3D and FIG. 4B) Then, in this state, a current is passed through the wirings 311 to 313,
A second anodic oxide 315 having a thickness of 2000 to 2500 Å,
316 and 317 were formed. However, the part where the polyimide is previously provided is not anodized, and the contact hole 3
18 remains. (Fig. 3 (E))

Finally, as an interlayer insulator, the thickness is 2000 to 5
A 000 Å silicon oxide film 319 was deposited to form a contact hole. In a part of the wiring 312 (a portion 322 surrounded by a dotted line in FIG. 4C), the interlayer insulating material was entirely removed to expose the second anodic oxide 316. And
Tantalum nitride (thickness 500Å) and aluminum (thickness 3)
Wiring / electrodes 320, 321 using a multilayer film of 500 Å)
To complete the circuit. At this time, the wiring 321 forms a capacitance with the wiring 312 by 322, and is further connected to the wiring 313 by a contact 323.
(FIG. 3 (F) and FIG. 4 (C))

[Third Embodiment] FIG. 5 shows the present embodiment. 5A to 5C are cross-sectional views of a manufacturing process of a thin film transistor. First, a base silicon oxide film 502 was formed on a substrate (Corning 7059) 501, and an island-shaped amorphous silicon film was formed to a thickness of 1000 to 1500 Å. Then, in a nitrogen or argon atmosphere, 500 to 6
The amorphous silicon was crystallized by annealing at 00 ° C. for 2 to 48 hours. Thus, crystalline island silicon 503 was formed. Furthermore, a silicon oxide film 504 having a thickness of 1000 Å which functions as a gate insulating film.
Was deposited. Then, an aluminum coating (thickness 5000Å) containing 1 to 2% of silicon was deposited by a sputtering method, and a photoresist was further formed by a spin coating method. Then, patterning was performed by a known photolithography method, and anisotropic etching was performed by a RIE (reactive ion etching) method using the photoresist 506 generated in this step as a mask to form an aluminum gate electrode / wiring 505. (Figure 5 (A))

Next, the etching mode was set to a normal plasma mode, and isotropic etching was performed. As a result, the side surfaces of the aluminum gate electrode / wiring have receded. By adjusting the etching time, the retreat of the gate electrode was controlled to 2000 to 3000Å. Then, an impurity is introduced into the silicon film 503 by a plasma doping method to form an impurity region 507. (Fig. 5
(B))

Next, the photoresist 506 is peeled off,
The gate electrode / wiring was exposed, and activation was performed by irradiating with KrF excimer laser light in this state. In this activation step, the boundary between the impurity region and the active region (indicated by X in FIG. 5C) is also laser-irradiated. (FIG. 5 (C)) After that, the substrate is dipped in an ethylene glycol solution of tartaric acid, and the gate wiring is anodized.
A 2500 Å anodic oxide 508 was formed. (Fig. 5
(D))

Finally, as an interlayer insulator 509, a thickness of 200
A 0 to 5000 Å silicon oxide film was deposited and contact holes were formed in the impurity regions. Then, the wiring / electrode 510 using a multilayer film of tantalum nitride (thickness 500Å) and aluminum (thickness 3500Å) was formed to complete the thin film transistor. (Fig. 5 (E))

Fourth Embodiment FIG. 6 shows this embodiment. A base silicon oxide film was formed on a substrate (Corning 7059) 601, and an island-shaped amorphous silicon film was formed to a thickness of 1000 to 1500Å. Then, in a nitrogen or argon atmosphere, it is 2 to 4 at 500 to 600 ° C.
The amorphous silicon was crystallized by annealing for 8 hours. In this way, crystalline island silicon 602 was formed. Further, a silicon oxide film 603 having a thickness of 1000 Å which functions as a gate insulating film is deposited, and aluminum wiring (thickness 5000 Å) 604, 605, 6 is formed.
06 was formed. (Fig. 6 (A))

Further, the surfaces of these wirings 604 to 606 are covered with anodic oxides 607 and 6 having a thickness of 1000 to 2000Å.
Covered with 08,609. Then, impurities are introduced into the silicon film 602 by a plasma doping method using the wiring portion thus treated as a mask to form an impurity region 610. (FIG. 6B) Next, the aluminum wirings 604 to 606 are all etched together with the anodic oxide to expose the surface of the semiconductor region 602, and activation is performed by irradiating with KrF excimer laser light in this state. . (Fig. 6 (C))

Then, again, the aluminum wiring 611,
612 and 613 were formed. The wiring pattern at this time was the same as that of the wirings 604 to 606 formed previously.
Then, a polyimide film having a thickness of 1 to 5 μm was provided so as to cover the wiring 611. As the polyimide, it is easy to use a photosensitive polyimide because it is easily patterned. (Fig. 6
(D)) In this state, a current is passed through the wirings 611 to 613,
Anodized oxide 615, 616 with a thickness of 2000-2500Å
Was formed. However, the portion of the wiring 611 where the polyimide was first provided was not anodized. (Fig. 6
(E))

Finally, as an interlayer insulator, the thickness is 2000 to 5
A 000Å silicon oxide film 617 is deposited to
A contact hole was formed at 0. Further, in the part 620 of the wiring 613, the interlayer insulating material is completely removed to remove the anodic oxide 6
16 was exposed. And tantalum nitride (thickness 50
Wiring / electrodes 618 and 619 using a multilayer film of 0Å) and aluminum (thickness 3500Å) were formed to complete the circuit. At this time, the wiring 619 is 620 to form a capacitor using the wiring 613 and the anodic oxide 616 as a dielectric.
(Fig. 6 (F))

[0039]

According to the present invention, the reliability of MIS type semiconductor devices such as MOS transistors and thin film transistors manufactured by a low temperature process can be improved. Specifically, the source is grounded, and one or both of the drain and the gate are +20 V or more, or -2.
Even when left for 10 hours or more with a potential of 0 V or less applied, the characteristics of the transistor were not significantly affected.
Although the thin film transistors were the main examples in the examples, it goes without saying that the effects of the present invention can also be obtained in a MIS type semiconductor device manufactured on a single crystal semiconductor substrate.
Further, as for the semiconductor material, in addition to the silicon mentioned in the examples, the same effect can be obtained with silicon-germanium alloy, silicon carbide, germanium, cadmium selenide, cadmium sulfide, gallium arsenide and the like.
As described above, the present invention is an industrially useful invention.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention. (Cross section)

FIG. 2 shows an example of a conventional technique. (Cross section)

FIG. 3 shows an embodiment of the present invention. (Cross section)

FIG. 4 shows an embodiment of the present invention. (Top view)

FIG. 5 shows an embodiment of the present invention. (Cross section)

FIG. 6 shows an embodiment of the present invention. (Cross section)

[Explanation of symbols]

101 ... Substrate 102 ... Base insulating film 103 ... Island semiconductor region 104 ... Gate insulating film 105 ... Mask material 106 ... Impurity region 107 ... Gate electrode portion (gate electrode) Anodic oxide around it) 108 ... Interlayer insulator 109 ... Electrode (wiring)

─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-4-360581 (JP, A) JP-A-58-206121 (JP, A) JP-A-58-145146 (JP, A) JP-A-1- 173635 (JP, A) JP-A-4-360580 (JP, A) JP-A-5-235031 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21 / 336 H01L 21/265 602

Claims (2)

(57) [Claims] 1. A first that can be anodized using a photomask .
Of the conductive material is patterned, forming a first patterning step of forming a first wiring through the insulating film on the semiconductor region, the first wiring portion of the first wiring surface by anodizing <br And a step of forming an impurity region and an active region narrowed by the impurity by introducing impurities into the semiconductor region using the first wiring part as a mask, and the first wiring part. A step of removing the impurity regions and the active regions sandwiched between them to expose them, and irradiating a laser or strong light equivalent thereto to improve the crystallinity of the impurity regions; and a second step using the photomask. Patterning conductive material
And a second patterning step of forming a second wiring, and manufacturing a MIS type semiconductor device. 2. The anode according to claim 1, wherein the second wiring surface is an anode.
A method of manufacturing a MIS type semiconductor device, comprising a step of oxidizing .