JP2008205333A - Thin film transistor and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make thin the thickness of the inter-layer insulating film of a contact hole formation part, and to form a uniform contact hole in a thin film transistor where upper layer wiring is connected to a semiconductor layer. <P>SOLUTION: A multi-crystal semiconductor layer 3 is formed as an active layer, and wiring is connected through a contact hole 7 formed in an inter-layer insulating film 6 to the multi-crystal semiconductor layer 3. The wiring connected to the multi-crystal semiconductor layer 3 is upper layer wiring (second wiring 8) in the second or more layers in multilayered wiring. A base pattern 10 having predetermined thickness is formed at a position corresponding to the contact hole 7, and a connection part (source region 3a and drain region 3b) to the second wiring 8 of the multi-crystal semiconductor layer 3 is formed on the base pattern 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly to a thin film transistor in which an upper layer wiring of a multilayer wiring is connected to a semiconductor layer through a contact hole and a method for manufacturing the same.

  In an active matrix liquid crystal display element, one thin film transistor is required to drive a liquid crystal of one pixel, and a technology for forming a polycrystalline thin film transistor using polycrystalline silicon (polysilicon) as a channel layer on a glass substrate. Has been developed. Advances in process technology have made it possible to form high performance polycrystalline thin film transistors on glass substrates at low process temperatures.

  In the manufacture of a liquid crystal display panel using a polycrystalline silicon film, a thin film transistor constituting a driving circuit such as a driver circuit or a power supply circuit is formed on a substrate as described above. For example, an external integrated circuit ( The drive circuit that has been installed as an IC) is also being built in the frame area of the liquid crystal display panel.

  In this case, the narrowing of the frame area necessary for forming the wiring around the liquid crystal display panel is a big problem. If an attempt is made to incorporate a circuit in the liquid crystal transistor array, the number of thin film transistors and the number of wirings increase, and thus the width of the frame region must be increased. When the signal line is formed with a single-layer wiring as in the prior art, the wiring must be laid out in parallel, and the area occupied by the wiring increases, making it difficult to reduce the frame area. In order to realize the narrowing of the frame region, for example, it is conceivable to make the wiring finer. However, if the wiring is made finer, an increase in wiring resistance may be a problem.

Therefore, it has been studied to make the wiring multi-layered (double-layered) (see, for example, Patent Document 1). Patent Document 1 includes an array substrate having a display portion and a frame portion. The display portion includes a plurality of wirings and a plurality of thin film transistors connected to the wirings. The frame portion drives the thin film transistors. There is disclosed an image display device including a driving circuit that includes a first wiring layer formed of a first wiring material and a second wiring layer formed on the first wiring layer. In the invention described in Patent Document 1, the wiring is composed of the first wiring layer and the second wiring layer, and in these wiring layers, a material suitable for miniaturization and a low-resistance material are selectively used according to the role, thereby narrowing the width. A frame is realized.
JP 2002-297057 A

  By the way, when wiring is connected to a semiconductor layer, a contact hole is generally formed in an interlayer insulating film, and the wiring is formed here to achieve connection with the semiconductor layer. The same applies to the case where the upper layer wiring of the multilayer wiring is connected. In this case, however, the interlayer insulating film is thicker than the case where the lower layer wiring and the semiconductor layer are connected or the connection between the wirings is performed. Therefore, there is a problem that it is difficult to form a uniform contact hole. When the connection between the lower layer wiring and the semiconductor layer and the connection between the upper layer wiring and the semiconductor layer are mixed, the difference in film thickness of the interlayer insulating film becomes large, which makes it difficult to form a uniform contact hole. As a result, for example, if the interlayer insulating film remains at the bottom of the contact hole, it causes connection failure.

  The present invention has been proposed in view of the above-described conventional situation, and even when the upper layer wiring is connected to the semiconductor layer, the thickness of the interlayer insulating film in the contact hole forming portion can be reduced and uniform. It is an object of the present invention to provide a thin film transistor in which contact holes can be formed and in which poor connection or the like does not occur, and further to provide a manufacturing method thereof.

  In order to achieve the above object, a thin film transistor of the present invention is a thin film transistor in which a semiconductor layer is an active layer, and a wiring is connected to the semiconductor layer through a contact hole formed in an interlayer insulating film, The wiring connected to the semiconductor layer is an upper layer wiring of the second layer or more of the multilayer wiring, and a base pattern having a predetermined thickness is formed at a position corresponding to the contact hole, and the base pattern is formed on the base pattern. A connection portion between the semiconductor layer and the upper layer wiring is formed.

  In the thin film transistor manufacturing method of the present invention, a semiconductor layer is used as an active layer, and an upper layer wiring of the second or more layers of the multilayer wiring is connected to the semiconductor layer through a contact hole formed in the interlayer insulating film. A method of manufacturing a thin film transistor comprising: a step of forming a base pattern having a predetermined thickness at a position corresponding to a contact hole on a substrate; and a semiconductor so that a connection portion with an upper layer wiring overlaps the base pattern A step of forming a layer; a step of forming an interlayer insulating film covering the semiconductor layer; a step of forming a contact hole in the interlayer insulating film; and an upper layer wiring connected to the semiconductor layer through the contact hole And a step of forming.

  In the present invention, the connection portion with the upper layer wiring of the semiconductor layer is raised by the base pattern, and as a result, the thickness of the interlayer insulating film formed on the connection portion with the upper layer wiring of the semiconductor layer Is thinner than the surrounding area. If the thickness of the interlayer insulating film is reduced, the contact hole can be easily formed. For example, when a thin film transistor to which the first wiring which is the lowest layer and the semiconductor layer are connected and a thin film transistor to which the second wiring (upper layer wiring) and the semiconductor layer are connected are mixed, the interlayer insulating film Therefore, even when contact holes are formed simultaneously, uniform contact holes can be formed. The same applies to the contact hole connecting the first wiring and the second wiring and the contact hole connecting the second wiring and the semiconductor layer.

  According to the present invention, the thickness of the interlayer insulating film in the contact hole forming portion for connecting to the upper layer wiring can be reduced, and the interlayer insulating film between the contact hole forming portion and the wiring for connecting to the lower layer wiring can be reduced. Therefore, even if contact holes are formed at the same time, uniform contact holes can be formed. Therefore, it is possible to provide a highly reliable thin film transistor in which connection failure or the like does not occur.

  Embodiments of a thin film transistor to which the present invention is applied and a method for manufacturing the same will be described below in detail with reference to the drawings.

(First embodiment)
In the present embodiment, a base pattern for raising the semiconductor layer is formed of a conductive material, and the semiconductor layer is formed in direct contact with the base pattern.

  In the thin film transistor of this embodiment, as shown in FIG. 1, a polycrystalline semiconductor layer (polysilicon layer) 3 is formed on a glass substrate 1 via an undercoat layer 2, and the polycrystalline semiconductor layer 3 is formed as an active layer ( Channel layer).

  The polycrystalline semiconductor layer 3 formed on the undercoat layer 2 is annealed amorphous silicon (a-Si) formed by, for example, a plasma CVD method, and then polycrystallized by laser irradiation or the like. Is formed. This polycrystalline semiconductor layer 3 is element-isolated into an island shape by etching. In the polycrystalline semiconductor layer 3, a source region 3a and a drain region 3b are formed by impurity implantation, and an LDD region (low concentration impurity diffusion region) is formed as necessary.

  On the other hand, a gate electrode 5 is formed on the polycrystalline semiconductor layer 3 with a predetermined line width via a gate insulating film 4. The gate insulating film 4 is formed so as to be interposed between the gate electrode 5 and the polycrystalline semiconductor layer 3, and the polycrystalline semiconductor layer 3 is covered with the gate insulating film 4.

  The gate insulating film 4 and the gate electrode 5 are further covered with an interlayer insulating film 6, and the second wiring 8 is connected to the polycrystalline semiconductor layer 3 (source region) through a contact hole 7 formed in the interlayer insulating film 6. 3a and drain region 3b). In the present embodiment, the second wiring 8 is the second-layer wiring from the bottom among the plurality of wirings, and corresponds to the upper layer wiring. The surface of the second wiring 8 is covered with a protective film 9.

  When the second wiring 8 is connected to the source region 3 a and the drain region 3 b of the polycrystalline semiconductor layer 3, it is necessary to form a contact hole 7 in the interlayer insulating film 6, but the second wiring 8 and the polycrystalline semiconductor layer 3 The inter-layer insulating film 6 includes a first interlayer insulating film 6a for forming the first wiring and a second interlayer insulating film 6b for forming the second wiring 8 on the first wiring. .

  Therefore, if no measures are taken, the thickness L1 of the entire interlayer insulating film 6 in the portion where the contact hole 7 is formed becomes thicker as shown schematically in FIG. It is difficult to form a contact hole simultaneously (for example, a contact hole between the first wiring and the polycrystalline semiconductor layer 3 or a contact hole between the first wiring and the second wiring 8) at the same time. For example, the contact hole is larger than the film thickness L2 of the first interlayer insulating film 6a between the first wiring and the polycrystalline semiconductor layer 3 and the film thickness L3 of the second interlayer insulating film 6b between the first wiring and the second wiring 8. This is because the total thickness L1 of the interlayer insulating film 6 on which 7 is formed is nearly double.

  Therefore, in the present embodiment, the base pattern 10 is formed corresponding to the contact hole 7 formation portion of the polycrystalline semiconductor layer 3, that is, the source region 3a and the drain region 3b, and this portion is raised, compared with the other portions. To increase the height. In the present embodiment, the base pattern 10 is formed in direct contact with the polycrystalline semiconductor layer 3, and the base pattern 10 is formed of a conductive material.

  When such a base pattern 10 is formed, as schematically shown in FIG. 2B, the thickness L4 of the interlayer insulating film 6 in the contact hole 7 formation portion becomes thinner than the previous thickness L1, The film thickness difference is alleviated. As a result, even when the contact hole 7 is formed at the same time as the contact hole between the first wiring and the polycrystalline semiconductor layer 3 or the contact hole between the first wiring and the second wiring 8, a uniform contact hole can be formed. Thus, for example, connection failure due to insufficient etching does not occur.

  In order to alleviate the film thickness difference of the interlayer insulating film 6 as described above, it is preferable to form the second interlayer insulating film 6b with a planarizing material. If the second interlayer insulating film 6b is formed of a planarizing material, the second interlayer insulating film 6b is formed so as to flatten the step, and the second interlayer insulating film formed on the stepped portion (on the base pattern 10). The film thickness of 6b becomes relatively thin. Examples of the second interlayer insulating film 6b made of a planarizing material include a coating film, a fluid CVD film, and a reflow film.

  As described above, the formation of the base pattern 10 is effective for the uniform formation of the contact holes 7, but in the case of the present embodiment, since the base pattern 10 is formed of a conductive material, the reliability of electrical connection is increased. Can be secured sufficiently. Usually, in the connection by forming the contact hole 7, the connection between the second wiring 8 and the polycrystalline semiconductor layer 3 is the connection by the bottom contact (the bottom surface of the second wiring 8 and the top surface of the polycrystalline semiconductor layer 3 are in contact with each other). Connection) or side wall contact (connection caused by contact of the outer peripheral surface of the second wiring 8 with the polycrystalline semiconductor layer 3 facing the side wall of the contact hole 7). When the contact hole 7 is formed so as to penetrate the polycrystalline semiconductor layer 3, the latter connection form is formed, and the contact resistance may be increased because the contact area is small. In consideration of connection resistance and the like, it is preferable to form the contact hole 7 up to the middle position of the polycrystalline semiconductor layer 3, but since the thickness of the polycrystalline semiconductor layer 3 is extremely thin, the etching is controlled in such a state. Difficult to do.

  On the other hand, if the base pattern 10 is formed of a conductive material, even when the contact hole 7 is formed by over-etching, sufficient contact is ensured and an increase in connection resistance can be prevented. That is, even when the contact hole 7 is formed so as to penetrate the polycrystalline semiconductor layer 3, the second wiring 8 is in contact with the underlying pattern 10 in addition to the sidewall contact. Since the base pattern 10 is formed of a conductive material and is formed in direct contact with the polycrystalline semiconductor layer 3, the second wiring 8 is in contact with the polycrystalline semiconductor layer 3 with a sufficient contact area. It is equivalent and sufficient conductivity is ensured.

  Next, a method for manufacturing a thin film transistor having the above structure will be described.

  FIG. 3 is a drawing showing a manufacturing process of the thin film transistor shown in FIG. 1 in the order of steps. In order to manufacture the thin film transistor shown in FIG. 1, first, the undercoat layer 2 is formed on the glass substrate 1, and the base material layer 11 is formed on the undercoat layer 2 as shown in FIG. In the case of this embodiment, the base material layer 11 is formed of a conductive material. Further, since the height of the base pattern 10 is determined by the thickness of the base material layer 11, the thickness may be set as appropriate in consideration of the thickness of the interlayer insulating film 6 and the like.

  Next, as shown in FIG. 3B, the base material layer 11 is etched with a predetermined pattern to form a base pattern 10. The base pattern 10 is formed at a position corresponding to the contact hole 7 formation portion of the polycrystalline semiconductor layer 3.

  After the formation of the base pattern 10, the polycrystalline semiconductor layer 3 and the like are formed according to a normal process. The polycrystalline semiconductor layer 3 is formed, for example, by forming an amorphous silicon film by a technique such as CVD and then polycrystallizing it by a technique such as laser annealing. As shown in FIG. 3C, the polycrystalline semiconductor layer 3 is etched according to the arrangement of the thin film transistors and separated into islands.

  After the polycrystalline semiconductor layer 3 is separated into islands, a gate insulating film 4 and a metal film are formed on the entire surface so as to cover the polycrystalline semiconductor layer 3 as shown in FIG. The metal film corresponds to the gate electrode. Next, the metal film is etched to form the gate electrode 5. Here, the metal film is etched using a resist corresponding to the pattern shape of the gate electrode 5 as a mask. After the etching of the gate insulating film 4, impurities are implanted into the polycrystalline semiconductor layer 3 using the gate electrode 5 as a mask to form a source region 3a and a drain region 3b, and further an LDD region (low concentration impurity diffusion region). To do.

  Next, as shown in FIG. 3E, a first interlayer insulating film 6a is formed on the entire surface, and further, after forming a first wiring (not shown), a second interlayer insulating film 6b is formed. . The first interlayer insulating film 6a may be formed, for example, using silicon oxide or silicon nitride by a technique such as CVD. The first wiring is formed by patterning by photolithography after forming a metal film on the entire surface. The second interlayer insulating film 6b is preferably formed of a planarizing material. For example, a coating film, a fluid CVD film, a reflow film, or the like may be formed as the second interlayer insulating film 6b. By forming the second interlayer insulating film 6b with a planarizing material, the second interlayer insulating film 6b is formed so as to fill the step, and the second interlayer insulating film 6b formed on the step (on the base pattern 10) is formed. The film thickness can be reduced.

  After the interlayer insulating film 6 (first interlayer insulating film 6a and second interlayer insulating film 6b) is formed as described above, a contact hole 7 is formed in the interlayer insulating film 6 as shown in FIG. The second wiring 8 formed on the interlayer insulating film 6b and the polycrystalline semiconductor layer 3 (source region 3a and drain region 3b) are electrically connected. The contact hole 7 is formed by forming a resist pattern by photolithography and etching using the resist pattern as a mask.

  After the formation of the contact hole 7, as shown in FIG. 3G, the second wiring 8 is formed and connection with the polycrystalline semiconductor layer 3 is achieved. Since the contact hole 7 can be formed uniformly and no etching residue or the like occurs, a highly reliable connection state can be realized. Further, a protective film 9 is formed to complete the thin film transistor.

  The above-described thin film transistor can be used as a driving transistor or the like in a display device such as a liquid crystal display device. For example, in a liquid crystal display device, narrowing the frame area is a major issue, and multilayer wiring is being studied. By adopting the thin film transistor structure of the present invention in a multi-layered liquid crystal display device, a highly reliable connection state can be maintained, which is effective in promoting the narrowing of the frame region.

  Hereinafter, an example of a liquid crystal display device to which the present invention is applied will be described. The liquid crystal display device includes a liquid crystal display panel 21 including an array substrate 22 and a counter substrate 23 as shown in FIG. The liquid crystal layer between the counter substrate 23 and the counter substrate 23 is driven by using a thin film transistor (pixel transistor) formed on the array substrate 22 as a switching element, thereby displaying an image.

  Here, in the display region H, pixel electrodes are formed on the array substrate 22 corresponding to the respective pixels in a matrix, scanning lines are formed along the row direction of the pixel electrodes, and signals along the column direction are formed. A line is formed. Further, the pixel transistor is formed at the intersection of each scanning line and signal line.

  On the other hand, in the peripheral region of the array substrate 22 (the frame region of the liquid crystal display panel 21), a signal line drive circuit 24 that supplies drive signals to the signal lines arrayed on the array substrate 22 and a drive signal is supplied to the scanning lines. A driving circuit such as the scanning line driving circuit 25 is formed. These drive circuits are composed of a plurality of thin film transistors and a plurality of wirings connected to the thin film transistors. By adopting the thin film transistors having the above-described structure as the thin film transistors, a highly reliable liquid crystal display device is realized. Can do.

(Second Embodiment)
In the present embodiment, the polycrystalline semiconductor layer 3 is formed on the base pattern 10 via the undercoat layer 2. Other configurations are the same as those of the first embodiment.

  FIG. 5 shows the structure of the thin film transistor of this embodiment, and FIG. 6 is a schematic view showing the contact hole forming portion in an enlarged manner. In the present embodiment, the base pattern 10 is directly formed on the glass substrate 1, and the polycrystalline semiconductor layer 3 is formed thereon with the undercoat layer 2 interposed therebetween.

  In the thin film transistor of this embodiment, since the undercoat layer 2 that is an insulating film exists between the base pattern 10 and the polycrystalline semiconductor layer 3, the connection between the second wiring 8 and the polycrystalline semiconductor layer 3 is premised on the side wall contact. Become. Therefore, the base pattern 10 does not have to be a conductive material, and may be formed of any material as long as the thickness (height) can be secured and the material can withstand the thermal history. However, for example, when the base pattern 10 is formed of a Si material, there is a possibility that a problem occurs that the selection ratio at the time of etching is small and the processing margin is narrowed. From such a viewpoint, Ti, Mo, W, or the like is preferable as the material of the base pattern 10. Ti, Mo, W, etc. have the advantage that the selection ratio at the time of etching is larger than that of Si-based materials and the processing margin is wide.

  Also in the thin film transistor of this embodiment, since the base pattern 10 is formed and the contact hole forming portion of the polycrystalline semiconductor layer 3 is formed thereon, a uniform contact hole can be formed, for example, connection due to insufficient etching There will be no defects.

It is a schematic sectional drawing which shows the structure of the thin-film transistor of 1st Embodiment. (A) is a schematic diagram showing an enlarged view of the vicinity of a contact hole of a thin film transistor having no underlying pattern, and (b) is an enlarged schematic view showing the vicinity of a contact hole of a thin film transistor having an underlying pattern. It is a schematic sectional drawing which shows the manufacturing process of the thin-film transistor of 1st Embodiment, (a) is a base material layer formation process, (b) is a base pattern formation process, (c) is a polycrystalline-semiconductor layer formation process, (d ) Shows a gate insulating electrode forming step, (e) shows an interlayer insulating film forming step, (f) shows a contact hole forming step, and (g) shows a second wiring forming step. It is a perspective view which shows schematic structure of a liquid crystal display panel. It is a schematic sectional drawing which shows the structure of the thin-film transistor of 2nd Embodiment. It is a schematic diagram which expands and shows the contact hole vicinity of the thin-film transistor of 2nd Embodiment.

Explanation of symbols

1 glass substrate, 2 undercoat layer, 3 polycrystalline semiconductor layer, 3a source region, 3b drain region, 4 gate insulating film, 5 gate electrode, 6 interlayer insulating film, 6a first interlayer insulating film, 6b second interlayer insulating film , 7 Contact hole, 8 Second wiring, 9 Protective film, 10 Base pattern, 21 Liquid crystal display panel, 22 Array substrate, 23 Counter substrate, 24 Signal line drive circuit, 25 Scan line drive circuit

Claims (5)

A thin film transistor in which a semiconductor layer is an active layer and a wiring is connected to the semiconductor layer through a contact hole formed in an interlayer insulating film,
The wiring connected to the semiconductor layer is an upper layer wiring of the second layer or more of the multilayer wiring,
A thin film transistor, wherein a base pattern having a predetermined thickness is formed at a position corresponding to the contact hole, and a connecting portion of the semiconductor layer to the upper layer wiring is formed on the base pattern.   2. The thin film transistor according to claim 1, wherein at least part of the interlayer insulating film is formed of a planarizing material.   3. The thin film transistor according to claim 1, wherein the base pattern is formed of a conductive material, and the semiconductor layer is formed in direct contact with the base pattern.   3. The thin film transistor according to claim 1, wherein the semiconductor layer is formed on the base pattern through an undercoat layer. A method of manufacturing a thin film transistor in which a semiconductor layer is an active layer, and an upper layer wiring of a second layer or more of multilayer wirings is connected to the semiconductor layer through a contact hole formed in an interlayer insulating film,
Forming a base pattern having a predetermined thickness at a position corresponding to a contact hole on the substrate;
Forming a semiconductor layer so that a connection portion with an upper layer wiring overlaps the base pattern;
Forming an interlayer insulating film covering the semiconductor layer;
Forming a contact hole in the interlayer insulating film;
And a step of forming an upper layer wiring connected to the semiconductor layer through the contact hole.

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