JP2010056136A - Wiring, method of manufacturing the same, thin film transistor, and display element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide wiring that suppresses oxidation of a copper wiring layer and diffusion of copper while securing excellent shape controllability. <P>SOLUTION: A seed layer 52 formed on a metal diffusion preventive film 51 is selectively removed using resist. After the resist is removed, the copper wiring layer 53 and a metal mask layer 54 disposed on the copper wiring layer 53 are formed, in an electroless plating method, while covering the seed layer 52. The metal diffusion preventive layer 51 is selectively removed using the metal mask layer 54. While the excellent shape controllability is secured, the copper wiring layer 53 is prevented from having its surface roughened owing to etching etc., during the formation of the metal diffusion preventive film 51, thereby suppressing the oxidation of the copper wiring layer 53 and the diffusion of copper. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a wiring including a copper wiring layer, a manufacturing method thereof, a thin film transistor, and a display element.

  Conventionally, for example, thin film transistors (TFTs) used in various devices such as liquid crystal display elements or organic EL display elements or semiconductor devices, semiconductor layers, gate electrodes, source electrodes, drain electrodes, etc. It is formed by laminating in the form of a thin film via.

  In such a thin film transistor, in recent years, damage due to electromigration in the gate electrode has become a problem due to an increase in current density accompanying miniaturization and high integration of various devices. Therefore, the structure which forms a gate electrode with copper with high tolerance with respect to electromigration has increased.

  When forming such a gate electrode with copper, for example, a metal diffusion prevention film and a seed layer made of copper are sequentially formed on an insulating substrate, a resist is formed on the seed layer, and the seed layer is formed. After removing and patterning selectively by etching or the like, and depositing a copper wiring layer on the seed layer, the metal diffusion prevention film is selectively removed by etching or the like and patterned using the copper wiring layer. It is known (for example, see Patent Document 1).

  Further, a metal diffusion prevention film and a seed layer formed of copper are sequentially formed on the insulating substrate, a copper wiring layer is formed at a predetermined position on the seed layer, and the metal diffusion prevention film and the A configuration in which the seed layer is patterned by etching or the like is also conceivable.

Further, a metal diffusion prevention film and a seed layer formed of copper are sequentially formed on the insulating substrate, a copper wiring layer is formed on the seed layer at a predetermined position, and the seed layer is etched using the copper wiring layer. It is also conceivable that the resist is patterned on the metal diffusion prevention film so as to be wider than the copper wiring layer, and the metal diffusion prevention film is patterned in a bowl shape by etching or the like.
JP 2004-134771 A

  However, in the above-described wiring manufacturing method, since the copper wiring layer itself is used for etching the metal diffusion prevention film and no mask is used, the shape controllability of the copper wiring layer is not sufficient, and the metal diffusion prevention film is etched. At this time, there is a problem that the surface becomes rough, and this roughness may promote the diffusion of copper from the end portion of the metal diffusion preventing film or the side surface of the copper wiring film.

  The present invention has been made in view of the above points, and provides a wiring capable of suppressing oxidation and copper diffusion of a copper wiring layer while ensuring good shape controllability, a manufacturing method thereof, a thin film transistor, and a display element. For the purpose.

  The present invention relates to a metal diffusion prevention film formed on an insulating substrate, a seed layer formed on the metal diffusion prevention film, and a copper wiring layer formed on the metal diffusion prevention film so as to cover the seed layer. And a metal mask layer formed so as to cover the seed layer and the copper wiring layer and aligned with the metal diffusion prevention film.

  The present invention also provides a first metal diffusion prevention film formed on an insulating substrate, a seed layer formed on the first metal diffusion prevention film, a copper wiring layer formed on the seed layer, A second metal diffusion prevention film formed to cover the seed layer and the copper wiring layer and aligned with the first metal diffusion prevention film is provided.

  Furthermore, the present invention forms a metal diffusion prevention film on an insulating substrate, forms a seed layer on the metal diffusion prevention film, forms a resist on the seed layer, and selectively removes the seed layer. After removing the resist, the seed layer is covered, a copper wiring layer and a metal mask layer located on the copper wiring layer are formed by an electroless plating method, and the metal mask layer is used to form the metal The diffusion preventing film is selectively removed.

  According to the present invention, a first metal diffusion prevention film is formed on an insulating substrate, a seed layer is formed on the first metal diffusion prevention film, a first resist is formed on the seed layer, and a copper wiring layer is formed. And a metal mask layer located on the copper wiring layer, and after removing the first resist, the seed layer is selectively removed using the metal mask layer, and the metal mask layer is removed. After the removal, a second metal diffusion prevention film is formed to cover the copper wiring layer and the seed layer, and a second resist is formed on the second metal diffusion prevention film to form the first metal diffusion prevention film and the first metal diffusion prevention film. The second metal diffusion prevention film is selectively removed to remove the second resist.

  According to the present invention, the seed layer formed on the metal diffusion prevention film is selectively removed using a resist, and after removing this resist, the copper layer is covered by an electroless plating method covering the seed layer, Forming a metal mask layer located on the copper wiring layer, and selectively removing the metal diffusion prevention film using the metal mask layer, while ensuring good shape controllability, and the metal diffusion prevention film It is possible to prevent the surface of the copper wiring layer from being roughened at the time of forming and to suppress the oxidation of the copper wiring layer and the diffusion of copper.

  According to the present invention, the first resist is formed on the seed layer formed on the first metal diffusion prevention film, the copper wiring layer and the metal mask layer are formed by plating, the first resist is removed, and then the metal mask is formed. The seed layer is selectively removed using the layer and the metal mask layer is removed, and then a second metal diffusion prevention film is formed to cover the copper wiring layer and the seed layer, and the second metal diffusion prevention film is formed on the second metal diffusion prevention film. By forming the second resist and selectively removing the first metal diffusion prevention film and the second metal diffusion prevention film, the copper wiring layer is formed at the time of forming each metal diffusion prevention film while ensuring good shape controllability. It is possible to prevent the surface roughness of the copper and the like, and to suppress the oxidation of the copper wiring layer and the diffusion of copper.

  Hereinafter, the configuration of the first embodiment of the present invention will be described with reference to FIGS.

  In FIG. 6, reference numeral 11 denotes a liquid crystal display element as a display element, that is, a liquid crystal panel which is an LCD (Liquid Crystal Display). A transmission type that modulates and transmits the image.

  The liquid crystal panel 11 is, for example, an active matrix type capable of color display, and an array substrate 16 as a first substrate and a counter substrate 17 as a second substrate are connected via a spacer (not shown) that is a gap holding member. The liquid crystal layer 18 that is a light modulation layer is interposed between the substrates 16 and 17, and polarizing plates (not shown) are attached to the substrates 16 and 17, respectively. A rectangular display region 20 in which sub-pixels SP (FIG. 5), which are pixels for displaying an image, are formed in a matrix is formed in a substantially central portion by being bonded and fixed by a seal portion 19 as an adhesive portion. In addition, a frame portion 21 that is a frame-like non-display region is formed around the display region 20.

  The array substrate 16 includes, for example, a glass substrate 25 that is a first substrate body as a light-transmitting substrate. On the main surface of the glass substrate 25 on the liquid crystal layer 18 side, a conductor such as a metal member is used. The scanning lines (gate wirings) 31 (FIG. 5) and the signal lines (source wirings) 32 (FIG. 5), which are a plurality of wirings formed in a thin film, are arranged in a lattice pattern so as to be substantially orthogonal to each other. Further, a pixel driving thin film transistor (TFT) 33 (FIG. 5) as a switching element is provided at each crossing position of the scanning line 31 and the signal line 32, and the alignment of the liquid crystal molecules of the liquid crystal layer 18 is provided thereon. An alignment film (not shown) is provided. As shown in FIG. 5, the scanning line 31 is electrically connected to a gate driver 36 which is a scanning line driving circuit as a driving circuit, and the signal line 32 is a signal line driving circuit as a driving circuit. It is electrically connected to a certain source driver 37.

  The thin film transistor 33 is, for example, a top gate type thin film transistor. As shown in FIG. 4, an active layer 33c as a semiconductor layer is formed on a glass substrate 25, and the active layer 33c is formed of a silicon oxide film or a silicon nitride film. A gate electrode 33g as a wiring is formed on the interlayer insulating film 41, and the gate electrode 33g is covered with a silicon oxide film or nitride. A gate insulating film 42, which is a second insulating film such as a silicon film, is formed. A source electrode 33s and a drain electrode 33d are formed on the gate insulating film 42, and the source electrode 33s and the drain electrode 33d are respectively connected to the contact holes 44. , 45 and is electrically connected to the active layer 33c and covers the source electrode 33s and the drain electrode 33d, and is a silicon oxide film or A protective insulating film 47, which is a third insulating film such as a silicon nitride film, is formed.

  The active layer 33c is formed in an island shape from, for example, polycrystalline silicon which is a non-oxide semiconductor, that is, polysilicon (p-Si). In the active layer 33c, a source region 33cs electrically connected to the source electrode 33s is formed on one side, and a drain region 33cd electrically connected to the drain electrode 33d is formed on the other side, and the gate A channel region 33cc facing the electrode 33g is formed between the source region 33cs and the drain region 33cd.

  As shown in FIG. 1, the gate electrode 33g covers the metal diffusion prevention film 51 formed on the gate insulating film 42, the seed layer 52 formed on the metal diffusion prevention film 51, and the seed layer 52. A copper (Cu) wiring layer 53 and a metal mask layer 54 are formed.

  The metal diffusion preventing film 51 is, for example, a tantalum (Ta) film, a tantalum nitride (TaN) film, a titanium nitride (TiN) film, a TaSiN film, a WSiN film, or the like.

  The seed layer 52 is made of, for example, copper, and the upper surface side serves as a deposition electrode portion when the copper wiring layer 53 is formed by an electroless plating method.

  The copper wiring layer 53 is formed over the metal diffusion preventing film 51 so as to cover the entire seed layer 52. That is, the copper wiring layer 53 has a peripheral surface 53s located outside the peripheral surface 52s of the seed layer 52.

  The metal mask layer 54 is used for alignment of the metal diffusion prevention film 51 and is formed on the metal diffusion prevention film 51 so as to cover the entire copper wiring layer 53 by nickel (Ni) or tin (Sn), for example. . That is, the metal mask layer 54 has a peripheral surface 54s located outside the peripheral surface 53s of the copper wiring layer 53.

  The source electrode 33s and the drain electrode 33d are made of, for example, aluminum.

  As shown in FIG. 5, the thin film transistor 33 is switched by applying a signal from the gate driver 36 to the gate electrode 33g through the scanning line 31, and is input from the source driver 37 through the signal line 32. By applying a voltage to the pixel electrode in response to the signal, the subpixels SP can be driven to turn on / off independently.

  The gate driver 36 and the source driver 37 are electrically connected to a controller (not shown) that is formed on the glass substrate 25 (FIG. 6) and includes a data processing circuit and a clock generation circuit. Here, the data processing circuit processes RGB data input from an external device or the like and outputs it as a video signal to the source driver 37. The clock generation circuit operates in each of the drivers 36 and 37. A clock signal for controlling the timing is generated and output.

  The contact holes 44 and 45 shown in FIG. 4 are formed through the gate insulating film 42 and the interlayer insulating film 41 by etching or the like, for example.

  Further, as shown in FIG. 6, the counter substrate 17 has a glass substrate 55 which is a second substrate body as a light-transmitting substrate. On the glass substrate 55, a color filter layer and a counter electrode (not shown) are provided. In addition, an alignment film and the like are sequentially stacked.

  The color filter layer is formed in a thin film shape for each sub-pixel SP, for example, with a synthetic resin corresponding to the three primary colors of RGB, and has, for example, a stripe shape in plan view. The color filter layer may be formed on the array substrate 16 side.

  The counter electrode is formed by a sputtering method or the like with a transparent conductive material such as ITO at a position corresponding to the pixel electrode in the display region 20.

  The liquid crystal layer 18 is a light modulation layer formed of a predetermined liquid crystal material.

  Further, the seal portion 19 is formed in a frame shape (frame shape) surrounding the display region 20 with a predetermined adhesive or the like.

  Next, the operation of the first embodiment will be described.

  When manufacturing the array substrate 16, first, an amorphous silicon (a-Si) film is formed on the glass substrate 25 on which an undercoat layer (not shown) is formed by, for example, a CVD (Chemical Vapor Deposition) method (amorphous silicon). Film forming step), after annealing for a predetermined time at a predetermined temperature (annealing step), this amorphous silicon film is melt-crystallized by, for example, excimer laser annealing (ELA) method to form a polysilicon film, and into a predetermined shape by photoetching or the like Patterning is performed (polysilicon film forming step).

  Next, an interlayer insulating film 41 is formed so as to cover the polysilicon film by, eg, CVD (interlayer insulating film forming step).

  Thereafter, various thin films (not shown) are deposited on the interlayer insulating film 41 and patterned into a predetermined shape, thereby forming the gate electrode 33g together with the scanning lines 31 and the like (gate electrode forming step).

  In this gate electrode formation step, first, as shown in FIG. 2, a metal diffusion prevention film 51 is formed on the interlayer insulating film 41 by, for example, a sputtering method (metal diffusion prevention film formation step). At this time, when the metal diffusion preventing film 51 is, for example, a tantalum nitride film, argon gas and nitrogen gas are used as sputtering gases and tantalum is used as a target. When the metal diffusion preventing film 51 is a tantalum film, for example, argon gas is used as a sputtering gas and tantalum is used as a target.

  Next, a seed layer 52 is formed on the metal diffusion prevention film 51 by sputtering or the like (seed layer forming step).

  Further, a resist R is formed at a position corresponding to the position where the copper wiring layer 53 is formed on the seed layer 52 (resist forming step), and the seed layer 52 is selectively removed by etching and patterned (seed layer patterning). Process).

  Next, after removing the resist R (resist removing step), as shown in FIG. 3, a copper wiring layer 53 and a metal mask layer located on the copper wiring layer 53 are formed by electroless plating using the seed layer 52 as an electrode. 54 are sequentially formed (a copper wiring layer forming step and a metal mask layer forming step).

  Then, as shown in FIG. 1, the metal diffusion prevention film 51 is selectively removed by etching using the metal mask layer 54 and patterned (metal diffusion prevention film patterning step). That is, the metal diffusion preventing film 51 is self-aligned by the metal mask layer 54, and completes the gate electrode 33g.

  Thereafter, a source region 33cs and a drain region 33cd are formed in the active layer 33c by partially masking with a resist or the like applied so that impurities are not implanted and doping with boron or phosphorus, for example (doping). Process). At this time, the channel region 33cc is formed between the source region 33cs and the drain region 33cd.

  Further, the gate insulating film 42 covering the gate electrode 33g is formed by using, for example, PECVD (Plasma Enhanced CVD) (gate insulating film forming step).

  Then, contact holes 44 and 45 are formed in the gate insulating film 42 and the interlayer insulating film 41 by, for example, photoetching (first contact hole forming step), and further, tantalum, chromium, aluminum, molybdenum, tungsten, copper, etc. Each electrode 33s, 33d is formed (electrode forming step) by depositing a single layer or a laminated film thereof or an alloy film and patterning it into a predetermined shape by a photoetching method or the like, thereby completing the thin film transistor 33.

  Thereafter, a protective insulating film 47 is formed by PECVD or the like so as to cover these electrodes 33s and 33d (protective insulating film forming step), for example, a contact hole is formed by a photoetching method (second contact hole forming step), For example, an ITO film is formed by sputtering or the like, and then patterned into a predetermined shape by a photoetching method or the like to form a pixel electrode (pixel electrode forming step), and further, an alignment film and a spacer are formed to form an array substrate 16 To complete.

  As described above, according to the first embodiment, the seed layer 52 formed on the metal diffusion prevention film 51 is selectively removed using the resist R, and after removing the resist R, the seed layer 52 is removed. A copper wiring layer 53 and a metal mask layer 54 located on the copper wiring layer 53 are formed by electroless plating so as to cover the layer 52, and the metal diffusion prevention film 51 is selectively used by using the metal mask layer 54. By removing the gate electrode 33g, the surface of the copper wiring layer 53 due to etching or the like during the formation of the metal diffusion prevention film 51 is prevented while ensuring good shape controllability. The oxidation of the wiring layer 53 and the diffusion of copper can be suppressed.

  In addition, by forming the thin film transistor 33 having the gate electrode 33g that has good shape controllability and can suppress the oxidation and copper diffusion of the copper wiring layer 53, the reliability can be improved while ensuring the resistance to electromigration. By using the thin film transistor 33 for driving the sub-pixel SP, the reliability of the liquid crystal panel 11 can be secured.

  Next, a second embodiment will be described with reference to FIGS. In addition, about the structure and effect | action similar to the said 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  In the second embodiment, instead of the gate electrode 33g of the first embodiment, a first metal diffusion preventing film 61 and a seed layer 52 are formed on an interlayer insulating film 41 as shown in FIG. And a gate electrode 33g having a copper wiring layer 53 and a second metal diffusion prevention film 62.

  The first metal diffusion preventing film 61 is, for example, a tantalum (Ta) film, a tantalum nitride (TaN) film, a titanium nitride (TiN) film, a TaSiN film, a WSiN film, or the like.

  The seed layer 52 is formed on the first metal diffusion prevention film 61.

  The copper wiring layer 53 is formed on the seed layer 52. That is, the copper wiring layer 53 has a peripheral surface 53s1 that is substantially flush with the peripheral surface 52s1 of the seed layer 52.

  Like the first metal diffusion prevention film 61, the second metal diffusion prevention film 62 is, for example, a tantalum (Ta) film, or a tantalum nitride (TaN) film, a titanium nitride (TiN) film, a TaSiN film, or a WSiN film. The seed layer 52 and the copper wiring layer 53 are formed on the first metal diffusion prevention film 61. That is, the second metal diffusion preventing film 62 is formed on the peripheral surface 62s1 that is located outward from the peripheral surface 53s1 of the copper wiring layer 53, and at the position that protrudes outward from the lower end of the peripheral surface 62s1. The peripheral surface 61s of the prevention film 61 and the peripheral surface 62s2 that is substantially flush with the peripheral surface 61s.

  In the gate electrode forming step, first, as shown in FIG. 8, a first metal diffusion preventing film 61 is formed on the interlayer insulating film 41 by, for example, a sputtering method (first metal diffusion preventing film forming step). At this time, when the metal diffusion preventing film 51 is, for example, a tantalum nitride film, argon gas and nitrogen gas are used as sputtering gases and tantalum is used as a target. When the metal diffusion preventing film 51 is a tantalum film, for example, argon gas is used as a sputtering gas and tantalum is used as a target.

  Next, a seed layer 52 is formed on the first metal diffusion preventing film 61 by sputtering or the like (seed layer forming step).

  Further, a first resist R1 is formed on the seed layer 52 except for a position corresponding to the position where the copper wiring layer 53 is formed (first resist forming step), and the groove formed in the first resist R1 is formed. Then, a copper wiring layer 53 and a metal mask layer 64 are formed on the seed layer 52 by an electroless plating method or an electrolytic plating method (a copper wiring layer forming step and a metal mask layer forming step).

  Next, as shown in FIG. 9, after removing the first resist R1 (first resist removal step), the seed layer 52 is selectively removed by etching using the metal mask layer 64 and patterned (seed layer patterning). Process). That is, the seed layer 52 is self-aligned by the metal mask layer 64.

  Also, as shown in FIG. 10, after removing the metal mask layer 64 (metal mask removal step), the second metal diffusion prevention film 62 is covered with the first metal diffusion prevention film 62 so as to cover the copper wiring layer 53 and the seed layer 52. 61 is formed (second metal diffusion prevention film forming step).

  Further, as shown in FIG. 11, a second resist R2 is formed on the second metal diffusion preventing film 62 at a portion corresponding to the copper wiring layer 53 (second resist forming step), and this second resist R2 is used. Then, the first metal diffusion prevention film 61 and the second metal diffusion prevention film 62 are selectively removed by etching and patterned (metal diffusion prevention film patterning step), and the second resist R2 is removed (second resist removal step). ) To complete the gate electrode 33g.

  Thus, according to the second embodiment, the first resist R1 is formed on the seed layer 52 formed on the first metal diffusion prevention film 61, and the copper wiring layer 53 and the metal mask layer 64 are formed by plating. After removing the first resist R1, the seed layer 52 is selectively removed using the metal mask layer 64, and after removing the metal mask layer 64, the copper wiring layer 53 and the seed layer 52 are covered and the second layer is covered. A metal diffusion prevention film 62 is formed, a second resist R2 is formed on the second metal diffusion prevention film 62, and the first metal diffusion prevention film 61 and the second metal diffusion prevention film 62 are selectively removed. By forming the gate electrode 33g, it is possible to prevent surface roughness of the copper wiring layer 53 due to etching or the like during the formation of the respective metal diffusion prevention films 61 and 62 while ensuring good shape controllability, thereby preventing the copper wiring layer 53 oxidation and copper diffusion can be suppressed.

  In addition, by forming the thin film transistor 33 having the gate electrode 33g that has good shape controllability and can suppress the oxidation and copper diffusion of the copper wiring layer 53, the reliability can be improved while ensuring the resistance to electromigration. By using the thin film transistor 33 for driving the sub-pixel SP, the reliability of the liquid crystal panel 11 can be secured.

  In each of the above embodiments, the insulating base on which the wiring is formed can be not only the interlayer insulating film 41 but also any other insulating material.

  The thin film transistor 33 may be used not only for driving the sub-pixel SP of the display element but also for each of the drivers 36 and 37.

  Furthermore, as a display element, not only the liquid crystal panel 11 but also an arbitrary display element such as an organic EL display element can be supported.

  The thin film transistor 33 may be not only a top gate type but also a bottom gate type, and can be used not only for a display element but also for any semiconductor device.

  Further, as the wiring, not only the gate electrode 33g of the thin film transistor 33 but also any wiring can be used.

It is explanatory sectional drawing which shows the wiring of the 1st Embodiment of this invention. It is explanatory sectional drawing which shows the resist formation process and seed layer patterning process of the manufacturing method of wiring same as the above. It is explanatory sectional drawing which shows the copper wiring layer formation process and metal mask layer formation process of the manufacturing method of wiring same as the above. It is explanatory sectional drawing which shows the thin-film transistor provided with the same wiring. It is a circuit diagram which shows the display element provided with the thin-film transistor same as the above. It is a description side view which shows a display element same as the above. It is explanatory sectional drawing which shows the wiring of the 2nd Embodiment of this invention. It is explanatory sectional drawing which shows the 1st metal diffusion prevention film formation process thru | or metal mask layer formation process of the manufacturing method of wiring same as the above. It is explanatory sectional drawing which shows the seed layer patterning process of the manufacturing method of a wiring same as the above. It is explanatory sectional drawing which shows the 2nd metal diffusion prevention film formation process of the manufacturing method of wiring same as the above. It is explanatory sectional drawing which shows the metal diffusion prevention film patterning process of the manufacturing method of wiring same as the above.

Explanation of symbols

11 Liquid crystal panels as display elements
25, 55 Glass substrate as substrate
33 Thin-film transistors
33c Active layer as semiconductor layer
33cc channel region
33cd drain region
33cs source area
33d drain electrode
33g Gate electrode as wiring
33s source electrode
41 Interlayer insulating film as an insulating substrate
51 Metal diffusion prevention film
52 Seed layer
53 Copper wiring layer
54, 64 Metal mask layer
61 First metal diffusion barrier
62 Second metal diffusion prevention film R resist
R1 1st resist
R2 2nd resist
Sub pixel that is SP pixel

Claims (6)

A metal diffusion prevention film formed on the insulating substrate;
A seed layer formed on the metal diffusion barrier film;
A copper wiring layer formed on the metal diffusion barrier film covering the seed layer;
A wiring comprising: a metal mask layer formed to cover the seed layer and the copper wiring layer and aligned with the metal diffusion prevention film. A first metal diffusion prevention film formed on the insulating substrate;
A seed layer formed on the first metal diffusion barrier film;
A copper wiring layer formed on the seed layer;
A wiring comprising: a second metal diffusion prevention film formed to cover the seed layer and the copper wiring layer and aligned with the first metal diffusion prevention film. Forming a metal diffusion prevention film on the insulating substrate,
A seed layer is formed on the metal diffusion prevention film,
Forming a resist on the seed layer to selectively remove the seed layer;
After removing the resist, covering the seed layer, forming a copper wiring layer and a metal mask layer located on the copper wiring layer by an electroless plating method,
A method of manufacturing a wiring, wherein the metal diffusion prevention film is selectively removed using the metal mask layer. Forming a first metal diffusion barrier film on the insulating substrate;
Forming a seed layer on the first metal diffusion barrier film;
Forming a first resist on the seed layer and plating a copper wiring layer and a metal mask layer located on the copper wiring layer;
After removing the first resist, the seed layer is selectively removed using the metal mask layer,
After removing the metal mask layer, a second metal diffusion prevention film is formed to cover the copper wiring layer and the seed layer,
Forming a second resist on the second metal diffusion prevention film and selectively removing the first metal diffusion prevention film and the second metal diffusion prevention film;
Removing the second resist. A method of manufacturing a wiring. A semiconductor layer comprising a channel region and a source region and a drain region located on both sides of the channel region;
The wiring according to claim 1 or 2, formed at a position corresponding to the channel region of the semiconductor layer and electrically insulated from the channel region,
A source electrode electrically connected to the source region of the semiconductor layer;
A thin film transistor comprising: a drain electrode electrically connected to the drain region of the semiconductor layer. A pair of substrates arranged opposite to each other;
Pixels formed on either one of these substrates,
A display element comprising: the thin film transistor according to claim 5 that drives each of the pixels.

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