KR102037406B1 - Display device and method of manufacturing the same - Google Patents
Display device and method of manufacturing the same Download PDFInfo
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- KR102037406B1 KR102037406B1 KR1020120035658A KR20120035658A KR102037406B1 KR 102037406 B1 KR102037406 B1 KR 102037406B1 KR 1020120035658 A KR1020120035658 A KR 1020120035658A KR 20120035658 A KR20120035658 A KR 20120035658A KR 102037406 B1 KR102037406 B1 KR 102037406B1
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- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 231
- 239000002184 metal Substances 0.000 claims abstract description 231
- 239000010949 copper Substances 0.000 claims abstract description 70
- 238000000034 method Methods 0.000 claims abstract description 48
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052802 copper Inorganic materials 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 96
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 62
- 239000000758 substrate Substances 0.000 claims description 40
- 239000010409 thin film Substances 0.000 claims description 35
- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000000956 alloy Substances 0.000 claims description 24
- 229910045601 alloy Inorganic materials 0.000 claims description 24
- 229910052759 nickel Inorganic materials 0.000 claims description 23
- 239000011651 chromium Substances 0.000 claims description 14
- 239000010936 titanium Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- ZPZCREMGFMRIRR-UHFFFAOYSA-N molybdenum titanium Chemical compound [Ti].[Mo] ZPZCREMGFMRIRR-UHFFFAOYSA-N 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 9
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 229910052804 chromium Inorganic materials 0.000 claims description 7
- 229910052750 molybdenum Inorganic materials 0.000 claims description 7
- 239000011733 molybdenum Substances 0.000 claims description 7
- 239000002356 single layer Substances 0.000 claims description 7
- 229910052715 tantalum Inorganic materials 0.000 claims description 7
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 6
- 238000007772 electroless plating Methods 0.000 abstract description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 18
- 238000000206 photolithography Methods 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 229910004205 SiNX Inorganic materials 0.000 description 7
- 238000011109 contamination Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical group [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000001994 activation Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Optics & Photonics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention discloses a display device that can not only improve the performance and reliability of the switching element but also simplify the process.
The disclosed display device includes a pixel region defined by crossing a plurality of gate lines and data lines, a gate electrode branched from the plurality of gate lines, and a single gate insulating layer and a gate insulating layer formed on the gate electrode. A source / drain electrode formed thereon, the gate electrode including first to third metal patterns, the first and second metal patterns being sequentially deposited, and the third metal pattern being first and second metal patterns Using the seed layer as a seed layer has a structure that covers the second metal pattern containing copper (Cu) to be closed from the outside by an electroless plating method.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and to a display device and a method of manufacturing the same, which can improve performance and reliability of a switching element and can simplify a process.
Recently, liquid crystal display devices, organic light emitting display devices, and the like, which have advantages of light weight, thinness, and low power consumption, have been used for office automation devices and audio / video devices.
The liquid crystal display device includes a liquid crystal layer as the electro-optical active layer, and the organic light emitting display device includes an organic light emitting layer as the electro-optical active layer.
The liquid crystal display displays an image by changing an electrical signal into visual information by using a characteristic in which light transmittance of a liquid crystal, which is an intermediate state material between a liquid and a crystal, changes according to an applied voltage. Conventional liquid crystal display devices are composed of two substrates provided with electrodes and a liquid crystal layer interposed between the two substrates. Such a liquid crystal display device is lighter in weight, smaller in volume, and operates with less power than other display devices having the same screen size.
A liquid crystal display device displays an image by selectively transmitting light generated from a light source at a rear side to each pixel of a liquid crystal display panel at a front side as a kind of light switch. That is, the conventional cathode ray tube (CRT) controls the brightness by adjusting the intensity of the electron beam, whereas the LCD displays the screen by controlling the intensity of light generated from the light source.
In the liquid crystal display panel of the liquid crystal display device as described above, the color filter substrate (upper substrate) on which the color filter is formed and the thin film transistor substrate (lower substrate) on which the thin film transistor (TFT) is formed are bonded together with the liquid crystal layer interposed therebetween. Consists of a structure.
In a thin film transistor substrate of a typical liquid crystal display panel, a gate line and a data line cross each other, and a thin film transistor TFT is formed at an intersection of the gate line and the data line.
The thin film transistor includes a gate electrode and a source / drain electrode with a gate insulating layer interposed therebetween, and the drain electrode is electrically connected to the pixel electrode.
A protective layer is formed on the gate insulating layer including the source / drain electrode and the pixel electrode, and a common electrode wiring and a common electrode pattern are formed on the protective layer.
As described above, the thin film transistor substrate included in the general liquid crystal display device uses copper (Cu) having low resistance as a material of the gate electrode and the source / drain electrode.
Such copper (Cu) is mainly used to form an opaque metal pattern of a thin film transistor substrate.
However, the copper (Cu) causes a problem of contaminating the semiconductor pattern through the silicon oxide (SiO 2) used as the gate insulating layer.
A general thin film transistor substrate forms a gate insulating layer of a multilayer structure in which silicon nitride (SiNx) and silicon oxide (SiO 2) are sequentially deposited in order to prevent performance of the thin film transistor due to copper (Cu).
However, in the general liquid crystal display device, even if a gate insulating layer including silicon nitride (SiNx) is formed to prevent performance degradation of the thin film transistor due to copper (Cu), contamination of the semiconductor pattern may not be completely prevented. Dry etching and wet etching processes for visualizing silicon nitride (SiNx) and silicon oxide (SiO2) must be sequentially performed when forming contact holes for contact between the electrodes and the pixel electrodes, gate pads, and data pads. There was a problem that the process was complicated.
It is an object of the present invention to provide a display device and a method of manufacturing the same, which can improve performance and reliability of a switching element, as well as simplify the process.
A display device according to an embodiment of the present invention,
A pixel region defined by crossing a plurality of gate lines and data lines; A gate electrode branched from the plurality of gate lines; A single gate insulating layer formed on the gate electrode; And a source / drain electrode formed on the gate insulating layer, wherein the gate electrode includes first to third metal patterns, and the first and second metal patterns are sequentially deposited and the third metal The pattern has a structure in which the second metal pattern including copper (Cu) is closed from outside by using the first and second metal patterns as seed layers.
Method of manufacturing a liquid crystal display device according to another embodiment of the present invention,
The first and second metal patterns are formed by laminating a photolithography process using a mask on a transparent substrate, and copper (Cu) is formed by electroless plating using the first and second metal patterns as seed layers. Forming a gate electrode and a gate line including forming a third metal pattern covering the second metal pattern to be closed from the outside; Forming a single gate insulating layer on the transparent substrate including the gate electrode and the gate line; Forming a semiconductor pattern on the gate insulating layer; And forming a source / drain electrode and a data line on the semiconductor pattern and the gate insulating layer.
The display device according to the exemplary embodiment of the present invention proposes a multilayer structure in which a metal pattern made of nickel (Ni) closes a metal pattern made of copper (Cu) in the gate electrode and the source / drain electrode. Has the advantage of simplifying the process by forming a single layer (silicon oxide). That is, the gate insulating layer of the present invention can simplify the manufacturing process by omitting the dry etching process for forming the contact hole by omitting silicon nitride of the general gate insulating layer of the multi-layer structure.
In addition, the present invention proposes a multilayer structure in which a metal pattern made of nickel (Ni) closes a metal pattern made of copper (Cu) in a gate electrode and a source / drain electrode, thereby providing a semiconductor layer made of copper (Cu). It has the advantage of improving the performance and reliability of TFT by preventing contamination.
1 is a plan view illustrating unit pixels of a thin film transistor substrate according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a thin film transistor substrate cut along lines II ′, II-II ′, III-III ′, and IV-IV ′ of FIG. 1.
3 is an enlarged cross-sectional view illustrating a thin film transistor region cut along the line II ′ of FIG. 2.
4A through 10C are plan and cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.
11 is a cross-sectional view illustrating a thin film transistor region of a thin film transistor substrate according to another exemplary embodiment of the present invention.
The present invention provides a pixel region defined by crossing a plurality of gate lines and data lines, a gate electrode branched from the plurality of gate lines, and a source formed on a single gate insulating layer and a gate insulating layer formed on the gate electrode. / Drain electrodes, the gate electrodes include first to third metal patterns, the first and second metal patterns are sequentially deposited, and the third metal pattern is the first and second metal patterns as seed layers. Thus, the second metal pattern including copper (Cu) is covered by an electroless plating method so as to be closed from the outside.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
One embodiment of the present invention is intended to sufficiently convey the technical spirit of the present invention to those skilled in the art. Therefore, the present invention is not limited to the embodiments described below, and other embodiments may be added based on the technical spirit of the present invention.
1 is a plan view illustrating unit pixels of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a line II-I ', II-II', III-III ', or IV-IV' of FIG. 1. FIG. 3 is a cross-sectional view illustrating a thin film transistor substrate cut along the line II ′ of FIG. 2.
As shown in FIGS. 1 to 3, a thin film transistor substrate according to an embodiment of the present invention is a thin film transistor for driving a liquid crystal cell at an intersection of a plurality of gate lines GL and a plurality of data lines DL. (TFT) is formed.
The gate line GL and the data line DL cross each other to define a pixel area. Here, the
A gate pad GP electrically connected to the gate line GL is formed at one end of the gate line GL, and a data pad electrically connected to the data line DL at one end of the data line DL. DP) is formed.
The thin film transistor TFT includes a
The
The
The
A second
The
The
The
The
The first and
That is, the first and
The
The
In detail, the
Therefore, the
Here, referring to the electroless plating, the organic material or oxide remaining in the portion where the metal layer pattern (for example, the second metal pattern 112) is formed through the pre-dip process, and then the activation process is performed. Palladium substitution plating through. For example, the
In addition, the gate line GL and the gate pad GP are simultaneously formed at the time of forming the
In addition, the gate pad GP may include a lower
A
The
In the present invention, the
The source /
The source /
The
The
The
The fourth and
That is, the fourth and
The
The
In detail, the
Therefore, the
The data line DL and the data pad DP are simultaneously formed when the source /
In addition, the data pad DP may include a lower
As described above, in the display device according to the exemplary embodiment, the second and fifth metal patterns made of copper (Cu) are formed by the third and
In addition, according to the present invention, the second and
4A through 10C are plan and cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.
4A to 4C, after depositing the first and second metal layers on the
Although not shown in detail in the drawing, in the photolithography process using the first mask, a photoresist, which is a photosensitive material, is formed on the deposited first and second metal layers, and then a mask having a transmissive region and a non-transmissive region is used. The exposure and development processes are performed to form a photoresist pattern.
Then, the metal film is etched using the photoresist pattern as a mask to form first and
The
The
5A through 5C, a
The
The
That is, the
6A through 6C, a
The
Each of the
7A to 7C, after depositing first and second metal layers on the
The fourth and
Although not shown in detail in the drawing, in the photolithography process using the fourth mask, a photoresist, which is a photosensitive material, is formed on the deposited first and second metal layers, and then a mask having a transmissive region and a non-transmissive region is used. The exposure and development processes are performed to form a photoresist pattern.
Next, the metal film is etched using the photoresist pattern as a mask to form fourth and
The
The
8A through 8C, a
The
The
That is, in the present invention, the
9A through 9C, a first passivation layer may be formed on the
The first
The first contact hole C1 is formed to expose the
The second contact hole C2 is formed to expose the lower
The third contact hole C3 is formed to expose the lower
10A to 10C, a transparent metal film is deposited on the
The
In the above description, the opaque
In the display device according to the exemplary embodiment, the second and
In addition, according to the present invention, the second and
The thin film transistor according to the exemplary embodiment of the present invention described above has a bottom gate structure.
11 is a cross-sectional view illustrating a thin film transistor region of a thin film transistor substrate according to another exemplary embodiment of the present invention.
As illustrated in FIG. 11, a thin film transistor of a thin film transistor substrate according to another exemplary embodiment has a top gate structure.
A
The
The
The
Each of the
The
An
The
According to another exemplary embodiment, the
The first and
The second and
The third and
The first and
The third and
Accordingly, the second and
In the display device according to the exemplary embodiment, the second and
In addition, according to the present invention, the second and
Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.
110 and 210:
112, 212:
140a, 240a:
141 and 241:
143 and 243: sixth metal pattern
Claims (19)
A plurality of gate lines and a plurality of data lines arranged to intersect on the base substrate;
A gate electrode disposed on the base substrate;
A gate insulating layer disposed on the gate electrode;
A semiconductor pattern disposed on the gate insulating layer;
A protective layer on the semiconductor pattern so as to correspond to the gate electrode; And
A source electrode and a drain electrode disposed on the semiconductor pattern to cover a portion of the protective layer;
The thin film transistor including the gate electrode, the semiconductor pattern, the source electrode, and the drain electrode is disposed at an intersection of the gate line and the data line.
The pixel electrode and the common electrode are alternately arranged in the pixel area arranged by the intersection of the gate line and the data line,
The pixel electrode is electrically connected to the drain electrode,
The common electrode includes a first metal pattern of a common electrode, a second metal pattern of a common electrode, and a third metal pattern of a common electrode sequentially stacked, and are disposed on the same layer as the gate electrode,
The data line includes a fourth metal pattern of data lines sequentially stacked, a fifth metal pattern of data lines, and a sixth metal pattern of data lines,
The gate electrode includes a first metal pattern of the gate electrode, a second metal pattern of the gate electrode and a third metal pattern of the gate electrode sequentially stacked,
The source electrode and the drain electrode may include a fourth metal pattern of the source electrode and the drain electrode sequentially stacked, a fifth metal pattern of the source electrode and the drain electrode, and a sixth metal pattern of the source electrode and the drain electrode.
The second metal pattern and the fifth metal pattern are made of copper (Cu) or an alloy containing copper,
The third metal pattern of the common electrode is disposed to surround the top and side surfaces of the second metal pattern of the common electrode and the side surface of the first metal pattern of the common electrode, so that the second metal pattern of the common electrode is closed from the outside. Make sure,
The third metal pattern of the gate electrode is disposed to surround the top and side surfaces of the second metal pattern of the gate electrode and the side surface of the first metal pattern of the gate electrode, so that the second metal pattern of the gate electrode is closed from the outside. To ensure that
The sixth metal pattern of the data line is disposed to surround the top and side surfaces of the fifth metal pattern of the data line and the side surface of the fourth metal pattern of the data line, such that the fifth metal pattern of the data line is closed from the outside. Make sure,
The sixth metal pattern of the source electrode and the drain electrode is disposed to surround the top and side surfaces of the fifth metal pattern of the source electrode and the drain electrode and the side surfaces of the fourth metal pattern of the source electrode and the drain electrode. And a fifth metal pattern of the drain electrode closed from the outside.
A plurality of gate lines and a plurality of data lines arranged to intersect on the base substrate;
An active pattern disposed on the base substrate
A gate insulating layer disposed on the active pattern;
A gate electrode disposed on the gate insulating layer;
An interlayer insulating layer disposed on the gate insulating layer and covering the gate electrode; And
A source electrode and a drain electrode disposed on the interlayer insulating layer around the gate electrode and connected to the active pattern;
The thin film transistor including the gate electrode, the active pattern, the source electrode, and the drain electrode is disposed at an intersection of the gate line and the data line.
The pixel electrode and the common electrode are alternately arranged in the pixel area arranged by the intersection of the gate line and the data line,
The pixel electrode is electrically connected to the drain electrode,
The common electrode includes a first metal pattern of a common electrode, a second metal pattern of a common electrode, and a third metal pattern of a common electrode sequentially stacked, and are disposed on the same layer as the gate electrode,
The data line includes a fourth metal pattern of a data line sequentially stacked, a fifth metal pattern of a data line, and a sixth metal pattern of a data line,
The gate electrode includes a first metal pattern of the gate electrode, a second metal pattern of the gate electrode and a third metal pattern of the gate electrode sequentially stacked,
The source electrode and the drain electrode may include a fourth metal pattern of the source electrode and the drain electrode sequentially stacked, a fifth metal pattern of the source electrode and the drain electrode, and a sixth metal pattern of the source electrode and the drain electrode.
The second metal pattern and the fifth metal pattern are made of copper (Cu) or an alloy containing copper,
The third metal pattern of the common electrode is disposed to surround the top and side surfaces of the second metal pattern of the common electrode and the side surface of the first metal pattern of the common electrode, so that the second metal pattern of the common electrode is closed from the outside. Make sure,
The third metal pattern of the gate electrode is disposed to surround the top and side surfaces of the second metal pattern of the gate electrode and the side surface of the first metal pattern of the gate electrode, so that the second metal pattern of the gate electrode is closed from the outside. To ensure that
The sixth metal pattern of the data line is disposed to surround the top and side surfaces of the fifth metal pattern of the data line and the side surface of the fourth metal pattern of the data line, such that the fifth metal pattern of the data line is closed from the outside. Make sure,
The sixth metal pattern of the source electrode and the drain electrode is disposed to surround the top and side surfaces of the fifth metal pattern of the source electrode and the drain electrode and the side surfaces of the fourth metal pattern of the source electrode and the drain electrode. And a fifth metal pattern of the drain electrode closed from the outside.
And the third metal pattern and the sixth metal pattern are made of nickel (Ni) or an alloy containing nickel.
The first metal pattern and the fourth metal pattern may include at least one of tantalum (Ta), titanium (Ti), chromium (Cr), molybdenum (Mo), tungsten (W), and titanium molybdenum (TiMo). Display device made of an alloy combined above.
The protective layer is made of silicon oxide (SiO 2 ).
The gate insulating layer is a single layer made of silicon oxide (SiO 2 ).
Forming a gate insulating layer on the gate electrode, the gate line and the common electrode;
Forming a semiconductor pattern on the gate insulating layer;
Forming a protective layer on the semiconductor pattern to correspond to the gate electrode; And
A fourth metal pattern and a fifth metal pattern are sequentially stacked on the semiconductor pattern to cover a portion of the passivation layer, and surround upper and side surfaces of the fifth metal pattern and side surfaces of the fourth metal pattern. Forming a sixth metal pattern to form a data line, a source electrode, and a drain electrode including the fourth metal pattern, the fifth metal pattern, and the sixth metal pattern to close the fifth metal pattern from the outside; Including,
The second metal pattern and the fifth metal pattern are formed of copper (Cu) or an alloy containing copper,
The thin film transistor including the gate electrode, the semiconductor pattern, the source electrode and the drain electrode is formed at an intersection of the gate line and the data line,
In the pixel region formed by the intersection of the gate line and the data line, the pixel electrode and the common electrode are sequentially formed alternately.
And the pixel electrode is electrically connected to the drain electrode.
And the third metal pattern and the sixth metal pattern are made of nickel (Ni) or an alloy containing nickel.
The first metal pattern and the fourth metal pattern may include at least one of tantalum (Ta), titanium (Ti), chromium (Cr), molybdenum (Mo), tungsten (W), and titanium molybdenum (TiMo). Method of manufacturing a display device consisting of an alloy combined with the above.
The gate insulating layer is a single layer made of silicon oxide (SiO 2).
A gate pad electrically connected to the gate line is disposed at one end of the gate line;
The gate pad includes a lower gate pad electrode and an upper gate pad electrode connected to the lower gate pad electrode.
The lower gate pad electrode may include a first metal pattern of a sequentially stacked lower gate pad electrode, a second metal pattern of a lower gate pad electrode, and a third metal pattern of a lower gate pad electrode. 2 metal pattern is made of copper (Cu) or an alloy containing copper,
The third metal pattern of the lower gate pad electrode is disposed to surround upper and side surfaces of the second metal pattern of the lower gate pad electrode and side surfaces of the first metal pattern of the lower gate pad electrode. To allow the second metal pattern to be closed from the outside,
The upper gate pad electrode is disposed on the same layer as the pixel electrode,
The lower gate pad electrode is disposed on the same layer as the common electrode.
A data pad electrically connected to the data line is disposed at one end of the data line.
The data pad includes a lower data pad electrode and an upper data pad electrode connected on the lower data pad electrode.
The lower data pad electrode may include a fourth metal pattern of the lower data pad electrode, a fifth metal pattern of the lower data pad electrode, and a sixth metal pattern of the lower data pad electrode sequentially stacked. 5 The metal pattern consists of copper (Cu) or an alloy containing copper,
The sixth metal pattern of the lower data pad electrode is disposed to surround upper and side surfaces of the fifth metal pattern of the lower data pad electrode and side surfaces of the fourth metal pattern of the lower data pad electrode. The fifth metal pattern is closed from the outside,
The upper data pad electrode is disposed on the same layer as the pixel electrode,
The lower data pad electrode is disposed on the same layer as the data line.
The pixel electrode and the common electrode are disposed on different layers.
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| KR102162580B1 (en) * | 2013-12-23 | 2020-10-07 | 엘지디스플레이 주식회사 | Display device having in-cell type touch electrode and fabricating method thereof |
| KR20210070110A (en) * | 2019-12-04 | 2021-06-14 | 주성엔지니어링(주) | Method of forming electrode |
| CN111446265B (en) * | 2020-05-08 | 2024-01-26 | 武汉华星光电半导体显示技术有限公司 | OLED display panel and preparation method thereof |
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| JP2002353222A (en) * | 2001-05-29 | 2002-12-06 | Sharp Corp | Metal wiring, thin film transistor and display device using the same |
| JP2010056136A (en) * | 2008-08-26 | 2010-03-11 | Toshiba Mobile Display Co Ltd | Wiring, method of manufacturing the same, thin film transistor, and display element |
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| KR101421243B1 (en) * | 2006-12-21 | 2014-07-21 | 삼성디스플레이 주식회사 | Thin film transistor substrate and method of manufacturing the same |
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| JP2002353222A (en) * | 2001-05-29 | 2002-12-06 | Sharp Corp | Metal wiring, thin film transistor and display device using the same |
| JP2010056136A (en) * | 2008-08-26 | 2010-03-11 | Toshiba Mobile Display Co Ltd | Wiring, method of manufacturing the same, thin film transistor, and display element |
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