KR20100006412A - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a manufacturing method are provided to prevent deterioration of afterimage and reduction of life cycle of a liquid crystal display due to the increase of off current by absorbing the light from the backlight unit. CONSTITUTION: An LCD device comprises a gate line, a data line(119), a thin film transistor, and pixel electrodes(146a,146b). The thin film transistor comprises the gate electrode, the active layer(108b), the protective film(120), and source/drain electrodes(110a,110b). The semiconductor layer(108) is formed in the lower part of the source/drain electrode. The semiconductor layer is not formed in the lower part of the data line. The semiconductor layer of the channel region is smaller than the line width of the gate electrode. The off characteristic by the photo current is improved.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing the same that can simplify the process and minimize off current.

As the information society develops, the demand for display devices is increasing in various forms.In recent years, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and vacuum fluorescent display (VFD) have been developed. Various flat panel display devices have been studied, and some are already used as display devices in various devices.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption, and mobile type such as monitor of notebook computer. In addition, it is being developed in various ways, such as a television for receiving and displaying broadcast signals, and a monitor of a computer.

In general, a liquid crystal display device is largely composed of a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer formed between the two substrates.

The thin film transistor substrate includes a plurality of gate lines and data lines arranged vertically and horizontally on the substrate to define a plurality of pixel regions, a thin film transistor which is a switching element formed at an intersection of the gate lines and the data lines, and a pixel electrode formed on the pixel region. .

The color filter substrate is composed of color filters that implement color, and a black matrix for distinguishing between color filters and preventing external light reflection.

As the thin film transistor array substrate of the liquid crystal display device includes a semiconductor process and requires a plurality of mask processes, the manufacturing process is complicated, and the manufacturing cost of the liquid crystal display device increases.

Accordingly, in recent years, a technique for reducing the number of mask processes required for forming a thin film transistor array substrate is required.

In order to solve the above problems, the present invention relates to a liquid crystal display device and a method of manufacturing the same that can simplify the process and minimize the off current (Off Current).

According to an aspect of the present invention, a liquid crystal display device includes a gate line formed on a substrate, a data line intersecting the gate line to form a pixel region, and a gate line and a data line. And a pixel electrode connected to the thin film transistor in the pixel region, wherein the thin film transistor includes a gate electrode branched from the gate line and a gate insulating film disposed on the gate electrode. A protective film having an active layer formed to overlap each other, a first and second contact holes exposing an ohmic contact layer facing each other with a channel interposed therebetween, and the ohmic through the first and second contact holes. And source and drain electrodes connected to the contact layer.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including a gate pattern including a gate electrode and a gate line on a substrate, and a gate insulating layer, an active layer, and an ohmic contact layer having a width less than or equal to the gate pattern on the gate pattern. Forming a passivation layer having a first contact hole and a second contact hole exposing the ohmic contact layer facing each other with the channel region on the gate electrode interposed therebetween; And forming a source electrode and a drain electrode connected to the ohmic contact layer and a pixel electrode formed to be connected to the drain electrode.

The liquid crystal display and the method of manufacturing the same according to the present invention have the following effects.

Since the semiconductor layer of the channel region is formed to have an island shape smaller than the line width of the gate electrode, and there is no semiconductor layer under the source and drain electrodes, the aperture ratio loss problem in the four mask process and the Ioff due to photo current Properties can be improved. In addition, as the semiconductor layer absorbs light from the backlight unit, problems such as shortening of lifespan and deterioration of afterimage due to an increase in off current may be solved.

In addition, a lift-off process is generally required in a three-mask process to simplify the process. The lift-off process has a poor reproducibility and a problem in terms of yield because there are more defects during the process of the larger area of the liquid crystal panel. Therefore, by eliminating such a lift process, a three-mask process is performed to minimize process defects in a large-area liquid crystal panel compared to a three-mask process using a lift-off process, thereby improving reliability and reducing costs. That is, the three mask process of the present invention can obtain a seven-step process, that is about 27% process reduction effect compared to the general four mask process, and at least 25% reduction effect in the Tact Time.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a thin film transistor substrate of an in-plane switching mode liquid crystal display device according to the present invention, and FIG. 2 is a cross-sectional view of the first embodiment of the present invention taken along lines II ′ to III-III ′ of FIG. 1. A cross-sectional view showing a thin film transistor substrate.

The in-plane switching mode liquid crystal display shown in FIGS. 1 and 2 is formed to intersect the gate line 104 with a plurality of gate lines 104 formed on the substrate 100 and a gate insulating layer 113 interposed therebetween. And a plurality of data lines 119 defining pixel regions, a thin film transistor TFT formed at a portion where the gate line 104 and the data line 119 intersect, and a pixel electrode connected to the thin film transistor TFT ( 146, a common electrode 148 forming a horizontal electric field with the pixel electrode 146 in each pixel region, and a common voltage connected to the common electrode 148 to supply a common voltage to drive the liquid crystal to the common electrode 148. A common line 140, a gate pad 85 connected to the gate line 104, and a data pad 149 connected to the data line 119.

The thin film transistor TFT may include a gate electrode 102 branched from the gate line 104, a gate insulating layer 113 and an ohmic contact layer 108a sequentially formed to overlap the gate electrode 102 on the gate electrode 102. ) And an active layer 108b, a first passivation layer 120 having first and second contact holes 160 and 170 on the semiconductor layer 108, and a first passivation layer 120. Source electrode 110a formed on branch line of data line 119 and connected to semiconductor layer 108 through first contact hole 160, and second contact hole 170 on first passivation layer 120. And a drain electrode 110b connected to the semiconductor layer 108 and facing the source electrode 110a.

Here, the line width of the semiconductor layer 108 is formed smaller than the line width of the gate electrode 102. The semiconductor layer 108 is formed under the source and drain electrodes 110a and 110b and is not formed under the data line 119.

Accordingly, by forming the semiconductor layer 108 in the channel region smaller than the line width of the gate electrode 102, the Ioff characteristic due to photo current can be improved, and the semiconductor layer 108 is lighted from the backlight unit. By absorbing the liquid crystal, problems such as shortening of lifespan and deterioration of afterimage due to an increase in off current can be solved.

The pixel electrode 146 is formed by branching from the drain electrode 110b, and is connected to the pixel electrode finger portion 146b which forms a horizontal electric field with the common electrode 148, and the pixel electrode finger portions 146b to form a gate line ( And a pixel electrode horizontal portion 146a formed in parallel with the 104.

In order to shield the crosstalk from the transverse electric field between the common electrode 148 and the pixel electrode 146 due to the voltage flowing to the data line 119, a common line ( 140). The common line 140 is formed in a direction parallel to the gate line 104, and is parallel to the first horizontal common line 140a and the first horizontal common line 140a formed to overlap the pixel electrode horizontal part 146a. And a second horizontal common line 140c connected through the fourth contact hole 150 and first and second horizontal common lines 140a and 140c to be parallel to the common electrode finger 148b. It includes a vertical common line 140b formed in the direction.

Here, the first and second horizontal common lines 140a and 140c and the vertical common line 140b may be formed in a mesh structure, thereby minimizing load by reducing load.

The first horizontal common line 140a overlaps the pixel electrode horizontal portion 146a with the gate insulating layer 113 and the semiconductor layer 108 interposed therebetween to form a storage capacitor.

The gate insulating layer 113 and the semiconductor layer 108 are formed in the same pattern on the first horizontal common line 140a, and the third contact hole 165 exposing the ohmic contact layer 108a is exposed on the active layer 108b. The provided first protective film 120 is formed. The ohmic contact layer 108a and the pixel electrode horizontal portion 146a are connected through the third contact hole 165.

The gate pad 85 may include a gate lower pad 80 formed of the same material as the gate line 104, and a gate contact hole between the gate insulating pad 113 and the semiconductor layer 108 on the gate lower pad 80. A gate upper pad 83 is formed to be electrically connected to the gate lower pad 80 through 87.

Here, the pixel electrode 146, the common electrode 148, the gate upper pad 83, and the data pad 149 may be formed in plural layers, and may be formed of molybdenum (Mo) as the lowermost first source / drain metal layer 115. A second source / drain metal layer, which is formed of a metal such as aluminum (Al), aluminum-neodymium (Al-Nd), copper (Cu), chromium (Cr), titanium (Ti), and a combination thereof, 116) molybdenum-titanium (MoTi), indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (Indium tin zinc oxide) : ITZO) or a combination thereof. Here, the second source / drain metal layer 115, which is the uppermost layer, serves as a protective layer of the metal lines and also serves as the pixel electrode 146.

Although omitted in the drawings, the thin film transistor substrate 100 is bonded to each other with the color filter substrate and the liquid crystal layer interposed therebetween. The color filter substrate includes a black matrix formed to prevent light leakage and to separate pixel areas, and a color filter layer for expressing color colors. Here, the black matrix is formed to correspond to metal patterns such as the gate line 104 and the data line 119 of the thin film transistor substrate 100.

3A to 3F are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 2.

As shown in FIG. 3A, the gate metal layer 112 is deposited on the substrate 100 through a deposition method such as sputtering, and then a plasma enhanced chemical vapor deposition (PECVD) or a chemical vapor deposition (CVD) on the gate metal layer 112 is performed. The gate insulating layer 113 and the semiconductor layer 108 are sequentially deposited through a deposition method such as vapor deposition.

Materials of the gate metal layer 112 include aluminum (Al), aluminum-neodymium (Al-Nd), molybdenum (Mo), titanium (Ti), tantalum (Ta), molybdenum alloy (Mo alloy), copper (Cu) ) And the like are used.

As the material of the gate insulating film 113, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

The semiconductor layer 108 is formed of an active layer 108b made of amorphous silicon (a-Si) not doped with impurities and an ohmic contact layer 108a made of amorphous silicon doped with impurities (n +).

A photoresist material (not shown) is then applied over the ohmic contact layer 108a and the first mask (not shown) is aligned thereon. The photoresist pattern 200 exposing a region in which the pixel electrode 146 of FIG. 1, the common electrode 148 of FIG. 1, and the data pad 149 of FIG. 1 will be formed using a first mask (not shown). To form. In the photoresist pattern 200, the thickness of the photoresist pattern 200 corresponding to the region where the channel of the thin film transistor TFT is to be formed is lower than the thickness of the photoresist pattern 200 in the remaining regions.

The first mask uses a diffraction exposure or a halftone mask to cause the photoresist pattern 200 to have a double step.

Referring to FIG. 3B, a gate pattern including the gate electrode 102, the first horizontal common line 140a, and the gate lower pad 80 may be overlapped with the gate pattern through an etching process using the photoresist pattern 200. Except for the gate insulating layer 113 and the semiconductor layer 108 formed on the gate pattern, the gate metal layer 112, the gate insulating layer 113, and the semiconductor layer 108 in the remaining regions are removed.

Subsequently, the thickness of the photoresist pattern 200 is lowered through an ashing process to expose the ohmic contact layer 108a in the channel region of the thin film transistor TFT.

 After the ohmic contact layer 108a of the channel region exposed through etching using the remaining photoresist pattern 200 is removed, the remaining photoresist pattern 200 is removed through a strip process.

Referring to FIG. 3C, the gate pattern including the gate lower pad 80, the gate electrode 102, and the first horizontal common line 140a, the gate insulating layer 113 and the semiconductor layer 108 formed on the gate pattern After forming the first protective film 120 through a deposition method such as plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), and the like, a photoresist material (not shown) is applied.

The second mask (not shown) is arranged on the photoresist material (not shown), and then exposed and developed to form a data line (119 in FIG. 1), a pixel electrode (146 in FIG. 1), a common electrode 148, and The photoresist pattern 202 is formed to expose the region where the data pad 149 is to be formed.

The photoresist pattern 202 may include a region excluding a region where a channel of the thin film transistor TFT is to be formed, and a thickness of the photoresist pattern 202 corresponding to the first horizontal common line 140a may correspond to the photoresist pattern of the remaining region. It is formed to a thickness lower than the thickness of 202, and exposes the region where the gate contact hole 87 is to be formed on the gate lower pad 80.

The second mask, like the first mask, uses a diffraction exposure or a halftone mask to cause the photoresist pattern 202 to have a double step.

Subsequently, the gate contact hole exposing the gate lower pad 80 by removing the first passivation layer 120, the semiconductor layer 108, and the gate insulating layer 113 exposed through an etching process using the photoresist pattern 202 ( 87).

Referring to FIG. 3D, the thickness of the photoresist pattern 202 is lowered through an ashing process, so that the semiconductor layer 108 region excluding the channel region of the TFT and the first horizontal common line 140a are formed. ) Will be exposed.

The first and second contact holes 160 may be removed by removing the first passivation layer 120 to expose the semiconductor layer 108 except for the channel region of the thin film transistor TFT through etching using the remaining photoresist pattern 202. 170, the first passivation layer 120 is removed to form the third contact hole 165 so that the semiconductor layer 108 on the first horizontal common line 140a is exposed.

Then, the remaining photoresist pattern 202 is removed through a strip process.

Referring to FIG. 3E, first and second deposition methods, such as sputtering, on the first passivation layer 120 including the gate contact hole 87 and the first to third contact holes 160, 170, and 165. Source / drain metal layers 115 and 116 are deposited sequentially, followed by application of a photoresist material (not shown).

Subsequently, the source and drain electrodes (110a and 110b of FIG. 1) are formed to align the third mask on a photoresist material (not shown), and then expose and develop the third mask to expose the channel region of the thin film transistor TFT. And the photoresist pattern 204 so as to correspond to the region where the pixel electrode 146 of FIG. 1, the common electrode 148 of FIG. 1, the data pad 149 of FIG. 1, and the gate upper pad 83 of FIG. 1 are to be formed. ).

Referring to FIG. 3F, the first and second source / drain metal layers 115 and 116 exposed through the etching process using the photoresist pattern 204 are removed to separate the source and drain electrodes 110a and 110b. A source / drain pattern including the pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149, and the gate upper pad 83 is formed.

The source and drain electrodes 110a and 110b are connected to the ohmic contact layer 108a exposed through the first and second contact holes 160 and 170, respectively, and the pixel electrode horizontal part 146a is connected to the third contact hole ( The storage device may be connected to the ohmic contact layer 108a exposed through the gate 165 and overlap the first common line horizontal portion 140a with the gate insulating layer 113 and the semiconductor layer 108 therebetween to form a storage capacitor.

Subsequently, the ohmic contact layer 108a of the channel region between the source and drain electrodes 110a and 110b is removed.

The source / drain pattern may be formed of a plurality of layers, and the lowermost first source / drain metal layer 115 may include copper (Cu), molybdenum (Mo), aluminum (Al), aluminum-neodymium (AlNd), and molybdenum-titanium. The second source / drain metal layer 116 formed of (MoTi), chromium (Cr), or a combination thereof may include molybdenum-titanium (MoTi), indium tin oxide (ITO), and tin oxide (Tin). Oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (Indium Tin Zinc Oxide: ITZO), or a combination thereof.

The gate upper pad 83 is electrically connected to the gate lower pad 80 through the gate contact hole 87.

The remaining photoresist pattern (204 of FIG. 3E) is then removed via a strip process.

As such, since the semiconductor layer 108 in the channel region is formed in an island shape smaller than the line width of the gate electrode 102, and there is no semiconductor layer under the source and drain electrodes, the aperture ratio loss problem in the four-mask process and the photo Ioff characteristics due to current (photo current) can be improved. In addition, since the semiconductor layer 108 absorbs light from the backlight unit, problems such as shortening of lifespan and deterioration of afterimage due to an increase in off current may be solved.

In addition, a lift-off process is generally required in a three-mask process to simplify the process. The lift-off process has a poor reproducibility and a problem in terms of yield because there are more defects during the process of the larger area of the liquid crystal panel. Therefore, by eliminating such a lift process, a three-mask process is performed to minimize process defects in a large-area liquid crystal panel compared to a three-mask process using a lift-off process, thereby improving reliability and reducing costs. That is, the three mask process of the present invention can obtain a seven-step process, that is about 27% process reduction effect compared to the general four mask process, and at least 25% reduction effect in the Tact Time.

4 is a cross-sectional view illustrating a thin film transistor substrate according to a second exemplary embodiment of the present invention, taken along lines II ′ to III-III ′ of FIG. 1.

In the thin film transistor substrate illustrated in FIG. 4, a description of overlapping components will be omitted in comparison with FIG. 2.

Referring to FIG. 4, the data line 119, the source and drain electrodes 110a and 110b, and the pixel electrode horizontal portion 146b are formed of a plurality of two layers, and the lowermost layer is the first source / drain metal layer 115. Indium Tin Oxide (ITO), Tin Oxide (TO), Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO) The top layer is a second source / drain metal layer 116, which is formed of copper (Cu), molybdenum (Mo), aluminum (Al), aluminum-neodymium (AlNd), molybdenum-titanium (MoTi), and chromium. (Cr) or a combination thereof. Here, molybdenum (Mo) capable of dry etching is mainly used as the material of the second source / drain metal layer 116.

When the indium tin oxide (ITO), which is the first source / drain metal layer 115 contacts, a spike occurs, so that the ohmic contact layer 108a and the source and drain electrodes ( A conductive medium layer (not shown) formed of molybdenum-titanium (MoTi) material may be further provided between 110a and 110b.

The second passivation layer 121 is formed on the data lines 119, the source and drain electrodes 110a and 110b, and the pixel electrode horizontal part 146b of the plurality of layers.

The pixel electrode finger 146b, the common electrode finger 148b, the data pad 149, and the gate upper pad 83 include the data line 119, the source and drain electrodes 110a and 110b, and the pixel electrode horizontal portion ( The gate upper pad 83 is formed of the same transparent conductive layer as the first source / drain metal layer 115, which is the lowest layer material of 146b, and the gate is formed through the gate contact hole 87 with the first passivation layer 120 therebetween. It is connected to the lower pad 80.

The first common line horizontal portion 140a overlaps the pixel electrode horizontal portion 146b with the gate insulating layer 113 and the semiconductor layer 118 interposed therebetween to form a storage capacitor.

5A through 5G are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 4.

Since the first and second mask processes of the second embodiment are the same as those of the first embodiment, that is, the manufacturing method of FIGS. 5A to 5D is the same as the manufacturing method of FIGS. 3A to 3D, and thus descriptions of the same manufacturing method will be omitted. Shall be.

Referring to FIG. 5E, a deposition method such as sputtering on the first passivation layer 120 having the gate contact hole (87 in FIG. 5D) and the first to third contact holes (160, 170, and 165 in FIG. 5D) may be performed. First and second source / drain metal layers 115 and 116 are formed thereon, and the second passivation layer 121 is sequentially deposited by the same sputtering method, followed by a photoresist material (not shown). Apply. As the material of the second passivation layer 121, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), molybdenum-titanium (MoTi), indium tin oxide (ITO), tin oxide (Tin Oxide) : TO), Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO), or a combination thereof is used.

Next, an area in which the source and drain electrodes 110a and 110b are to be formed so that the third mask is aligned on the photoresist material (not shown), and then exposed and developed to expose the channel region of the TFT, and the pixel The photoresist pattern 204 is formed to correspond to the region where the electrode 146, the common electrode 148, the data pad 149, and the gate upper pad 83 are to be formed.

The photoresist pattern 204 has a thickness of the photoresist pattern 204 corresponding to a region in which the pixel electrode finger 146b, the common electrode finger 148b, the data pad 149, and the gate upper pad 83 are to be formed. Is formed to a thickness lower than the thickness of the photoresist pattern 204 in the remaining areas.

The third mask, like the first and second masks, uses a diffraction exposure or a halftone mask to cause the photoresist pattern 204 to have a double step.

Subsequently, the first and second source / drain metal layers 115 and 116 and the second passivation layer 121 exposed through an etching process using the photoresist pattern 204 are removed to remove the plurality of data lines 119 and the source. And the drain electrodes 110a and 110b, the pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149 and the gate upper pad 83 are formed.

The first source / drain metal layer 115 may be a transparent conductive layer of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc oxide ( Indium Tin Zinc Oxide (ITZO) or a combination thereof, and the second source / drain metal layer 116 may include copper (Cu), molybdenum (Mo), aluminum (Al), aluminum-neodymium (AlNd), and molybdenum. It is formed of titanium (MoTi), chromium (Cr) or a combination thereof. Here, molybdenum (Mo) capable of dry etching is mainly used as the material of the second source / drain metal layer 116.

Referring to FIG. 5F, the thickness of the photoresist pattern 204 may be reduced through an ashing process, such that the data line 119, the source and drain electrodes 110a and 110b, and the first common line horizontal portion 146b are formed. ), The photoresist pattern 204 remains only.

 The second passivation layer 121 on the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149, and the gate upper pad 83 exposed through etching using the remaining photoresist pattern 204. And the second source / drain metal layer 116 is removed and the source and drain electrodes 110a and 110b are formed separately.

Accordingly, the pixel electrode finger 146b, the common electrode finger 148b, the data pad 149, and the gate upper pad 83 are connected to the first source / drain metal layer 115, which is a transparent conductive layer, as shown in FIG. 5G. Is formed.

Then, the remaining photoresist pattern 204 is removed through a strip process.

In the second embodiment, the gate electrode 102 and the semiconductor layer 108 are formed in the same pattern, and the first and second source / drain metal layers 115 and 116 and the second passivation layer 121 are sequentially deposited. The dry etching and ashing process is performed in one equipment in a batch.

As such, since the semiconductor layer 108 in the channel region is formed in an island shape smaller than the line width of the gate electrode 102, and there is no semiconductor layer under the source and drain electrodes, the aperture ratio loss problem in the four-mask process and the photo Ioff characteristics due to current (photo current) can be improved. In addition, since the semiconductor layer 108 absorbs light from the backlight unit, problems such as shortening of lifespan and deterioration of afterimage due to an increase in off current may be solved.

In addition, by eliminating the lift-off process, the three-mask process is performed, thereby minimizing process defects in the large-area liquid crystal panel compared to the three-mask process using the lift-off process, thereby improving reliability and reducing costs. Can be. That is, the three mask process of the present invention can obtain a seven-step process, that is about 27% process reduction effect compared to the general four mask process, and at least 25% reduction effect in the Tact Time.

FIG. 6 is a cross-sectional view illustrating a thin film transistor substrate according to a third exemplary embodiment of the present invention, taken along lines II ′ to III-III ′ of FIG. 1.

In the thin film transistor substrate illustrated in FIG. 6, redundant components will be omitted from those of the first and second embodiments.

Referring to FIG. 6, the data line 119, the source and drain electrodes 110a and 110b, the pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, and the data pad 149. ) And the gate upper pad 83 are formed of a plurality of two layers, and the lowermost layer is the first source / drain metal layer 115 of copper (Cu), molybdenum (Mo), aluminum (Al), and aluminum-neodymium. (AlNd), molybdenum-titanium (MoTi), chromium (Cr), or a combination thereof, and the uppermost layer is a second source / drain metal layer 116 of molybdenum-titanium (MoTi), indium tin oxide (Indium Tin Oxide): ITO), tin oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or a combination thereof. Here, the second source / drain metal layer 115, which is the uppermost layer, serves as a protective layer of the metal lines and also serves as the pixel electrode 146.

A plurality of data lines 119, source and drain electrodes 110a and 110b, pixel electrode horizontal portions 146a, pixel electrode finger portions 146b, common electrode finger portions 148b, data pads 149, gates The upper pad 83 is formed on the first passivation layer 120 having the first to second contact holes 160 and 170 and the gate contact hole 87.

Here, the semiconductor layer 108 on the gate electrode 102 of the thin film transistor TFT is formed smaller than the line width of the gate electrode. That is, the pattern of the semiconductor layer 108 and the gate insulating layer 113 on the gate electrode 102 is formed in an island shape smaller than the line width of the gate electrode 102, so that the gates of the semiconductor layer 108 and the gate insulating layer 113 are formed on both sides of the pattern. The electrode 102 is exposed.

The source and drain electrodes 110a and 110b are connected to the ohmic contact layer 108a of the semiconductor layer through the first and second contact holes 160 and 170, and the gate upper pad 83 is the gate contact hole 87. ) Is connected to the gate lower pad 80.

7A to 7F are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 6.

As shown in FIG. 7A, the gate metal layer 112 is deposited on the substrate 100 through a deposition method such as sputtering, and then plasma enhanced chemical vapor deposition (PECVD) and chemical vapor deposition (CVD) on the gate metal layer 112. The gate insulating layer 113 and the semiconductor layer 108 are sequentially deposited through a deposition method such as vapor deposition.

Materials of the gate metal layer 112 include aluminum (Al), aluminum-neodymium (AlNd), molybdenum (Mo), titanium (Ti), tantalum (Ta), molybdenum alloy (Mo alloy), copper (Cu), and the like. This is used.

As the material of the gate insulating film 113, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

The semiconductor layer 108 is formed of an active layer 108b made of amorphous silicon (a-Si) not doped with impurities and an ohmic contact layer 108a made of amorphous silicon doped with impurities (n +).

A photoresist material (not shown) is then applied over the ohmic contact layer 108a and the first mask is aligned thereon. The photoresist pattern 300 exposing a predetermined area of the pixel electrode finger 146b, the common electrode finger 148b, and the data pad 149 is formed using the first mask. The photoresist pattern 300 is formed to a first thickness in a region where the gate electrode 102, the first horizontal common line 140a, and the gate lower pad 80 are to be formed, and a channel of the thin film transistor TFT may be formed. The second thickness is higher than the first thickness in the region, and the third thickness is higher than the second thickness in the region in which the semiconductor layer 108 except for the channel region is to be formed.

The first mask uses a multi-tone mask (MTM) for causing the photoresist pattern 300 to have a triple step.

Referring to FIG. 7B, a gate pattern including the gate electrode 102, the first horizontal common line 140a, and the gate lower pad 80 may be overlapped with the gate pattern through an etching process using the photoresist pattern 300. Except for the gate insulating layer 113 and the semiconductor layer 108 formed on the gate pattern, the gate metal layer 112, the gate insulating layer 113, and the semiconductor layer 108 in the remaining regions are removed.

Subsequently, the thickness of the photoresist pattern 300 is lowered through the first ashing process so that only the region where the thin film transistor TFT is to be formed remains, and the photoresist pattern 300 of the region corresponding to the channel region is formed. Is formed to a thickness lower than that of the photoresist pattern 300 in the region corresponding to the semiconductor layer 108 except for the channel region.

Referring to FIG. 7C, the gate insulating layer 113 and the semiconductor layer 108 on the gate electrode 102 are formed smaller than the line width of the gate electrode 102 through an etching process using the remaining photoresist pattern 300. The gate electrode 102 is exposed to both sides of the insulating layer 113 and the semiconductor layer 108. The exposed first horizontal common line 140a and the gate insulating layer 113 and the semiconductor layer 108 on the gate lower pad 80 are removed.

Subsequently, after forming the photoresist pattern 300 to expose the channel region between the source and drain electrodes 110a and 110b through the second ashing process, the ohmic contact layer of the channel region exposed through the etching process. Remove 108a.

Subsequently, the remaining photoresist pattern 300 is removed through a strip process.

Referring to FIG. 7D, after sequentially depositing the first passivation layer 120 through a deposition method such as plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD) on the entire surface of the substrate 100 including the gate pattern, A photoresist material (not shown) is applied thereon.

The first passivation layer 120 and the gate upper pad 80 in the region excluding the region where the channel of the thin film transistor TFT is to be formed by aligning the second mask on a photoresist material (not shown) and exposing and developing the TFT. The photoresist pattern 302 is formed to expose the first passivation layer 120 on the image.

Subsequently, the ohmic contact layer of the semiconductor layer 108 except for the region where the channel of the thin film transistor TFT is to be formed by removing the exposed first passivation layer 120 through an etching process using the photoresist pattern 302 ( The first and second contact holes 160 and 170 are formed to expose 108a, and the gate contact holes 87 are formed to expose the gate lower pad 80.

Then, the remaining photoresist pattern 302 is removed through a strip process.

Referring to FIG. 7E, the first and second sources / s may be deposited on the first passivation layer 120 including the gate contact holes 87 and the first and second contact holes 160 and 170 by sputtering or the like. After forming the drain metal layers 115 and 116 sequentially, a photoresist material (not shown) is applied thereon.

Next, an area in which the source and drain electrodes 110a and 110b are to be formed so that the third mask is aligned on the photoresist material (not shown), and then exposed and developed to expose the channel region of the TFT, and the pixel The photoresist pattern 304 is formed to correspond to a region where the electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149, and the gate upper pad 83 are formed. do.

Referring to FIG. 7F, the first and second source / drain metal layers 115 and 116 exposed through the etching process using the photoresist pattern 304 are removed to form the source and drain electrodes on the first passivation layer 120. Sources 110a and 110b are formed separately and include a pixel electrode horizontal portion 146a, a pixel electrode finger portion 146b, a common electrode finger portion 148b, a data pad 149 and a gate upper pad 83 A drain pattern is formed.

The pixel electrode horizontal part 146a overlaps the first horizontal common line 140a with the first passivation layer 120 interposed therebetween to form a storage capacitor. Here, since the semiconductor layer 108 and the gate insulating layer 113 do not exist on the first horizontal common line 140a, and the first protective layer 120, which is an insulating layer, exists, the storage capacitor can be increased to increase the opening ratio. It can increase.

The source / drain pattern is formed of a plurality of layers, and the lowermost layer is the first source / drain metal layer 115, and includes copper (Cu), molybdenum (Mo), aluminum (Al), aluminum-neodymium (AlNd), and molybdenum-titanium. (MoTi), chromium (Cr) or a combination thereof, and the uppermost layer is a second source / drain metal layer 116 of molybdenum-titanium (MoTi), indium tin oxide (ITO), and tin oxide (Tin). Oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (Indium Tin Zinc Oxide: ITZO), or a combination thereof.

The gate upper pad 83 is electrically connected to the gate lower pad 80 through the gate contact hole 87.

The remaining photoresist pattern is then removed via a strip process.

As such, since the semiconductor layer 108 in the channel region is formed in an island shape smaller than the line width of the gate electrode 102, and there is no semiconductor layer under the source and drain electrodes, the aperture ratio loss problem in the four-mask process and the photo Ioff characteristics due to current (photo current) can be improved. In addition, since the semiconductor layer 108 absorbs light from the backlight unit, problems such as shortening of lifespan and deterioration of afterimage due to an increase in off current may be solved.

In addition, a lift-off process is generally required in a three-mask process to simplify the process. The lift-off process has a poor reproducibility and a problem in terms of yield because there are more defects during the process of the larger area of the liquid crystal panel. Therefore, such a lift process may be omitted, and the three mask process may be performed to improve reliability and reduce cost. That is, the three mask process of the present invention can obtain a seven-step process, that is about 27% process reduction effect compared to the general four mask process, and at least 25% reduction effect in the Tact Time.

8 is a cross-sectional view illustrating a thin film transistor substrate according to a fourth exemplary embodiment of the present invention, taken along lines II ′ to III-III ′ of FIG. 1.

In the thin film transistor substrate illustrated in FIG. 8, a description of overlapping components will be omitted in comparison with FIG. 6.

Referring to FIG. 8, the data line 119, the source and drain electrodes 110a and 110b are formed of a plurality of three layers and include copper (Cu), molybdenum (Mo), aluminum (Al), and aluminum-neodymium. It is formed of aluminum (AlNd), molybdenum-titanium (MoTi), chromium (Cr) or a combination thereof. Preferably, the lowermost first source / drain metal layer 115 is molybdenum-titanium (MoTi), and the middle layer second source / drain metal layer 116 is copper (Cu), molybdenum (Mo), aluminum (Al), aluminum. -Formed of neodymium (AlNd), molybdenum-titanium (MoTi), chromium (Cr) or a combination thereof), the uppermost third source / drain metal layer 117 is formed of molybdenum-titanium (MoTi). In this case, the second source / drain metal layer 116 preferably uses copper (Cu) to minimize the line resistance because the liquid crystal display device has a large area and a line resistance increases. The uppermost third source / drain metal layer 117 serves as a protective layer of the metal lines and also serves as the pixel electrode 146.

The pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149, and the gate upper pad 83 are formed on the first passivation layer 120. Molybdenum-titanium (MoTi) material such as the metal layer 115 is formed in a single layer.

9A to 9G are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 8.

Since the first and second mask processes of the fourth embodiment are the same as those of the third embodiment, that is, the manufacturing methods of FIGS. 9A to 9D are the same as the manufacturing methods of FIGS. 7A to 7D, and thus descriptions of the same manufacturing method will be omitted. Shall be.

Referring to FIG. 9E, the first to third sources / s may be deposited on the first passivation layer 120 including the gate contact holes 87 and the first and second contact holes 160 and 170 by sputtering or the like. Drain metal layers 115, 116, and 117 are formed, and a photoresist material (not shown) is applied thereon.

Next, an area in which the source and drain electrodes 110a and 110b are to be formed so that the third mask is aligned on the photoresist material (not shown), and then exposed and developed to expose the channel region of the TFT, and the pixel The photoresist pattern 304 is formed to correspond to a region where the electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149, and the gate upper pad 83 are formed. do.

The photoresist pattern 304 corresponds to a region where the pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149 and the gate upper pad 83 are to be formed. The thickness of the photoresist pattern 304 is formed to be lower than the thickness of the photoresist pattern 304 in the remaining areas.

The third mask uses a diffraction exposure or a halftone mask to cause the photoresist pattern 304 to have a double step.

Subsequently, the third source / drain metal layer 117 exposed through the etching process using the photoresist pattern 304 is removed.

Referring to FIG. 9F, the thickness of the photoresist pattern 304 is reduced through an ashing process, thereby leaving the photoresist pattern 304 only on the region where the source and drain electrodes 110a and 110b are to be formed. The photoresist pattern 304 of the region is removed.

 Subsequently, the second source / drain metal layer 116 of the channel region exposed through the etching process using the photoresist pattern 304 is removed, and the pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, and the common electrode are removed. The second source / drain metal layer 116 is patterned using the remaining third source / drain metal layer 117 as a mask for the region where the finger portion 148b, the data pad 149, and the gate upper pad 83 are to be formed.

Referring to FIG. 9G, a second region in which the pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149 and the gate upper pad 83 is formed is left. And the first source / drain metal layer 115 is patterned using the third source / drain metal layers 116 and 117 as a mask, and the first source / drain metal layer 115 of the channel region is removed to thereby remove the source and drain electrodes 110a. , 110b) are separated.

Subsequently, the second and second regions on the pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149 and the gate upper pad 83 are formed through an etching process. The pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, and the common electrode finger portion 148b of a single layer formed of the first source / drain metal layer 115 by removing the third source / drain metal layers 116 and 117. The data pad 149 and the gate upper pad 83 are formed.

Then, the remaining photoresist pattern 304 is removed through a strip process.

FIG. 10 is a cross-sectional view illustrating a thin film transistor substrate according to a fifth exemplary embodiment of the present invention, taken along lines II ′ to III-III ′ of FIG. 1.

The thin film transistor substrate illustrated in FIG. 10 differs only from the materials of the TFT region and the first to third source / drain metal layers 115, 116, and 117 in FIG. The description will be omitted.

The data line 119 and the source and drain electrodes 110a and 110b of FIG. 10 are formed of a plurality of three layers, and the lowermost first source / drain metal layer 115 is a transparent conductive layer. A second source formed of an intermediate layer formed of oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or a combination thereof The / drain metal layer 116 is formed of copper (Cu), molybdenum (Mo), aluminum (Al), aluminum-neodymium (AlNd), molybdenum-titanium (MoTi), chromium (Cr), or a combination thereof, The uppermost third source / drain metal layer 117 is a transparent conductive layer like the first source / drain metal layer 115, and is indium tin oxide (ITO), tin oxide (TO), and indium zinc oxide. (Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO) or a combination thereof The. In this case, the second source / drain metal layer 116 preferably uses copper (Cu) to minimize the line resistance because the liquid crystal display device has a large area and a line resistance increases. The uppermost third source / drain metal layer 117 serves as a protective layer of the metal lines and also serves as the pixel electrode 146.

The conductive medium layer 133 is formed of molybdenum-titanium (MoTi) on the ohmic contact layer 108a of the semiconductor layer 108 except for the channel region of the thin film transistor TFT. For example, when the ohmic contact layer 108a and the indium tin oxide (ITO), which is the first source / drain metal layer 115 of the source and drain electrodes 110a and 110b, come into contact with each other, the spikeing may occur. Since a phenomenon occurs, a conductive medium layer 133 formed of molybdenum-titanium (MoTi) material is formed between the ohmic contact layer 108a and the source and drain electrodes 110a and 110b.

The pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149, and the gate upper pad 83 are formed on the first passivation layer 120. It is formed of a single layer of a transparent conductive layer such as the metal layer 115.

11A through 11G are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 10.

As shown in FIG. 11A, the gate metal layer 112 is deposited on the substrate 100 through a deposition method such as sputtering, and then, plasma enhanced chemical vapor deposition (PECVD) and chemical vapor deposition (CVD) are deposited on the gate metal layer 112. After the deposition of the gate insulating layer 113 and the semiconductor layer 108 in sequence through a deposition method such as vapor deposition, and the like, the conductive medium layer 133 is deposited on the semiconductor layer 108 through a deposition method such as sputtering. .

Materials of the gate metal layer 112 include aluminum (Al), aluminum-neodymium (Al-Nd), molybdenum (Mo), titanium (Ti), tantalum (Ta), molybdenum alloy (Mo alloy), copper (Cu) ) And the like are used.

As the material of the gate insulating film 113, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

The semiconductor layer 108 is formed of an active layer 108b made of amorphous silicon (a-Si) not doped with impurities and an ohmic contact layer 108a made of amorphous silicon doped with impurities (n +).

The conductive medium layer 133 is formed of copper (Cu), molybdenum (Mo), aluminum (Al), aluminum-neodymium (AlNd), molybdenum-titanium (MoTi), chromium (Cr), or a combination thereof. It is preferably formed of molybdenum-titanium (MoTi).

Next, a photoresist material (not shown) is applied to the entire surface of the conductive medium layer 133 and the first mask is aligned thereon. The photoresist pattern 300 exposing a predetermined area of the pixel electrode finger 146b, the common electrode finger 148b, and the data pad 149 is formed using the first mask. The photoresist pattern 300 is formed to a first thickness in a region where the gate electrode 102, the first horizontal common line 140a, and the gate lower pad 80 are to be formed, and a channel of the thin film transistor TFT may be formed. The second thickness is higher than the first thickness in the region, and the third thickness is higher than the second thickness in the region in which the semiconductor layer 108 except for the channel region is to be formed.

The first mask uses a multi-tone mask (MTM) for causing the photoresist pattern 300 to have a triple step.

Referring to FIG. 11B, a gate pattern including the gate electrode 102, the first horizontal common line 140a, and the gate lower pad 80 overlaps with the gate pattern through an etching process using the photoresist pattern 300. The gate metal layer 112, the gate insulating layer 113, the semiconductor layer 108, and the conductive medium in the remaining regions except for the gate insulating layer 113, the semiconductor layer 108, and the conductive intermediate layer 133 formed on the gate pattern, may be used. Remove layer 133.

Subsequently, the thickness of the photoresist pattern 300 is lowered through the first ashing process so that only the region where the thin film transistor TFT is to be formed remains, and the photoresist pattern 300 of the region corresponding to the channel region is formed. The thickness of is formed to be lower than the thickness of the photoresist pattern 300 of the region corresponding to the conductive medium layer 133 excluding the channel region.

Referring to FIG. 11C, the gate insulating layer 113, the semiconductor layer 108, and the conductive medium layer 133 on the gate electrode 102 may be larger than the line width of the gate electrode through an etching process using the remaining photoresist pattern 300. The gate electrode 102 is formed to be small, and the gate electrode 102 is exposed to both sides of the gate insulating layer 113, the semiconductor layer 108, and the conductive medium layer 133. The exposed first horizontal common line 140a and the gate insulating layer 113, the semiconductor layer 108, and the conductive medium layer 133 on the gate lower pad 80 are removed. Next, after forming the photoresist pattern 300 to expose the channel region between the source and drain electrodes 110a and 110b through the second ashing process, the ohmic contact layer of the channel region exposed through the etching process. Remove 108a.

Subsequently, the remaining photoresist pattern 300 is removed through a strip process.

Referring to FIG. 11D, after sequentially depositing the first passivation layer 120 on the entire surface of the substrate 100 including the gate pattern by a deposition method such as plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD), etc. A photoresist material (not shown) is applied thereon.

The first passivation layer 120 and the lower gate pad 80 of the region excluding the region where the channel of the thin film transistor TFT is to be formed by aligning the second mask on a photoresist material (not shown) and then exposing and developing the TFT. The photoresist pattern 302 is formed to expose the first passivation layer 120 on the image.

Subsequently, the first passivation layer 120 exposed through the etching process using the photoresist pattern 302 is removed to expose the conductive media layer 133 in the region except for the region where the channel of the thin film transistor TFT is to be formed. The first and second contact holes 160 and 170 are formed, and the gate contact hole 87 is formed to expose the lower gate pad 80.

Then, the remaining photoresist pattern 302 is removed through a strip process.

Referring to FIG. 11E, the first to third sources / drains may be deposited on the first passivation layer 120 including the gate contact holes 87 and the first and second contact holes 160 170 through a deposition method such as sputtering. After forming the metal layers 115, 116, 117, a photoresist material (not shown) is applied thereon.

Subsequently, the source and drain electrodes 110a and 110b are formed to align the third mask on a photoresist material (not shown), and then expose and develop the channel regions of the TFT, and the pixel; The photoresist pattern 304 is formed to correspond to a region where the electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149, and the gate upper pad 83 are formed. do.

The third mask uses a diffraction exposure or a halftone mask to cause the photoresist pattern 304 to have a double step.

Subsequently, the third source / drain metal layer 117 exposed through the etching process using the photoresist pattern 304 is removed.

The lowermost first source / drain metal layer 115 is a transparent conductive layer, indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc. The second source / drain metal layer 116, which is formed of an indium tin zinc oxide (ITZO) or a combination thereof, may be formed of copper (Cu), molybdenum (Mo), aluminum (Al), aluminum-neodymium ( A third source / drain metal layer 117 formed of AlNd), molybdenum-titanium (MoTi), chromium (Cr), or a combination thereof is indium as a transparent conductive layer such as the first source / drain metal layer 115. It is formed of tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or a combination thereof. In this case, the second source / drain metal layer 116 preferably uses copper (Cu) to minimize the line resistance because the liquid crystal display device has a large area and a line resistance increases.

Referring to FIG. 11F, the thickness of the photoresist pattern 304 is reduced through an ashing process, so that the photoresist pattern 304 remains only on the region where the source and drain electrodes 110a and 110b are to be formed. The photoresist pattern 304 of the region is removed.

 Subsequently, the second source / drain metal layer 116 of the channel region exposed through the etching process using the photoresist pattern 304 is removed, and the pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, and the common electrode are removed. The second source / drain metal layer 116 is patterned using the remaining third source / drain metal layer 117 as a mask for the region where the finger portion 148b, the data pad 149, and the gate upper pad 83 are to be formed.

Referring to FIG. 11G, a region in which the pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149 and the gate upper pad 83 is formed is left second. And the first source / drain metal layer 115 is patterned using the third source / drain metal layers 115 and 116 as a mask, and the first source / drain metal layer 115 in the channel region is removed to thereby remove the source and drain electrodes 110a. , 110b) are separated. The source and drain electrodes 110a and 110b are connected to the conductive medium layer 133 through the first and second contact holes 160 and 170 to form the source and drain electrodes 110a and 110b, that is, indium tin oxide. When formed of oxide (ITO), when it comes into contact with the semiconductor layer 108, a spike phenomenon occurs. This can be prevented.

The pixel electrode horizontal part 146a overlaps the first horizontal common line 140a with the first passivation layer 120 interposed therebetween to form a storage capacitor. Here, since the semiconductor layer 108 and the gate insulating layer 113 do not exist on the first horizontal common line 140a, and the first protective layer 120, which is an insulating layer, exists, the storage capacitor can be increased, thereby increasing the aperture ratio. Can be.

Subsequently, the second and second regions on the pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, the common electrode finger portion 148b, the data pad 149 and the gate upper pad 83 are formed through an etching process. The pixel electrode horizontal portion 146a, the pixel electrode finger portion 146b, and the common electrode finger portion 148b of a single layer formed of the first source / drain metal layer 115 by removing the third source / drain metal layers 116 and 117. The data pad 149 and the gate upper pad 83 are formed.

Then, the remaining photoresist pattern 302 is removed through a strip process.

As such, since the semiconductor layer 108 in the channel region is formed in an island shape smaller than the line width of the gate electrode 102, and there is no semiconductor layer under the source and drain electrodes, the aperture ratio loss problem in the four-mask process and the photo Ioff characteristics due to current (photo current) can be improved. In addition, since the semiconductor layer 108 absorbs light from the backlight unit, problems such as shortening of lifespan and deterioration of afterimage due to an increase in off current may be solved.

In addition, a lift-off process is generally required in a three-mask process to simplify the process. The lift-off process has a poor reproducibility and a problem in terms of yield because there are more defects during the process of the larger area of the liquid crystal panel. Therefore, such a lift process is omitted so that the three mask process is performed, thereby improving reliability and reducing costs. That is, the three mask process of the present invention can obtain a seven-step process, that is about 27% process reduction effect compared to the general four mask process, and at least 25% reduction effect in the Tact Time.

The structure and manufacturing method of the thin film transistor substrate can be applied not only to the IPS mode but also to various modes such as TN, ECB, and VA modes.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those who have knowledge.

1 is a plan view illustrating a thin film transistor substrate of an in-plane switching mode liquid crystal display according to the present invention.

FIG. 2 is a cross-sectional view illustrating a thin film transistor substrate according to a first exemplary embodiment of the present invention, taken along lines II ′ to III-III ′ of FIG. 1.

3A to 3F are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 2.

4 is a cross-sectional view illustrating a thin film transistor substrate according to a second exemplary embodiment of the present invention, taken along lines II ′ to III-III ′ of FIG. 1.

5A through 5G are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 4.

FIG. 6 is a cross-sectional view illustrating a thin film transistor substrate according to a third exemplary embodiment of the present invention, taken along lines II ′ to III-III ′ of FIG. 1.

7A to 7F are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 6.

8 is a cross-sectional view illustrating a thin film transistor substrate according to a fourth exemplary embodiment of the present invention, taken along lines II ′ to III-III ′ of FIG. 1.

9A to 9G are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 8.

FIG. 10 is a cross-sectional view illustrating a thin film transistor substrate according to a fifth exemplary embodiment of the present invention, taken along lines II ′ to III-III ′ of FIG. 1.

11A through 11G are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 10.

<Description of Symbols for Main Parts of Drawings>

85: gate pad 100: substrate

102 gate electrode 104 gate line

108: semiconductor layer 113: gate insulating film

110a, 110b: source and drain electrodes 119: data line

140: common line 146: pixel electrode

148: common electrode 149: data pad

Claims (10)

A gate line formed on the substrate, A data line crossing the gate line to form a pixel area; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the thin film transistor in the pixel region, The thin film transistor, A gate electrode branched from the gate line, An active layer formed on the gate electrode with a gate insulating film interposed therebetween; A protective film having first and second contact holes exposing opposing ohmic contact layers on the active layer with the channels interposed therebetween; And source and drain electrodes connected to the ohmic contact layer through the first and second contact holes. The method of claim 1, A common electrode forming a horizontal electric field with the pixel electrode; A common line applying a common voltage to the common electrode; A gate lower pad connected to the gate line and formed on the same layer as the gate electrode, and connected to the gate lower pad through a gate contact hole formed on the same layer as the pixel electrode and exposing the gate lower pad. A gate pad including a gate upper pad, And a data pad formed in connection with the data line. And the horizontal portion of the pixel electrode overlaps the horizontal portion of the common line with a gate insulating layer and a semiconductor layer or a protective layer therebetween to form a storage capacitor. The method of claim 1, The data line, source and drain electrodes are formed of two or three layers. When formed in two layers, one of the uppermost layer and the lowermost layer is formed of a metal of molybdenum, aluminum, aluminum-neodymium, copper, chromium, titanium, and a combination thereof, and the remaining layers are molybdenum-titanium, indium tin oxide, It is formed of tin oxide, indium zinc oxide, indium tin zinc oxide and combinations thereof, When formed in three layers, each of the uppermost layer and the lowermost layer is formed of a metal of molybdenum, aluminum, aluminum-neodymium, copper, chromium, titanium, and a combination thereof, or molybdenum-titanium, indium tin oxide, tin oxide, indium zinc. An oxide, an indium tin zinc oxide and a combination thereof, and the intermediate layer is formed of a metal of molybdenum, aluminum, aluminum-neodymium, copper, chromium, titanium and a combination thereof. The method of claim 2, The source and drain electrodes are formed of two or more layers of the top and bottom layers, or a plurality of three layers of the top, middle, and bottom layers. The pixel electrode, the common electrode, the data pad, and the gate upper pad may be formed of the lowermost layer of the source and drain electrodes, or may be formed of a plurality of uppermost and lowermost layers. When the source and drain electrodes are formed of two layers, one of the uppermost layer and the lower layer is formed of a metal of molybdenum, aluminum, aluminum-neodymium, copper, chromium, titanium, and a combination thereof, and the other layer is molybdenum It is formed of titanium, indium tin oxide, tin oxide, indium zinc oxide, indium tin zinc oxide and combinations thereof, When the source and drain electrodes are formed of three layers, each of the uppermost layer and the lowermost layer is formed of a metal of molybdenum, aluminum, aluminum-neodymium, copper, chromium, titanium, and a combination thereof, or molybdenum-titanium or indium tin. Oxide, tin oxide, indium zinc oxide, indium tin zinc oxide and combinations thereof, and the intermediate layer is formed of a metal of molybdenum, aluminum, aluminum-neodymium, copper, chromium, titanium and combinations thereof. Liquid crystal display device. The method of claim 3, wherein When the lowermost layer of the source and drain electrodes is formed of indium tin oxide, tin oxide, indium zinc oxide, indium tin zinc oxide and a combination thereof, And a conductive medium layer formed between the source and drain electrodes and the ohmic contact layer. Forming a gate pattern including a gate electrode and a gate line on the substrate, a gate insulating layer, an active layer, and an ohmic contact layer having a width less than or equal to the gate pattern on the gate pattern; Forming a passivation layer having first and second contact holes exposing opposing ohmic contact layers with the channel region on the gate electrode interposed therebetween; And forming source and drain electrodes connected to the ohmic contact layer through the first and second contact holes, and pixel electrodes connected to the drain electrodes. . The method of claim 6, Forming a common line and a gate lower pad when forming the gate pattern; Forming a gate contact hole penetrating the passivation layer to expose the lower gate pad; The method may further include forming a common electrode, a data pad, and a gate upper pad when the pixel electrode is formed. A gate lower pad and a gate upper pad are connected through the gate contact hole, And a storage capacitor overlapping the horizontal portion of the pixel electrode with the horizontal portion of the common line and the gate insulating layer and the semiconductor layer or the protective layer interposed therebetween. The method of claim 6, The source and drain electrodes are formed of two or three layers. When formed in two layers, one of the uppermost layer and the lowermost layer is formed of a metal of molybdenum, aluminum, aluminum-neodymium, copper, chromium, titanium, and a combination thereof, and the remaining layers are indium tin oxide, tin oxide, indium Zinc oxide, indium tin zinc oxide and combinations thereof; When formed in three layers, each of the uppermost layer and the lowermost layer is formed of metals of molybdenum, aluminum, aluminum-neodymium, copper, chromium, titanium, and combinations thereof, or indium tin oxide, tin oxide, indium zinc oxide, indium tin. And an intermediate layer formed of a metal of molybdenum, aluminum, aluminum-neodymium, copper, chromium and titanium and a combination thereof. The method of claim 7, wherein The source and drain electrodes are formed of two or more layers of the top and bottom layers, or a plurality of three layers of the top, middle, and bottom layers. The pixel electrode, the common electrode, the data pad, and the gate upper pad may be formed of the lowermost layer of the source and drain electrodes, or may be formed of a plurality of uppermost and lowermost layers. When the source and drain electrodes are formed of two layers, one of the uppermost layer and the lower layer is formed of a metal of molybdenum, aluminum, aluminum-neodymium, copper, chromium, titanium, and a combination thereof, and the other layer is molybdenum It is formed of titanium, indium tin oxide, tin oxide, indium zinc oxide, indium tin zinc oxide and combinations thereof, When the source and drain electrodes are formed of three layers, each of the uppermost layer and the lowermost layer is formed of a metal of molybdenum, aluminum, aluminum-neodymium, copper, chromium, titanium, and a combination thereof, or molybdenum-titanium or indium tin. Oxide, tin oxide, indium zinc oxide, indium tin zinc oxide and combinations thereof, and the intermediate layer is formed of a metal of molybdenum, aluminum, aluminum-neodymium, copper, chromium, titanium and combinations thereof. Method of manufacturing a liquid crystal display device. The method of claim 8, When the lowermost layer of the source and drain electrodes is formed of indium tin oxide, tin oxide, indium zinc oxide, indium tin zinc oxide and a combination thereof, And a conductive medium layer between the source and drain electrodes and the ohmic contact layer.

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