KR20110056962A - Method of fabricating substrate for thin film transistor - Google Patents

Abstract

PURPOSE: A method of fabricating a substrate for a thin film transistor is provided to improve the process uniformity of a large size substrate by adopting an etch stopper structure to protect a back channel area. CONSTITUTION: In a method of fabricating a substrate for a thin film transistor, a gate line(116) and a data line(117) are formed on a substrate(110). A gate electrode(121) is connected to the gate line. A source electrode(122) is connected to the data line. A drain electrode(123) is connected to a pixel electrode. An active layer(124) made of the oxide semiconductor form a conductive channel between the source electrode and the drain electrode.

Description

Method for manufacturing thin film transistor substrate {METHOD OF FABRICATING SUBSTRATE FOR THIN FILM TRANSISTOR}

The present invention relates to a method for manufacturing a thin film transistor substrate, and more particularly, to a method for manufacturing a thin film transistor substrate using an oxide semiconductor as an active layer of a thin film transistor.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate, a thin film transistor substrate, and a liquid crystal layer formed between the color filter substrate and the thin film transistor substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer formed between the color filter substrate 5 and the thin film transistor substrate 10 and the color filter substrate 5 and the thin film transistor substrate 10. It consists of 30.

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the thin film transistor substrate 10 may be arranged in a vertical direction and in a plurality of gate lines 16 and data lines 17 defining a plurality of pixel regions P, and the gate lines 16 and data lines 17. And a pixel electrode 18 formed on the pixel region P.

The color filter substrate 5 and the thin film transistor substrate 10 are joined to face each other by a sealant (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. 5) and the thin film transistor substrate 10 are bonded together through a bonding key (not shown) formed on the color filter substrate 5 or the thin film transistor substrate 10.

Amorphous silicon thin film transistors used in the above-described liquid crystal display device can be fabricated in a low temperature process, but have very low mobility and do not satisfy the constant current bias condition. Polycrystalline silicon thin film transistors, on the other hand, have high mobility and satisfactory constant current test conditions, and are difficult to obtain uniform characteristics, making it difficult to large area and require high temperature processes.

Accordingly, an oxide thin film transistor having an active layer formed of an oxide semiconductor is being developed. When the oxide semiconductor is applied to a thin film transistor having a bottom gate structure, the oxide semiconductor is damaged during the etching process of the source / drain electrodes. There is a problem causing degeneration.

2 is a cross-sectional view schematically illustrating a structure of a general oxide thin film transistor.

As shown in the drawing, a general oxide thin film transistor includes a gate electrode 21 formed on a predetermined substrate 10, a gate insulating film 15a formed on the gate electrode 21, and an oxide semiconductor on the gate insulating film 15a. The active layer 24 formed, the source / drain electrodes 22 and 23 electrically connected to a predetermined region of the active layer 24, the passivation layer 15b and the drain formed on the source / drain electrodes 22 and 23. The pixel electrode 18 is electrically connected to the electrode 23.

At this time, for example, in the process of depositing and etching the source / drain electrodes 22 and 23, the lower active layer 24 (particularly, the back channel region of the active layer 24) is damaged and denatured. In some cases, there is a problem in the reliability of the device.

That is, the source / drain electrode metal is limited to molybdenum-based metal in consideration of contact resistance with the oxide semiconductor. When forming the source / drain electrode by wet etching, physical properties of the oxide semiconductor are vulnerable to etchant. (Activity) causes loss or damage of the active layer, and even when the source / drain electrodes are formed by dry etching, the active layer is formed due to back-sputtering and oxygen deficiency of the oxide semiconductor. Will be denatured.

As such, the oxide semiconductor has a weak bonding structure, so that an etch stopper is additionally formed on the active layer as a barrier layer to prevent damage to the back channel region by a subsequent process after deposition of the oxide semiconductor. In this case, there is a disadvantage in that the number of masks is increased compared to the conventional amorphous silicon thin film transistor.

The mask process (ie, photolithography process) is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern, and includes a plurality of processes such as photoresist coating, exposure, and developing processes. The masking process lowers the production yield. In particular, the mask designed to form the pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the thin film transistor substrate increases in proportion to this.

The present invention has been made to solve the above problems, and an object thereof is to provide a method for manufacturing a thin film transistor substrate using an oxide semiconductor as an active layer of a thin film transistor.

Another object of the present invention is to adopt the etch stopper structure to ensure the reliability of the device, while forming the thin film transistor in a total of four mask processes by forming the etch stopper, the active layer and the pad contact hole in one mask process. The present invention provides a method for manufacturing a thin film transistor substrate.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate of the present invention comprises the steps of providing a substrate consisting of a pixel portion, a gate pad portion and a data pad portion; Forming a gate electrode and a gate line on the pixel portion of the substrate through a first mask process, and forming a gate pad line and a data pad line on the gate pad portion and the data pad portion of the substrate, respectively; Forming a gate insulating film on a substrate on which the gate electrode, gate line, gate pad line, and data pad line are formed; Forming an active layer made of an oxide semiconductor on the gate electrode on which the gate insulating film is formed through a second mask process, and forming an etch stopper made of an insulating film on the active layer; Forming a first contact hole for exposing a portion of the data pad line of the link unit using the second mask process, and exposing a portion of the gate pad line and the data pad line to the gate pad portion and the data pad portion of the substrate, respectively; Forming a second contact hole and a third contact hole; Forming a source / drain electrode electrically connected to the source / drain regions of the active layer on the active layer through a third mask process, and forming a data line crossing the gate line to define a pixel region; And forming a pixel electrode electrically connected to the drain electrode through a fourth mask process.

As described above, the method of manufacturing a thin film transistor substrate according to the present invention has an excellent uniformity as an oxide semiconductor is used as an active layer of the thin film transistor, thereby providing an effect applicable to a large area display.

In addition, the method of manufacturing a thin film transistor substrate according to the present invention adopts an etch stopper structure to protect the back channel region, thereby improving the reliability of the device and providing an effect of improving the process uniformity in a large area substrate. .

In addition, the method of manufacturing a thin film transistor substrate according to the present invention reduces the number of masks used in the manufacture of the thin film transistor by reducing the number of masks used in the manufacture of the thin film transistor by forming the etch stopper, the active layer, and the pad contact hole in one mask process. Provide effect.

Hereinafter, exemplary embodiments of a method of manufacturing a thin film transistor substrate according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view schematically illustrating a portion of a thin film transistor substrate according to an exemplary embodiment of the present invention, and schematically illustrates an oxide thin film transistor substrate structure using an oxide semiconductor as an active layer.

4 is a cross-sectional view schematically illustrating a portion of a thin film transistor substrate according to an exemplary embodiment of the present invention, wherein a cross section taken along lines A-A 'and BB of the thin film transistor substrate shown in FIG. For example.

3 and 4 illustrate one pixel including a gate pad part, a data pad part, and a thin film transistor of the pixel part. 4 illustrates a part of a link unit that connects a data line and a data pad line.

As shown in the figure, a gate line 116 and a data line 117 are formed on the thin film transistor substrate 110 according to the embodiment of the present invention, which are arranged vertically and horizontally on the substrate 110 to define a pixel region. have. In addition, an oxide thin film transistor, which is a switching element, is formed in an intersection area of the gate line 116 and the data line 117, and is connected to the oxide thin film transistor in the pixel area, thereby common to a color filter substrate (not shown). A pixel electrode 118 for driving a liquid crystal layer (not shown) is formed together with the electrode.

An oxide thin film transistor according to an exemplary embodiment of the present invention includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain connected to the pixel electrode 118. It consists of an electrode 123. In addition, the oxide thin film transistor includes an active layer 124 formed of an oxide semiconductor that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121. ).

In this case, a portion of the pixel electrode 118 is overlapped with a portion of the gate line 116 therebetween with the gate insulating layer 115a interposed therebetween to form a storage capacitor Cst. The storage capacitor Cst keeps the voltage applied to the liquid crystal capacitor constant until the next signal comes in. The storage capacitor Cst has effects such as stability of gray scale display and reduction of flicker and afterimage in addition to signal retention.

In addition, a gate pad electrode 126p and a data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in an edge region of the thin film transistor substrate 110. The scan signal and the data signal applied from the driving circuit unit (not shown) are transferred to the gate line 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend toward the driving circuit part and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively, and the gate pad line 116p and the data pad A line 117p is a scan signal and a data signal from a driving circuit unit through a gate pad electrode 126p and a data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, respectively. You will be authorized.

In this case, the data pad line 117p is connected to the data line 117 through the first contact hole formed in the link portion, and the gate pad electrode 126p is connected to the gate pad through the second contact hole 140b. It is electrically connected to the line 116p and the data pad electrode 127p is electrically connected to the data pad line 117p through the third contact hole 140c.

The oxide thin film transistor according to the embodiment of the present invention configured as described above has high mobility and constant current test conditions as well as uniform characteristics as it forms an active layer using an oxide semiconductor such as zinc oxide. It has the advantage of being applicable to area display.

The zinc oxide is a material capable of realizing all three properties of conductivity, semiconductivity, and resistance according to oxygen content. An oxide thin film transistor using an amorphous zinc oxide semiconductor material as an active layer is used for a liquid crystal display and an organic light emitting display. It can be applied to a large area display including.

In addition, a tremendous interest and activity has recently been focused on transparent electronic circuits, and oxide thin film transistors using the amorphous zinc oxide-based semiconductor materials as active layers have high mobility and can be manufactured at low temperatures, thereby making it possible to manufacture the transparent electronic circuits. There is an advantage that can be used.

The oxide thin film transistor according to the embodiment of the present invention having the above characteristics has a predetermined insulating film between the source electrode 122 and the drain electrode 123 on the back channel region of the active layer 124. An etch stopper 150 is formed. The etch stopper 150 serves to prevent damage to the back channel region by a subsequent process. That is, the etch stopper 150 according to the embodiment of the present invention is formed on the back channel region of the active layer 124 so that the back channel region of the active layer 124 is chemically formed by the mask process during the subsequent process. It serves to prevent exposure to materials, wet or dry etching and plasma processes.

In particular, the etch stopper 150, the active layer 124, and the first, second, and third contact holes 140b and 140c according to the embodiment of the present invention may be formed using a multi-exposure mask or a half-tone mask. By forming in one mask process, the number of masks can be reduced in manufacturing the thin film transistor substrate 110.

As described above, the thin film transistor substrate according to the exemplary embodiment of the present invention has a multi-exposure mask, that is, a blocking region consisting of a dark portion, a first transmission region for transmitting all light, a second transmission region for half-tone, and a half-tone and slit portion. By forming an etch stopper, an active layer, and a contact hole in one mask process using a multi-tone mask of the third transmission region, a thin film transistor can be manufactured through a total of four mask processes. It demonstrates in detail through the manufacturing method of a transistor substrate.

5A through 5D are plan views sequentially illustrating a manufacturing process of the thin film transistor substrate illustrated in FIG. 3.

6A to 6D are cross-sectional views sequentially illustrating a manufacturing process of the thin film transistor substrate illustrated in FIG. 4.

As shown in FIGS. 5A and 6A, a substrate 110 made of a transparent insulating material forms a gate electrode 121 and a gate line 116 in a pixel portion, and a gate pad portion in a gate pad portion and a data pad portion, respectively. Line 116p and data pad line 117p are formed.

At this time, the oxide semiconductor applied to the oxide thin film transistor of the present invention can be a low temperature deposition, it is possible to use a substrate that can be applied to low-temperature processes such as plastic substrate, soda lime glass. In addition, because of the amorphous properties, it is possible to use a substrate for a large area display.

In addition, the gate electrode 121, the gate line 116, the gate pad line 116p, and the data pad line 117p are deposited on the entire surface of the substrate 110 after the first conductive film is deposited. It is formed by selectively patterning through a mask process).

The first conductive layer may include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), Low resistance opaque conductive materials such as molybdenum (Mo), titanium (Ti), platinum (platinum; Pt), tantalum (Ta), and the like may be used. In addition, the first conductive layer may be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the conductive material may be stacked in two or more kinds. It can also be formed into a multi-layered structure.

Next, as shown in FIGS. 5B and 6B, a gate insulating film is formed on the entire surface of the substrate 110 on which the gate electrode 121, the gate line 116, the gate pad line 116p, and the data pad line 117p are formed. After forming the 115a and the oxide semiconductor thin film and the insulating film, the active layer 124 formed of the oxide semiconductor on the gate electrode 121 is selectively patterned by a photolithography process (second mask process). The etch stopper 150 formed of the insulating layer is formed on the back channel region of the active layer 124.

The etch stopper 150 is formed in an island shape on the back channel region of the active layer 124 to prevent the back channel of the thin film transistor from being damaged when the source / drain electrodes are patterned in a process to be described later.

In this case, a portion of the gate insulating layer 115a is removed from the link portion of the substrate 110 so that a first contact hole 140a exposing a portion of the data pad line 117p is formed. A portion of the gate insulating layer 115a is removed from the pad portion of the 110 to expose a portion of the gate pad line 116p and the data pad line 117p, respectively. 140c is formed.

Here, the active layer 124, the etch stopper 150, and the contact holes 140a to 140c according to the embodiment of the present invention may use a single exposure mask or a half-tone mask and ashing process. The mask process (second mask process) is formed at the same time, the second mask process will be described in detail below with reference to the drawings.

7A to 7H are cross-sectional views illustrating in detail a second mask process according to an exemplary embodiment of the present invention illustrated in FIGS. 5B and 6B, and illustrate a second mask process using a multi-exposure mask.

As shown in FIG. 7A, the gate insulating layer 115a and the oxide semiconductor are formed on the entire surface of the substrate 110 on which the gate electrode 121, the gate line 116, the gate pad line 116p, and the data pad line 117p are formed. The thin film 120 and the insulating film 130 are formed.

In this case, the gate insulating layer 115a and the insulating layer 130 may be formed of an inorganic insulating layer such as silicon nitride layer (SiNx) or silicon oxide layer (SiO ₂ ), or a highly dielectric oxide layer such as hafnium (Hf) oxide or aluminum oxide. .

In addition, the gate insulating film 115a and the insulating film 130 are formed by a CVD method using a plasma enhanced chemical vapor deposition (PECVD) device or a physical vapor deposition (PVD) method using a sputtering device. It can be formed as.

And, as shown in Figure 7b, after forming a photosensitive film 170 made of a photosensitive material such as a photoresist on the entire surface of the substrate 110, through the multiple exposure mask 180 according to an embodiment of the present invention Light is selectively irradiated to the photosensitive film 170.

In this case, the multiple exposure mask 180 has a first transmission region I for transmitting all of the irradiated light and a second transmission region II having half-tone portions and half-tones to transmit only a part of the light and block some of the light. A third transmission region III consisting of a portion and a slit portion and a blocking region IV for blocking all irradiated light are provided, and only the light transmitted through the multiple exposure mask 180 is irradiated to the photosensitive film 170. .

Subsequently, after the photoresist film 170 exposed through the multiple exposure mask 180 is developed, as shown in FIG. 7C, the blocking region IV, the second transmission region II, and the third transmission region are illustrated. The first photoresist pattern 170a to the fourth photoresist pattern 170d having a predetermined thickness remain in the region where all the light is blocked or partially blocked through (III), and the first transmission region I through which all the light is transmitted. The photoresist film is completely removed to expose the surface of the insulating film 130.

In this case, the first photoresist pattern 170a formed in the blocking region IV may include the second photoresist pattern 170b to the fourth photoresist pattern formed through the second transmission region II and the third transmission region III. Thicker than 170d). In addition, the second photoresist pattern 170b and the third photoresist pattern 170c formed through the third transmission region III may be less than the fourth photoresist pattern 170d formed through the second transmission region II. The photoresist is completely removed in a region where the light is transmitted through the first transmission region I. This is because the photoresist of the positive type is used, and the present invention is not limited thereto. You may use a photoresist.

Next, as shown in FIG. 7D, the gate insulating film 115a and the oxide semiconductor thin film 120 formed under the first photosensitive film pattern 170a to the fourth photosensitive film pattern 170d formed as a mask are used as a mask. ) And the insulating layer 130 are selectively removed, a first contact hole 140a exposing a portion of the data pad line 117p is formed in the link portion of the substrate 110, and the substrate 110 is formed. A second contact hole 140b and a third contact hole 140c are formed to expose portions of the gate pad line 116p and the data pad line 117p, respectively.

Subsequently, when the ashing process of removing a part of the thickness of the first photoresist pattern 170a to the fourth photoresist pattern 170d is performed, as illustrated in FIG. 7E, a fourth portion of the second transmission region II is formed. The photoresist pattern is completely removed.

In this case, the first photoresist pattern to the third photoresist pattern may include the blocking region IV and the fifth photoresist pattern 170a 'through the seventh photoresist pattern 170c' where the thickness of the fourth photoresist pattern is removed. Only the source and drain regions corresponding to the third transmission region (III) and the channel region between the source and drain regions remain.

Subsequently, as shown in FIG. 7F, when the remaining fifth photoresist pattern 170a ′ through seventh photoresist pattern 170c ′ are used as masks, the oxide semiconductor thin film and the insulating layer formed thereunder are selectively removed. The active layer 124 made of the oxide semiconductor is formed in the pixel portion of the substrate 110.

In this case, an insulating layer pattern 130 ′ formed of the insulating layer and patterned in substantially the same shape as the active layer 124 is formed on the active layer 124.

Subsequently, when the ashing process of removing a part of the thickness of the fifth photoresist pattern 170a ′ to the seventh photoresist pattern 170c ′ is performed, as illustrated in FIG. 7G, the third transmission region III may be formed. The sixth photoresist pattern and the seventh photoresist pattern are completely removed.

In this case, the fifth photoresist pattern is an eighth photoresist pattern 170a ″ removed by the thickness of the sixth photoresist pattern and the seventh photoresist pattern and remains only in the channel region corresponding to the blocking region III.

Subsequently, as shown in FIG. 7H, a partial region of the insulating layer is selectively removed by using the remaining eighth photoresist pattern 170a ″ as a mask to form the insulating layer on the active layer 124 and the active layer. An etch stopper 150 is formed to protect the channel region of layer 124.

As such, the active layer 124, the etch stopper 150, and the contact holes 140a to 140c according to the embodiment of the present invention may be formed through a single mask process by using a multiple exposure mask. As a result, the number of masks used in the manufacture of the thin film transistor is reduced, thereby reducing the manufacturing process and cost.

In addition, the thin film transistor according to the embodiment of the present invention forms and protects the etch stopper 150 so that the back channel region of the active layer 124 is not exposed, thereby making the thickness of the active layer 124 relatively thin. The back channel region of the active layer 124 may be prevented from being contaminated. As a result, the thickness of the active layer 124 and the gate insulating film 115a can be made thin, thereby substantially reducing the driving voltage and the threshold voltage of the thin film transistor.

Meanwhile, as described above, the active layer, the etch stopper, and the contact hole may be formed through one mask process by using a half-tone mask and an additional ashing process, which will be described in detail with reference to the following drawings.

8A to 8H are cross-sectional views illustrating another second mask process according to the embodiment of the present invention shown in FIGS. 5B and 6B in detail, and show a second mask process using a half-tone mask and an ashing process. .

As shown in FIG. 8A, the gate insulating film 215a and the oxide semiconductor thin film are formed on the entire surface of the substrate 210 on which the gate electrode 221, the gate line 216, the gate pad line 216p, and the data pad line 217p are formed. 220 and an insulating film 230 are formed.

Then, as shown in Figure 8b, after forming a photosensitive film 270 made of a photosensitive material such as photoresist on the entire surface of the substrate 210, a half-tone mask 280 or diffraction according to an embodiment of the present invention Light is selectively irradiated to the photosensitive film 270 through a mask (hereinafter, referred to as a half-tone mask).

In this case, the half-tone mask 280 blocks the first transmission region I through which all of the irradiated light is transmitted, the second transmission region II through which only a part of the light is transmitted and partly blocks and blocks all the irradiated light. The region III is provided, and only the light passing through the half-tone mask 280 is irradiated to the photosensitive film 270.

Subsequently, after the photoresist 270 exposed through the half-tone mask 280 is developed, light passes through the blocking region III and the second transmission region II, as shown in FIG. 8C. The first photoresist pattern 270a and the second photoresist pattern 270b having a predetermined thickness remain in the blocked or partially blocked region, and the photoresist is completely removed in the first transmission region I through which all the light is transmitted. The surface of the insulating film 230 is exposed.

In this case, the first photoresist layer pattern 270a formed in the blocking region III is thicker than the second photoresist layer pattern 270b formed through the second transmission region II. In addition, the photosensitive film is completely removed in a region where all the light is transmitted through the first transmission region I. This is because a positive type photoresist is used, and the present invention is not limited thereto. You may use a resist.

Next, as shown in FIG. 8D, the gate insulating film 215a and the oxide semiconductor thin film 220 formed under the first photosensitive film pattern 270a and the second photosensitive film pattern 270b formed as a mask are used as masks. ) And the insulating layer 230 are selectively removed, the first contact hole 240a exposing a part of the data pad line 217p is formed in the link portion of the substrate 210, and the substrate 210 is formed. A second contact hole 240b and a third contact hole 240c exposing portions of the gate pad line 216p and the data pad line 217p are formed in the pad portion of the pad portion.

Subsequently, when the ashing process of removing a part of the thicknesses of the first photoresist pattern 270a and the second photoresist pattern 270b is performed, as illustrated in FIG. 8E, a second portion of the second transmission region II is formed. The photoresist pattern is completely removed.

In this case, the first photoresist pattern is a third photoresist pattern 270a 'from which the thickness of the second photoresist pattern is removed, and a source region and a drain region corresponding to the blocking region III, and between the source region and the drain region. It remains only in the channel region of.

Subsequently, as shown in FIG. 8F, when the oxide semiconductor thin film and the insulating film formed thereon are selectively removed by using the remaining third photoresist pattern 270a ′ as a mask, the pixel portion of the substrate 210 may be removed. An active layer 224 made of the oxide semiconductor is formed.

In this case, an insulating layer pattern 230 ′ formed of the insulating layer and patterned in substantially the same shape as the active layer 224 is formed on the active layer 224.

Subsequently, when the ashing process of removing a part of the thickness of the third photoresist pattern 270a 'is performed, a portion of the width is also removed together with the fourth photoresist pattern 270a ". Only the channel area remains.

Subsequently, as shown in FIG. 8H, a partial region of the insulating layer is selectively removed by using the remaining fourth photoresist pattern 270a ″ as a mask to form the insulating layer on the active layer 224 and the active layer. An etch stopper 250 is formed to protect the channel region of layer 224.

Next, as shown in FIGS. 5C and 6C, after the second conductive layer is deposited on the entire surface of the substrate 110 on which the active layer 124 and the etch stopper 150 are formed, a photolithography process (third mask) is performed. The source / drain electrodes 122 and 123 formed of the second conductive layer in the pixel portion of the substrate 110 and electrically connected to the source / drain regions of the active layer 124 by selectively patterning the same through a process). Will form.

In addition, the data line 117 is formed of the second conductive layer through the third mask process and crosses the gate line 116 to define a pixel region. In this case, the data line 117 is electrically connected to the data pad line 117p at the lower portion of the link unit through the first contact hole 140a.

In this case, a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, nickel, chromium, molybdenum, titanium, platinum, tantalum, or the like may be used for forming the source electrode, the drain electrode, and the data line. . In addition, the second conductive layer may be formed of a transparent conductive material such as indium tin oxide, indium zinc oxide, or a multilayer structure in which two or more conductive materials are stacked.

Next, as shown in FIGS. 5D and 6D, after forming a third conductive film on the entire surface of the substrate 110 on which the source electrode 122, the drain electrode 123, and the data line 117 are formed, photolithography The pixel electrode 118 formed of the third conductive layer and electrically connected to the drain electrode 123 may be formed by selectively removing the same through a process (fourth mask process). .

The gate pad line 116p and the data pad line 117p are formed of the third conductive layer through the fourth mask process, respectively, through the second contact hole 140b and the third contact hole 140c. ) And a gate pad electrode 126p and a data pad electrode 127p electrically connected to each other.

In this case, the third conductive layer includes a transparent conductive material having excellent transmittance such as indium tin oxide or indium zinc oxide to form the pixel electrode, the gate pad electrode, and the data pad electrode.

The thin film transistor substrate according to the embodiment of the present invention manufactured as described above is bonded to the color filter substrate by a sealant formed on the outside of the image display area, wherein the thin film transistor, the gate line, and the data are attached to the color filter substrate. A black matrix is formed to prevent light leaking into the lines, and a color filter is formed to realize red, green, and blue colors.

In this case, the bonding of the color filter substrate and the thin film transistor substrate is performed through a bonding key formed on the color filter substrate or the thin film transistor substrate.

As described above, the present invention can be used not only in a liquid crystal display device but also in another display device manufactured using a thin film transistor, for example, an organic light emitting display device in which an organic light emitting element is connected to a driving transistor.

In addition, the present invention has an advantage that it can be used in a transparent electronic circuit or a flexible display by applying an oxide semiconductor having a high mobility while processing at a low temperature as an active layer.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2 is a cross-sectional view schematically showing the structure of a typical oxide thin film transistor.

3 is a plan view schematically illustrating a portion of a thin film transistor substrate according to an exemplary embodiment of the present invention.

4 is a schematic cross-sectional view of a portion of a thin film transistor substrate according to an exemplary embodiment of the present invention.

5A through 5D are plan views sequentially illustrating a manufacturing process of the thin film transistor substrate illustrated in FIG. 3.

6A to 6D are cross-sectional views sequentially illustrating a manufacturing process of the thin film transistor substrate illustrated in FIG. 4.

7A to 7H are cross-sectional views illustrating a second mask process according to an exemplary embodiment of the present invention shown in FIGS. 5B and 6B.

8A to 8H are cross-sectional views showing in detail another second mask process according to the embodiment of the present invention shown in FIGS. 5B and 6B.

DESCRIPTION OF REFERENCE NUMERALS

110: substrate 116: gate line

116p: gate pad line 117: data line

117p: data pad line 118: pixel electrode

121: gate electrode 122: source electrode

123: drain electrode 124: active layer

126p: gate pad electrode 127p: data pad electrode

150: etch stopper

Claims (10)

Providing a substrate including a pixel portion, a gate pad portion, and a data pad portion; Forming a gate electrode and a gate line on the pixel portion of the substrate through a first mask process, and forming a gate pad line and a data pad line on the gate pad portion and the data pad portion of the substrate, respectively; Forming a gate insulating film on a substrate on which the gate electrode, gate line, gate pad line, and data pad line are formed; Forming an active layer made of an oxide semiconductor on the gate electrode on which the gate insulating film is formed through a second mask process, and forming an etch stopper made of an insulating film on the active layer; Forming a first contact hole for exposing a portion of the data pad line of the link unit using the second mask process, and exposing a portion of the gate pad line and the data pad line to the gate pad portion and the data pad portion of the substrate, respectively; Forming a second contact hole and a third contact hole; Forming a source / drain electrode electrically connected to the source / drain regions of the active layer on the active layer through a third mask process, and forming a data line crossing the gate line to define a pixel region; And And forming a pixel electrode electrically connected to the drain electrode through a fourth mask process. The method of claim 1, wherein the data line is electrically connected to a data pad line of the link unit through the first contact hole. The method of claim 1, further comprising forming a gate pad electrode and a data pad electrode electrically connected to the gate pad line and the data pad line through the second contact hole and the third contact hole, respectively, using the fourth mask process. The method of manufacturing a thin film transistor substrate, further comprising the step. The method of claim 1, wherein the second mask process Forming an oxide semiconductor thin film and an insulating film on the gate insulating film; Forming a first to fourth photoresist pattern on the insulating layer by applying a multiple exposure mask; Selectively removing the gate insulating layer, the oxide semiconductor thin film, and the insulating layer using the first to fourth photoresist patterns as a mask to form a first contact hole exposing a portion of the data pad line in the link portion of the substrate; Forming a second contact hole and a third contact hole exposing portions of the gate pad line and the data pad line, respectively, in the gate pad part and the data pad part of the substrate; Forming a fifth to seventh photoresist pattern by removing the fourth photoresist pattern through an ashing process and removing a portion of the thickness of the first to third photoresist patterns; Selectively removing the oxide semiconductor thin film and the insulating layer using the fifth to seventh photoresist patterns as a mask to form an active layer formed of the oxide semiconductor in the pixel portion of the substrate; Forming an eighth photoresist pattern by removing the sixth photoresist pattern and the seventh photoresist pattern through an ashing process and simultaneously removing a portion of the fifth photoresist pattern; And And selectively removing a portion of the insulating layer by using the eighth photoresist pattern as a mask to form an etch stopper formed of the insulating layer on the active layer. The method of claim 4, wherein the eighth photosensitive film pattern corresponds to a channel region of the active layer. The method of claim 4, wherein the sixth photoresist pattern and the seventh photoresist pattern correspond to a source region and a drain region of the active layer. The method of claim 1, wherein the second mask process Forming an oxide semiconductor thin film and an insulating film on the gate insulating film; Forming a first photoresist pattern and a second photoresist pattern on the insulating layer by applying a half-tone mask; Selectively removing the gate insulating film, the oxide semiconductor thin film and the insulating film using the first photoresist pattern and the second photoresist pattern as a mask to form a first contact hole exposing a portion of the data pad line in a link portion of the substrate, Forming a second contact hole and a third contact hole exposing portions of the gate pad line and the data pad line, respectively, in the gate pad part and the data pad part of the substrate; Removing the second photoresist pattern through an ashing process and forming a third photoresist pattern by removing part of the thickness of the first photoresist pattern; Selectively removing the oxide semiconductor thin film and the insulating layer using the third photoresist pattern as a mask to form an active layer formed of the oxide semiconductor in a pixel portion of the substrate; Forming a fourth photoresist pattern by removing a part of the thickness and width of the third photoresist pattern through an ashing process; And And selectively removing a portion of the insulating layer using the fourth photoresist pattern as a mask to form an etch stopper formed of the insulating layer on the active layer. The method of claim 7, wherein the fourth photoresist pattern corresponds to a channel region of the active layer. The method of claim 1, wherein the substrate is formed of a glass substrate or a plastic substrate. The method of claim 1, wherein the active layer is formed of an amorphous zinc oxide semiconductor.

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