KR20130036681A - Oxide thin film transistor array substrate and the method of manufacturing the same - Google Patents

Abstract

PURPOSE: An oxide thin film transistor array substrate and a manufacturing method thereof are provided to omit an additional mask process for forming a pixel electrode. CONSTITUTION: A gate electrode(120) and a gate line(123) of a gate pad part are formed at the same time. A drain electrode(142) is connected to a pixel electrode(137). A drain electrode pattern, a pixel electrode pattern, and an active layer are made of oxide semiconductor. The patterns and the active layer are patterned at the same time by using one mask. A plasma process is performed on the patterns to form the drain electrode and the pixel electrode.

Description

[0001] The present invention relates to an oxide thin film transistor array substrate and a method of manufacturing the same,

Embodiments of the present invention relate to an oxide thin film transistor array substrate and a manufacturing method thereof, and more particularly, to an oxide thin film transistor array substrate for reducing the number of process masks and a manufacturing method thereof.

In a flat panel display such as a liquid crystal display device, each pixel is provided with an active element such as a thin film transistor to drive the display element. In the active matrix method, the thin film transistor is arranged in each pixel to drive the corresponding pixel.

On the other hand, a general thin film transistor has used amorphous silicon as a semiconductor layer. However, since the amorphous silicon has a slow electron transfer rate, it has been difficult to realize a high resolution and a high driving capability in a very large screen. Therefore, an oxide thin film transistor having an electron transfer rate 10 times faster than that of amorphous silicon has emerged. Recently, it has been attracting attention as a device suitable for high resolution of over UD (Ultra Definition) and high-speed driving of 240 Hz or more.

The liquid crystal display device is manufactured by a complicated process such as a photolithography process using a mask. The structure and manufacturing process of the conventional oxide-oxide-TFT array substrate substrate will be described in detail with reference to FIGS. 1 and 2. FIG.

FIG. 1 is a cross-sectional view of a conventional oxide-oxide-thin-film transistor array substrate, and FIG. 2 is a flow chart of a manufacturing process of a conventional oxide-oxide thin film transistor array substrate.

As shown in FIG. 1, a metal layer (not shown) is first formed on the substrate 10 to form a first photoresist pattern (not shown) by a first mask process.

Then, a gate line (not shown) and a gate electrode 20 are formed on the substrate 10 by performing the etching process in a state where the metal layer (not shown) is blocked with the first photoresist pattern.

After the first photoresist pattern is removed, a gate insulating layer 25, an oxide semiconductor and an etch stopper layer (etch stopper) 35 are sequentially deposited on the entire substrate 10 including the gate electrode 20 (S2, S3, S4)

Next, a second photoresist layer (not shown) is coated on the etch stopper layer 35, and a second photoresist pattern (not shown) is formed on the second photoresist layer by a second mask process. Next, the etch stopper 35 is formed by etching the portion of the etch stopper 35 located on the channel region with the second photoresist pattern (not shown) in a blocking state.

Next, a third photoresist pattern (not shown) is formed by applying a third photoresist (not shown) and then using a third mask (not shown). Then, the active layer 30 is formed by etching a part of the oxide semiconductor layer with the third photoresist pattern (not shown) being blocked. (S6)

Next, a metal conductive material is deposited on the entire substrate 10, a fourth photosensitive film (not shown) is coated on the metal conductive material layer, and a fourth photosensitive film pattern (not shown) is formed by a fourth mask process. Then, the source electrode 41 and the drain electrode 42 are formed by etching a portion of the metal conductive material layer with the fourth photoresist pattern being blocked (S7)

Then, a passivation layer 50 is deposited on the substrate 10 to a predetermined thickness or more (S8)

Then, a fifth photosensitive film (not shown) is coated on the passivation layer 50, and a fifth photosensitive film pattern (not shown) is formed in the fifth mask process. Then, the passivation layer 50 is selectively etched using the fifth photoresist pattern (not shown) to expose the drain electrode 42, and a contact hole (not shown) Thereby forming a hole (not shown). (S9)

After the fifth photoresist pattern is removed, a transparent conductive material such as ITO is deposited on the passivation layer 50 including the contact hole (not shown). A sixth photoresist pattern (not shown) is formed on the transparent conductive material layer by a sixth mask process and etched to form a pixel electrode P electrically connected to the drain electrode 42. In operation S10,

Since the mask process includes a thin film deposition, a photoresist (not shown) application, a photolithography process, a photoresist pattern formation process, and an etching process, a single mask process requires much time and cost.

Accordingly, the above-described process has been disadvantageous in that it requires a lot of cost and time due to a lot of mask processes since the conventional method of manufacturing an oxide thin film transistor array substrate using amorphous silicon.

Accordingly, in order to solve the above problems, the embodiments of the present invention aim to reduce the number of mask processes of the oxide thin film transistor array substrate. Other objects and features of the present invention will be described in the following detailed description and claims.

According to an aspect of the present invention, there is provided an oxide thin film transistor array substrate comprising: a substrate; A gate electrode formed on the substrate; A gate insulating layer formed on the gate electrode; An active layer formed on the gate insulating film, the active layer being formed of an oxide semiconductor and overlapping the gate electrode; A drain electrode formed on the gate insulating layer and extending from the active layer, and a pixel electrode extending from the drain electrode; An etch stop formed on the active layer; And a source electrode formed on the etch stopper and in contact with the active layer, wherein the pixel electrode and the drain electrode are formed of a conductive metal in which the oxide semiconductor is metallized through a plasma treatment.

Advantageously, the etch stopper is configured to block the metalization of the active layer during the plasma treatment.

Further, the active layer is formed of an a-IGZO semiconductor (In-Ga-Zn-O-based composite oxide semiconductor).

In addition, the pixel electrode and the drain electrode are formed of a conductive metal obtained by metallizing the a-IGZO semiconductor.

A passivation layer over the source electrode and over the entire surface of the substrate; And a common electrode formed on the passivation layer so as to overlap the pixel electrode.

The common electrode is formed with a plurality of slits at the upper portion of the pixel electrode to form the pixel electrode and the fringe field.

Meanwhile, an oxide thin film transistor array substrate according to another embodiment includes a substrate; A source electrode formed on the substrate; An active layer overlying the substrate, the active layer being overlapped with the source electrode and formed of an oxide semiconductor; A pixel electrode formed on the substrate and extending from the active layer and extending from the drain electrode; An etch stop formed on top of the active layer; An insulating layer formed on the front surface of the substrate and above the etch stopper; And a gate electrode formed on the insulating layer, the gate electrode overlapping the active layer, and the pixel electrode and the drain electrode are formed of a conductive metal formed by metallizing the oxide semiconductor through a plasma treatment.

According to another aspect of the present invention, there is provided a method of fabricating an oxide thin film transistor array substrate, including: forming a gate electrode on a substrate; Sequentially depositing a gate insulating layer and an oxide semiconductor layer on the entire surface of the substrate over the gate electrode; Patterning the oxide semiconductor layer with a single mask to form an active layer, a drain electrode pattern and a pixel electrode pattern connected to each other; Forming an etch stopper on top of the active layer; Forming a drain electrode and a pixel electrode by metallizing the drain electrode pattern and the pixel electrode pattern by plasma treatment; Forming a source electrode in contact with the active layer on top of the etch stopper; And a control unit.

Preferably, the step of forming the drain electrode and the pixel electrode is characterized in that the etch stopper interrupts the metallization of the active layer from the plasma treatment.

Further, the oxide semiconductor layer is an a-IGZO semiconductor.

Forming a passivation layer on the entire surface of the substrate above the source electrode; And forming a common electrode in an area of the passivation layer and overlapping the pixel electrode.

The oxide thin film transistor array substrate and the manufacturing method thereof according to at least one embodiment of the present invention configured as described above,

By patterning the pixel electrode using the same mask as the drain electrode and the active layer, it is possible to eliminate a separate mask process for forming the pixel electrode conventionally.

Further, by reducing one mask process, simplification of the process, improvement of productivity, cost and time reduction can be achieved.

In addition, by forming the region where the drain electrode and the contact hole are conventionally formed from a transparent conductive material, the aperture ratio can be improved.

1 is a cross-sectional view of a conventional oxide-oxide-thin-film transistor array substrate.
FIG. 2 is a flowchart illustrating a manufacturing process of a conventional oxide-oxide-thin-film transistor array substrate.
3A is a plan view of an oxide thin film transistor array substrate according to the first embodiment of the present invention.
FIG. 3B is a cross-sectional view illustrating cut-away surfaces of the thin film transistor and the pixel region of FIG. 3A and the cut-off surfaces of C1-C1 'showing data pads A1-A1', B1-B1 'of the gate pad and data pad.
4A is a plan view of an oxide thin film transistor array substrate according to a second embodiment of the present invention.
FIG. 4B is a cross-sectional view of the thin film transistor and the pixel region of FIG. 4A taken along the line A2-A2 ', the gate pad B2-B2', and the data pad C2-C2 '.
5A is a plan view of an oxide thin film transistor array substrate according to a second embodiment of the present invention.
FIG. 5B is a cross-sectional view illustrating cut-away surfaces of the thin film transistor and the pixel region of FIG. 5A, A3 to A3 'of the pixel region, B3 to B3' of the gate pad, and C3 to C3 'of the data pad.
6A to 6G are sectional views of a method of manufacturing an oxide thin film transistor array substrate according to a second embodiment of the present invention.
7 is a flowchart of an oxide thin film transistor array substrate according to a second embodiment of the present invention.

Hereinafter, an oxide thin film transistor array substrate according to an embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the drawings.

In the present specification, similar components are denoted by similar reference numerals in different embodiments, and the description thereof is replaced with the first explanation.

As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise.

In addition, it should be considered that the constituent elements of the drawings attached hereto can be enlarged or reduced for convenience of explanation.

FIG. 3A is a plan view of an oxide thin film transistor array substrate according to the first embodiment of the present invention. FIG. 3B is a cross-sectional view taken along line A1-A1 ' Sectional views taken along lines C1 to C1 'shown in FIG.

The first embodiment of the present invention is characterized by being in the TN mode, which shows only one pixel region of the array substrate.

3A, a space between a data line 143 and a gate line 123 intersecting with each other is defined as a pixel region, and a thin film transistor (not shown) is formed in one space of the pixel region.

The thin film transistor is a switching element, which includes a gate electrode 120 connected to the gate line 123 at the lowest layer of the substrate, a gate insulating film as an upper layer thereof, an active layer above the gate insulating film, A source electrode 141 formed to extend in the direction of the gate electrode 120 in one region of the data line 143 and a source electrode 141 formed on the opposite side of the source electrode 141 with respect to the active layer, A drain electrode 142, and a drain electrode 142. As shown in FIG.

In the operation of the thin film transistor, when the channel is conducted to the active layer by the gate voltage transmitted from the gate line 123, the data voltage transmitted from the data line 143 is applied to the source electrode 141, And is then applied to the pixel electrode 137 to be driven.

One surface of the drain electrode 142 may extend in one direction and may be connected to the pixel electrode 137. The pixel electrode 137 can form an electric field with a common electrode formed on the upper surface of a color filter substrate (not shown) opposite to the oxide thin film transistor array substrate, and a liquid crystal The molecular arrangement of the liquid crystal layer can be changed by applying the electric field to the layer.

The pixel electrode 137 has a rectangular shape except a region where the thin film transistor is formed, and may have a size corresponding to one pixel.

Although not shown in the drawing, a storage capacitor is formed at a portion overlapping one area of the pixel electrode 137, and data applied to the liquid crystal during the off operation of the thin film transistor is applied to the pixel electrode The voltage of the pixel electrode 137 can be maintained. The storage capacitor may include a first storage electrode (not shown) which overlaps with one region of the pixel electrode 137 and a second storage electrode which is the same as the pixel electrode 137, have.

A data pad may be formed at an end portion extending from the data line 143, and a gate pad may be formed at an end portion extending from the gate line 123.

The data pad and the gate pad are connected to the data line 143 and the gate line 123, respectively, and a transparent conductive metal connected to the lines is connected to the data driver and the gate driver to transmit a signal voltage to each line .

Hereinafter, a cross-sectional view of the thin film transistor will be described in detail with reference to FIG. 3B.

The thin film transistor may have a structure in which a gate electrode 120, a gate insulating film, an active layer, a drain electrode 142, an etch stopper 135, and a source electrode 141 are sequentially stacked.

The gate electrode 120 may be formed simultaneously with the gate line 123 of the gate pad portion.

The active layer may be formed on the gate insulating film in a region overlapping the gate electrode 120.

On the other hand, the active layer may be formed of an oxide semiconductor, and the kind of the oxide semiconductor is not limited. For example, a Zn oxide-based material, and may be formed of a material containing Zn oxide, In-Zn oxide, Ga-In-Zn oxide, or the like and further containing other substances such as organic substances.

Preferably, the oxide semiconductor may be an a-IGZO semiconductor containing heavy metals such as indium (In) and gallium (Ga) in ZnO.

The a-IGZO semiconductor can transmit visible light and is transparent, and the oxide thin film transistor fabricated from the a-IGZO semiconductor has a mobility of 1 to 100 cm / Vs, so that the a-IGZO semiconductor has a higher mobility characteristic than the amorphous silicon thin film transistor .

In addition, the a-IGZO semiconductor can produce UV light emitting diode (LED), white LED, and other components having a wide band gap and high color purity and can process at low temperature to produce a light and flexible product .

Moreover, since the oxide thin film transistor fabricated from the a-IGZO semiconductor exhibits a uniform characteristic similar to that of an amorphous silicon thin film transistor, the structure of the oxide thin film transistor is as simple as an amorphous silicon thin film transistor and has advantages of being applicable to a large area display.

Meanwhile, a drain electrode 142 is electrically connected to one of the active layers, and the drain electrode 142 is connected to the pixel electrode 137.

Here, the drain electrode pattern, the pixel electrode pattern, and the active layer are formed of the same oxide semiconductor, and can be simultaneously patterned using one mask.

The drain electrode pattern and the pixel electrode pattern may be metallized by a plasma treatment to form the drain electrode 142 and the pixel electrode 137 of the conductive metal.

Due to the plasma treatment, the drain electrode 142 and the pixel electrode 137 can be changed from a transparent oxide semiconductor to a transparent conductive metal.

However, since the etch stopper 135 exists on the active layer, the etch stopper 135 serves as an interruption of the plasma treatment, so that the active layer is not plasma-treated.

Meanwhile, the etch stopper 135 serves to prevent damage to the upper portion of the active layer in which the channel is formed during the etching process.

The first embodiment of the present invention has the active layer 130 and the drain electrode 142 and the pixel electrode 137 as the pixel electrode 137. However, It is not necessary to use an independent mask for the pixel electrode 137 by patterning using a single mask, so that the number of mask processes can be reduced.

Meanwhile, the source electrode 141 may be formed on the etch stopper 135 in electrical contact with the active layer, and the data line 143 may be formed on the data pad portion at the same time.

A passivation layer may be formed on the upper surface of the source electrode 141 and on the entire surface of the substrate. The data pad and the gate pad may have first contact holes 171 and second A contact hole 172 may be formed. The first and second contact holes 172 are formed of a transparent conductive metal film and contact the gate line 123 and the data line 143, respectively.

Hereinafter, the structure of the oxide thin film transistor array substrate according to the second and third embodiments of the present invention will be described in detail.

The second and third embodiments of the present invention are characterized by being FFS (Fringe Field Switching) mode, the second embodiment is a bottom gate type, the third embodiment is a top gate type )to be.

First, the second embodiment of the present invention will be described.

FIG. 4A is a plan view of an oxide thin film transistor array substrate according to a second embodiment of the present invention. FIG. 4B is a cross-sectional view of the thin film transistor of FIG. Sectional view taken along line II-II 'in FIG.

An oxide thin film transistor array substrate according to a second embodiment of the present invention includes a gate line, a data line, a thin film transistor, a common electrode, and a pixel electrode, a gate pad, and a data pad.

The gate lines are arranged in a first direction, for example, in a lateral direction, and the data lines are arranged in the second direction, for example, a longitudinal direction. The data lines may be arranged in a second direction, and each of the data lines may be formed by bending in a S-shape. At this time, the gate line and the data line are arranged in an intersecting manner to define a pixel region.

The thin film transistor is formed in a region where the gate line and the data line cross each other. The thin film transistor includes a gate electrode, a gate insulating film, an active layer, an etch stopper, a source electrode, and a drain electrode 340.

And the gate electrode may be formed at the same time as the gate line and may refer to one region of the gate line overlapping the source electrode in the figure. The gate electrode may extend from the gate line in a second direction.

A gate insulating layer is deposited on the gate electrode using an insulating material such as an oxide or a nitride used for a general semiconductor device.

Then, an active layer is formed on the gate insulating film. The active layer is formed of an oxide semiconductor in an intermediate layer between the gate electrode and the source and drain electrodes 320 and 340 to form a channel through which electrons move when the thin film transistor operates.

At this time, the oxide semiconductor may be an a-IGZO semiconductor containing heavy metals such as indium (In) and gallium (Ga) in ZnO.

According to the second embodiment of the present invention, the active layer can be patterned simultaneously with the drain electrode and the pixel electrode through one mask process.

At this time, the drain electrode and the pixel electrode may be formed of the same oxide semiconductor as the active layer, patterned simultaneously with the active layer through the same mask, and then metallized with a transparent conductive metal through a plasma treatment.

However, the active layer may be affected by the plasma treatment, but an etch stopper may be formed on the active layer to block the metallization by the plasma treatment. The etch stopper may also prevent damage to the channel forming region of the active layer.

Therefore, in the prior art, a pixel electrode is formed using a transparent ITO (In-Tin-Oxide) or IZO (InZnO) conductive film by a separate mask process. However, in the second embodiment of the present invention, the IGZO is metallized since the drain electrode and the pixel electrode are patterned at the same time in the pattern of the oxide semiconductor, a separate mask for the pixel electrode is unnecessary, and the number of mask processes can be reduced.

By reducing the number of mask processes, the process can be simplified, cost and time for the process can be reduced, and productivity can be improved.

In addition, conventionally, the contact hole region for contacting the drain electrode, the pixel electrode, and the drain electrode is formed of an opaque conductive metal. However, since the second embodiment of the present invention utilizes the transparent characteristic of the IGZO, the region through which light is transmitted in the thin film transistor region is expanded, so that the aperture ratio can be improved.

The source electrode may extend in a first direction in which the gate line extends from the data line to an upper portion of the etch stopper. At this time, the source electrode is in electrical contact with the active layer, and the data voltage of the data line can be supplied to the drain electrode through the channel of the active layer.

And the drain electrode is formed to be connected at the side of the active layer and may be formed in electrical contact with the active layer.

The pixel electrode may be formed on the entire surface of the pixel region, which is connected to the drain electrode and forms a border between the data line and the gate line.

Although not shown in FIG. 4A, the common electrode may include a plurality of slit-shaped second openings having the same shape as a data line at an upper portion overlapping the pixel electrodes, And may be formed on the entire surface of the pixel region except for the second opening.

Therefore, in the cross-sectional view of FIG. 4B, the common electrode may have a plurality of second openings corresponding to a plurality of slits, while the pixel electrode is formed entirely, and the first openings may be formed in the thin film transistor region .

The reason why the first opening is provided is that when the common electrode is formed in the thin film transistor region, interference may occur in the movement of electrons in the channel region of the active layer.

However, the present invention is not limited to the above example. If the common electrode and the pixel electrode form a fringe field, the common electrode may be formed in a plate shape, and the pixel electrode may have a shape in which a plurality of slits are provided in the pixel region .

A gate pad is formed at an end portion extending from the gate line, and a data pad is formed at an end portion extending from the data line.

The gate pad has a first contact hole formed on an upper portion thereof to be in contact with a gate line, and a transparent conductive metal layer is formed on the first contact hole to allow a gate voltage to be applied to the gate line.

The data pad may have a second contact hole formed thereon to be in contact with the data line, and a transparent conductive metal film may be formed on the second contact hole to allow a data voltage to be applied to the data line.

In the second embodiment of the present invention which has been discussed above, by selecting an FFS-type oxide thin film transistor array substrate, it is possible to secure a higher viewing angle, a lower viewing angle, and a side viewing angle than the first embodiment.

Hereinafter, an oxide thin film transistor array substrate according to a third embodiment of the present invention will be described in detail.

5A is a plan view of an oxide thin film transistor array substrate according to a second embodiment of the present invention. FIG. 5B is a cross-sectional view taken along the line A3-A3 ' Sectional view taken along line III-II 'of FIG.

In the oxide thin film transistor array substrate, a gate line and a data line intersect each other in a first direction and a second direction, respectively, as in the second embodiment, and a pixel region is defined. In the pixel region, a pixel electrode is formed in a rectangular plate shape And a common electrode is formed on the upper surface, except for the first opening above the thin film transistor region and the second opening with a plurality of slits.

The gate pad and the data pad may be connected to each other through a transparent conductive metal film formed on the gate line and the data line and the first contact hole and the second contact hole, respectively.

The thin film transistor according to the third embodiment will now be described in detail with reference to the thin film transistor region which is largely different from the second embodiment.

The oxide thin film transistor according to the third embodiment of the present invention has a top gate type in which source and drain electrodes, an active layer, an etch stopper, an insulating layer, and a gate electrode are sequentially stacked.

The source electrode may be formed on the substrate and may extend in a first direction on one side of the data line.

Then, the active layer, the drain electrode pattern, and the pixel electrode pattern can be formed by depositing the oxide semiconductor. The drain electrode pattern and the pixel electrode pattern may be metallized to the drain electrode and the pixel electrode through a plasma processing process as described in the first and second embodiments.

At this time, the etch stopper is formed on the active layer, and the active layer is not metallized during the plasma treatment process.

And a flat insulating layer may be formed on the upper surface of the etch stopper and over the entire surface of the substrate.

A gate electrode may be formed on the insulating layer at a position overlapping the active layer. The gate electrode may be a part of the gate line, or may extend in one direction from the gate line.

A gate insulating layer may be formed on the gate line, and a common electrode may be formed on the gate insulating layer, leaving the first and second openings as described in the second embodiment.

The oxide thin film transistor array substrate according to the third embodiment discussed above can simultaneously form the drain electrode and the pixel electrode in the same mask process as in the second embodiment, thereby reducing the number of mask processes compared with the conventional technique.

Hereinafter, a method of manufacturing an oxide thin film transistor according to embodiments of the present invention will be described in detail through a process sectional view and a flowchart.

Hereinafter, the oxide thin film transistor array substrate according to the second embodiment of the present invention will be described with reference to the manufacturing method.

6A to 6G are sectional views of a method of manufacturing an oxide thin film transistor array substrate according to a second embodiment of the present invention, and FIG. 7 is a flowchart of an oxide thin film transistor array substrate according to a second embodiment of the present invention.

First, referring to FIG.

A gate electrode and a gate line may be formed on a substrate made of a transparent insulating material. The gate electrode is formed by selectively depositing a first conductive layer (not shown) on the entire surface of the substrate, and then selectively patterning the layer through a photolithography process using a first photoresist layer and a first mask. Here, the first conductive layer may be formed of one selected from the group consisting of Al, Al alloy, tungsten, copper, nickel, chromium, molybdenum, titanium, A low resistance opaque conductive material such as platinum (Pt), tantalum (Ta), or the like can be used. The first conductive layer may be formed of an opaque conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or the like. Layer structure. (SS1)

Next, an inorganic insulating film such as a silicon nitride film (SiNx) or a silicon oxide film (SiO2) or a gate insulating film made of hafnium (Hf) oxide or a high dielectric oxide film such as aluminum oxide is deposited on the entire surface of the substrate on which the gate electrode is formed . At this time, the gate insulating layer may be formed by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). (SS2)

An oxide semiconductor layer is deposited on the entire surface of the substrate having the gate insulating film formed thereon. At this time, the kind of the oxide semiconductor layer is not limited. For example, a Zn oxide-based material, and may be formed of a material containing Zn oxide, In-Zn oxide, Ga-In-Zn oxide, or the like and further containing other substances such as organic substances. (SS3)

However, preferably, the oxide semiconductor layer may be an a-IGZO semiconductor containing heavy metals such as indium (In) and gallium (Ga) in ZnO. The a-IGZO semiconductor may be formed by a sputtering method using a composite target of gallium oxide (Ga2O3), indium oxide (In2O3) and zinc oxide (ZnO), or may be formed by chemical vapor deposition or atomic deposition Layer deposition (ALD)) may be used.

Then, the oxide semiconductor layer is patterned as shown in FIG. 6B. At this time, a second photoresist layer (not shown) is coated on the oxide semiconductor layer and a second photoresist layer pattern is formed by a second mask process. The second photoresist pattern is a pattern for forming an active layer, a pixel electrode pattern, and a drain electrode pattern. Next, an active layer, a pixel electrode pattern, and a drain electrode pattern are formed through an etching process. The oxide semiconductor layer patterns may all have a connected shape. (SS4)

An etch stop layer may be formed on the oxide semiconductor layer. (SS5)

Thereafter, the etch stopper can be patterned as shown in Fig. 6C. At this time, a third photosensitive film (not shown) is coated on the etch stopper layer, and a third photosensitive film pattern (not shown) is formed on the third photosensitive film by a third mask process. Next, an etch stopper is formed by etching in a state where the region overlapping the gate electrode is blocked with the third photoresist pattern (not shown). (SS6)

Then, the drain electrode pattern and the pixel electrode pattern are metallized through a plasma process as shown in FIG. 6D.

The plasma treatment is performed by injecting gas molecules such as He, H 2, SF 6, Ag, N 2 and SiH 4 into the chamber and ionizing the target using a plasma generated by applying an electrical field Can proceed.

On the other hand, since the etch stopper is formed on the active layer to serve as a blocking function, the active layer can remain as the oxide semiconductor without being affected by the plasma treatment. (SS7)

Next, as shown in FIG. 6E, a second conductive film is formed on the entire surface of the substrate on which the active layer is formed to form the source electrode and the data line. At this time, an opaque conductive material such as a gate electrode may be used for the second conductive film. Then, the fourth photoresist film is applied, the fourth photoresist film is patterned using the fourth mask process, and then the source electrode and the data line are formed through the etching process. The source electrode is formed on the etch stopper, and may be formed in electrical contact with the active layer. (SS8)

Subsequently, as shown in FIG. 6F, a passivation layer may be formed of an organic or inorganic insulating material over the entire surface of the substrate on which the active layer and the source and drain electrodes are formed. (SS9)

Then, a fifth conductive film is applied to form a contact hole of the gate pad and the data pad, a fifth photoresist pattern is formed using the fifth mask process, and then the first contact hole and the second contact hole are etched through the etching process (SS10).

Finally, as shown in FIG. 6G, a third conductive layer is formed on the entire surface of the substrate on which the passivation layer is formed, and a common electrode, a first contact hole metal layer, and a second contact hole metal layer are formed through a sixth mask process and an etching process . The third conductive layer may be formed of a conductive material having a high transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO). (SS11)

As described above, the method of manufacturing an oxide thin film transistor array substrate according to an embodiment of the present invention does not require an independent mask process for forming a pixel electrode. In comparison with the flowchart of FIG. 2 referred to in the prior art, although the conventional method uses six masks until the common electrode is formed, one embodiment of the present invention uses five masks, It can be seen that a small number of mask processes are performed.

Thus, the process time and cost can be reduced and the productivity can be improved.

The embodiments of the present invention described above can be used not only in the TN mode and the FFS mode but also in the VA mode and the IPS mode and can also be applied to other display devices manufactured using thin film transistors such as organic electroluminescent display devices .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Therefore, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also within the scope of the present invention.

110, 210, 310: substrate 120, 220, 320: gate electrode
123, 223, 323: gate line 130, 230, 330: active layer
135, 235, 335: etch stopper 137, 237, 337: pixel electrode
141, 241, 341: source electrode 142, 242, 342: drain electrode
143, 243, 343: data line 265, 365: common electrode

Claims (11)

Board;
A gate electrode formed on the substrate;
A gate insulating layer formed on the gate electrode;
An active layer formed on the gate insulating film, the active layer being formed of an oxide semiconductor and overlapping the gate electrode;
A drain electrode formed on the gate insulating layer and extending from the active layer, and a pixel electrode extending from the drain electrode;
An etch stop formed on the active layer; And
And a source electrode formed on the etch stopper and in contact with the active layer,
Wherein the pixel electrode and the drain electrode are formed of a conductive metal in which the oxide semiconductor is metallized through plasma treatment. The method according to claim 1,
Wherein the etch stop prevents the active layer from being metallized during the plasma treatment. ≪ RTI ID = 0.0 > 11. < / RTI > The method according to claim 1,
Wherein the active layer is formed of a-IGZO semiconductor (In-Ga-Zn-O-based composite oxide semiconductor). The method of claim 3,
Wherein the pixel electrode and the drain electrode are formed of a conductive metal obtained by metallizing the a-IGZO semiconductor. The method according to claim 1,
A passivation layer over the source electrode and over the entire surface of the substrate; And
Further comprising a common electrode formed on the passivation layer to overlap the pixel electrode. 6. The method of claim 5,
Wherein the common electrode is formed with a plurality of slits at an upper portion of the pixel electrode to form a fringe field with the pixel electrode. Board;
A source electrode formed on the substrate;
An active layer overlying the substrate, the active layer being overlapped with the source electrode and formed of an oxide semiconductor;
A pixel electrode formed on the substrate and extending from the active layer and extending from the drain electrode;
An etch stop formed on top of the active layer;
An insulating layer formed on the front surface of the substrate and above the etch stopper; And
And a gate electrode formed on the insulating layer and overlapping the active layer,
Wherein the pixel electrode and the drain electrode are formed of a conductive metal in which the oxide semiconductor is metallized through plasma treatment. Forming a gate electrode on top of the substrate;
Sequentially depositing a gate insulating layer and an oxide semiconductor layer on the entire surface of the substrate over the gate electrode;
Patterning the oxide semiconductor layer with a single mask to form an active layer, a drain electrode pattern and a pixel electrode pattern connected to each other;
Forming an etch stopper on top of the active layer;
Forming a drain electrode and a pixel electrode by metallizing the drain electrode pattern and the pixel electrode pattern by plasma treatment; And
Forming a source electrode in contact with the active layer on top of the etch stopper;
Wherein the oxide thin film transistor array substrate comprises a plurality of oxide thin film transistor array substrates. 9. The method of claim 8,
Wherein forming the drain electrode and the pixel electrode is such that the etch stopper blocks metallization of the active layer from the plasma treatment. 9. The method of claim 8,
Wherein the oxide semiconductor layer is an a-IGZO semiconductor. 9. The method of claim 8,
Forming a passivation layer on the entire surface of the substrate and over the source electrode; And
Forming a common electrode on an upper portion of the passivation layer and overlapping the pixel electrode;
Further comprising a step of forming an oxide thin film transistor array substrate.

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