KR20070093752A - Method for fabricating thin film transistor array substrate - Google Patents

Abstract

A method for manufacturing a TFT array substrate is provided to reduce remarkably the number of mask processes and to improve the efficiency of processing. A gate conduction layer is formed on an insulating substrate(10). A gate electrode(24) is formed on the resultant structure by etching selectively the gate conduction layer using a first photoresist pattern as an etch mask. A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer, a data conduction layer and a second photoresist pattern are sequentially deposited on the resultant structure. Source and drain electrodes(65,66) are formed by etching the data conduction layer using the second photoresist pattern as an etch mask. Resistive contact layers(55,56) with the same patterns as those of the source and drain electrodes are formed by etching the doped amorphous silicon layer. A protection layer and a third photoresist pattern are formed on the resultant structure. The protection layer is etched by using the third photoresist pattern as an etch mask. The substrate is exposed to the outside at a pixel region by etching the amorphous silicon layer and the gate insulating layer. A transparent conductive oxide layer is formed on the resultant structure. A pixel electrode is formed on the exposed portion of the substrate by removing the third photoresist pattern and the conductive oxide layer.

Description

Method for fabricating thin film transistor array substrate

1 is a layout diagram of a thin film transistor array substrate manufactured by a method according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1.

3 and 7 are layout diagrams illustrating process steps of a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention.

4 through 6 are cross-sectional views illustrating the process steps taken along the line IV-IV ′ of FIG. 3.

8 to 11 are cross-sectional views of the process steps taken along the line VII-VII 'of FIG. 7.

<Description of the symbols for the main parts of the drawings>

10: insulating substrate 22: gate line

24: gate electrode 26: sustain electrode

31: gate insulating film pattern 44: semiconductor layer

55, 56: ohmic contact layer 62: data line

65 source electrode 66 drain electrode

71: protective film pattern 82: pixel electrode

100: photoresist pattern

The present invention relates to a method of manufacturing a thin film transistor array substrate, and more particularly, to a method of manufacturing a thin film transistor array substrate in which the number of slit mask processes is reduced and the process efficiency is improved by improving the etching order.

In the modern society, the role of semiconductor integrated circuits, semiconductor devices, semiconductor devices, and the like is becoming increasingly important and widely used in various industrial fields. In particular, as the information society has accelerated, the electronic display field has been continuously developed, and a new function electronic display device capable of performing various functions required by the information society has been developed.

Conventionally, such a field of electronic display is a cathode ray tube (cathode ray tube). However, since cathode ray tubes have limitations in heavy weight, large volume, and high power consumption, flat panel display devices such as liquid crystal displays, organic electroluminescent displays, and plasma display panels are used. Has been spotlighted as a replacement for cathode ray tubes. Dual liquid crystal display devices have been applied to various fields such as monitors, notebook computers, televisions, mobile phones, etc. because they are thin and light.

In the dual liquid crystal display device or the organic EL device, the liquid crystal display device uses a thin film transistor array substrate having a thin film transistor array formed thereon as one substrate. The thin film transistor array substrate includes various wiring patterns including gate lines, data lines, and the like, and a mask process using a photoresist (PR) pattern is used to form such a wiring pattern finely. However, such a mask process increases the process time and increases the cost of the product, and thus, researches for reducing the number of processes using the mask in various ways have been continued.

As one example, a three mask process is used in which a gate electrode is patterned using a first mask, a channel portion is patterned using a second mask, and a protective film and / or pixel electrode is patterned using a third mask. However, such a conventional three mask process requires a slit mask process in the second mask and the third mask, and the process is complicated because the wet etching and the dry etching must be alternately performed two or more times during the patterning of the channel portion. The time may be delayed.

An object of the present invention is to provide a method of manufacturing a thin film transistor array substrate in which the number of slit mask processes is reduced and the process efficiency is improved by improving the etching order.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate, in which a gate conductive layer is stacked on an insulating substrate, a first photoresist pattern is formed on the gate conductive layer, and The gate conductive layer is etched using a first photoresist pattern as an etch mask to form a gate electrode, and a gate insulating film, an amorphous silicon layer, a doped amorphous silicon layer, and a data conductive layer are sequentially stacked on the entire surface of the resultant product. Forming a second photoresist pattern on the data conductive layer, etching the data conductive layer using the second photoresist pattern as an etching mask to form a source electrode and a drain electrode, and forming a doped amorphous silicon layer. Etched resists having a pattern substantially the same as those of the source and drain electrodes by etching Forming a layer, laminating a protective film on the resultant, forming a third photoresist pattern on the protective film, etching the protective film using the third photoresist pattern as an etching mask, and forming the lower amorphous silicon layer And etching the gate insulating film to expose the insulating substrate in the pixel region, laminating a transparent conductive oxide layer on the entire surface of the resultant, and removing the third photoresist pattern and the conductive oxide layer stacked thereon. Forming a pixel electrode located on the substrate.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate, in which a gate conductive layer is stacked on an insulating substrate, a first photoresist pattern is formed on the gate conductive layer, and The gate conductive layer is etched using a first photoresist pattern as an etch mask to form a gate electrode and a sustain electrode, and a gate insulating film, an amorphous silicon layer, a doped amorphous silicon layer, and a data conductive layer are sequentially formed on the entire surface of the resultant product. Stacked on the data conductive layer, a second photoresist pattern is formed on the data conductive layer, and the data conductive layer is etched using the second photoresist pattern as an etching mask to form a source electrode and a drain electrode, and the doped amorphous layer The silicon layer is etched to form substantially the same pattern as the source and drain electrodes. A resistive contact layer having a resistive layer, a protective film laminated on the resultant, a first region covering the source electrode and the drain electrode, and a second region covering the sustain electrode and thicker than the first region; Forming a third photoresist pattern, etching the passivation layer using the first region of the third photoresist pattern as an etch mask, and etching the amorphous silicon layer and the gate insulating layer below to etch the insulating substrate in the pixel region. Expose a gate insulating film on the sustain electrode by etching the second region, the lower protective film and the amorphous silicon layer of the third photoresist pattern, and simultaneously depositing a transparent conductive oxide layer on the entire surface of the resultant material, The exposure by removing the first region of the third photoresist pattern and the conductive oxide layer stacked thereon; Forming a pixel electrode on the insulating substrate and the gate insulating film on the sustain electrode.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

When elements or layers are referred to as "on" or "on" of another element or layer, intervening other elements or layers as well as intervening another layer or element in between It includes everything. On the other hand, when a device is referred to as "directly on" or "directly on" indicates that no device or layer is intervened in the middle. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

As used herein, the term "thin film transistor array substrate" refers to a substrate including at least one thin film transistor, and does not exclude a case where another structure is interposed between the thin film transistor and the substrate or another structure is formed thereon. Do not.

Hereinafter, a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention will be described.

First, the structure of a thin film transistor array substrate manufactured by a method according to an embodiment of the present invention will be described. The thin film transistor array substrate includes a pixel electrode arranged in a matrix on an insulating substrate and a thin film transistor which is a switching element connected to the pixel electrode. The pixel of the thin film transistor substrate is defined by, for example, two adjacent gate lines and two adjacent data lines, and most pixel regions cover the pixel electrode. The gate lines are arranged between the pixel electrodes in the row direction of the pixel electrode, and the data lines are arranged between the pixel electrodes in the column direction of the pixel electrode, which are connected to the thin film transistor.

The pixel structure of the thin film transistor array substrate will be described in more detail. 1 is a layout diagram of a thin film transistor array substrate manufactured by a method according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1.

1 and 2, a plurality of gate lines 22 extending in a first direction are formed on an insulating substrate 10 made of transparent glass, plastic, or the like. The gate line 22 forms a gate electrode 26 protruding toward the pixel region at regular intervals. In addition, the gate line 22 extends in the opposite direction of the gate electrode 26 to form the storage electrode 26. The gate line 22, the gate electrode 24, and the storage electrode 26 may be formed of, for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), and titanium (Ti). ), Tantalum (Ta) or an alloy thereof, or the like, or a single layer or multiple layers.

The gate insulating film pattern 31 is formed on the gate line 22, the gate electrode 24, and the storage electrode 26. The gate insulating layer pattern 31 is formed so as to cover the formation region of the gate line 22, the gate electrode 24, and the storage electrode 26, and expose a space occupying most of the pixel region. The gate insulating layer pattern 31 may be made of, for example, silicon nitride (SiNx) or the like.

A semiconductor layer 44 made of a semiconductor such as hydrogenated amorphous silicon is formed on the gate insulating film pattern 31. The semiconductor layer 44 is at least overlapped with the gate electrode 24 such that the semiconductor layer 44 forms a channel portion of the thin film transistor. The semiconductor layer 44 is formed to cover most of the gate insulating layer patterns 31 except for the storage electrode 26 region. The semiconductor layer 44 may also be positioned on, for example, the gate insulating layer pattern 31 on the gate line 22.

On the semiconductor layer 44, ohmic contacts 55 and 56 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of n-type impurities are formed. The ohmic contacts 55 and 56 are positioned on the semiconductor layer 44 in the region where the upper data line 62, the source electrode 65, and the drain electrode 66 are formed, and are not formed on the gate line 22. Do not.

A plurality of data lines 62 extending in the second direction are formed on the ohmic contacts 55 and 56. The data line 62 is branched toward the pixel region at regular intervals to form the source electrode 65. A drain electrode 66 separated from the source electrode 65 is formed on the opposite side of the source electrode 65 with respect to the gate electrode 24. The data line 62, the source electrode 65 and the drain electrode 66 may be, for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti), It may be composed of a single layer or multiple layers including tantalum (Ta) or alloys thereof. Here, the source electrode 65 and the drain electrode 66 constitute a thin film transistor together with the gate electrode 24 and the semiconductor layer 44.

A passivation layer pattern 71 made of silicon nitride (SiNx) or the like is formed on the data line 62, the source electrode 65, and the drain electrode 66. The passivation layer pattern 71 has a pattern substantially the same as that of the lower semiconductor layer 44 except for partially exposing an end portion of the lower drain electrode 66. Thus, for example, it may not be located on the sustain electrode 26, but may be located on the gate electrode 24.

The pixel electrode 82 is formed on the drain electrode 66 which is not covered by the protective film pattern 71, and covers the insulating substrate 10 on the pixel region. The pixel electrode 82 is disposed on the gate insulating layer pattern 31 on the storage electrode 26 and forms a storage capacitor together with the lower storage electrode 26 using the gate insulating layer pattern 31 as a dielectric layer.

As another example of the above-described thin film transistor array substrate, the sustain electrode 26 may be formed separately from the gate line 22 unlike the illustrated example of FIGS. 1 and 2, and may not be formed when the amount of the capacitor is sufficient. It may not. Details of such other embodiments will be easily deduced or understood by the above description, and thus detailed descriptions thereof will be omitted.

Hereinafter, the manufacturing method of the thin film transistor array substrate which has a structure as mentioned above is demonstrated. In the present embodiment, the material constituting each configuration, etc. may be applied in the same manner as the materials described in the embodiments of FIGS. 1 and 2, and thus, detailed descriptions thereof are omitted. In addition, in each step, the same reference numeral is added for the same configuration as the reference numeral referred to in the embodiment of Figs.

3 and 7 are layout diagrams illustrating process steps of a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention. 4 through 6 are cross-sectional views illustrating the process steps taken along the line IV-IV ′ of FIG. 3. 8 to 11 are cross-sectional views of the process steps taken along the line VII-VII 'of FIG. 7.

First, referring to FIGS. 3 and 4, a gate conductive layer (not shown) is stacked on the entire surface of the insulating substrate 10. For example, sputtering or the like is used for lamination of the gate conductive layer.

Subsequently, a photoresist film is coated on the resultant, exposed and developed to form a first photoresist pattern (not shown) defining the gate line 22, the gate electrode 24, and the storage electrode 26. Subsequently, the gate conductive layer is etched using the first photoresist pattern as an etching mask. The etching of the gate conductive layer proceeds, for example, by wet etching. As a result, the gate line 22, the gate electrode 24, and the sustain electrode 26 are formed as shown in FIG. 4.

Subsequently, referring to FIG. 5, the gate insulating layer 30, the intrinsic amorphous silicon layer 40, and the doped amorphous silicon layer 50 are formed on the entire surface of the resultant product. This step can be used, for example, Chemical Vapor Deposition (CVD), and can be carried out by continuous deposition or in-situ.

Then, the doped amorphous silicon layer 50 data conductive layer 60 is deposited. For example, sputtering or the like is used for stacking the data conductive layer 60.

Next, referring to FIG. 6, a second photoresist that defines a data line 62, a source electrode 65, and a drain electrode 66 by applying a photoresist film on the data conductive layer 60, and exposing and developing the photoresist film. The pattern 100 is formed. The second photoresist pattern 100 may be a photoresist pattern having a uniform thickness for each region. Thus, no additional slit mask process or the like is required.

7 and 8, the data conductive layer 60 is etched using the second photoresist pattern 100 as an etching mask. The etching of the data conductive layer 60 is, for example, wet etching. As a result, the data line 62, the source electrode 65 and the drain electrode 66 are completed.

Subsequently, the lower doped amorphous silicon layer 50 is etched using the second photoresist pattern 100 as an etching mask. As a result, the ohmic contacts 55 and 56 are completed. In this case, the amorphous silicon layer 40 under the ohmic contacts 55 and 56 is controlled not to be removed, and for this purpose, an EPD method or a time controlled etching method may be used. Next, the second photoresist pattern 100 is removed. On the other hand, as a modification of this step, after patterning the data line 62, the source electrode 65 and the drain electrode 66, the second photoresist pattern 100 is removed, the data line 62, the source electrode The lower doped amorphous silicon layer 50 may be patterned using the 65 and drain electrodes 66 as etch masks.

Next, referring to FIG. 9, a protective film 70 is stacked on the entire surface of the resultant product. For example, the chemical vapor deposition method may be used for the deposition of the protective film 70.

Subsequently, a photoresist film is coated on the entire surface of the protective film 70, exposed to light, and developed to form third photoresist patterns 111-113. The third photoresist pattern covers the data line 62, the source electrode 65, the drain electrode 66, and the gate electrode 24, and the first region 111 having the first thickness d1. And second regions 112 and 113 covering the sustain electrode 26 and the gate line 22 formation region. In this case, the first region 111 is formed so as not to cover a part of the drain electrode 66. In addition, the second region is formed in the region of the gate line 22, and is formed in the first section 112 having the second thickness d2 and the region of the sustain electrode 26, and has a third thickness d3. The second section 113 is included. Here, the first thickness d1 of the first region 111 and the second thickness d2 of the first region 112 of the second region 111 may be substantially the same, but the second region 113 of the second region 113 may be substantially the same. ) Is formed to be smaller than the first thickness d1 and the second thickness d2.

The third photoresist patterns 111-113 having different thicknesses as described above may be formed using a slit mask or a halftone mask.

Next, referring to FIG. 10, the passivation layer 70, the amorphous silicon layer 40, and the gate insulating layer 30 are etched using the third photoresist patterns 111-113 as etching masks. Each step may be performed by dry etching, and may be performed in situ. In addition, it may proceed using one etching gas for process efficiency. Examples of the etching gas that can be applied in this step include SF ₆ , CF ₄ , O ₂ , or HCl, these may be used alone or in combination. As a result, the insulating substrate 10 in the pixel region is exposed. At this time, the etching of the passivation layer 70 using the first region 111 as an etching mask forms a protrusion of the drain electrode 66. Since the drain electrode 66 is hardly etched by dry etching, a subsequent dry etching process is performed. In FIG. 3, the etching mask functions as an etching mask of the lower amorphous silicon layer 40 and the gate insulating layer 30.

Meanwhile, the height of the third photoresist patterns 111-113 is also lowered by the dry etching. Here, when the second section 113 of the second region has a relatively sufficiently small thickness d3, it is completely removed during the dry etching process to expose the lower passivation layer 70. Therefore, the passivation layer 70 and the lower portion of the amorphous silicon layer 40 may be etched by the continuous dry etching process. Preferably, dry etching is performed under the condition that only the gate insulating layer 30 remains in the sustain electrode 26 region. Such control of the residual film and its thickness may be made by controlling the thickness of the second section 113, the selection of the etching gas, and the adjustment of the etching time.

As described above, the thickness d1 'of the first region 111' of the third photoresist pattern and the thickness d2 'of the second region 112' of the third photoresist pattern are also reduced. The drain electrode 66 is partially exposed. In addition, as a result of this step, the protective film pattern 71 and the gate insulating film pattern 31 are completed. In this step, since the gate conductive layer or the data conductive layer requiring wet etching are not included in the three layers sequentially sequentially described above, the process efficiency may be performed only by dry etching, and may be performed in situ. This can be improved.

Next, referring to FIG. 11, transparent conductive oxide layers 81 and 82 are stacked on the resultant. This step can proceed, for example, by sputtering.

Here, a part of the conductive oxide layer 81 is formed on the third photoresist patterns 111 ′ and 112 ′, and a part of the conductive oxide layer 82 is formed of the insulating substrate 10 in the remaining region, that is, the pixel region, It is formed on the protruding portion of the drain electrode 66 and the gate insulating film pattern 31 on the sustain electrode 26.

1 and 2, the third photoresist patterns 111 ′ and 112 ′ and the conductive oxide layer 81 positioned thereon are removed. For example, when the third photoresist patterns 111 'and 112' are stripped using a photoresist stripper, the conductive oxide layer 81 thereon is also lifted off and removed. As a result, the pixel electrode 82 as shown in FIG. 2 is completed.

Meanwhile, as another embodiment of the present invention, when the storage electrode 26 is not formed, a photoresist pattern having a uniform thickness may be used as the third photoresist pattern. In addition, when the sustain electrode 26 is formed separately from the gate line 22, it will be readily understood that the shapes of the first photoresist pattern and the third photoresist pattern may be modified.

In addition, in the above embodiment, the passivation layer pattern and the pixel electrode pattern are formed using one etching mask, but the passivation layer pattern and the pixel electrode pattern may be formed using different masks, respectively. That is, after lamination of the protective film, the protective film pattern is formed using the third photoresist pattern as an etching mask, and the third photoresist pattern is removed. Subsequently, after the conductive oxide layer is stacked and the fourth photoresist pattern is formed, the pixel electrode pattern may be formed using the fourth photoresist pattern as an etching mask. In this case, of course, the lift-off process as in the embodiment of the present invention can be omitted.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments but may be manufactured in various forms, and having ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the method of manufacturing the thin film transistor array substrate according to the embodiments of the present invention, the number of mask processes may be reduced, and the number of slit mask or halftone mask processes may be reduced. In addition, since the etching process of the protective film, the amorphous silicon layer and the gate insulating film can be performed in situ, the process efficiency can be improved.

Claims (9)

Stacking a gate conductive layer on an insulating substrate, and forming a first photoresist pattern on the gate conductive layer, Etching the gate conductive layer using the first photoresist pattern as an etching mask to form a gate electrode, Sequentially depositing a gate insulating film, an amorphous silicon layer, a doped amorphous silicon layer, and a data conductive layer on the entire surface of the resultant, and forming a second photoresist pattern on the data conductive layer, The data conductive layer is etched using the second photoresist pattern as an etch mask to form a source electrode and a drain electrode, and the doped amorphous silicon layer is etched to have a resistance substantially the same as that of the source electrode and the drain electrode. Forming a contact layer, A protective film is laminated on the resultant, and a third photoresist pattern is formed on the protective film. The protective layer is etched using the third photoresist pattern as an etch mask, and the lower portion of the amorphous silicon layer and the gate insulating layer are etched to expose the insulating substrate in the pixel region, Laminating a transparent conductive oxide layer on the front of the resultant, And removing the third photoresist pattern and the conductive oxide layer stacked thereon to form a pixel electrode positioned on the exposed insulating substrate. According to claim 1, The passivation layer etching includes partially exposing the drain electrode, And etching the amorphous silicon layer and the gate insulating layer using the exposed portions of the third photoresist pattern and the drain electrode as an etching mask. The method of claim 2, The passivation layer etching, the amorphous silicon layer etching and the gate insulating layer etching is a dry etching method of manufacturing a thin film transistor array substrate. The method of claim 3, wherein The protective layer dry etching, the amorphous silicon layer dry etching, and the gate insulating film dry etching may be performed in situ. Stacking a gate conductive layer on an insulating substrate, and forming a first photoresist pattern on the gate conductive layer, Etching the gate conductive layer using the first photoresist pattern as an etching mask to form a gate electrode and a sustain electrode, Sequentially depositing a gate insulating film, an amorphous silicon layer, a doped amorphous silicon layer, and a data conductive layer on the entire surface of the resultant, and forming a second photoresist pattern on the data conductive layer, The data conductive layer is etched using the second photoresist pattern as an etch mask to form a source electrode and a drain electrode, and the doped amorphous silicon layer is etched to have a resistance substantially the same as that of the source electrode and the drain electrode. Forming a contact layer, A protective film is stacked on the resultant, and a third photoresist pattern including a first region covering the source electrode and the drain electrode and a second region covering the sustain electrode and thicker than the first region are formed on the protective layer. and, The protective layer is etched using the first region of the third photoresist pattern as an etch mask, and the lower portion of the amorphous silicon layer and the gate insulating layer are etched to expose the insulating substrate in the pixel region, and at the same time, the third photoresist. Etching the second region of the pattern, the lower passivation layer and the amorphous silicon layer to expose the gate insulating layer on the sustain electrode; Laminating a transparent conductive oxide layer on the front of the resultant, And removing the first region of the third photoresist pattern and the conductive oxide layer stacked thereon to form pixel electrodes positioned on the exposed insulating substrate and the gate insulating layer on the sustain electrode. Method of manufacturing a substrate. The method of claim 5, The protective layer etching using the first region of the third photoresist pattern as an etching mask includes exposing the drain electrode partially. Exposing the insulating substrate by etching the lower amorphous silicon layer and the gate insulating layer may include exposing the insulating substrate by etching by using an exposed portion of the first region and the drain electrode of the third photoresist pattern as an etching mask. A method of manufacturing a thin film transistor array substrate. The method of claim 6, The protective layer etching, the amorphous silicon layer etching, and the gate insulating film etching using the first region of the third photoresist pattern as an etching mask are performed by dry etching. The method of claim 7, wherein The protective layer dry etching, the amorphous silicon layer dry etching, and the gate insulating film dry etching may be performed in situ. The method of claim 5, And a pixel electrode positioned on the gate insulating film to form a storage capacitor using the gate insulating film as a dielectric layer together with the storage electrode.

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