KR20130113234A

KR20130113234A - Display device and method of manufacturing the same

Info

Publication number: KR20130113234A
Application number: KR1020120035658A
Authority: KR
Inventors: 남승희; 류순성; 문태형
Original assignee: 엘지디스플레이 주식회사
Priority date: 2012-04-05
Filing date: 2012-04-05
Publication date: 2013-10-15
Also published as: KR102037406B1

Abstract

The present invention discloses a display device that can not only improve the performance and reliability of the switching element but also simplify the process.
The disclosed display device includes a pixel region defined by crossing a plurality of gate lines and data lines, a gate electrode branched from the plurality of gate lines, and a single gate insulating layer and a gate insulating layer formed on the gate electrode. A source / drain electrode formed thereon, the gate electrode including first to third metal patterns, the first and second metal patterns being sequentially deposited, and the third metal pattern being first and second metal patterns Using the seed layer as a seed layer has a structure that covers the second metal pattern containing copper (Cu) to be closed from the outside by an electroless plating method.

Description

TECHNICAL FIELD [0001] The present invention relates to a display device and a method of manufacturing the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and to a display device and a method of manufacturing the same, which can improve performance and reliability of a switching element, as well as simplify the process.

Recently, liquid crystal display devices, organic light emitting display devices, and the like, which have advantages of light weight, thinness, and low power consumption, have been used for office automation devices and audio / video devices.

The liquid crystal display device includes a liquid crystal layer as the electro-optical active layer, and the organic light emitting display device includes an organic light emitting layer as the electro-optical active layer.

The liquid crystal display displays an image by changing an electrical signal into visual information by using a characteristic in which light transmittance of a liquid crystal, which is an intermediate state material between a liquid and a crystal, changes according to an applied voltage. Conventional liquid crystal display devices are composed of two substrates provided with electrodes and a liquid crystal layer interposed between the two substrates. Such a liquid crystal display device is light in weight, small in volume, and operates with a small power as compared with other display devices having the same screen size.

A liquid crystal display device displays an image by selectively transmitting light generated from a light source at a rear side to each pixel of a liquid crystal display panel at a front side as a kind of light switch. That is, the conventional cathode ray tube (CRT) controls the brightness by adjusting the intensity of the electron beam, whereas the LCD displays the screen by controlling the intensity of light generated from the light source.

In the liquid crystal display panel of the liquid crystal display device as described above, the color filter substrate (upper substrate) on which the color filter is formed and the thin film transistor substrate (lower substrate) on which the thin film transistor (TFT) is formed are bonded together with the liquid crystal layer interposed therebetween. Consists of a structure.

In a thin film transistor substrate of a typical liquid crystal display panel, a gate line and a data line cross each other, and a thin film transistor TFT is formed at an intersection of the gate line and the data line.

The thin film transistor includes a gate electrode and a source / drain electrode with a gate insulating layer interposed therebetween, and the drain electrode is electrically connected to the pixel electrode.

A protective layer is formed on the gate insulating layer including the source / drain electrode and the pixel electrode, and a common electrode wiring and a common electrode pattern are formed on the protective layer.

As described above, the thin film transistor substrate included in the general liquid crystal display device uses copper (Cu) having low resistance as a material of the gate electrode and the source / drain electrode.

Such copper (Cu) is mainly used to form an opaque metal pattern of a thin film transistor substrate.

However, the copper (Cu) causes a problem of contaminating the semiconductor pattern through the silicon oxide (SiO 2) used as the gate insulating layer.

A general thin film transistor substrate forms a gate insulating layer of a multilayer structure in which silicon nitride (SiNx) and silicon oxide (SiO 2) are sequentially deposited in order to prevent performance of the thin film transistor due to copper (Cu).

However, in the general liquid crystal display device, even if a gate insulating layer including silicon nitride (SiNx) is formed to prevent performance degradation of the thin film transistor due to copper (Cu), contamination of the semiconductor pattern may not be completely prevented. Dry etching and wet etching processes for visualizing silicon nitride (SiNx) and silicon oxide (SiO2) must be sequentially performed when forming contact holes for contact between the electrodes and the pixel electrodes, gate pads, and data pads. There was a problem that the process was complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device and a method of manufacturing the same, which can not only improve performance and reliability of switching elements but also simplify the process.

According to an embodiment of the present invention,

A pixel region defined by crossing a plurality of gate lines and data lines; A gate electrode branched from the plurality of gate lines; A single gate insulating layer formed on the gate electrode; And a source / drain electrode formed on the gate insulating layer, wherein the gate electrode includes first to third metal patterns, and the first and second metal patterns are sequentially deposited and the third metal. The pattern has a structure in which the second metal pattern including copper (Cu) is closed from outside by using the first and second metal patterns as seed layers.

Method of manufacturing a liquid crystal display device according to another embodiment of the present invention,

The first and second metal patterns are formed by laminating a photolithography process using a mask on a transparent substrate, and copper (Cu) is formed by electroless plating using the first and second metal patterns as seed layers. Forming a gate electrode and a gate line including forming a third metal pattern covering the second metal pattern to be closed from the outside; Forming a single gate insulating layer on the transparent substrate including the gate electrode and the gate line; Forming a semiconductor pattern on the gate insulating layer; And forming a source / drain electrode and a data line on the semiconductor pattern and the gate insulating layer.

The display device according to the exemplary embodiment of the present invention proposes a multilayer structure in which a metal pattern made of nickel (Ni) closes a metal pattern made of copper (Cu) in the gate electrode and the source / drain electrode. Has the advantage of simplifying the process by forming a single layer (silicon oxide). That is, the gate insulating layer of the present invention can simplify the manufacturing process by omitting the dry etching process for forming the contact hole by omitting silicon nitride of the general gate insulating layer of the multi-layer structure.

In addition, the present invention proposes a multilayer structure in which a metal pattern made of nickel (Ni) closes a metal pattern made of copper (Cu) in a gate electrode and a source / drain electrode, thereby providing a semiconductor layer made of copper (Cu). It has the advantage of improving the performance and reliability of TFT by preventing contamination.

1 is a plan view illustrating unit pixels of a thin film transistor substrate according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a thin film transistor substrate cut along lines II ′, II-II ′, III-III ′, and IV-IV ′ of FIG. 1.
3 is an enlarged cross-sectional view illustrating a thin film transistor region cut along the line II ′ of FIG. 2.
4A through 10C are plan and cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.
11 is a cross-sectional view illustrating a thin film transistor region of a thin film transistor substrate according to another exemplary embodiment of the present invention.

The present invention provides a pixel region defined by crossing a plurality of gate lines and data lines, a gate electrode branched from the plurality of gate lines, and a source formed on a single gate insulating layer and a gate insulating layer formed on the gate electrode. / Drain electrodes, the gate electrodes include first to third metal patterns, the first and second metal patterns are sequentially deposited, and the third metal pattern is the first and second metal patterns as seed layers. Thus, the second metal pattern including copper (Cu) is covered by an electroless plating method so as to be closed from the outside.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the accompanying drawings, embodiments of the present invention will be described in detail.

One embodiment of the present invention is intended to enable a person skilled in the art to fully understand the technical idea of the present invention. Therefore, the present invention is not limited to the embodiments described below, and other embodiments can be added on the basis of the technical idea of the present invention.

1 is a plan view illustrating unit pixels of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a line II-I ', II-II', III-III ', or IV-IV' of FIG. 1. FIG. 3 is a cross-sectional view illustrating a thin film transistor substrate cut along the line II ′ of FIG. 2.

As shown in FIGS. 1 to 3, a thin film transistor substrate according to an embodiment of the present invention is a thin film transistor for driving a liquid crystal cell at an intersection of a plurality of gate lines GL and a plurality of data lines DL. (TFT) is formed.

The gate line GL and the data line DL cross each other to define a pixel area. Here, the pixel electrode 150 and the common electrode 152 are alternately formed in the pixel area.

A gate pad GP electrically connected to the gate line GL is formed at one end of the gate line GL, and a data pad electrically connected to the data line DL at one end of the data line DL. DP) is formed.

The thin film transistor TFT includes a gate electrode 110 formed on the base substrate 100, a gate insulating layer 120 formed on the gate electrode 110, and the base substrate 100, and the gate insulating layer ( The semiconductor pattern 130 formed on the semiconductor pattern 130 and the source / drain electrodes 140a and 140b formed on the semiconductor pattern 130 are included.

The gate electrode 110 is formed on the gate line GL and has a width wider than that of the gate line GL.

The first passivation layer 121 is formed on the gate insulating layer 120 including the source / drain electrodes 140a and 140b.

The drain electrode 140b is exposed to the outside by the first contact hole C1 from which the first protective layer 131 is removed, and is electrically connected to the pixel electrode 150.

A second protective layer 131 is formed on the semiconductor pattern 130 to prevent damage during the pattern formation process of the source / drain electrodes 140a and 140b.

The gate electrode 110 includes first to third metal patterns 111, 112, and 113.

The first metal pattern 111 may be formed of any one of tantalum (Ta), titanium (Ti), chromium (Cr), molybdenum (Mo), tungsten (W), and titanium molybdenum (TiMo), or may be combined with at least one. It may be made of an alloy. Preferably, the titanium molybdenum (TiMo) may be used as the first metal pattern 111.

The second metal pattern 112 may be made of copper (Cu) or an alloy including copper.

The third metal pattern 113 may be made of nickel (Ni) or an alloy containing nickel.

The first and second metal patterns 111 and 112 are formed by depositing a double metal layer on the base substrate 100 through a sputtering process and developing and etching through a photolithography process using a mask.

That is, the first and second metal patterns 111 and 112 have a stacked structure sequentially.

The third metal pattern 113 may be formed after the first and second metal patterns 111 and 112 are formed.

The third metal pattern 113 is formed on the first and second metal patterns 111 and 112 by using electroless plating.

In detail, the third metal pattern 113 is formed on the top and side surfaces of the second metal pattern 112 and is formed on the side surface of the first metal pattern 111.

Therefore, the second metal pattern 112 is closed without being exposed to the outside in the form of being wrapped in the third metal pattern 113.

Here, referring to the electroless plating, the organic material or oxide remaining in the portion where the metal layer pattern (for example, the second metal pattern 112) is formed through the pre-dip process, and then the activation process is performed. Palladium substitution plating through. For example, the third metal pattern 113 may be formed by adding a metal binary with a reducing agent through a plating process after the palladium substitution plating.

In addition, the gate line GL and the gate pad GP are simultaneously formed at the time of forming the gate electrode 110 to include the first to third metal patterns 111, 112, and 113.

In addition, the gate pad GP may include a lower gate pad electrode 160 including the first to third metal patterns 111, 112, and 113 and the lower pad electrode 160 through a second contact hole C2. ) And an upper gate pad electrode 161 connected thereto.

A gate insulating layer 120 including a single layer is formed on the gate electrode 110, the gate line GL, and the gate pad GP.

The gate insulating layer 120 may be formed of silicon oxide (SiO 2).

In the present invention, the second metal pattern 112 made of copper (Cu) is closed by the third metal pattern 113 made of nickel (Ni) to prevent contamination of the semiconductor pattern 130 by copper (Cu). Therefore, silicon nitride (SiNx) included in a gate insulating layer of a general thin film transistor substrate may be omitted.

The source / drain electrodes 140a and 140b are formed on the semiconductor pattern 130 and have the same structure as the gate electrode 110.

The source / drain electrodes 140a and 140b include fourth to sixth metal patterns 141, 142, and 143.

The fourth metal pattern 141 may be formed of any one of tantalum (Ta), titanium (Ti), chromium (Cr), molybdenum (Mo), tungsten (W), and titanium molybdenum (TiMo), or may be combined with at least one. It may be made of an alloy. Preferably, the titanium molybdenum (TiMo) may be used as the fourth metal pattern 141.

The fifth metal pattern 142 may be formed of copper (Cu) or an alloy including copper.

The sixth metal pattern 143 may be made of nickel (Ni) or an alloy containing nickel.

The fourth and fifth metal patterns 141 and 142 are formed by depositing a double metal layer on the base substrate 100 through a sputtering process and developing and etching through a photolithography process using a mask.

That is, the fourth and fifth metal patterns 141 and 142 have a stacked structure sequentially.

The sixth metal pattern 143 may be formed after the fourth and fifth metal patterns 141 and 142 are formed.

The sixth metal pattern 143 is formed on the fourth and fifth metal patterns 141 and 142 using electroless plating.

In detail, the sixth metal pattern 143 is formed on the top and side surfaces of the fifth metal pattern 142 and is formed on the side surface of the fourth metal pattern 141.

Therefore, the fifth metal pattern 142 is closed without being exposed to the outside in a form surrounded by the sixth metal pattern 143.

The data line DL and the data pad DP are simultaneously formed when the source / drain electrodes 140a and 140b are formed to include the fourth to sixth metal patterns 141, 142, and 143.

In addition, the data pad DP may include a lower data pad electrode 170 including the fourth to sixth metal patterns 141, 142, and 143 and a lower data pad electrode (eg, a third contact hole C3). And an upper data pad electrode 171 connected to 170.

As described above, in the display device according to the exemplary embodiment, the second and fifth metal patterns made of copper (Cu) are formed by the third and sixth metal patterns 113 and 143 made of nickel (Ni). By closing (112, 142), the gate insulating layer 120 is formed in a single layer, which has the advantage of simplifying the process. That is, the gate insulating layer 120 of the present invention omits the dry etching process for forming the first to third contact holes C1 C2 and C3 by omitting silicon nitride (SiNx) of the general gate insulating layer having a multilayer structure. , Streamline the manufacturing process.

In addition, according to the present invention, the second and fifth metal patterns 112 and 142 made of copper (Cu) are closed by the third and sixth metal patterns 113 and 143 made of nickel (Ni). By preventing the contamination of the semiconductor pattern (130) by) has the advantage that can improve the performance and reliability of the thin film transistor (TFT).

4A through 10C are plan and cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

4A to 4C, after depositing the first and second metal layers on the transparent base substrate 100 by sputtering, the first and second metal patterns may be formed through a photolithography process using a first mask. 111 and 112 are formed.

Although not shown in detail in the drawing, in the photolithography process using the first mask, a photoresist, which is a photosensitive material, is formed on the deposited first and second metal layers, and then a mask having a transmissive region and a non-transmissive region is used. The exposure and development processes are performed to form a photoresist pattern.

Then, the metal film is etched using the photoresist pattern as a mask to form first and second metal patterns 111 and 112.

5A through 5C, a third metal pattern 113 is formed using an electroless plating method using the first and second metal patterns 111 and 112 as seed layers.

The third metal pattern 113 may be formed to completely surround the second metal pattern 112 to be closed from the outside.

That is, the third metal pattern 113 is formed on the base substrate 100 to form the gate electrode 110, the common electrode 152, and the lower gate pad electrode 160.

6A through 6C, a gate insulating layer 120 is formed on the base substrate 100 including the gate electrode 110, the common electrode 152, and the lower gate pad electrode 160, and the gate electrode The semiconductor pattern 130 and the second protective layer 131 are formed on the gate insulating layer 120 corresponding to 110.

The gate insulating layer 120 and the second protective layer 131 may be formed of silicon oxide (SiO 2).

Each of the semiconductor pattern 130 and the second passivation layer 131 may be formed through a photolithography process using second and third masks.

7A to 7C, after depositing first and second metal layers on the gate insulating layer 120 including the semiconductor pattern 130 and the second protective layer 131 by sputtering, a fourth The fourth and fifth metal patterns 141 and 142 are formed through a photolithography process using a mask.

The fourth and fifth metal patterns 141 and 142 may be formed on the semiconductor pattern 130 corresponding to the gate electrode 110, and may be formed in an area corresponding to the data line and the data pad.

Although not shown in detail in the drawing, in the photolithography process using the fourth mask, a photoresist as a photosensitive material is formed on the deposited first and second metal layers, and then a mask having a transmissive region and a non-transmissive region is used. The exposure and development processes are performed to form a photoresist pattern.

Next, the metal film is etched using the photoresist pattern as a mask to form fourth and fifth metal patterns 141 and 142.

The fourth metal pattern 141 may be formed of any one of tantalum (Ta), titanium (Ti), chromium (Cr), molybdenum (Mo), tungsten (W), and titanium molybdenum (TiMo), or may be combined with at least one. It may be made of an alloy. Preferably, the titanium molybdenum (TiMo) may be used as the first metal pattern 141.

8A through 8C, a sixth metal pattern 143 is formed using an electroless plating method using the fourth and fifth metal patterns 141 and 142 as seed layers.

The sixth metal pattern 143 may be formed to completely surround the fifth metal pattern 142 so as to be closed from the outside.

That is, in the present invention, the sixth metal pattern 143 is formed to form the source / drain electrodes 140a and 140b, the data line DL, and the lower data pad electrode 170.

9A through 9C, a first passivation layer may be formed on the gate insulating layer 120 including the source / drain electrodes 140a and 140b, the data line DL, and the lower data pad electrode 170. 121 is deposited, and first to third contact holes C1, C2, and C3 are formed through a photolithography process using a fifth mask.

The first protective layer 121 may be made of silicon oxide (SiO 2).

The first contact hole C1 is formed to expose the drain electrode 140b.

The second contact hole C2 is formed to expose the lower gate pad electrode 160.

The third contact hole C3 is formed to expose the lower data pad electrode 170.

10A to 10C, a transparent metal film is deposited on the first passivation layer 121, and a pixel electrode 150, an upper gate pad electrode 161, and a photolithography process using a sixth mask. The upper data pad electrode 171 is formed.

The pixel electrode 150, the gate pad electrode 161, and the upper data pad electrode 171 may be formed of any one of ITO, ZnO, and IZO.

In the above description, the opaque common electrode 152 is formed on the gate insulating layer 120 and the first passivation layer 121, and the thin film transistor substrate manufactured by using a total of six masks is limited, but not limited thereto. In addition, the method and material of forming the common electrode 152 may be changed as many times, and the number of mask processes may be changed.

In the display device according to the exemplary embodiment, the second and fifth metal patterns 112 and 142 made of copper (Cu) are formed by the third and sixth metal patterns 113 and 143 made of nickel (Ni). By closing, the gate insulating layer 120 is formed in a single layer, which simplifies the process. That is, the gate insulating layer 120 of the present invention omits the silicon nitride (SiNx) of the general gate insulating layer of the multi-layer structure to omit the dry etching process for forming the first to third contact holes (C1, C2, C3). This simplifies the manufacturing process.

The thin film transistor according to the exemplary embodiment of the present invention described above has a bottom gate structure.

11 is a cross-sectional view illustrating a thin film transistor region of a thin film transistor substrate according to another exemplary embodiment of the present invention.

As illustrated in FIG. 11, a thin film transistor of a thin film transistor substrate according to another exemplary embodiment has a top gate structure.

A buffer layer 201 and a gate insulating layer 220 are formed on the transparent substrate 200, the gate electrode 210 branched from the gate line on the gate insulating layer 220, and the gate insulating layer 220. An interlayer insulating layer 221 is formed on the source electrode 240a and the drain electrode 240b formed on the interlayer insulating layer 221 around the gate electrode 210, the gate insulating layer 220, and The active pattern 230 forms a channel between the source electrode 240a and the drain electrode 240b through a contact hole formed in the interlayer insulating layer 221.

The active pattern 230 is formed on the transparent substrate 200 with the buffer layer 201 interposed therebetween.

The gate electrode 210 overlaps the channel region 231 of the active pattern 230 with the gate insulating layer 220 therebetween.

The gate insulating layer 220 may be formed of silicon oxide (SiO 2).

Each of the source electrode 240a and the drain electrode 240b is in contact with the source region 232 and the drain region 233 into which the impurities of the active pattern 230 are injected by the contact hole, respectively.

The planarization layer 223 is formed on the interlayer insulating layer 221.

An electrode pattern 250 of a transparent conductive material is formed on the flat layer 223.

The electrode pattern 250 is electrically connected to the drain electrode 240b through a contact hole penetrating the flat layer 223.

According to another exemplary embodiment, the gate electrode 210 may include first to third metal patterns 211, 212, and 213, and the source / drain electrodes 240a and 240b may include fourth to sixth metals. Patterns 241, 242, and 243.

The first and fourth metal patterns 211 and 241 may be formed of any one of tantalum (Ta), titanium (Ti), chromium (Cr), molybdenum (Mo), tungsten (W), and titanium molybdenum (TiMo). It may be made of at least one bonded alloy. Preferably, the titanium molybdenum (TiMo) may be used as the first metal patterns 211 and 241.

The second and fifth metal patterns 212 and 242 may be made of copper (Cu) or an alloy including copper.

The third and sixth metal patterns 213 and 243 may be made of nickel (Ni) or an alloy containing nickel.

The first and second metal patterns 211, 212, 241, and 242 may be sequentially deposited through a sputtering process and a photolithography process using a mask.

The third and sixth metal patterns 213 and 243 may be formed using the electroless plating method using the first and second metal patterns 211, 212, 241 and 242 as seed layers. Can be formed.

Accordingly, the second and fourth metal patterns 212 and 242 are closed from the outside by the third and sixth metal patterns 213 and 243.

In the display device according to the exemplary embodiment, the second and fifth metal patterns 212 and 242 made of copper (Cu) are formed by the third and sixth metal patterns 213 and 243 made of nickel (Ni). By closing, the gate insulating layer 220 is formed in a single layer, which simplifies the process. That is, the gate insulating layer 220 of the present invention can simplify the manufacturing process by omitting the dry etching process for forming contact holes by omitting silicon nitride (SiNx) of the general gate insulating layer having a multilayer structure.

In addition, according to the present invention, the second and fifth metal patterns 212 and 242 made of copper (Cu) are closed by the third and sixth metal patterns 213 and 243 made of nickel (Ni). By preventing the contamination of the active pattern 230 by), it has the advantage of improving the performance and reliability of the thin film transistor.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

110 and 210: gate electrodes 111 and 211: first metal pattern
112, 212: second metal pattern 113, 213: third metal pattern
140a, 240a: source electrode 140b, 240b: drain electrode
141 and 241: fourth metal pattern 142 and 242: fifth metal pattern
143 and 243: sixth metal pattern

Claims

A pixel region defined by crossing a plurality of gate lines and data lines;
A gate electrode branched from the plurality of gate lines;
A single gate insulating layer formed on the gate electrode; And
A source / drain electrode formed on the gate insulating layer;
The gate electrode includes first to third metal patterns, the first and second metal patterns are sequentially deposited, and the third metal pattern is electroless using the first and second metal patterns as seed layers. A display device having a structure in which the second metal pattern including copper (Cu) is covered to be closed from the outside by a plating method.

The method according to claim 1,
And the source / drain electrodes have the same structure as the gate electrode.

The method of claim 2,
Each of the source / drain electrodes includes fourth to sixth metal patterns, and the fourth and fifth metal patterns are sequentially deposited, and the sixth metal pattern is used as the seed layer. And a structure in which the fifth metal pattern including copper (Cu) is covered to be closed from the outside by an electroless plating method.

The method of claim 3,
The sixth metal pattern is made of nickel (Ni) or an alloy containing nickel.

The method of claim 3,
The fourth metal pattern is formed of any one of tantalum (Ta), titanium (Ti), chromium (Cr), molybdenum (Mo), tungsten (W), and titanium molybdenum (TiMo), or a display made of at least one bonded alloy. Device.

The method according to claim 1,
The third metal pattern is made of nickel (Ni) or an alloy containing nickel.

The method according to claim 1,
The first metal pattern is formed of any one of tantalum (Ta), titanium (Ti), chromium (Cr), molybdenum (Mo), tungsten (W), or titanium molybdenum (TiMo), or a display made of at least one bonded alloy. Device.

The method according to claim 1,
And the gate insulating layer is formed of silicon oxide (SiO 2).

The first and second metal patterns are formed by laminating a photolithography process using a mask on a transparent substrate, and copper (Cu) is formed by electroless plating using the first and second metal patterns as seed layers. Forming a gate electrode and a gate line including forming a third metal pattern covering the second metal pattern to be closed from the outside;
Forming a single gate insulating layer on the transparent substrate including the gate electrode and the gate line;
Forming a semiconductor pattern on the gate insulating layer; And
And forming a source / drain electrode and a data line on the semiconductor pattern and the gate insulating layer.

10. The method of claim 9,
And the source / drain electrodes have the same structure as the gate electrode.

The method of claim 10,
Each of the source / drain electrodes includes fourth to sixth metal patterns, and the fourth and fifth metal patterns are sequentially deposited, and the sixth metal pattern is used as the seed layer. And cover the fifth metal pattern including copper (Cu) to be closed from the outside by an electroless plating method.

12. The method of claim 11,
And the sixth metal pattern is made of nickel (Ni) or an alloy containing nickel.

12. The method of claim 11,
The fourth metal pattern is formed of any one of tantalum (Ta), titanium (Ti), chromium (Cr), molybdenum (Mo), tungsten (W), and titanium molybdenum (TiMo), or a display made of at least one bonded alloy. Method of manufacturing the device.

10. The method of claim 9,
And the third metal pattern is made of nickel (Ni) or an alloy containing nickel.

10. The method of claim 9,
The first metal pattern is formed of any one of tantalum (Ta), titanium (Ti), chromium (Cr), molybdenum (Mo), tungsten (W), or titanium molybdenum (TiMo), or a display made of at least one bonded alloy. Method of manufacturing the device.

10. The method of claim 9,
And the gate insulating layer is formed of silicon oxide (SiO 2).