JP2007033786A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a display device from decreasing in yield or reliability owing to a defect in contacting of a contact plug connecting mutually different wiring layers to each other in a peripheral driving circuit area which is narrower in wiring width than a display area of the display device. <P>SOLUTION: The film thickness of a second inter-layer insulating film 10 in the peripheral driving circuit area 3 which is narrower in wiring width than the display area 2 is made less than the film thickness of a first inter-layer insulating film 9 in the display area 2, and then the aspect ratio of a contact hole in the peripheral driving circuit area 3 can be made close to the aspect ratio in the display area 2, so that a source electrode 13 and a drain electrode 14 formed in the contact hole by a sputtering method are easily connected to a polycrystalline silicon film 6. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device.

  In recent years, in a liquid crystal display device or an organic EL display device, a plurality of pixel thin film transistors (hereinafter referred to as TFTs) are integrated in a display region using a polycrystalline silicon on a glass substrate, and a peripheral drive circuit is integrated in a peripheral region. System On Glass (hereinafter, referred to as SOG) technology that can reduce costs by reducing the number of external parts and can be miniaturized to form modules has attracted attention.

  In general, in a display device using SOG, the pixel TFTs in the display area and the TFTs constituting the peripheral driver circuit have different uses, and therefore require different operating characteristics and miniaturization of TFTs.

  On the other hand, recently, a technique has been disclosed that can obtain optimum TFT operating characteristics by injecting impurities of appropriate concentrations into the active layers of the pixel TFT and the TFT constituting the peripheral drive circuit. (For example, refer to Patent Document 1).

  On the other hand, in order to realize further high integration while maintaining high definition and a narrow frame, it is particularly necessary to make the TFTs and wirings of the peripheral drive circuit smaller than the display area. For this reason, in the peripheral drive circuit, the proportion of the TFT and the wiring increases, and accordingly, the number of contact plugs connecting the upper wiring layer and the lower wiring layer increases.

  Next, the contact plug will be described with reference to FIGS.

  13 and 14 are cross-sectional views showing the process of forming the contact plug. First, as shown in FIG. 13, a contact hole 104 is provided in an interlayer film 103 on a lower wiring layer 102 formed on an insulating substrate 101.

Next, as shown in FIG. 14, a metal film is formed in the contact hole 104 and on the interlayer film 103 by sputtering, which is physical vapor deposition (hereinafter referred to as PVD), and the contact plug 105 and An upper wiring layer 106 is formed.
JP 2001-7343 A

  However, in the peripheral drive circuit region that is made finer than the display region, the hole diameter of the contact hole is reduced because the wiring width is narrow. For this reason, the aspect ratio of the contact hole defined by the ratio between the hole diameter and the depth of the contact hole is lowered.

  Generally, when a metal film is formed using a sputtering method in a contact hole having a low aspect ratio, the film is formed inside the contact hole with respect to the film thickness of the upper wiring layer formed on the interlayer film. The contact plug may be very thin or may not be formed. For this reason, contact failure occurs in the contact plug connecting the upper wiring layer and the lower wiring layer, and the yield and reliability of the display device are reduced. There is a problem of lowering.

  The present invention has been made in view of the above, and in a peripheral drive circuit region where the wiring width is narrower than the display region in the display device, the yield and reliability decrease due to contact failure of contact plugs connecting different wiring layers. The purpose is to prevent.

  In the display device according to the present invention, a lower wiring layer and an upper layer are formed in a first contact hole provided in a first interlayer insulating film disposed between a lower wiring layer and an upper wiring layer on an insulating substrate. The display area in which the first contact plug for connecting the wiring layer is embedded, and the periphery of the display area, the wiring width is set narrower than the display area, and the first contact plug is disposed between the lower wiring layer and the upper wiring layer. And a peripheral circuit region having a peripheral circuit in which a second contact plug for connecting the lower wiring layer and the upper wiring layer is embedded in a second contact hole provided in the second interlayer insulating film. An apparatus is characterized in that the film thickness of the second interlayer insulating film is smaller than the film thickness of the first interlayer insulating film.

  In the present invention, the thickness of the second interlayer insulating film in the peripheral circuit region having a wiring width narrower than that of the display region is made smaller than the thickness of the first interlayer insulating film in the display region. The aspect ratio of the second contact hole in the circuit region can be made close to the aspect ratio of the first contact hole in the display region, and the second contact plug formed by the PVD method is connected to the upper wiring layer and the lower wiring layer. Makes it easier to connect.

  In the above display device, the thickness of the second interlayer insulating film is reduced so that the aspect ratio of the second contact hole is the same as the aspect ratio of the first contact hole.

  In the present invention, the second interlayer insulating film is made thin so that the aspect ratio of the contact hole in the peripheral circuit region is the same as the aspect ratio of the contact hole in the display region. The contact plug makes it easier to connect the upper wiring layer and the lower wiring layer.

  In the display region, the upper wiring layer and the upper wiring layer are disposed in the third contact hole provided in the third interlayer insulating film disposed between the upper wiring layer and the upper wiring layer. A third contact plug to be connected is buried, and in the peripheral circuit region, a wiring width is set narrower than that of the display region, and a fourth interlayer insulating film disposed between the upper wiring layer and the upper wiring layer. A fourth contact plug for connecting the upper wiring layer and a further upper wiring layer is embedded in the fourth contact hole provided in the fourth contact hole, and the fourth interlayer contact hole has a thickness greater than that of the third interlayer insulating film. The insulating film is thin.

  In the present invention, the thickness of the fourth interlayer insulating film in the peripheral circuit region having a wiring width narrower than that of the display region is made smaller than the thickness of the third interlayer insulating film in the display region. The aspect ratio of the fourth contact hole in the circuit region can be set to an appropriate value, and the fourth contact plug formed by the PVD method can easily connect different wiring layers.

  In the above display device, the thickness of the fourth interlayer insulating film is reduced so that the aspect ratio of the fourth contact hole is the same as the aspect ratio of the third contact hole.

  In the present invention, the thickness of the fourth interlayer insulating film is reduced so that the aspect ratio of the contact hole in the peripheral circuit region is the same as the aspect ratio of the contact hole in the display region. The contact plug makes it easier to connect the upper wiring layer and the lower wiring layer.

  According to the display device of the present invention, it is possible to prevent a decrease in yield and reliability due to contact failure of contact plugs connecting different wiring layers in a peripheral circuit region having a wiring width narrower than that of the display region.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a plan view of the display panel of the liquid crystal display device according to the present embodiment as viewed from above. As shown in the figure, the display panel 1 has a display area 2 and a peripheral drive circuit area 3.

  The display area 2 has a plurality of pixel TFTs for displaying an image. The peripheral drive circuit region 3 is located around the display region 2 and has a peripheral drive circuit composed of TFTs that are drive circuit elements. The pixel TFT and the peripheral drive circuit are integrally formed on the same glass substrate.

  Here, the peripheral driver circuit is a circuit group necessary for performing liquid crystal display such as a scanning line driver circuit, a signal line driver circuit, an interface circuit, a timing generator, a reference driver, a counter electrode driver, a DC / DC converter, and a memory. Show.

  Next, the structure of the display region and the peripheral driver circuit region included in the display panel of the present invention will be described with reference to the cross-sectional view of FIG. In the peripheral drive circuit region 3, finer design rules are used than in the display region 2. For example, the contact provided in the peripheral drive circuit region 3 with respect to the hole diameter of 4 μm of the contact hole provided in the display region 2. The hole diameter is 2 μm.

  FIG. 2 is a partial cross-sectional view of the display area 2 and the peripheral drive circuit area 3 of the display panel 1 of FIG. As shown in the figure, the display region 2 is further formed on an insulating substrate 4, an undercoat film 5 formed on the insulating substrate 4, and a polycrystalline silicon film 6 formed on the undercoat film 5. The TFT includes a gate insulating film 7 formed and a gate electrode 8 formed on the gate insulating film 7. Here, in the display panel 1, a description of constituent members such as a counter substrate disposed opposite to the insulating substrate 4 and a liquid crystal layer disposed between both substrates is omitted.

  The TFT further includes a first interlayer insulating film 9 formed on the entire surface including the gate insulating film 7 and the gate electrode 8, and a source region through a contact hole provided in the first interlayer insulating film 9 and the gate insulating film 7. A source electrode 13 formed so as to be connected to the drain region and a drain electrode 14 formed so as to be connected to the drain region. Here, the film thickness t1 of the first interlayer insulating film 9 is set to, for example, 800 nm.

  That is, the source electrode 13 and the drain electrode 14 connected to the polycrystalline silicon film 6 are buried as contact plugs in the contact hole provided in the first interlayer insulating film 9 having a film thickness t1 of 800 nm.

  Further, the TFT is connected to the drain electrode 14 through a third interlayer insulating film 11 formed on the entire surface including the source electrode 13 and the drain electrode 14 and a contact hole provided in the third interlayer insulating film 11. And a pixel electrode 15 formed. Here again, the film thickness t3 of the third interlayer insulating film 11 is set to 800 nm.

  That is, the pixel electrode 15 connected to the drain electrode 14 is buried as a contact plug in the contact hole provided in the third interlayer insulating film 11 having a film thickness t3 of 800 nm.

  The peripheral drive circuit region 3 includes an insulating substrate 4, an undercoat film 5 formed on the insulating substrate 4, and a gate insulation further formed on the polycrystalline silicon film 6 formed on the undercoat film 5. The TFT includes a film 7 and a gate electrode 8 formed on the gate insulating film 7. In this case, in the display panel 1 as well, a description of constituent members such as a counter substrate disposed opposite to the insulating substrate 4 and a liquid crystal layer disposed between both substrates is omitted.

  The TFT further includes a source region through a second interlayer insulating film 10 formed on the entire surface including the gate insulating film 7 and the gate electrode 8 and a contact hole provided in the second interlayer insulating film 10 and the gate insulating film 7. A source electrode 13 formed so as to be connected to the drain region and a drain electrode 14 formed so as to be connected to the drain region. Here, for example, a part of the insulating film is removed by dry etching, so that the film thickness t2 of the second interlayer insulating film 10 is set to 500 nm.

  That is, the source electrode 13 and the drain electrode 14 connected to the polycrystalline silicon film 6 are buried as contact plugs in the contact hole provided in the second interlayer insulating film 10 having a thickness t2 of 500 nm.

  Further, the TFT connects the fourth interlayer insulating film 12 formed on the entire surface including the source electrode 13 and the drain electrode 14 and the drain electrode 14 through a contact hole provided in the fourth interlayer insulating film 12. And a further upper wiring layer 17. Also here, for example, a part of the insulating film is removed by dry etching, so that the film thickness t4 of the fourth interlayer insulating film 12 is set to 500 nm.

  That is, an upper wiring layer 17 connected to the drain electrode 14 is buried as a contact plug in the contact hole provided in the fourth interlayer insulating film 12 having a thickness t4 of 500 nm.

  Next, the effect of the present invention will be described. First, the aspect ratio of the contact hole in each region is calculated. The aspect ratio R is expressed by the following equation (1) using the hole diameter φ and the hole depth d.

R = φ / d (1)
Here, the depth d of the hole is substantially equal to the film thickness t of the interlayer insulating film in which the hole is provided.

  Since the hole diameter φA of the contact hole in the display region 2 is 4 μm, the film thickness t1 of the first interlayer insulating film 9 and the film thickness t3 of the third interlayer insulating film 11 are 800 nm, the aspect ratio is 5 (= 4 μm / 800 nm). It becomes.

  Since the hole diameter φB of the contact hole in the peripheral drive circuit region 3 is 2 μm and the film thickness t2 of the second interlayer insulating film 10 or the film thickness t4 of the fourth interlayer insulating film 12 is 500 nm, the aspect ratio is obtained from the equation (1). 4 (= 2 μm / 500 nm).

  Thus, by making the film thickness of the interlayer insulating film in the peripheral drive circuit region 3 smaller than the film thickness of the interlayer insulating film in the display region 2, the aspect ratio of the contact hole in the peripheral drive circuit region 3 can be reduced. 2 aspect ratio.

  FIG. 3 is an enlarged cross-sectional view of the vicinity of the drain electrode 14 in the peripheral drive circuit region 3 in the cross-sectional view of FIG. As shown in the figure, the drain electrode 14 includes a main wiring 25 and upper and lower barrier metals 26. For the main wiring 25, a metal material such as Al or Cu or an alloy thereof is used. The upper and lower barrier metals 26 improve the adhesion between the metal material constituting the main wiring 25 and the first interlayer insulating film 9 and prevent the metal material from diffusing into the first interlayer insulating film 9.

  The barrier metal 26 has a higher resistance value than the main wiring 25 and needs to be as thin as possible. Therefore, for example, the film thickness is desirably set between 20 and 100 nm.

  In the drawing, the drain electrode 14 in the contact hole functions as a contact plug for connecting the drain electrode 14 on the first interlayer insulating film 9 and the polycrystalline silicon film 6. In the peripheral drive circuit region 3, since the aspect ratio of the contact hole is improved, the drain electrode 14 which is a metal film formed by sputtering is easily connected to the polycrystalline silicon film 6 inside the contact hole. This also has the same effect in the source electrode 13 which is another contact plug, and also in the upper wiring layer 17.

  Therefore, according to the present embodiment, the film thickness of the second interlayer insulating film 10 in the peripheral drive circuit region 3 having a wiring width narrower than that of the display region 2 is set to the film thickness of the first interlayer insulating film 9 in the display region 2. By making the thickness smaller than the thickness, the aspect ratio of the contact hole in the peripheral drive circuit region 3 can be brought close to the aspect ratio in the display region 2, and the source electrode 13 and the drain electrode 14 formed inside the contact hole by the sputtering method. However, it becomes easy to connect to the polycrystalline silicon film 6.

  Similarly, the thickness of the fourth interlayer insulating film 12 in the peripheral drive circuit region 3 is made thinner than the thickness of the third interlayer insulating film 11 in the display region 2, thereby further forming the inside of the contact hole. The upper wiring layer 17 is easily connected to the upper wiring layer 16.

  In the present embodiment, the thickness of the second interlayer insulating film 10 and the fourth interlayer insulating film 12 in the peripheral drive circuit region is set to 500 nm, so that the aspect ratio of the contact hole (4 = 2 μm / 500 nm). ) Is set to be close to the aspect ratio of the contact hole in the display region 2 (5 = 4 μm / 800 nm), but is not limited thereto.

  For example, the film thickness of the second interlayer insulating film 10 is adjusted by adjusting the dry etching processing time in the peripheral drive circuit region so that the contact holes have the same aspect ratio in the display region and the peripheral drive circuit region. You may set to 400 nm. As a result, the source electrode 13 and the drain electrode 14 formed in the contact hole are more easily connected to the polycrystalline silicon film 6.

  Similarly, by setting the thickness of the fourth interlayer insulating film 12 to 400 nm, the upper wiring layer 17 formed inside the contact hole can be more easily connected to the upper wiring layer 16.

  In the present embodiment, each of the display region 2 and the peripheral drive circuit region 3 has a multilayer wiring structure having two layers of an interlayer insulating film and a wiring layer. However, the present invention is not limited to this. A multilayer wiring structure having a further increased number of interlayer insulating films and wiring layers and having two or more layers of three or more interlayer insulating films and wiring layers may be used.

  In the present embodiment, the film thickness of the interlayer insulating film is set to an arbitrary film thickness depending on the processing time of dry etching, but is not limited to this. As a first example, part of the laminated film may be removed by wet etching instead of dry etching.

  As a second example, the interlayer insulating film may have a laminated structure, and the film thickness may be set by selectively removing only the upper interlayer insulating film during dry etching. Usually, the etching rate of dry etching differs depending on the etching conditions (gas type, pressure, power, etc.) and the film to be etched (for example, silicon oxide film, silicon nitride film).

  FIG. 4 is a cross-sectional view illustrating a method for adjusting the film thickness when the interlayer insulating film has a laminated structure. As shown in the figure, an etching condition or film having a high etching rate is used as the upper interlayer insulating film 23, and an etching condition or film having a low etching rate is used as the lower interlayer insulating film 24. Over-etching is easily performed when the insulating film 23 is removed. For this reason, since it is possible to reduce variations in processing time and in-plane distribution during etching, it is possible to easily adjust the film thickness of the interlayer insulating film.

  As a third example, an interlayer insulating film having a thickness of 300 nm may be formed first only in the display region, and then an interlayer insulating film having a thickness of 500 nm may be formed on the entire surface of the substrate.

  In the present embodiment, the contact plug is formed into a thin film by a sputtering method. However, the present invention is not limited to this as long as it is a thin film forming method using the PVD method. However, the same effect can be obtained by applying the present invention.

  In this embodiment mode, the display device is a liquid crystal display device. However, the present invention is not limited to this, and a similar effect can be obtained by applying the present invention to a display device using an organic EL. be able to.

  Next, the manufacturing process of the display panel of the display device according to this embodiment will be described with reference to the drawings. First, a thin film is formed on an insulating substrate using chemical vapor deposition (hereinafter referred to as CVD). FIG. 5 is a first process diagram for explaining the manufacturing method of the display device. As shown in the figure, an undercoat film 5 is formed on an insulating substrate 4 made of low melting point glass or the like. The undercoat film 5 is, for example, a laminated film of a silicon nitride film (insulating substrate side) having a thickness of 50 nm and a silicon oxide film having a thickness of 100 nm, a silicon nitride film, a silicon oxide film, or the like. These films can be continuously formed using a plasma CVD method, a low pressure chemical vapor deposition method (hereinafter referred to as an LPCVD method), or the like. Next, an amorphous silicon film 18 having a thickness of 50 nm is formed on the undercoat film 5 by using a plasma CVD method, an LPCVD method, or the like.

  Next, a TFT is formed. FIG. 6 is a second process diagram. As shown in the figure, the amorphous silicon film 18 formed in the first step is subjected to an annealing process such as an excimer laser annealing method (hereinafter referred to as ELA) to crystallize the polycrystalline silicon film 6. Reform. Thereafter, the polycrystalline silicon film 6 is etched and patterned.

  Next, a gate insulating film 7 made of a silicon oxide film and having a thickness of 100 nm is formed on the entire surface of the insulating substrate 4. Here, the gate insulating film 7 is not limited to the silicon oxide film, but may be a silicon nitride film or a laminated film thereof. Further, if necessary, an impurity such as phosphorus (P) or boron (B) is implanted into a part of the polycrystalline silicon film 6 using a resist by photolithography as a mask, using an ion implantation method or the like.

  Next, a gate electrode 8 made of MoW having a thickness of 300 nm is formed. Here, the material of the gate electrode 8 is not limited to MoW, and Al, Ti, W, Co, Mo, Cr, doped polycrystalline silicon, or an alloy thereof may be used.

  Next, by using an ion implantation method or the like, impurities such as phosphorus or boron are implanted into a part of the polycrystalline silicon film 6 by using the resist by photolithography or the gate electrode 8 as a mask. Thereby, P-type and N-type TFTs are formed.

  Here, activation processing of dopants (phosphorus and boron in this case) implanted into the polycrystalline silicon film 6 is performed. The activation treatment is performed by heat treatment at 400 to 600 ° C. using a furnace or lamp annealing. Thereafter, hydrogen plasma treatment is performed, and the diffused hydrogen is supplied to the polycrystalline silicon film 6.

  Next, interlayer insulating films having different thicknesses are formed in the display region and the peripheral driver circuit region by etching. FIG. 7 is a third process diagram. As shown in the figure, an insulating film having a thickness of 800 nm is formed on the entire surface of the substrate including the gate electrode 8 and the gate insulating film 7. The insulating film is, for example, a silicon oxide film or a silicon nitride film. As a formation method, for example, a coating method such as a plasma CVD method, an LPCVD method, or a spin on glass (hereinafter referred to as SOG) is used.

  Next, a resist is formed on the insulating film in the display region 2 and dry etching is performed. Note that the dry etching process does not remove all of the insulating film, but half-etches to remove a part of the interlayer film (for example, a film thickness of 300 nm). The used resist 19 is removed by ashing after dry etching. In this manner, the film thickness of the second interlayer insulating film 10 in the peripheral drive circuit region 3 is made thinner than the film thickness of the first interlayer insulating film 9 in the display region 2. Here, the shape of the boundary region between the display region 2 and the peripheral drive circuit region 3 is, for example, stepped, and has a step difference of 300 nm in film thickness difference between the first interlayer insulating film 9 and the second interlayer insulating film 10.

  Next, as shown in the fourth step diagram of FIG. 8, a first contact hole 20 is provided in the first interlayer insulating film 9 and the gate insulating film 7, and the second interlayer insulating film 10 and the gate insulating film 7 are provided. A second contact hole 21 is provided.

  Next, as shown in the fifth process diagram of FIG. 9, on the first interlayer insulating film 9 and in the first contact hole 20, on the second interlayer insulating film 10 and in the second contact hole 21. The metal film 22 made of the same material is simultaneously formed by sputtering.

  Next, as shown in the sixth step diagram of FIG. 10, the metal film 22 is processed by using, for example, dry etching, and the source electrode 13, the drain electrode 14, and other upper wiring layers 16 are formed.

  Next, as shown in the seventh step diagram of FIG. 11, a third interlayer insulating film 11 and a fourth interlayer insulating film 12 are formed by the same manufacturing method as the steps described in FIGS. Further, the metal film formed by the sputtering method is processed to form the pixel electrode 15 and the upper wiring layer 17. Here, a transparent conductive film such as ITO or IZO is used for the pixel electrode 15.

  In addition, although the shape of the boundary between the display region and the peripheral drive circuit region formed in the manufacturing process of the display device is a staircase shape, it is not limited to this. For example, the shape of the boundary between both regions may be inclined.

  FIG. 12 is a cross-sectional view of the vicinity of the boundary between the display area and the peripheral drive circuit area. As shown in the figure, the interlayer insulating film 27 is inclined at the boundary surface between the display region 2 and the peripheral drive circuit region 3. Thereby, the wiring 28 on the interlayer insulating film 27 can be smoothly connected between the two regions without being cut off by a step. As for the method of inclining, for example, a resist having an inclined end is adopted by changing resist formation conditions (for example, resist material, exposure conditions, baking conditions) when forming the interlayer insulating film 27. Etching is performed.

It is the top view which looked at the display panel of the liquid crystal display device which concerns on this Embodiment from the top. FIG. 2 is a partial cross-sectional view of a display area and a peripheral drive circuit area of the display panel of FIG. 1. FIG. 2 is an enlarged cross-sectional view of the vicinity of a drain electrode in a peripheral drive circuit region in the cross-sectional view of FIG. 1. It is sectional drawing which shows the method of adjusting the film thickness of the interlayer insulation film made into the laminated structure. FIG. 4 is a first process diagram illustrating a method for manufacturing the display panel of FIG. 1. FIG. 10 is a second process diagram illustrating the method for manufacturing the display panel of FIG. 1. FIG. 10 is a third process diagram illustrating the method for manufacturing the display panel in FIG. 1. FIG. 10 is a fourth process diagram illustrating the method for manufacturing the display panel in FIG. 1. FIG. 10 is a fifth process diagram illustrating the method for manufacturing the display panel in FIG. 1. FIG. 10 is a sixth process diagram illustrating the method for manufacturing the display panel in FIG. 1. FIG. 10 is a seventh process diagram for explaining the method for manufacturing the display panel in FIG. 1; It is sectional drawing of the boundary vicinity of a display area and a periphery drive circuit area | region. It is sectional drawing which shows the 1st formation process of a contact plug. It is sectional drawing which shows the 2nd formation process of a contact plug.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Display panel 2 ... Display area 3 ... Peripheral drive circuit area 4 ... Insulating substrate 5 ... Undercoat film 6 ... Polycrystalline silicon film 7 ... Gate insulating film 8 ... Gate electrode 9 ... First interlayer insulating film 10 ... First Two interlayer insulating films 11 ... third interlayer insulating film 12 ... fourth interlayer insulating film 13 ... source electrode 14 ... drain electrode 15 ... pixel electrode 16 ... upper wiring layer 17 in the same layer as the source and drain electrodes ... Upper wiring layer 18 ... amorphous silicon film 19 ... resist 20 ... first contact hole 21 ... second contact hole 22 ... metal film 23 ... upper interlayer insulating film 24 ... lower interlayer insulating film 25 ... main wiring 26 ... Barrier metal 27 ... Interlayer insulating film 28 ... Wiring 101 ... Insulating substrate 102 ... Lower layer wiring layer 103 ... Interlayer film 104 ... Contact hole 105 ... Contact plug 106 ... Upper layer wiring layer A: Hole diameter φB of the contact hole in the display area ... Hole diameter t1 of the contact hole in the peripheral drive circuit area ... Film thickness t2 of the first interlayer insulating film ... Film thickness t3 of the second interlayer insulating film ... Third layer Insulating film thickness t4... Fourth interlayer insulating film thickness

Claims (4)

The lower wiring layer and the upper wiring layer are connected to each other inside the first contact hole provided in the first interlayer insulating film disposed between the lower wiring layer and the upper wiring layer on the insulating substrate. A display area in which the first contact plug is embedded;
In the periphery of the display area, the wiring width is set narrower than the display area, and in the second contact hole provided in the second interlayer insulating film disposed between the lower wiring layer and the upper wiring layer, A peripheral circuit region including a peripheral circuit in which a second contact plug for connecting the lower wiring layer and the upper wiring layer is embedded;
The display device, wherein the thickness of the second interlayer insulating film is smaller than the thickness of the first interlayer insulating film.   The film thickness of the second interlayer insulating film is reduced so that the aspect ratio of the second contact hole is the same as the aspect ratio of the first contact hole. Display device. In the display region, the upper wiring layer and the upper wiring are provided in a third contact hole provided in a third interlayer insulating film disposed between the upper wiring layer and the upper wiring layer. A third contact plug connecting the layers is embedded;
In the peripheral circuit region, a wiring width is set narrower than that of the display region, and a fourth contact hole provided in a fourth interlayer insulating film disposed between the upper wiring layer and a further upper wiring layer. A fourth contact plug for connecting the upper wiring layer and the upper wiring layer is embedded therein,
3. The display device according to claim 1, wherein the thickness of the fourth interlayer insulating film is smaller than the thickness of the third interlayer insulating film.   The film thickness of the fourth interlayer insulating film is reduced so that the aspect ratio of the fourth contact hole is the same as the aspect ratio of the third contact hole. Display device.

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