JP2009252887A - Thin-film transistor, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily ensure conduction between a high-density area 21 and a source electrode 17 and a drain electrode 18 by eliminating a contact hole 23 requiring a large area in a transistor. <P>SOLUTION: The thin-film transistor includes a semiconductor layer 12, a gate electrode layer 13, an gate electrode 14, a source electrode 17, and a drain electrode 18 on a substrate 10. In this case, the gate electrode 14 is covered with an insulation layer, and the source electrode 17 and the drain electrode 18 are in contact with the semiconductor layer 12. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly to a thin film transistor having no contact hole between a source / drain electrode and a semiconductor layer and a method for manufacturing the same.

  Currently, a very large number of displays are used in multimedia devices, mobile phones, and communication devices. Further, common demands for displays from these electronic devices are high performance and high definition.

  For this reason, in a display using a thin film transistor (hereinafter referred to as TFT), there has been a demand for higher performance of the TFT constituting the pixel portion.

  Recently, a display has been developed in which polysilicon having an electron mobility of about 1 to 2 digits higher than that of conventional amorphous silicon is used for a semiconductor layer and an external drive circuit portion is built outside the pixel portion.

  In order to satisfy these requirements, TFTs have been miniaturized, and mobility and lower voltage have been promoted.

  FIG. 10 is a schematic cross-sectional view showing the structure of a conventional thin film transistor.

  An undercoat layer 11 is formed on the insulating substrate 10, a semiconductor layer 12 is formed thereon, and a gate electrode 14 is formed via a gate insulating layer 13.

  The source electrode 17 and the drain electrode 18 are connected to a high concentration region 21 formed by ion doping the semiconductor layer 12.

  The gate electrode 14, the source electrode 17, and the drain electrode 18 have a multilayer wiring structure via the first insulating layer 15.

  FIG. 11 is a cross-sectional view illustrating a structure of a conventional thin film transistor having an LDD structure (Lightly Doped Drain structure).

  An LDD-structured thin film transistor is a structure that is used from the viewpoint of improving the resistance to device characteristic deterioration caused by hot electrons and reducing the off-leakage current flowing between the source electrode and the drain electrode (Patent Document 1).

  The manufacturing method of the LDD structure shown in FIG. 11 is disclosed in Patent Document 2.

Further, Patent Document 3 discloses a technique for producing a thin film transistor having the LDD structure shown in FIG.
JP 58-105574 A JP 05-275450 A Japanese Patent Laid-Open No. 2001-111058

  Each of the thin film transistors described above takes the following manufacturing process.

  That is, after the semiconductor layer 12, the gate insulating layer 13, and the gate electrode 14 are formed, the first insulating layer 15 that becomes an interlayer insulating film is formed. Thereafter, contact holes 23 are formed in the first insulating layer 15 by a photolithography process and an etching process.

  Then, by burying the contact hole 23 with a metal layer, the source electrode 17 and the drain electrode 18 electrically connected to the high concentration region 21 in the semiconductor layer 12 are formed.

  Here, in order to ensure electrical connection between the high-concentration region 21 and the source electrode 17 and the drain electrode 18, the contact hole 23 needs to perform mask alignment with high accuracy. Normally, the design is performed with a sufficient margin in consideration of the mask alignment accuracy.

  FIG. 13 shows a conventional thin film transistor.

  The high-concentration region 21 in the semiconductor layer 12 that is electrically connected to the source electrode 17 and the drain electrode 18 is designed with a size 24 larger than the contact hole 23 in consideration of mask alignment accuracy.

  Since the size of the minimum pattern that can be created in the exposure process is the same in the process of forming the gate electrode 14 and the contact hole 23, the occupied area in the transistor of the high-concentration region 21 that needs to secure a margin for mask alignment is the gate. It is larger than the electrode 14.

  In the future miniaturization of the thin film transistor, it is important to improve the mask alignment accuracy and reduce the overall size of the thin film transistor together with the miniaturization of the gate electrode 14, the source electrode 17 and the drain electrode 18.

  However, a display, which is an application field of thin film transistors, requires exposure to a large substrate, and it is difficult to improve alignment accuracy uniformly over the entire exposure region. Moreover, even if the accuracy is improved, the mask alignment accuracy is obtained, so that the process time of the exposure process is increased, resulting in an increase in the overall cost.

  In view of the above, an object of the present invention is to eliminate the contact hole 23 which requires a large area in the transistor, and to easily ensure the conduction between the high concentration region 21 and the source electrode 17 and the drain electrode 18.

  As a means for solving the above-mentioned problems, the present invention provides a thin film transistor in which a semiconductor layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode are formed over a substrate. The structure is covered with an insulating layer, and the source electrode and the drain electrode are in contact with the semiconductor layer.

  According to the present invention, the insulating layer covering the gate electrode is formed along the gate insulating layer, the first insulating layer formed on the gate electrode, and the gate electrode and the first insulating layer. And a second insulating layer to be formed.

  The present invention also includes a step of forming a semiconductor layer, a step of forming a layer to be a gate insulating layer over the semiconductor layer, a step of forming a metal layer over the gate insulating layer, A step of forming an insulating layer on the layer; a step of patterning the metal layer and the insulating layer into the same shape to form a gate electrode and a first insulating layer; Forming a layer over the entire surface, removing the other insulating layer anisotropically, and forming a second insulating layer along the first insulating layer and the gate electrode; Patterning the layer to be the gate insulating layer using the first insulating layer and the second insulating layer as a mask to form a gate insulating layer, forming another metal layer, Forming a source electrode and a drain electrode by patterning another metal layer into a desired shape; Characterized in that it comprises a.

  The present invention also includes a step of forming a semiconductor layer, a step of forming a layer to be a gate insulating layer over the semiconductor layer, a step of forming a metal layer over the gate insulating layer, A step of forming an insulating layer on the layer; a step of patterning the metal layer and the insulating layer into the same shape to form a gate electrode and a first insulating layer; Forming a layer over the entire surface, removing the other insulating layer anisotropically, and forming a second insulating layer along the first insulating layer and the gate electrode; Patterning a layer to be the gate insulating layer using the first insulating layer and the second insulating layer as a mask to form a gate insulating layer; and forming the semiconductor layer using the first insulating layer as a mask. A step of doping ions at a high concentration, a step of forming another metal layer, A step of the source electrode and the drain electrode by patterning the layer of the genus into a desired shape, characterized in that it comprises a.

  The present invention also includes a step of forming a semiconductor layer, a step of forming a layer to be a gate insulating layer over the semiconductor layer, a step of forming a metal layer over the gate insulating layer, A step of forming an insulating layer on the layer; a step of patterning the metal layer and the insulating layer into the same shape to form a gate electrode and a first insulating layer; Forming a layer over the entire surface, removing the other insulating layer anisotropically, and forming a second insulating layer along the first insulating layer and the gate electrode; Using the first insulating layer and the second insulating layer as a mask, patterning the layer to be the gate insulating layer to form a gate insulating layer; and the first insulating layer and the second insulating layer And a step of doping ions into the semiconductor layer at a high concentration using the mask as a mask, and forming another metal layer. A step of, characterized by comprising the steps of: a source electrode and a drain electrode by patterning a layer of metal of said another into a desired shape, a.

  The present invention also includes a step of forming a semiconductor layer, a step of forming a layer to be a gate insulating layer over the semiconductor layer, a step of forming a metal layer over the gate insulating layer, Forming an insulating layer on the layer; patterning the metal layer and the insulating layer into the same shape to form a gate electrode and a first insulating layer; and the first insulating layer. A step of doping ions into the semiconductor layer at a low concentration using the layer as a mask, a step of forming another insulating layer over the entire surface, and removing the other insulating layer anisotropically, Forming a second insulating layer along the insulating layer and the gate electrode, and patterning the layer to be the gate insulating layer using the first insulating layer and the second insulating layer as a mask. And a step of forming a gate insulating layer, and the first insulating layer and the second insulating layer. A step of doping the semiconductor layer with a high concentration as a mask, a step of forming another metal layer, and patterning the other metal layer into a desired shape to form a source electrode and a drain electrode And a process.

  The present invention also includes a step of forming a semiconductor layer, a step of forming a layer to be a gate insulating layer on the semiconductor layer, a step of forming a metal layer on the gate insulating layer, Forming an insulating layer on the metal layer; patterning the metal layer and the insulating layer into the same shape to form a gate electrode and a first insulating layer; and the metal A step of forming a second insulating layer by oxidizing the side surface of the layer; and a step of forming a gate insulating layer by patterning the layer to be the gate insulating layer using the first insulating layer as a mask; A step of forming another metal layer and a step of patterning the another metal layer into a desired shape to form a source electrode and a drain electrode.

  The present invention also includes a step of forming a semiconductor layer, a step of forming a layer to be a gate insulating layer on the semiconductor layer, a step of forming a metal layer on the gate insulating layer, A step of forming an insulating layer on the metal layer; a step of patterning the insulating layer to form a first insulating layer; and the metal layer and a source or drain electrode. A step of covering a region to be connected with a resist, a step of forming a gate electrode by patterning a metal layer using the first insulating layer and the resist as a mask, a step of forming a second insulating layer, Forming a source electrode and the drain electrode.

  According to the present invention, since the gate electrode is covered with the insulating layer without undergoing an exposure process, it is not necessary to form a contact hole that requires highly accurate mask alignment.

  In addition, when the source electrode and the drain electrode are formed, conduction between the high concentration region in the semiconductor layer and the source electrode and the drain electrode can be ensured only by simple mask alignment.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best mode for carrying out the present invention will be described below with reference to the accompanying drawings.

(First embodiment)
FIG. 1A is a plan view showing the structure of a thin film transistor as a first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line BB ′.

  An undercoat layer 11 is formed on the insulating substrate 10, and a semiconductor layer 12 is formed thereon. A gate insulating layer 13 is formed on the semiconductor layer 12, and a gate electrode 14 is formed through the gate insulating layer 13.

  A first insulating layer 15 is formed on the gate electrode 14. In the present embodiment, the first insulating layer 15 is formed only on the gate electrode 14.

  The second insulating layer 16 is formed in contact with the side surfaces of the gate electrode 14 and the first insulating layer 15.

  The source electrode 17 and the drain electrode 18 are formed so as to cover the undercoat layer 11, the semiconductor layer 12, the second insulating layer 16, and the first insulating layer 15.

  As shown in FIG. 1, the gate electrode 14 is covered with an insulating layer.

  The semiconductor layer 12 in the same region as the region where the gate electrode 14 is formed is doped with impurities at a very low concentration by intrinsic or ion doping so as to function as the channel region 19.

  The threshold voltage of the thin film transistor can be controlled by the concentration of the impurity in the channel region 19, and the concentration of the impurity varies depending on the use application.

  Further, the semiconductor layer 12 other than the channel region 19 is doped as a high concentration region 21 with a high concentration impurity by an ion doping method.

  In the thin film transistor of FIG. 1, the lower surface of the gate electrode 14 is insulated from the semiconductor layer by the gate insulating film 13, and at the same time, the upper surface and the side surface are covered by the first insulating film 15 and the second insulating film 16, respectively. . The gate insulating film 13 is only on the lower surface of the gate electrode 14 and the lower surface of the second insulating film 16. Since the first and second insulating films and the gate insulating film are all provided along the gate electrode 14, the surface of the other semiconductor layer 12 and the surface of the undercoat layer 11 are covered with any insulating film. It is not exposed.

  Since the source electrode 17 and the drain electrode 18 are formed thereon, these electrodes can contact the semiconductor layer without passing through the contact holes.

  Therefore, not only the photolithography process for opening the contact hole in the insulating layer is unnecessary, but also the photolithography margin of the semiconductor layer around the contact hole is not required, and the size of the thin film transistor can be reduced.

  The source electrode 17 and the drain electrode 18 are formed simultaneously by forming a conductive film and patterning it by a photolithography process. Since the patterns are formed so as to be in contact with the semiconductor layer 12 respectively, a part of the source electrode 17 and the drain electrode 18 is formed on the first insulating layer 15 and the second insulating layer near the exposed surface of the semiconductor layer 12 as shown in FIG. Formed on layer 16. However, there is no contact with the gate electrode 14 covered with the first insulating film 15 and the second insulating film 16.

  FIG. 2 is a schematic cross-sectional view showing a method of manufacturing a thin film transistor as the first embodiment of the present invention.

  As shown in FIG. 2A, silicon oxide, silicon nitride, silicon oxynitride, or a multilayer film of these materials is formed on the insulating substrate 10 as the undercoat layer 11. The thickness is about 100 to 10,000 mm.

  Next, as shown in FIG. 2B, a semiconductor layer 12 made of silicon is formed on the entire surface, and the semiconductor layer 12 is patterned only in a region where a transistor is to be formed.

  The semiconductor layer 12 made of silicon is made of any of amorphous silicon, microcrystal silicon, or polysilicon. Amorphous silicon and microcrystal silicon can be formed by a plasma CVD method. Microcrystalline silicon and polysilicon can be formed by subjecting amorphous silicon to laser annealing or heat treatment. The thickness of the semiconductor layer 12 is 300 to 1000 mm, and the patterning is performed by dry etching after forming a photoresist pattern.

  Next, as shown in FIG. 2C, a gate insulating layer 13 is formed on the entire surface. As the gate insulating layer 13, silicon oxide, silicon nitride, silicon oxynitride, or a multilayer film of these materials is used. These gate insulating layers 13 can be formed by a CVD method, and the film thickness: a is about 600 to 3000 mm.

  Next, a metal layer is formed on the entire surface as the gate electrode 14, and then an insulating layer to be the first insulating layer 15 is formed on the entire surface.

  The gate electrode 14 and the first insulating layer 15 are formed in the same shape by continuously performing dry etching after forming a photoresist pattern.

  A sectional view of this state is shown in FIG. The metal layer to be the gate electrode 14 is made of an Al-based alloy, a refractory metal, or a multilayer film of these materials, and the film thickness: b is 500 to 5000 mm. The first insulating layer 15 is made of silicon oxide, silicon nitride, silicon oxynitride, or a multilayer film of these materials, and the film thickness: c is 3000 to 10,000 mm.

  As shown in FIG. 2E, in this state, ion doping is performed using the gate electrode 14 and the first insulating layer 15 as a mask, and a partial region of the semiconductor layer 12 is set as a high concentration region 21.

  Next, as shown in FIG. 2F, the second insulating layer 16 is formed on the entire surface. As a film formation method, a chemical vapor deposition method with high step coverage (hereinafter abbreviated as CVD: Chemical Vapor Deposition) is used to form an isotropic film. The film thickness d of the second insulating layer 16 is 3000 to 15000 mm. The second insulating layer 16 is made of silicon oxide, silicon nitride, or silicon oxynitride.

  Next, as shown in FIG. 2G, the second insulating layer 16 is anisotropically etched by a dry etching method to remove the second insulating layer 16 and the gate insulating layer 13 therebelow. . Here, anisotropic etching is a term for isotropic etching in the case of wet etching, and means an etching method having a large etching rate in a specific direction. The dry etching of this embodiment is anisotropic etching in which the etching rate in the film thickness direction is higher than the etching rate in the film surface direction.

  By anisotropic etching, the thickness of the insulating layer 16 is reduced uniformly regardless of the unevenness of the film surface. When the thickness of the second insulating layer 16 is removed, the upper surface of the first insulating layer 15 is exposed where the gate electrode 14 is, and the gate insulating film 13 is exposed otherwise. At this time, as described below with reference to FIG. 3, the second insulating layer 16 remains on the side surfaces of the gate electrode 14 and the first insulating layer 15.

  As an anisotropic dry etching method, reactive ion etching (RIE) is used.

  Furthermore, when the gate insulating layer 13 is anisotropically etched, the film thickness of the first insulating layer 15 also decreases at the same time. Therefore, depending on the thickness of the gate insulating film, the first insulating layer 15 on the gate electrode 14 may disappear, and the surface of the gate electrode 14 may be exposed. In order to prevent this, the film thickness c of the first insulating layer 15 is set larger than the film thickness a of the gate insulating layer 13.

  However, when the materials of the gate insulating layer 13, the first insulating layer 15, and the second insulating layer 16 are different and there is a difference in etching rate, the thickness of the first insulating layer 15 is arbitrary under the following conditions. The film thickness can be selected. That is, it is within a range where the surface of the gate electrode 14 is not exposed by etching within 3000 to 10000 mm.

  Here, how the width A of the second insulating layer 16 changes when the film thickness d of the second insulating layer 16 is changed will be described with reference to FIG.

  FIG. 3 is a cross-sectional view showing the structure of the state where the second insulating layer 16 is formed and the state after etching when the thickness d of the second insulating layer 16 is different.

  Since the second insulating layer 16 is formed by CVD, it is also formed on the side surfaces of the gate electrode 14 and the first insulating layer 15.

  As a result, the anisotropic dry etching method cannot remove the growth from the side surfaces of the gate electrode 14 and the first insulating layer 15. Therefore, a shape in which the second insulating layer 16 exists on the side surfaces of the gate electrode 14 and a part of the first insulating layer 15 can be formed even after dry etching.

  Since the thickness of the second insulating layer 16 grown on the side surfaces of the gate electrode 14 and the first insulating layer 15 has a positive relationship with the thickness d of the second insulating layer 16: d, the second insulating layer By changing the film thickness d of 16, the width A can be changed.

  At this point, the gate electrode 14 is surrounded by the gate insulating layer 13, the first insulating film 15, and the second insulating film 16.

  Next, as shown in FIG. 2H, a metal layer to be the source electrode 17 and the drain electrode 18 is formed and patterned into a desired shape, whereby the thin film transistor can be completed.

  In the above manufacturing method, it is not necessary to form a contact hole for ensuring the conduction between the source electrode 17 or the drain electrode 18 and the semiconductor layer 12.

  Further, in the conventional manufacturing method, it is not necessary to perform high-precision mask alignment even in the exposure process of the source electrode 17 and the drain electrode 18 in which high-precision mask alignment is performed on the contact hole. Therefore, an exposure process can be performed by simple mask alignment, and a fine thin film transistor can be formed regardless of mask alignment accuracy.

(Second Embodiment)
FIG. 4 is a cross-sectional view showing the structure of a thin film transistor as a second embodiment of the present invention.

  An undercoat layer 11 is formed on the insulating substrate 10, and a semiconductor layer 12 is formed thereon. A gate insulating layer 13 is formed on the semiconductor layer 12, and a gate electrode 14 is formed through the gate insulating layer 13.

  A first insulating layer 15 is formed on the gate electrode 14. In the present embodiment, the first insulating layer 15 is formed only on the gate electrode 14.

  The second insulating layer 16 is formed in contact with the side surfaces of the gate electrode 14 and the first insulating layer 15.

  A source electrode 17 or a drain electrode 18 is formed in contact with at least a part of the second insulating layer 16.

  The source electrode 17 and the drain electrode 18 are formed so as to cover the undercoat layer 11, the semiconductor layer 12, the second insulating layer 16, and the first insulating layer 15.

  As shown in FIG. 4, the gate electrode 14 is covered with an insulating layer.

  The semiconductor layer 12 under the gate insulating layer 13 is channel-doped with a very low concentration impurity by an intrinsic or ion doping method so as to function as the channel region 19.

  The semiconductor layer 12 (channel region 19 and offset region 22) under the gate electrode 14 and the second insulating layer 16 is channel-doped with a very low concentration impurity by an intrinsic or ion doping method through the gate insulating layer 13. Yes.

  Further, the semiconductor layer 12 other than the channel region 19 is doped as a high concentration region 21 with a high concentration impurity by an ion doping method.

  In this thin film transistor, the gate electrode 14 is surrounded by the gate insulating layer 13, the first insulating layer 15, and the second insulating layer 16. Therefore, insulation between the gate electrode 14 and the source electrode 17 or the drain electrode 18 is ensured without using an interlayer insulating layer, and there is no need to form a contact hole in the interlayer insulating layer.

  Further, in the conventional manufacturing method, it is not necessary to perform high-precision mask alignment even in the exposure process of the source electrode 17 and the drain electrode 18 in which high-precision mask alignment is performed on the contact hole. Therefore, the exposure process can be performed by simple mask alignment.

  Further, by providing the offset region 22 between the high concentration region 21 and the channel region 19 in the semiconductor layer 12, it is possible to reduce off-leakage current.

  FIG. 5 is a schematic cross-sectional view showing a method of manufacturing a thin film transistor as a second embodiment of the present invention.

  The forming process up to FIG. 5A is the same as the process of forming FIG.

  After the structure of FIG. 5A is formed, a second insulating layer 16 is formed on the entire surface as shown in FIG. The film thickness of the second insulating layer 16 is 5000 to 15000 mm. The second insulating layer 16 is made of silicon oxide, silicon nitride, or silicon oxynitride.

  Next, the second insulating layer 16 is anisotropically etched by a dry etching method, that is, selectively etched in the film thickness direction, and all the film thicknesses of the gate insulating layer 13 and the second insulating layer 16 are removed. End up. Then, as shown in FIG. 5C, the second insulating layer 16 remains on the side portions of the gate electrode 14 and the first insulating layer 15.

  Next, as shown in FIG. 5D, ion doping is performed using the first insulating layer 15 and the second insulating layer 16 as a mask, so that a partial region of the semiconductor layer 12 is a high concentration region 21.

  By this step, the offset region 22 can be formed between the channel region 19 in the semiconductor layer 12 below the gate insulating layer 13 and the high concentration region 21.

  Next, as shown in FIG. 5E, a metal layer to be the source electrode 17 and the drain electrode 18 is formed and patterned into a desired shape, whereby the thin film transistor can be completed.

  In the above manufacturing method, it is not necessary to form a contact hole for ensuring the conduction between the source electrode 17 or the drain electrode 18 and the semiconductor layer 12.

  Further, in the conventional manufacturing method, it is not necessary to perform high-precision mask alignment even in the exposure process of the source electrode 17 and the drain electrode 18 for performing high-precision mask alignment on the contact holes. Therefore, an exposure process can be performed by simple mask alignment, and a fine thin film transistor can be formed regardless of mask alignment accuracy.

  In the above manufacturing method, the thin film transistor having the offset structure can be formed by using the first insulating layer 15 and the second insulating layer 16 as a mask when the high concentration region 21 is formed. Therefore, a thin film transistor with low off-leakage current can be manufactured.

(Third embodiment)
FIG. 6 is a cross-sectional view showing the structure of a thin film transistor as a third embodiment of the present invention.

  An undercoat layer 11 is formed on the insulating substrate 10, and a semiconductor layer 12 is formed thereon. A gate insulating layer 13 is formed on the semiconductor layer 12, and a gate electrode 14 is formed through the gate insulating layer 13.

  A first insulating layer 15 is formed on the gate electrode 14. In the present embodiment, the first insulating layer 15 is formed only on the gate electrode 14.

  The second insulating layer 16 is formed in contact with the side surfaces of the gate electrode 14 and the first insulating layer 15.

  A source electrode 17 or a drain electrode 18 is formed in contact with at least a part of the second insulating layer 16.

  The source electrode 17 and the drain electrode 18 are formed so as to cover the undercoat layer 11, the semiconductor layer 12, the second insulating layer 16, and the first insulating layer 15.

  As shown in FIG. 6, the gate electrode 14 is covered with an insulating layer.

  The semiconductor layer 12 under the gate electrode 14 is channel-doped with a very low concentration impurity by an intrinsic or ion doping method so as to function as the channel region 19 via the gate insulating layer 13.

  The semiconductor layer 12 (low concentration region 20) under the second insulating layer 16 is doped with a low concentration impurity by an ion doping method through the gate insulating layer 13.

  The semiconductor layer 12 (high concentration region 21) in contact with the source electrode 17 or the drain electrode 18 is doped with a high concentration impurity by an ion doping method.

  In this thin film transistor, the gate electrode 14 is surrounded by the gate insulating layer 13, the first insulating layer 15, and the second insulating layer 16. Therefore, insulation between the gate electrode 14 and the source electrode 17 or the drain electrode 18 is ensured without using an interlayer insulating layer, and there is no need to form a contact hole in the interlayer insulating layer.

  Further, in the conventional manufacturing method, it is not necessary to perform high-precision mask alignment even in the exposure process of the source electrode 17 and the drain electrode 18 for performing high-precision mask alignment on the contact holes. Therefore, the exposure process can be performed by simple mask alignment.

  Further, by providing the low concentration region 21 between the high concentration region 21 and the channel region 19 in the semiconductor layer 12, an LDD structure is obtained. Therefore, it is possible to reduce off-leakage current and improve resistance against device characteristic deterioration due to hot electrons.

  FIG. 7 is a schematic cross-sectional view showing a method of manufacturing a thin film transistor as a third embodiment of the present invention.

  The forming process up to FIG. 7A is the same as the process of forming FIG.

  In the step of FIG. 7A, ion doping is performed using the first insulating layer 15 as a mask to form a low concentration region 20 in a partial region of the semiconductor layer 12.

  Next, as shown in FIG. 7B, a second insulating layer 16 is formed on the entire surface. The film thickness of the second insulating layer 16 is 5000 to 15000 mm. The second insulating layer 16 is made of silicon oxide, silicon nitride, or silicon oxynitride.

  Next, the second insulating layer 16 is anisotropically etched by a dry etching method, that is, selectively etched in the film thickness direction, and all the film thicknesses of the gate insulating layer 13 and the second insulating layer 16 are removed. End up. Then, as shown in FIG. 7C, the second insulating layer 16 remains on the side portions of the gate electrode 14 and the first insulating layer 15.

  Next, as shown in FIG. 7D, ion doping is performed using the first insulating layer 15 and the second insulating layer 16 as a mask, so that a partial region of the semiconductor layer 12 is a high concentration region 21.

  By this step, the low concentration region 20 can be formed between the channel region 19 and the high concentration region 21 in the semiconductor layer 12 facing the gate electrode 14 through the gate insulating layer 13.

  Next, as shown in FIG. 7E, a metal layer to be the source electrode 17 and the drain electrode 18 is formed and patterned into a desired shape, whereby the thin film transistor of this embodiment is completed.

  In the above manufacturing method, it is not necessary to form a contact hole for ensuring the conduction between the source electrode 17 or the drain electrode 18 and the semiconductor layer 12.

  Further, in the conventional manufacturing method, it is not necessary to perform high-precision mask alignment even in the exposure process of the source electrode 17 and the drain electrode 18 for performing high-precision mask alignment on the contact holes. Therefore, an exposure process can be performed by simple mask alignment, and a fine thin film transistor can be formed regardless of mask alignment accuracy.

  In the above manufacturing method, the first insulating layer 15 is used as a mask when the low concentration region 20 is formed, and the first insulating layer 15 and the second insulating layer 16 are used as a mask when the high concentration region 21 is formed. Yes. Therefore, a thin film transistor having an LDD structure can be formed. Therefore, a thin film transistor with low off-leakage current and high resistance to device characteristic deterioration due to hot electrons can be manufactured.

  In the thin film transistor of each of the above embodiments, silicon nitride can be used as the first insulating layer 15 and silicon oxide can be used as the second insulating layer 16.

  In the thin film transistor having such a structure, due to the difference in etching rate between the first insulating layer 15 and the second insulating layer 16, the film thickness change of the first insulating layer 15 is changed in the etching process when the second insulating layer is formed. Can be suppressed.

(Fourth embodiment)
FIG. 8 is a schematic cross-sectional view showing a method of forming the second insulating layer 16 by oxidizing the gate electrode 14 as the fourth embodiment of the present invention.

  The forming process up to FIG. 8A is the same as the process of forming FIG.

  In the step of FIG. 8B, thermal oxidation or anodic oxidation is performed on the gate electrode 14 to oxidize the side wall of the gate electrode 14 and perform insulation. At this time, the semiconductor layer 12 is covered with the gate insulating film 13 and is not oxidized.

  The oxide film formed in this step becomes the second insulating layer 16 covering the side surface of the gate electrode. The film thickness of the second insulating layer 16 is 3000 to 15000 mm.

  Next, in the step of FIG. 8C, the gate insulating layer 13 is etched using the first insulating layer 15 as a mask.

  Next, as shown in FIG. 8D, the thin film transistor of this embodiment is completed by forming the source electrode 17 and the drain electrode 18.

  In the above manufacturing method, since the second insulating layer 16 is formed using the oxide film of the gate electrode 14, the film forming process can be reduced.

(Fifth embodiment)
FIG. 9 is a schematic cross-sectional view showing a method for electrically connecting the gate electrode 14 and the source electrode 17 or the drain electrode 18 as the fifth embodiment of the present invention.

  The forming process up to FIG. 9A is the same as the process of forming FIG.

  2 is a schematic cross-sectional view of a thin film transistor, the semiconductor layer 12 is present. In FIG. 9, the semiconductor layer 12 is present because of a wiring region for electrically connecting the gate electrode 14 and the source electrode 17 or the drain electrode 18. do not do.

  In the step of FIG. 9B, the gate insulating layer 13, the gate electrode 14, and the first insulating layer 15 are formed.

  Next, as shown in FIG. 9C, the first insulating layer 15 is patterned by dry etching after forming a photoresist pattern. Dry etching removes only the first insulating layer 15.

  Next, as shown in FIG. 9D, only the region electrically connected between the gate electrode 14 and the source electrode 17 or the drain electrode 18 formed in the step of FIG. 9C is covered with a resist by a photolithography process. .

  Next, as shown in FIG. 9E, the gate electrode 14 is etched by dry etching. At this time, the first insulating layer 15 and the resist film formed in FIG. 9D serve as a mask, and the gate electrode 14 and the source electrode 17 or the drain electrode 18 are electrically connected while patterning the gate electrode 14. A region can be formed.

  Next, after forming the second insulating layer 16 as shown in FIG. 9 (f), the source electrode 17 or the drain electrode 18 is formed as shown in FIG. 9 (g). By doing so, the gate electrode 14 and the source electrode 17 or the drain electrode 18 can be electrically connected.

  In the present embodiment, the gate electrode 14 can be electrically connected to the source electrode 17 or the drain electrode 18 while the first to third embodiments are performed.

  Further, since the pattern connecting the gate electrode 14 and the source electrode 17 or the drain electrode 18 is formed using the same mask as the gate electrode 14, the pattern can be formed without worrying about alignment accuracy.

(Sixth embodiment)
FIG. 14 shows a configuration of a pixel circuit used in a liquid crystal display as a sixth embodiment of the present invention. In the pixel circuit of the liquid crystal display, one thin film transistor 1 is arranged per one pixel and is turned on by a selection signal of the gate line 14 to transmit a voltage signal of the source line to the liquid crystal element 2.

  A liquid crystal display is a matrix in which a plurality of pixel circuits in FIG. 14 are arranged in a row direction and a column direction.

  The gate line 14 extends from the gate electrode of the thin film transistor in the pixel circuit and is commonly connected to the pixels arranged in the row direction. The signal line 17 extends from the source electrode of the thin film transistor 1 in the pixel circuit, and is connected in common to the pixels arranged in the column direction.

  That is, the gate electrode 14 in FIG. 1A (under the first insulating layer 15) is extended in the row direction as it is to form the gate line 14 in FIG. The source electrode 17 is extended in the column direction to form the source line 17 in FIG.

  Components having the same reference numerals in FIGS. 1 and 14 have the same configuration. That is, the gate line 14 in FIG. 14 is formed simultaneously with the patterning of the gate line and the first insulating layer 15 in (d) in the manufacturing process described with reference to FIG. The source line 17 is formed simultaneously with the patterning of the source / drain electrodes in FIG.

  Therefore, the matrix display of FIG. 14 can also be manufactured by the same manufacturing process as that of FIG. 2, and no additional process is required.

  As shown in FIG. 14, in the pixel circuit of the liquid crystal display, the gate line 14 and the source line 17 are not electrically connected to each other. Therefore, a liquid crystal display is formed by the manufacturing process described in the first to third embodiments.

  FIG. 15 shows a configuration of a pixel circuit used in an EL (electroluminescence) display. In the pixel circuit of the EL display, a plurality of thin film transistors are used in one pixel. The gate electrode of the first transistor 3 is connected to the gate line 14 and the source electrode is connected to the source line 17. The drain electrode of the first transistor 3 is connected to the gate electrode of the second transistor 4. The second transistor 4 connects the power line 5 and the EL element 6 and supplies current to the EL element 6.

  As shown in FIG. 15, there are a plurality of thin film transistors in the pixel, and the drain electrode of the first transistor 3 is connected to the gate electrode of the second transistor 4. In the actual arrangement on the substrate, the drain electrode of the first transistor 3 is extended and joined to the gate electrode of the second transistor 4 through a contact hole opened in the first insulating layer. In addition, when the power supply line 5 is arranged in parallel with the same configuration as the gate line as shown in FIG. 15, the same connection structure can be formed at the place where the source electrode of the second transistor 4 and the power supply line 5 are connected.

  In order to make these connection structures, the method of electrically connecting the gate electrode 14 to the source electrode 17 or the drain electrode 18 described in the fifth embodiment of the present invention may be applied.

  The present invention is applicable to a thin film transistor used for a display such as a liquid crystal display device or an organic EL display.

It is sectional drawing which shows the structure of the thin-film transistor as the 1st Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the thin-film transistor as the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the state which formed the 2nd insulating layer 16 in case the film thickness: d of 2nd insulating layer 16 differs, and the state after an etching. It is sectional drawing which shows the structure of the thin-film transistor as the 2nd Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the thin-film transistor as the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the thin-film transistor as the 3rd Embodiment of this invention. It is a schematic cross section which shows the manufacturing method of the thin-film transistor as the 3rd Embodiment of this invention. It is a schematic cross section which shows the method of forming the 2nd insulating layer 16 by oxidizing the gate electrode 14 as the 4th Embodiment of this invention. It is a schematic cross section which shows the method of electrically connecting the gate electrode 14 and the source electrode 17 or the drain electrode 18 as the 5th Embodiment of this invention. It is a schematic cross section which shows the structure of the conventional thin-film transistor. It is sectional drawing which shows the structure of the thin-film transistor of the conventional LDD structure (Lightly Doped Drain structure). It is a schematic cross section which shows the structure of the conventional thin-film transistor. It is a figure which shows the thin-film transistor of a prior art. It is a figure which shows the pixel circuit of a liquid crystal display. It is a figure which shows the pixel circuit of EL display.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 3, 4 Thin-film transistor 2 Liquid crystal element 5 Power supply line 6 EL element 10 Insulating substrate 11 Undercoat layer 12 Semiconductor layer 13 Gate insulating layer 14 Gate electrode 15 1st insulating layer 16 2nd insulating layer 17 Source electrode 18 Drain Electrode 19 Channel region 20 Low concentration region 21 High concentration region 22 Offset region

Claims (12)

In a thin film transistor in which a semiconductor layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode are formed on a substrate,
The gate electrode is configured to be covered with an insulating layer,
The thin film transistor, wherein the source electrode and the drain electrode are in contact with the semiconductor layer. The insulating layer covering the gate electrode is formed along the gate insulating layer, a first insulating layer formed on the gate electrode, and a second formed along the gate electrode and the first insulating layer. The thin film transistor according to claim 1, comprising: The semiconductor layer in the same region as the region where the gate electrode is formed functions as a channel region,
3. The thin film transistor according to claim 1, wherein the semiconductor layer other than the channel region is doped with an impurity as a high concentration region. The semiconductor layer in the same region as the region where the gate electrode and the second insulating layer are formed functions as a channel region,
3. The thin film transistor according to claim 1, wherein the semiconductor layer other than the channel region is doped with an impurity as a high concentration region. The semiconductor layer in the same region as the region where the gate electrode is formed functions as a channel region,
The semiconductor layer in the same region as the region where the second insulating layer is formed is doped with impurities as a low concentration region,
3. The thin film transistor according to claim 1, wherein the semiconductor layer other than the channel region is doped with an impurity as a high concentration region. 6. The thin film transistor according to claim 1, wherein the first insulating layer is made of silicon nitride, and the second insulating layer is made of silicon oxide. Forming a semiconductor layer;
Forming a layer to be a gate insulating layer on the semiconductor layer;
Forming a metal layer on the gate insulating layer;
Forming an insulating layer on the metal layer;
Patterning the metal layer and the insulating layer into the same shape to form a gate electrode and a first insulating layer;
Forming another insulating layer on the entire surface;
Removing the other insulating layer anisotropically to form a second insulating layer along the first insulating layer and the gate electrode;
Using the first insulating layer and the second insulating layer as a mask, patterning the layer to be the gate insulating layer to form a gate insulating layer;
Depositing another metal layer;
And forming a source electrode and a drain electrode by patterning the another metal layer into a desired shape. Forming a semiconductor layer;
Forming a layer to be a gate insulating layer on the semiconductor layer;
Forming a metal layer on the gate insulating layer;
Forming an insulating layer on the metal layer;
Patterning the metal layer and the insulating layer into the same shape to form a gate electrode and a first insulating layer;
Forming another insulating layer on the entire surface;
Removing the other insulating layer anisotropically to form a second insulating layer along the first insulating layer and the gate electrode;
Using the first insulating layer and the second insulating layer as a mask, patterning the layer to be the gate insulating layer to form a gate insulating layer;
Doping the semiconductor layer with ions at a high concentration using the first insulating layer as a mask;
Depositing another metal layer;
And forming a source electrode and a drain electrode by patterning the another metal layer into a desired shape. Forming a semiconductor layer;
Forming a layer to be a gate insulating layer on the semiconductor layer;
Forming a metal layer on the gate insulating layer;
Forming an insulating layer on the metal layer;
Patterning the metal layer and the insulating layer into the same shape to form a gate electrode and a first insulating layer;
Forming another insulating layer on the entire surface;
Removing the other insulating layer anisotropically to form a second insulating layer along the first insulating layer and the gate electrode;
Using the first insulating layer and the second insulating layer as a mask, patterning the layer to be the gate insulating layer to form a gate insulating layer;
Doping the semiconductor layer with ions at a high concentration using the first insulating layer and the second insulating layer as a mask;
Depositing another metal layer;
And forming a source electrode and a drain electrode by patterning the another metal layer into a desired shape. Forming a semiconductor layer;
Forming a layer to be a gate insulating layer on the semiconductor layer;
Forming a metal layer on the gate insulating layer;
Forming an insulating layer on the metal layer;
Patterning the metal layer and the insulating layer into the same shape to form a gate electrode and a first insulating layer;
Doping the semiconductor layer with ions at a low concentration using the first insulating layer as a mask;
Forming another insulating layer on the entire surface;
Removing the other insulating layer anisotropically to form a second insulating layer along the first insulating layer and the gate electrode;
Using the first insulating layer and the second insulating layer as a mask, patterning the layer to be the gate insulating layer to form a gate insulating layer;
Doping the semiconductor layer with ions at a high concentration using the first insulating layer and the second insulating layer as a mask;
Depositing another metal layer;
And forming a source electrode and a drain electrode by patterning the another metal layer into a desired shape. Forming a semiconductor layer;
Forming a gate insulating layer on the semiconductor layer;
Forming a metal layer on the gate insulating layer;
Forming an insulating layer on the metal layer;
Patterning the metal layer and the insulating layer into the same shape to form a gate electrode and a first insulating layer;
Oxidizing the side surface of the metal layer to form a second insulating layer;
Using the first insulating layer as a mask, patterning the gate insulating layer to form a gate insulating layer;
Depositing another metal layer;
And patterning the another metal layer into a desired shape to form a source electrode and a drain electrode. Forming a semiconductor layer;
Forming a layer to be a gate insulating layer on the semiconductor layer;
Forming a metal layer on the gate insulating layer;
Forming an insulating layer on the metal layer;
Patterning the insulating layer to form a first insulating layer;
Covering the region connecting the metal layer and the source or drain electrode with a resist;
Using the first insulating layer and the resist as a mask to pattern the metal layer to form a gate electrode;
Forming a second insulating layer;
Forming the source electrode and the drain electrode. A method of manufacturing a thin film transistor, comprising: