JP5023465B2 - Thin film transistor panel - Google Patents

Thin film transistor panel Download PDF

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JP5023465B2
JP5023465B2 JP2005305140A JP2005305140A JP5023465B2 JP 5023465 B2 JP5023465 B2 JP 5023465B2 JP 2005305140 A JP2005305140 A JP 2005305140A JP 2005305140 A JP2005305140 A JP 2005305140A JP 5023465 B2 JP5023465 B2 JP 5023465B2
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thin film
electrode
film
source electrode
ohmic contact
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JP2007115859A (en
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裕満 石井
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Priority to KR1020060100599A priority patent/KR100828859B1/en
Priority to US11/582,886 priority patent/US8089068B2/en
Priority to TW095138543A priority patent/TWI323945B/en
Priority to CN2011100282131A priority patent/CN102163610B/en
Priority to CN200910168653XA priority patent/CN101699624B/en
Priority to CN2008102125665A priority patent/CN101369606B/en
Priority to CN200610171869A priority patent/CN100587958C/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit

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  • Mathematical Physics (AREA)
  • Thin Film Transistor (AREA)
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Description

この発明は薄膜トランジスタパネルに関する。 This invention relates to the thin film transistor panel.

従来の薄膜トランジスタには、基板の上面にゲート電極が設けられ、ゲート電極を含む基板の上面にゲート絶縁膜が設けられ、ゲート電極上におけるゲート絶縁膜の上面に真性アモルファスシリコンからなる半導体薄膜が設けられ、半導体薄膜の上面の所定の箇所に窒化シリコンからなるチャネル保護膜が設けられ、チャネル保護膜の上面両側及びその両側における半導体薄膜の上面にｎ型アモルファスシリコンからなるオーミックコンタクト層が設けられ、各オーミックコンタクト層の上面にソース電極及びドレイン電極が形成され設けられ、その上に窒化シリコンからなるオーバーコート膜が設けられたものがある（例えば、特許文献１参照）。   In a conventional thin film transistor, a gate electrode is provided on the upper surface of the substrate, a gate insulating film is provided on the upper surface of the substrate including the gate electrode, and a semiconductor thin film made of intrinsic amorphous silicon is provided on the upper surface of the gate insulating film on the gate electrode. A channel protective film made of silicon nitride is provided at a predetermined position on the upper surface of the semiconductor thin film, and an ohmic contact layer made of n-type amorphous silicon is provided on both sides of the upper surface of the channel protective film and on the upper surface of the semiconductor thin film on both sides thereof. In some cases, a source electrode and a drain electrode are formed and provided on the upper surface of each ohmic contact layer, and an overcoat film made of silicon nitride is provided thereon (see, for example, Patent Document 1).

特開２００５−９３４６０号公報JP 2005-93460 A

上記従来の薄膜トランジスタでは、ソース電極及びドレイン電極の幅を半導体薄膜上に直接設けられた領域の各オーミックコンタクト層の幅よりも大きくし、且つ、半導体薄膜上に直接設けられた領域の各オーミックコンタクト層をソース電極及びドレイン電極によって完全に覆っているので、その上に窒化シリコンからなるオーバーコート膜をプラズマＣＶＤ法により成膜しても、半導体薄膜上に直接設けられた領域の各オーミックコンタクト層の表面がプラズマダメージを受けることがなく、ひいてはＶｇ（ゲート電圧）−Ｉｄ（ドレイン電流）特性のマイナス側へのシフトを抑制することができる。   In the conventional thin film transistor, the width of the source electrode and the drain electrode is made larger than the width of each ohmic contact layer in the region directly provided on the semiconductor thin film, and each ohmic contact in the region directly provided on the semiconductor thin film. Since the layer is completely covered by the source electrode and the drain electrode, even if an overcoat film made of silicon nitride is formed thereon by the plasma CVD method, each ohmic contact layer in the region directly provided on the semiconductor thin film The surface of the substrate is not damaged by plasma, and thus the shift of the Vg (gate voltage) -Id (drain current) characteristic to the negative side can be suppressed.

しかしながら、上記従来の薄膜トランジスタでは、ソース電極及びドレイン電極の幅を半導体薄膜上に直接設けられた領域の各オーミックコンタクト層の幅よりも大きくしているので、ソース電極及びドレイン電極を形成するためのフォトリソグラフィ工程がオーミックコンタクト層を形成するためのフォトリソグラフィ工程と別となり、フォトリソグラフィ工程数が増加するという問題があった。   However, in the above-described conventional thin film transistor, the width of the source electrode and the drain electrode is larger than the width of each ohmic contact layer in the region directly provided on the semiconductor thin film, so that the source electrode and the drain electrode are formed. The photolithography process is different from the photolithography process for forming the ohmic contact layer, which increases the number of photolithography processes.

そこで、この発明は、Ｖｇ−Ｉｄ特性のマイナス側へのシフトを抑制することができる上、フォトリソグラフィ工程数が増加しないようにすることができる薄膜トランジスタパネルを提供することを目的とする。   In view of the above, an object of the present invention is to provide a thin film transistor panel that can suppress a negative shift of the Vg-Id characteristic and can prevent the number of photolithography processes from increasing.

この発明は、上記目的を達成するため、ゲート電極上にゲート絶縁膜を介して半導体薄膜が設けられた薄膜トランジスタと、前記薄膜トランジスタのソース電極に電気的に接続された画素電極と、を有し、
前記薄膜トランジスタが、前記半導体薄膜上に設けられたチャネル保護膜と、前記チャネル保護膜上及び前記半導体薄膜上に設けられたオーミックコンタクト層と、前記オーミックコンタクト層上に設けられた前記ソース電極及びドレイン電極とを有し、
前記ソース電極及び前記ドレイン電極が、前記チャネル長方向に平行な方向に延伸する２つの辺を有している薄膜トランジスタパネルであって、
前記画素電極と同一の層として形成されるとともに、前記画素電極とは電気的に絶縁された導電性被覆膜を有し、
前記導電性被覆膜は、少なくとも一部が前記２つの辺に重なるように、前記ドレイン電極上に前記ドレイン電極よりも幅広に形成され、
前記オーミックコンタクト層は、前記ソース電極及び前記ドレイン電極と同一のマスクに基づいてパターニングされていて、
前記半導体薄膜は、前記ソース電極及び前記ドレイン電極と同一のマスク及び前記チャネル保護膜に基づいてパターニングされていて、
前記チャネル保護膜のドレイン電極側の外側であって且つ前記ゲート電極上における、前記半導体薄膜、前記オーミックコンタクト層及び前記ドレイン電極のチャネル幅方向の両端面が、当該両端面に接触して設けられた前記導電性被覆膜によって覆われており、前記チャネル保護膜の前記ソース電極側の外側であって且つ前記ゲート電極上における、前記半導体薄膜、前記オーミックコンタクト層及び前記ソース電極のチャネル幅方向の両端面が、当該両端面に接触して設けられた前記画素電極によって覆われていることを特徴とするものである。 In order to achieve the above object, the present invention has a thin film transistor in which a semiconductor thin film is provided on a gate electrode through a gate insulating film, and a pixel electrode electrically connected to a source electrode of the thin film transistor,
Said thin film transistor, wherein the channel protective film provided on the semiconductor thin film, an ohmic contact layer formed on the channel protective film and the semiconductor thin film, the source electrode and the drain provided on the ohmic contact layer An electrode ,
The thin film transistor panel, wherein the source electrode and the drain electrode have two sides extending in a direction parallel to the channel length direction,
It is formed as the same layer as the pixel electrode, and has a conductive coating film that is electrically insulated from the pixel electrode,
The conductive coating film is formed wider on the drain electrode than the drain electrode so that at least a part thereof overlaps the two sides,
The ohmic contact layer is patterned based on the same mask as the source electrode and the drain electrode,
The semiconductor thin film is patterned based on the same mask and the channel protective film as the source electrode and the drain electrode,
Before SL channel protective film on the drain electrode side of the outer and was in and the gate electrode on the semiconductor thin film, both end faces in the channel width direction of the ohmic contact layer and the drain electrode is provided in contact with the end surfaces It was covered by the conductive coating film, in the an outer source electrode side and the gate electrode on the channel protective layer, the semiconductor thin film, the ohmic contact layer and the channel width of the source electrode Both end faces in the direction are covered with the pixel electrodes provided in contact with the both end faces .

この発明によれば、Ｖｇ−Ｉｄ特性のマイナス側へのシフトを抑制することができる上、フォトリソグラフィ工程数が増加しないようにすることができる。 According to the present invention, the negative shift of the Vg-Id characteristic can be suppressed, and the number of photolithography processes can be prevented from increasing.

（第１実施形態）
図１はこの発明の第１実施形態としての薄膜トランジスタパネルの要部の透過平面図を示し、図２（Ａ）は図１のIIA−IIAに沿う断面図を示し、図２（Ｂ）は図１のIIB−IIBに沿う断面図を示す。この薄膜トランジスタパネルはガラス基板１を備えている。ガラス基板１の上面には、マトリックス状に配置された複数の画素電極２と、これらの画素電極２に接続された薄膜トランジスタ３と、行方向に配置され、各薄膜トランジスタ３に走査信号（ゲート電圧）を供給する走査ライン４と、列方向に配置され、各薄膜トランジスタ３にデータ信号を供給するデータライン５とが設けられている。 (First embodiment)
FIG. 1 shows a transmission plan view of a main part of a thin film transistor panel as a first embodiment of the present invention, FIG. 2A shows a cross-sectional view along II A- II A in FIG. 1, and FIG. Shows a sectional view along II B -II B in FIG. The thin film transistor panel includes a glass substrate 1. On the upper surface of the glass substrate 1, a plurality of pixel electrodes 2 arranged in a matrix, thin film transistors 3 connected to these pixel electrodes 2, and arranged in the row direction, each thin film transistor 3 has a scanning signal (gate voltage). And a data line 5 arranged in the column direction and supplying a data signal to each thin film transistor 3 is provided.

すなわち、ガラス基板１の上面の所定の箇所にはクロムやアルミニウム系金属等からなるゲート電極６及び該ゲート電極６に接続された走査ライン４が設けられている。ゲート電極６及び走査ライン４を含むガラス基板１の上面には窒化シリコンからなるゲート絶縁膜７が設けられている。ゲート電極６上におけるゲート絶縁膜７の上面の所定の箇所には真性アモルファスシリコンからなる半導体薄膜８が設けられている。   That is, a gate electrode 6 made of chromium, aluminum-based metal, or the like and a scanning line 4 connected to the gate electrode 6 are provided at predetermined locations on the upper surface of the glass substrate 1. A gate insulating film 7 made of silicon nitride is provided on the upper surface of the glass substrate 1 including the gate electrode 6 and the scanning line 4. A semiconductor thin film 8 made of intrinsic amorphous silicon is provided at a predetermined position on the upper surface of the gate insulating film 7 on the gate electrode 6.

半導体薄膜８の上面の所定の箇所には窒化シリコンからなるチャネル保護膜９が設けられている。この場合、チャネル保護膜９は、そのサイズがゲート電極６のサイズよりもある程度小さく、ゲート電極６の中央部上における半導体薄膜８の上面に設けられている。チャネル保護膜９の上面においてチャネル長Ｌ方向の両側及びその両側における半導体薄膜８の上面にはｎ型アモルファスシリコンからなる一対のオーミックコンタクト層１０、１１が設けられている。各オーミックコンタクト層１０、１１の上面にはクロムやアルミニウム系金属等からなるソース電極１２及びドレイン電極１３が設けられている。   A channel protective film 9 made of silicon nitride is provided at a predetermined location on the upper surface of the semiconductor thin film 8. In this case, the channel protective film 9 has a size somewhat smaller than the size of the gate electrode 6 and is provided on the upper surface of the semiconductor thin film 8 on the central portion of the gate electrode 6. A pair of ohmic contact layers 10 and 11 made of n-type amorphous silicon are provided on both sides in the channel length L direction on the upper surface of the channel protective film 9 and on the upper surface of the semiconductor thin film 8 on both sides thereof. A source electrode 12 and a drain electrode 13 made of chromium, aluminum-based metal, or the like are provided on the upper surface of each ohmic contact layer 10, 11.

この場合、各オーミックコンタクト層１０、１１の周端面はソース電極１２及びドレイン電極１３の周端面と同じとなっている。すなわち、各オーミックコンタクト層１０、１１はソース電極１２及びドレイン電極１３下にのみ設けられている。半導体薄膜８の周端面はチャネル保護膜９を含む一対のオーミックコンタクト層１０、１１の周端面と同じとなっている。すなわち、半導体薄膜８はチャネル保護膜９を含む一対のオーミックコンタクト層１０、１１下にのみ設けられている。また、一対のオーミックコンタクト層１０、１１、ソース電極１２及びドレイン電極１３の相対向する一端側はチャネル保護膜９上に延出されている。   In this case, the peripheral end surfaces of the ohmic contact layers 10 and 11 are the same as the peripheral end surfaces of the source electrode 12 and the drain electrode 13. That is, the ohmic contact layers 10 and 11 are provided only under the source electrode 12 and the drain electrode 13. The peripheral end surface of the semiconductor thin film 8 is the same as the peripheral end surfaces of the pair of ohmic contact layers 10 and 11 including the channel protective film 9. That is, the semiconductor thin film 8 is provided only under the pair of ohmic contact layers 10 and 11 including the channel protective film 9. In addition, opposite one end sides of the pair of ohmic contact layers 10 and 11, the source electrode 12 and the drain electrode 13 are extended on the channel protective film 9.

ゲート絶縁膜７の上面の所定の箇所にはデータライン５が設けられている。データライン５は、下から順に、真性アモルファスシリコン層５ａ、ｎ型アモルファスシリコン層５ｂ、クロムやアルミニウム系金属等からなる金属層５ｃの３層構造となっている。そして、真性アモルファスシリコン層５ａ、ｎ型アモルファスシリコン層５ｂ及び金属層５ｃは、ドレイン電極１３形成領域における半導体薄膜８、オーミックコンタクト層１１及びドレイン電極１３に接続されている。   Data lines 5 are provided at predetermined positions on the upper surface of the gate insulating film 7. The data line 5 has a three-layer structure of an intrinsic amorphous silicon layer 5a, an n-type amorphous silicon layer 5b, and a metal layer 5c made of chromium, an aluminum-based metal, or the like in order from the bottom. The intrinsic amorphous silicon layer 5a, the n-type amorphous silicon layer 5b, and the metal layer 5c are connected to the semiconductor thin film 8, the ohmic contact layer 11, and the drain electrode 13 in the drain electrode 13 formation region.

ソース電極１２のチャネル保護膜９側の上面及びそのチャネル幅Ｗ方向の両側におけるチャネル保護膜９とゲート絶縁膜７の上面にはＩＴＯ等からなる一方の導電性被覆膜１４が設けられている。ドレイン電極１３とその近傍のデータライン５の金属層５ｃの上面及びそのチャネル幅Ｗ方向の両側におけるチャネル保護膜９とゲート絶縁膜７の上面にはＩＴＯ等からなる他方の導電性被覆膜１５が設けられている。この場合、各導電性被覆膜１４、１５のチャネル幅Ｗ方向の幅はソース電極１２及びドレイン電極１３の同方向の幅よりも幅広とされている。また、チャネル保護膜９上に延出されたソース電極１２及びドレイン電極１３の各先端は各導電性被覆膜１４、１５に覆われていない。また、他方の導電性被覆膜１５はドレイン電極１３から該ドレイン電極１３に接続されたデータライン（ドレイン配線）５の一部に跨るように延出されている。   On the upper surface of the source electrode 12 on the channel protective film 9 side and on the upper surfaces of the channel protective film 9 and the gate insulating film 7 on both sides in the channel width W direction, one conductive coating film 14 made of ITO or the like is provided. . The other conductive coating film 15 made of ITO or the like is formed on the upper surface of the drain electrode 13 and the metal layer 5c of the data line 5 in the vicinity thereof and the upper surfaces of the channel protective film 9 and the gate insulating film 7 on both sides in the channel width W direction. Is provided. In this case, the width of each of the conductive coating films 14 and 15 in the channel width W direction is wider than the width of the source electrode 12 and the drain electrode 13 in the same direction. The tips of the source electrode 12 and the drain electrode 13 extending on the channel protective film 9 are not covered with the conductive coating films 14 and 15. The other conductive coating film 15 extends from the drain electrode 13 so as to extend over a part of the data line (drain wiring) 5 connected to the drain electrode 13.

ここで、チャネル保護膜９の外側におけるゲート電極６上において、半導体薄膜８と各オーミックコンタクト層１０、１１との重合部分は、チャネル領域の外側領域であり、各オーミックコンタクト領域１６、１７を形成している。そして、一方のオーミックコンタクト領域１６における半導体薄膜８、一方のオーミックコンタクト層１０及びソース電極１２のチャネル幅Ｗ方向の両端面は、当該両端面に接触して設けられた一方の導電性被覆膜１４によって完全に覆われている。また、他方のオーミックコンタクト領域１７における半導体薄膜８、他方のオーミックコンタクト層１１及びドレイン電極１３のチャネル幅Ｗ方向の両端面は、当該両端面に接触して設けられた他方の導電性被覆膜１５によって完全に覆われている。   Here, on the gate electrode 6 outside the channel protective film 9, the overlapping portion of the semiconductor thin film 8 and the ohmic contact layers 10 and 11 is an outer region of the channel region, and forms the ohmic contact regions 16 and 17. is doing. The both ends of the semiconductor thin film 8, the one ohmic contact layer 10 and the source electrode 12 in the one ohmic contact region 16 in the channel width W direction are in contact with the both ends. 14 is completely covered. Also, the other conductive coating film provided in contact with both end surfaces of the semiconductor thin film 8, the other ohmic contact layer 11 and the drain electrode 13 in the channel width W direction of the other ohmic contact region 17 is provided. 15 is completely covered.

そして、ゲート電極６、ゲート絶縁膜７、半導体薄膜８、チャネル保護膜９、一対のオーミックコンタクト層１０、１１、ソース電極１２、ドレイン電極１３及び一対の導電性被覆膜１４、１５により、チャネル保護膜型でボトムゲート構造の薄膜トランジスタ３が構成されている。   The gate electrode 6, the gate insulating film 7, the semiconductor thin film 8, the channel protective film 9, the pair of ohmic contact layers 10 and 11, the source electrode 12, the drain electrode 13, and the pair of conductive coating films 14 and 15, A protective film type thin film transistor 3 having a bottom gate structure is formed.

ソース電極１２のチャネル保護膜９側とは反対側の上面及びゲート絶縁膜７の上面の所定の箇所にはＩＴＯ等からなる画素電極２が設けられている。この場合、一方の導電性被覆膜１４は画素電極２に連続するように一体的に形成されている。画素電極２及び薄膜トランジスタ３等を含むゲート絶縁膜７の上面には窒化シリコンからなるオーバーコート膜１８が設けられている。   A pixel electrode 2 made of ITO or the like is provided at a predetermined location on the upper surface of the source electrode 12 opposite to the channel protective film 9 side and the upper surface of the gate insulating film 7. In this case, one conductive coating film 14 is integrally formed so as to be continuous with the pixel electrode 2. An overcoat film 18 made of silicon nitride is provided on the upper surface of the gate insulating film 7 including the pixel electrode 2 and the thin film transistor 3.

ここで、この薄膜トランジスタパネルにおける薄膜トランジスタ３では、図１においてゲート電極６の右側つまり走査ライン４と平行する方向の右側に一方のオーミックコンタクト層１０及びソース電極１２が設けられ、その反対の左側に他方のオーミックコンタクト層１１及びドレイン電極１３が設けられている。この場合、半導体薄膜８のチャネル長Ｌはチャネル保護膜９の左右方向の長さとなっており、チャネル幅Ｗはオーミックコンタクト層１０、１１の上下方向の長さとなっている。   Here, in the thin film transistor 3 in this thin film transistor panel, one ohmic contact layer 10 and the source electrode 12 are provided on the right side of the gate electrode 6 in FIG. The ohmic contact layer 11 and the drain electrode 13 are provided. In this case, the channel length L of the semiconductor thin film 8 is the length of the channel protective film 9 in the left-right direction, and the channel width W is the length of the ohmic contact layers 10 and 11 in the vertical direction.

ところで、この薄膜トランジスタパネルにおける薄膜トランジスタ３では、各オーミックコンタクト領域１６、１７における半導体薄膜８及び各オーミックコンタクト層１０、１１のチャネル幅Ｗ方向両端面は、ソース電極１２及びドレイン電極１３のチャネル幅Ｗ方向の幅よりも幅広とされた各導電性被覆膜１４、１５によって完全に覆われている。また、各導電性被覆膜１４、１５は、ソース電極１２及びドレイン電極１３に接続されているので、ソース電極１２及びドレイン電極１３と同電位となる。   By the way, in the thin film transistor 3 in this thin film transistor panel, both end faces of the semiconductor thin film 8 and the ohmic contact layers 10 and 11 in the ohmic contact regions 16 and 17 in the channel width W direction are in the channel width W direction of the source electrode 12 and the drain electrode 13. It is completely covered by the respective conductive coating films 14 and 15 having a width wider than the width of the conductive coating films 14 and 15. In addition, since the conductive coating films 14 and 15 are connected to the source electrode 12 and the drain electrode 13, they have the same potential as the source electrode 12 and the drain electrode 13.

この結果、各オーミックコンタクト領域１６、１７における半導体薄膜８及び各オーミックコンタクト層１０、１１には、そのチャネル幅Ｗ方向両端面も含んで、ソース電極１２及びドレイン電極１３と同電位である各導電性被覆膜１４、１５とゲート電極６との間で形成される、ガラス基板１に対して垂直方向の縦電界がかかり、これにより、Ｖｇ−Ｉｄ特性のマイナス側へのシフトを抑制することができることが確認された。なお、ゲート電極６に印加されるゲートオン電圧とゲートオフ電圧とは、その絶対値が同じであることが望ましい。   As a result, the semiconductor thin film 8 and the ohmic contact layers 10 and 11 in the ohmic contact regions 16 and 17 include the both ends of the channel width W direction, and each conductive material having the same potential as the source electrode 12 and the drain electrode 13. The vertical electric field in the direction perpendicular to the glass substrate 1 formed between the conductive coating films 14 and 15 and the gate electrode 6 is applied, thereby suppressing the negative shift of the Vg-Id characteristic. It was confirmed that It is desirable that the gate-on voltage and the gate-off voltage applied to the gate electrode 6 have the same absolute value.

次に、この薄膜トランジスタパネルの製造方法の一例について説明する。まず、図３（Ａ）、（Ｂ）に示すように、ガラス基板１の上面の所定の個所に、スパッタ法により成膜されたクロム等からなる金属膜をフォトリソグラフィ法によりパターニングすることにより、ゲート電極６及び走査ライン４を形成する。次に、ゲート電極６及び走査ライン４を含むガラス基板１の上面に、ＣＶＤ法により、窒化シリコンからなるゲート絶縁膜７、真性アモルファスシリコン膜２１及び窒化シリコン膜２２を連続して成膜する。   Next, an example of a method for manufacturing the thin film transistor panel will be described. First, as shown in FIGS. 3A and 3B, by patterning a metal film made of chromium or the like formed by sputtering at a predetermined position on the upper surface of the glass substrate 1 by photolithography, A gate electrode 6 and a scanning line 4 are formed. Next, a gate insulating film 7 made of silicon nitride, an intrinsic amorphous silicon film 21 and a silicon nitride film 22 are successively formed on the upper surface of the glass substrate 1 including the gate electrode 6 and the scanning line 4 by a CVD method.

次に、窒化シリコン膜２２の上面のチャネル保護膜形成領域に、塗布されたレジスト膜をフォトリソグラフィ法によりパターニングすることにより、レジスト膜２３を形成する。次に、レジスト膜２３をマスクとして、窒化シリコン膜２２をエッチングすると、図４（Ａ）、（Ｂ）に示すように、レジスト膜２３下にチャネル保護膜９が形成される。次に、レジスト膜２３を剥離する。   Next, a resist film 23 is formed in the channel protective film formation region on the upper surface of the silicon nitride film 22 by patterning the applied resist film by photolithography. Next, when the silicon nitride film 22 is etched using the resist film 23 as a mask, the channel protective film 9 is formed under the resist film 23 as shown in FIGS. Next, the resist film 23 is peeled off.

次に、図５（Ａ）、（Ｂ）に示すように、チャネル保護膜９を含む真性アモルファスシリコン膜２１の上面に、ＣＶＤ法により、ｎ型アモルファスシリコン膜２４を成膜し、次いで、スパッタ法により、クロム等からなる金属膜２５を成膜する。次に、金属膜２５の上面の各所定の箇所に、塗布されたレジスト膜をフォトリソグラフィ法によりパターニングすることにより、レジスト膜２６ａ、２６ｂを形成する。この場合、レジスト膜２６ａはソース電極１２を形成するためのものであり、レジスト膜２６ｂはドレイン電極１３及びデータライン５を形成するためのものである。   Next, as shown in FIGS. 5A and 5B, an n-type amorphous silicon film 24 is formed by CVD on the upper surface of the intrinsic amorphous silicon film 21 including the channel protective film 9, and then sputtered. A metal film 25 made of chromium or the like is formed by the method. Next, resist films 26a and 26b are formed by patterning the applied resist film at a predetermined position on the upper surface of the metal film 25 by a photolithography method. In this case, the resist film 26 a is for forming the source electrode 12, and the resist film 26 b is for forming the drain electrode 13 and the data line 5.

次に、レジスト膜２６ａ、２６ｂ（チャネル保護膜９を含む）をマスクとして、金属膜２５、ｎ型アモルファスシリコン膜２４及び真性アモルファスシリコン膜２１を順次エッチングすると、図６（Ａ）、（Ｂ）に示すようになる。すなわち、レジスト膜２６ａ下にソース電極１２及びオーミックコンタクト層１０が形成され、レジスト膜２６ｂ下にドレイン電極１３及びオーミックコンタクト層１１が形成され、両オーミックコンタクト層１０、１１及びチャネル保護膜９下に半導体薄膜８が形成される。また、レジスト膜２６ｂ下に金属膜５ｃ、ｎ型アモルファスシリコン膜５ｂ及び真性アモルファスシリコン膜５ａからなる３層構造のデータライン５が形成される。次に、レジスト膜２６ａ、２６ｂを剥離する。   Next, using the resist films 26a and 26b (including the channel protective film 9) as a mask, the metal film 25, the n-type amorphous silicon film 24, and the intrinsic amorphous silicon film 21 are sequentially etched to obtain FIGS. 6A and 6B. As shown. That is, the source electrode 12 and the ohmic contact layer 10 are formed under the resist film 26a, the drain electrode 13 and the ohmic contact layer 11 are formed under the resist film 26b, and under both the ohmic contact layers 10 and 11 and the channel protective film 9 A semiconductor thin film 8 is formed. Further, the data line 5 having a three-layer structure including the metal film 5c, the n-type amorphous silicon film 5b, and the intrinsic amorphous silicon film 5a is formed under the resist film 26b. Next, the resist films 26a and 26b are peeled off.

この場合、レジスト膜２６ａ、２６ｂ（チャネル保護膜９を含む）をマスクとして、金属膜２５、ｎ型アモルファスシリコン膜２４及び真性アモルファスシリコン膜２１を順次エッチングして、ソース電極１２、ドレイン電極１３、一対のオーミックコンタクト層１０、１１及び半導体薄膜８を形成しているので、ソース電極１２及びドレイン電極１３を一対のオーミックコンタクト層１０、１１及び半導体薄膜８と別のフォトリソグラフィ工程で形成する場合と比較して、フォトリソグラフィ工程数を少なくすることができる。   In this case, the metal film 25, the n-type amorphous silicon film 24, and the intrinsic amorphous silicon film 21 are sequentially etched using the resist films 26a and 26b (including the channel protective film 9) as a mask, so that the source electrode 12, the drain electrode 13, Since the pair of ohmic contact layers 10 and 11 and the semiconductor thin film 8 are formed, the source electrode 12 and the drain electrode 13 are formed in a separate photolithography process from the pair of ohmic contact layers 10 and 11 and the semiconductor thin film 8. In comparison, the number of photolithography processes can be reduced.

なお、ソース電極１２及びドレイン電極１３を形成した後に、レジスト膜２６ａ、２６ｂを剥離し、次いで、ソース電極１２及びドレイン電極１３（チャネル保護膜９を含む）をマスクとして、ｎ型アモルファスシリコン膜２４及び真性アモルファスシリコン膜２１を順次エッチングして、一対のオーミックコンタクト層１０、１１及び半導体薄膜８を形成するようにしてもよい。   After forming the source electrode 12 and the drain electrode 13, the resist films 26 a and 26 b are peeled off, and then the n-type amorphous silicon film 24 using the source electrode 12 and the drain electrode 13 (including the channel protective film 9) as a mask. The pair of ohmic contact layers 10 and 11 and the semiconductor thin film 8 may be formed by sequentially etching the intrinsic amorphous silicon film 21.

次に、図７（Ａ）、（Ｂ）に示すように、ソース電極１２、ドレイン電極１３及びデータライン５を含むゲート絶縁膜７の上面に、スパッタ法により、ＩＴＯからなる画素電極形成用膜２７を成膜する。次に、画素電極形成用膜２７の上面の各所定の箇所に、塗布されたレジスト膜をフォトリソグラフィ法によりパターニングすることにより、レジスト膜２８ａ、２８ｂを形成する。この場合、レジスト膜２８ａは画素電極２及び一方の導電性被覆膜１４を形成するためのものであり、レジスト膜２８ｂは他方の導電性被覆膜１５を形成するためのものである。   Next, as shown in FIGS. 7A and 7B, a pixel electrode forming film made of ITO is formed on the upper surface of the gate insulating film 7 including the source electrode 12, the drain electrode 13 and the data line 5 by sputtering. 27 is deposited. Next, the resist film 28a, 28b is formed by patterning the applied resist film at a predetermined position on the upper surface of the pixel electrode forming film 27 by photolithography. In this case, the resist film 28 a is for forming the pixel electrode 2 and one conductive coating film 14, and the resist film 28 b is for forming the other conductive coating film 15.

次に、レジスト膜２８ａ、２８ｂをマスクとして画素電極形成用膜２７をエッチングすると、図８（Ａ）、（Ｂ）に示すようになる。すなわち、レジスト膜２８ａ下に画素電極２及び一方の導電性被覆膜１４が形成され、レジスト膜２８ｂ下に他方の導電性被覆膜１５が形成される。この場合、一対の導電性被覆膜１４、１５は、画素電極２と同一の材料によって画素電極２の形成と同時に形成しているので、フォトリソグラフィ工程数が増加しないようにすることができる。   Next, when the pixel electrode forming film 27 is etched using the resist films 28a and 28b as a mask, the result is as shown in FIGS. That is, the pixel electrode 2 and one conductive coating film 14 are formed under the resist film 28a, and the other conductive coating film 15 is formed under the resist film 28b. In this case, the pair of conductive coating films 14 and 15 are formed of the same material as the pixel electrode 2 at the same time as the pixel electrode 2 is formed, so that the number of photolithography processes can be prevented from increasing.

また、この状態では、一方の導電性被覆膜１４下のソース電極１２、オーミックコンタクト層１０及び半導体薄膜８のチャネル幅Ｗ方向の両端面は、一方の導電性被覆膜１４によって完全に覆われている。また、他方の導電性被覆膜１５下のドレイン電極１３、オーミックコンタクト層１１及び半導体薄膜８のチャネル幅Ｗ方向の両端面は、他方の導電性被覆膜１５によって完全に覆われている。   In this state, the source electrode 12, the ohmic contact layer 10, and the semiconductor thin film 8 under the one conductive coating film 14 are completely covered by the one conductive coating film 14 in the channel width W direction. It has been broken. Further, both end surfaces in the channel width W direction of the drain electrode 13, the ohmic contact layer 11, and the semiconductor thin film 8 under the other conductive coating film 15 are completely covered with the other conductive coating film 15.

次に、レジスト膜２８ａ、２８ｂを剥離する。次に、図１及び図２（Ａ）、（Ｂ）に示すように、画素電極２等を含むゲート絶縁膜７の上面に、プラズマＣＶＤ法により、窒化シリコンからなるオーバーコート膜１８を成膜する。かくして、図１及び図２（Ａ）、（Ｂ）に示す薄膜トランジスタパネルが得られる。   Next, the resist films 28a and 28b are peeled off. Next, as shown in FIGS. 1 and 2A and 2B, an overcoat film 18 made of silicon nitride is formed on the upper surface of the gate insulating film 7 including the pixel electrode 2 and the like by plasma CVD. To do. Thus, the thin film transistor panel shown in FIGS. 1 and 2A and 2B is obtained.

（第２実施形態）
図９はこの発明の第２実施形態としての薄膜トランジスタパネルの要部の透過平面図を示し、図１０（Ａ）は図９のＸA−ＸAに沿う断面図を示し、図１０（Ｂ）は図９のＸB−ＸBに沿う断面図を示す。この薄膜トランジスタパネルにおいて、図１及び図２（Ａ）、（Ｂ）に示す薄膜トランジスタパネルと異なる点は、画素電極２及び一方の導電性被覆膜１４をオーバーコート膜１８の上面に該オーバーコート膜１８に設けられたコンタクトホール１９を介してソース電極１２に接続させて設け、且つ、他方の導電性被覆膜１５をオーバーコート膜１８の上面に該オーバーコート膜１８に設けられたコンタクトホール２０を介してドレイン電極１３に接続させて設けた点である。 (Second Embodiment)
9 shows a transmission plan view of the main part of a thin film transistor panel as a second embodiment of the present invention, FIG. 10A shows a cross-sectional view along X A -X A of FIG. 9, and FIG. Shows a cross-sectional view along X B -X B of FIG. The thin film transistor panel is different from the thin film transistor panel shown in FIGS. 1, 2 </ b> A, and 2 </ b> B in that the pixel electrode 2 and one conductive coating film 14 are placed on the upper surface of the overcoat film 18. The other conductive coating film 15 is provided on the upper surface of the overcoat film 18 through the contact hole 19 provided in the overcoat film 18. This is a point provided by being connected to the drain electrode 13 via.

（第３実施形態）
図１１はこの発明の第３実施形態としての薄膜トランジスタパネルの要部の透過平面図を示し、図１２（Ａ）は図１０のXIIA−XIIAに沿う断面図を示し、図１２（Ｂ）は図１１のXIIB−XIIBに沿う断面図を示す。この薄膜トランジスタパネルにおいて、図１及び図２（Ａ）、（Ｂ）に示す薄膜トランジスタパネルと大きく異なる点は、薄膜トランジスタ３をチャネルエッチ型とした点である。 (Third embodiment)
FIG. 11 shows a transmission plan view of a main part of a thin film transistor panel as a third embodiment of the present invention, FIG. 12A shows a cross-sectional view along XII A -XII A in FIG. 10, and FIG. FIG. 11 shows a cross-sectional view along XII B -XII B in FIG. This thin film transistor panel is largely different from the thin film transistor panel shown in FIGS. 1 and 2A and 2B in that the thin film transistor 3 is a channel etch type.

すなわち、この薄膜トランジスタパネルにおける薄膜トランジスタ３では、チャネル保護膜９を備えておらず、ゲート絶縁膜７の上面の所定の箇所に平面ほぼ十字形状に設けられた比較的厚めの半導体薄膜８の上面において、一対のオーミックコンタクト層１０、１１下以外の領域に凹部８ａが形成されている。   That is, in the thin film transistor 3 in this thin film transistor panel, the channel protective film 9 is not provided, and the upper surface of the relatively thick semiconductor thin film 8 provided in a substantially cross-shaped plane at a predetermined position on the upper surface of the gate insulating film 7 A recess 8 a is formed in a region other than under the pair of ohmic contact layers 10 and 11.

また、この薄膜トランジスタ３では、各オーミックコンタクト領域１６、１７がソース電極１２及びドレイン電極１３のゲート電極６側の端面までとなるので、これらの端面の部分を各導電性被覆膜１４、１５で覆うようにする。なお、この場合の薄膜トランジスタ３はチャネルエッチ型であるので、チャネル長Ｌを上記第１実施形態の場合よりもある程度短くすることが可能となる。   In the thin film transistor 3, the ohmic contact regions 16 and 17 extend to the end surfaces of the source electrode 12 and the drain electrode 13 on the side of the gate electrode 6, so that these end surfaces are covered with the conductive coating films 14 and 15. Cover. Since the thin film transistor 3 in this case is a channel etch type, the channel length L can be made somewhat shorter than in the case of the first embodiment.

次に、この薄膜トランジスタパネルの製造方法の一例について簡単に説明する。まず、ゲート絶縁膜７の上面に比較的厚く成膜された真性アモルファスシリコン膜をフォトリソグラフィ法によりパターニングして比較的厚い半導体薄膜８を平面ほぼ十字状に形成し、この半導体薄膜８を含むゲート絶縁膜７の上面に連続して成膜されたｎ型アモルファスシリコン膜及び金属膜をフォトリソグラフィ法により順次パターニングしてソース電極１２、ドレイン電極１３及び一対のオーミックコンタクト層１０、１１を形成する。この場合、一対のオーミックコンタクト層１０、１１下以外の領域における半導体薄膜８の上面には、オーバーエッチングにより、凹部８ａが形成される。   Next, an example of a method for manufacturing the thin film transistor panel will be briefly described. First, an intrinsic amorphous silicon film formed relatively thick on the upper surface of the gate insulating film 7 is patterned by photolithography to form a relatively thick semiconductor thin film 8 in a plane substantially cross shape, and a gate including this semiconductor thin film 8 is formed. The n-type amorphous silicon film and the metal film continuously formed on the upper surface of the insulating film 7 are sequentially patterned by photolithography to form the source electrode 12, the drain electrode 13, and the pair of ohmic contact layers 10 and 11. In this case, a recess 8 a is formed by over-etching on the upper surface of the semiconductor thin film 8 in a region other than under the pair of ohmic contact layers 10 and 11.

次に、ソース電極１２及びドレイン電極１３等を含むゲート絶縁膜７の上面に成膜されたＩＴＯ膜をフォトリソグラフィ法によりパターニングして画素電極２及び一対の導電性被覆膜１４、１５を形成する。したがって、この場合も、フォトリソグラフィ工程数が増加することはない。なお、半導体薄膜８を形成するためのそれ専用のフォトリソグラフィ工程が必要となるが、チャネル保護膜を形成するためのフォトリソグラフィ工程が不要となるので、全体としてのフォトリソグラフィ工程数が増加することはない。   Next, the ITO film formed on the upper surface of the gate insulating film 7 including the source electrode 12 and the drain electrode 13 is patterned by photolithography to form the pixel electrode 2 and the pair of conductive coating films 14 and 15. To do. Therefore, also in this case, the number of photolithography processes does not increase. Note that a dedicated photolithography process for forming the semiconductor thin film 8 is required, but a photolithography process for forming the channel protective film is not necessary, and the number of photolithography processes as a whole increases. There is no.

（第４実施形態）
図１３はこの発明の第４実施形態としての薄膜トランジスタパネルの要部の透過平面図を示し、図１４（Ａ）は図１３のXIVA−XIVAに沿う断面図を示し、図１４（Ｂ）は図１３のXIVB−XIVBに沿う断面図を示す。この薄膜トランジスタパネルにおいて、図１１及び図１２（Ａ）、（Ｂ）に示す薄膜トランジスタパネルと異なる点は、画素電極２及び一方の導電性被覆膜１４をオーバーコート膜１８の上面に該オーバーコート膜１８に設けられたコンタクトホール１９を介してソース電極１２に接続させて設け、且つ、他方の導電性被覆膜１５をオーバーコート膜１８の上面に該オーバーコート膜１８に設けられたコンタクトホール２０を介してドレイン電極１３に接続させて設けた点である。 (Fourth embodiment)
FIG. 13 shows a transmission plan view of the main part of a thin film transistor panel as a fourth embodiment of the present invention, FIG. 14A shows a cross-sectional view along XIV A -XIV A of FIG. 13, and FIG. Shows a cross-sectional view along XIV B -XIV B in FIG. The thin film transistor panel is different from the thin film transistor panel shown in FIGS. 11, 12 </ b> A, and 12 </ b> B in that the pixel electrode 2 and one conductive coating film 14 are formed on the upper surface of the overcoat film 18. The other conductive coating film 15 is provided on the upper surface of the overcoat film 18 through the contact hole 19 provided in the overcoat film 18. This is a point provided by being connected to the drain electrode 13 via.

（第５実施形態）
図１５はこの発明の第５実施形態としての薄膜トランジスタパネルの要部の透過平面図を示し、図１６（Ａ）は図１５のXVIA−XVIAに沿う断面図を示し、図１６（Ｂ）は図１５のXVIB−XVIBに沿う断面図を示す。この薄膜トランジスタパネルにおいて、図１及び図２（Ａ）、（Ｂ）に示す薄膜トランジスタパネルと異なる点は、一方の導電性被覆膜１４を省略した点である。 (Fifth embodiment)
15 shows a transmission plan view of the main part of the thin film transistor panel as the fifth embodiment of the present invention, FIG. 16A shows a cross-sectional view along XVI A -XVI A of FIG. 15, and FIG. Shows a sectional view along XVI B -XVI B in FIG. The thin film transistor panel is different from the thin film transistor panel shown in FIGS. 1 and 2A and 2B in that one conductive coating film 14 is omitted.

なお、図１及び図２（Ａ）、（Ｂ）に示す場合において、他方の導電性被覆膜１５を省略してもよい。また、図９及び図１０（Ａ）、（Ｂ）に示す場合において、一対の導電性被覆膜１４、１５のうちのいずれか一方を省略してもよい。また、図１１及び図１２（Ａ）、（Ｂ）に示す場合において、一対の導電性被覆膜１４、１５のうちのいずれか一方を省略してもよい。さらに、図１３及び図１４（Ａ）、（Ｂ）に示す場合において、一対の導電性被覆膜１４、１５のうちのいずれか一方を省略してもよい。   In the case shown in FIG. 1 and FIGS. 2A and 2B, the other conductive coating film 15 may be omitted. Further, in the case shown in FIGS. 9 and 10A and 10B, any one of the pair of conductive coating films 14 and 15 may be omitted. Further, in the case shown in FIGS. 11 and 12A and 12B, either one of the pair of conductive coating films 14 and 15 may be omitted. Furthermore, in the case shown in FIG. 13 and FIGS. 14A and 14B, either one of the pair of conductive coating films 14 and 15 may be omitted.

（第６実施形態）
図１７はこの発明の第６実施形態としての薄膜トランジスタパネルの要部の透過平面図を示し、図１８（Ａ）は図１７のXVIIIA−XVIIIAに沿う断面図を示し、図１８（Ｂ）は図１７のXVIIIB−XVIIIBに沿う断面図を示す。この薄膜トランジスタパネルにおいて、図９及び図１０（Ａ）、（Ｂ）に示す薄膜トランジスタパネルと異なる点は、一方の導電性被覆膜１４を省略し、他方の導電性被覆膜１５をドレイン電極１３に接続させずにオーバーコート膜１８の上面に島状に設けた点である。すなわち、ドレイン電極１３上におけるオーバーコート膜１８にコンタクトホール２０を形成することがレイアウト的に困難な場合には、他方の導電性被覆膜１５をドレイン電極１３に電気的に接続させずにオーバーコート膜１８の上面に島状に設けるようにしてもよい。 (Sixth embodiment)
FIG. 17 shows a transmission plan view of the main part of a thin film transistor panel as a sixth embodiment of the present invention, FIG. 18A shows a cross-sectional view along XVIII A -XVIII A of FIG. 17, and FIG. FIG. 17 shows a cross-sectional view along XVIII B -XVIII B in FIG. The thin film transistor panel is different from the thin film transistor panel shown in FIGS. 9, 10 </ b> A, and 10 </ b> B in that one conductive coating film 14 is omitted and the other conductive coating film 15 is replaced with the drain electrode 13. This is that it is provided in an island shape on the upper surface of the overcoat film 18 without being connected to. That is, when it is difficult to form the contact hole 20 in the overcoat film 18 on the drain electrode 13 in terms of layout, the other conductive coating film 15 is not electrically connected to the drain electrode 13 and is overcoated. It may be provided in an island shape on the upper surface of the coating film 18.

この場合、他方の導電性被覆膜１５は島状であってドレイン電極１３と電気的に絶縁されているが、オーバーコート膜１８を介してドレイン電極１３と対向する部分において容量結合による縦電界が形成され、且つ、オーバーコート膜１８及びゲート絶縁膜７を介してゲート電極６と対向する部分において容量結合による縦電界が形成される。   In this case, the other conductive coating film 15 has an island shape and is electrically insulated from the drain electrode 13, but a vertical electric field due to capacitive coupling is formed at a portion facing the drain electrode 13 through the overcoat film 18. And a vertical electric field due to capacitive coupling is formed at a portion facing the gate electrode 6 through the overcoat film 18 and the gate insulating film 7.

この発明の第１実施形態としての薄膜トランジスタパネルの要部の透過平面図。FIG. 3 is a transmission plan view of the main part of the thin film transistor panel as the first embodiment of the present invention. （Ａ）は図１のIIA−IIAに沿う断面図、（Ｂ）は図１のIIB−IIBに沿う断面図。(A) is a sectional view taken along the II A -II A in FIG. 1, (B) is a sectional view taken along the II B -II B of FIG. 第１実施形態としての薄膜トランジスタパネルの製造方法の一例における当初の工程を説明するために示すものであって、（Ａ）は図１同様の透過平面図、（Ｂ）はそのIIIB−IIIBに沿う断面図。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view for explaining an initial process in an example of a method of manufacturing a thin film transistor panel according to a first embodiment, wherein (A) is a transmission plan view similar to FIG. 1 and (B) is its III B -III B FIG. （Ａ）は図３に続く工程の透過平面図、（Ｂ）はそのIVB−IVBに沿う断面図。(A) is transparent plan view of a step subsequent to FIG. 3, (B) is a sectional view taken along the IV B -IV B. （Ａ）は図４に続く工程の透過平面図、（Ｂ）はそのＶB−ＶBに沿う断面図。(A) is transparent plan view of a step subsequent to FIG. 4, (B) is a sectional view along its V B -V B. （Ａ）は図５に続く工程の透過平面図、（Ｂ）はそのVIB−VIBに沿う断面図。(A) is transparent plan view of a step subsequent to FIG. 5, (B) is a sectional view taken along the VI B -VI B. （Ａ）は図６に続く工程の透過平面図、（Ｂ）はそのVIIB−VIIBに沿う断面図。(A) is transparent plan view of a step subsequent to FIG. 6, (B) is a sectional view along its VII B -VII B. （Ａ）は図７に続く工程の透過平面図、（Ｂ）はそのVIIIB−VIIIBに沿う断面図。(A) is transparent plan view of a step subsequent to FIG. 7, (B) is a sectional view along its VIII B -VIII B. この発明の第２実施形態としての薄膜トランジスタパネルの要部の透過平面図。The permeation | transmission top view of the principal part of the thin-film transistor panel as 2nd Embodiment of this invention. （Ａ）は図９のＸA−ＸAに沿う断面図、（Ｂ）は図９のＸB−ＸBに沿う断面図。(A) is a sectional view taken along the X A -X A in FIG. 9, (B) is a sectional view taken along the X B -X B in FIG. この発明の第３実施形態としての薄膜トランジスタパネルの要部の透過平面図。The permeation | transmission top view of the principal part of the thin-film transistor panel as 3rd Embodiment of this invention. （Ａ）は図１１のXIIA−XIIAに沿う断面図、（Ｂ）は図１１のXIIB−XIIBに沿う断面図。(A) is a sectional view taken along the XII A XII A in FIG. 11, (B) is a sectional view taken along the XII B XII B in Fig. 11. この発明の第４実施形態としての薄膜トランジスタパネルの要部の透過平面図。The permeation | transmission top view of the principal part of the thin-film transistor panel as 4th Embodiment of this invention. （Ａ）は図１３のXIVA−XIVAに沿う断面図、（Ｂ）は図１３のXIVB−XIVBに沿う断面図。(A) is a sectional view taken along the XIV A XIV A in FIG. 13, (B) is a sectional view taken along the XIV B XIV B in FIG. この発明の第５実施形態としての薄膜トランジスタパネルの要部の透過平面図。The permeation | transmission top view of the principal part of the thin-film transistor panel as 5th Embodiment of this invention. （Ａ）は図１５のXVIA−XVIAに沿う断面図、（Ｂ）は図１５のXVIB−XVIBに沿う断面図。(A) is a sectional view taken along the XVI A -XVI A in FIG. 15, (B) is a sectional view taken along the XVI B -XVI B in FIG. この発明の第５実施形態としての薄膜トランジスタパネルの要部の透過平面図。The permeation | transmission top view of the principal part of the thin-film transistor panel as 5th Embodiment of this invention. （Ａ）は図１７のXVIIIA−XVIIIAに沿う断面図、（Ｂ）は図１７のXVIIIB−XVIIIBに沿う断面図。(A) is a sectional view taken along XVIII A -xviii A in FIG. 17, (B) is a sectional view taken along XVIII B -xviii B of Figure 17.

符号の説明Explanation of symbols

１ ガラス基板
２ 画素電極
３ 薄膜トランジスタ
４ 走査ライン
５ データライン
６ ゲート電極
７ ゲート絶縁膜
８ 半導体薄膜
９ チャネル保護膜
１０、１１ オーミックコンタクト層
１２ ソース電極
１３ ドレイン電極
１４、１５ 導電性被覆膜
１６、１７ オーミックコンタクト領域
１８ オーバーコート膜 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Pixel electrode 3 Thin film transistor 4 Scan line 5 Data line 6 Gate electrode 7 Gate insulating film 8 Semiconductor thin film 9 Channel protective film 10, 11 Ohmic contact layer 12 Source electrode 13 Drain electrode 14, 15 Conductive coating film 16, 17 Ohmic contact region 18 Overcoat film

Claims (2)

ゲート電極上にゲート絶縁膜を介して半導体薄膜が設けられた薄膜トランジスタと、前記薄膜トランジスタのソース電極に電気的に接続された画素電極と、を有し、
前記薄膜トランジスタが、前記半導体薄膜上に設けられたチャネル保護膜と、前記チャネル保護膜上及び前記半導体薄膜上に設けられたオーミックコンタクト層と、前記オーミックコンタクト層上に設けられた前記ソース電極及びドレイン電極とを有し、
前記ソース電極及び前記ドレイン電極が、前記チャネル長方向に平行な方向に延伸する２つの辺を有している薄膜トランジスタパネルであって、
前記画素電極と同一の層として形成されるとともに、前記画素電極とは電気的に絶縁された導電性被覆膜を有し、
前記導電性被覆膜は、少なくとも一部が前記２つの辺に重なるように、前記ドレイン電極上に前記ドレイン電極よりも幅広に形成され、
前記オーミックコンタクト層は、前記ソース電極及び前記ドレイン電極と同一のマスクに基づいてパターニングされていて、
前記半導体薄膜は、前記ソース電極及び前記ドレイン電極と同一のマスク及び前記チャネル保護膜に基づいてパターニングされていて、
前記チャネル保護膜のドレイン電極側の外側であって且つ前記ゲート電極上における、前記半導体薄膜、前記オーミックコンタクト層及び前記ドレイン電極のチャネル幅方向の両端面が、当該両端面に接触して設けられた前記導電性被覆膜によって覆われており、前記チャネル保護膜の前記ソース電極側の外側であって且つ前記ゲート電極上における、前記半導体薄膜、前記オーミックコンタクト層及び前記ソース電極のチャネル幅方向の両端面が、当該両端面に接触して設けられた前記画素電極によって覆われていることを特徴とする薄膜トランジスタパネル。 A thin film transistor in which a semiconductor thin film is provided on a gate electrode through a gate insulating film, and a pixel electrode electrically connected to a source electrode of the thin film transistor,
Said thin film transistor, wherein the channel protective film provided on the semiconductor thin film, an ohmic contact layer formed on the channel protective film and the semiconductor thin film, the source electrode and the drain provided on the ohmic contact layer An electrode ,
The thin film transistor panel, wherein the source electrode and the drain electrode have two sides extending in a direction parallel to the channel length direction,
It is formed as the same layer as the pixel electrode, and has a conductive coating film that is electrically insulated from the pixel electrode,
The conductive coating film is formed wider on the drain electrode than the drain electrode so that at least a part thereof overlaps the two sides,
The ohmic contact layer is patterned based on the same mask as the source electrode and the drain electrode,
The semiconductor thin film is patterned based on the same mask and the channel protective film as the source electrode and the drain electrode,
Before SL channel protective film on the drain electrode side of the outer and was in and the gate electrode on the semiconductor thin film, both end faces in the channel width direction of the ohmic contact layer and the drain electrode is provided in contact with the end surfaces It was covered by the conductive coating film, in the an outer source electrode side and the gate electrode on the channel protective layer, the semiconductor thin film, the ohmic contact layer and the channel width of the source electrode A thin film transistor panel , wherein both end faces in the direction are covered with the pixel electrodes provided in contact with the both end faces . 前記ソース電極は、前記チャネル長方向に平行な方向に延伸する２つの辺を有し、
前記画素電極は、少なくとも一部がソース側導電性被覆膜として前記ソース電極における前記２つの辺に重なるように、前記ソース電極上に前記ソース電極よりも幅広に形成されていることを特徴とする請求項１に記載の薄膜トランジスタパネル。 The source electrode has two sides extending in a direction parallel to the channel length direction,
The pixel electrode is formed wider on the source electrode than the source electrode so that at least a part thereof overlaps the two sides of the source electrode as a source-side conductive coating film. The thin film transistor panel according to claim 1 .
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