JP5046915B2 - Display device substrate, display device, and method of manufacturing display device substrate - Google Patents

Description

  The present invention relates to a display device substrate used in a display device such as an organic EL (electroluminescence) display device and a liquid crystal display device, a display device using the display device substrate, and a method for manufacturing the display device substrate. is there.

  Thin film transistors (hereinafter also referred to as TFTs), which are elements for independently driving each pixel of a display device, are used in display device substrates used in active matrix organic EL display devices and liquid crystal display devices. It is provided corresponding to each pixel. The thin film transistor is used, for example, as a driver element for controlling light emission of a light emitting element provided for each pixel or as a threshold voltage detecting element for detecting a threshold voltage of the driver element (see, for example, Patent Document 1). ).

By the way, in the thin film transistor, parasitic capacitance exists between the gate electrode and the source electrode and between the gate electrode and the drain electrode. Such a parasitic capacitance of the thin film transistor causes a decrease in writing efficiency when image data is written in the pixel, which in turn causes a decrease in luminance of the display device. In order to solve such a problem, the parasitic capacitance of the thin film transistor may be suppressed, and various methods for reducing the parasitic capacitance have been conventionally devised (for example, see Patent Documents 2 and 3).
JP 2006-209074 A JP 2001-1119029 A JP 2003-46089 A

  A conventional method for reducing the parasitic capacitance of a thin film transistor is to change the structure of the thin film transistor. Therefore, the manufacturing process of the existing display device substrate is greatly changed, resulting in a decrease in productivity and cost increase of the display device substrate and the display device using the display device substrate.

  The present invention has been made in view of the above problems, and the display device substrate, the display device, and the like that can reduce the influence of the parasitic capacitance of the thin film transistor without greatly changing the manufacturing process of the existing display device substrate, It is another object of the present invention to provide a method for manufacturing a substrate for a display device.

In order to solve the above-described problems and achieve the object, a substrate for a display device according to the present invention includes first and second capacitor electrodes constituting a storage capacitor for holding an image data potential, the storage capacitor and the electrical In the display device substrate having a gate electrode, a source electrode, and a drain electrode constituting a transistor connected to the gate electrode, the gate electrode and the first capacitor electrode electrically connected to the gate electrode are formed A substrate, an insulating layer formed on the substrate so as to cover the gate electrode and the first capacitor electrode, the source electrode partially facing the gate electrode through the insulating layer, and the insulation The drain electrode partially facing the gate electrode via a layer, and the second capacitance electrode facing the first capacitance electrode via the insulating layer, the first capacitance electrode and the Thickness of the insulating layer located between the second capacitor electrode is rather smaller than the thickness of the insulating layer located between the drain electrode and between the gate electrode and the source electrode and the gate electrode The second capacitor electrode overlaps with the first capacitor electrode in a plan view, and an outer periphery thereof is located on an inner side of an outer periphery of the first capacitor electrode .

  In the display device substrate of the present invention, a semiconductor layer is formed between the source electrode and the insulating layer and between the drain electrode and the insulating layer.

  In the display device substrate of the present invention, a contact hole penetrating the insulating layer is formed in the insulating layer.

  In addition, a display device of the present invention includes the display device substrate according to any one of the above, and a light emitting element connected to the drain electrode or the source electrode.

  The display device of the present invention is characterized in that the light emitting element is an organic light emitting diode.

In the method for manufacturing a substrate for a display device according to the present invention, a step of forming a gate electrode and a first capacitor electrode electrically connected to the gate electrode on the substrate, and covering the gate electrode and the first capacitor electrode are provided. Thus, the step of forming an insulating layer on the substrate, the step of forming a semiconductor layer so as to cover the insulating layer, and a portion of the semiconductor layer located on the first capacitor electrode by etching And removing the upper portion of the insulating layer located on the first capacitor electrode by performing etching, and a source electrode and a drain partly facing the gate electrode through the insulating layer to form the electrode, outside of the as through the insulating layer facing the first capacitor electrode, the outer peripheral with overlaps the first capacitor electrode in a plan view the first capacitor electrode And forming a second capacitor electrode so as to lie inside the.

In the method for manufacturing a substrate for a display device according to the present invention, a step of forming a gate electrode and a first capacitor electrode electrically connected to the gate electrode on the substrate, and covering the gate electrode and the first capacitor electrode are provided. Thus, after forming the insulating layer on the substrate, and forming the resist layer covering the insulating layer, the resist layer is exposed and developed to develop a portion of the resist layer corresponding to the contact hole Removing a part of the insulating layer from the resist layer and removing the upper portion of the resist layer until the resist layer located on the first capacitor electrode has a predetermined thickness; and A portion of the layer exposed from the resist layer is removed by etching to form a contact hole that penetrates the insulating layer, and the first container is etched by the etching. Removing the resist layer located on the electrode and the upper portion of the insulating layer; forming a source electrode and a drain electrode partially facing the gate electrode through the insulating layer; and passing through the insulating layer Forming a second capacitor electrode so as to face the first capacitor electrode so as to overlap the first capacitor electrode in a plan view and to have an outer periphery located inside the outer periphery of the first capacitor electrode ; including.

  According to the present invention, the influence of the parasitic capacitance of the thin film transistor can be suppressed without greatly changing the manufacturing process of the existing display device substrate.

  Exemplary embodiments of a display device substrate and a display device using the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In this embodiment, an organic EL display device using an organic light emitting diode as a light emitting element will be described as an example. In addition, the drawings of the display device substrate and the display device used in the following embodiments are schematic, and the dimensional ratios on the drawings do not necessarily match the actual ones.

[Pixel circuit]
FIG. 1 is a diagram showing a configuration of a pixel circuit corresponding to one pixel of a display device according to an embodiment of the present invention, and FIG. 2 is a diagram in which parasitic capacitance is drawn in the pixel circuit of FIG. The pixel circuit shown in FIG. 1 includes an organic light emitting diode OLED, a drive transistor Td, a threshold voltage detection transistor Tth, and a storage capacitor Cs.

  The drive transistor Td is a control element for controlling the amount of current flowing through the organic light emitting diode OLED according to the potential difference applied between the gate electrode and the source electrode. The threshold voltage detection transistor Tth has a function of electrically connecting the gate electrode and the drain electrode of the drive transistor Td when the transistor is turned on, and a potential difference between the gate electrode and the source electrode of the drive transistor Td. Has a function of detecting the threshold voltage Vth of the drive transistor Td by causing a current to flow from the gate electrode to the drain electrode of the drive transistor Td until becomes the threshold voltage Vth of the drive transistor Td.

  The organic light emitting diode OLED is an element having a characteristic in which a current flows when a potential difference equal to or higher than a threshold voltage (anode-cathode potential difference) flows to emit light. Specifically, the organic light emitting diode OLED includes an anode electrode and a cathode electrode formed of a conductive material such as Al, Cu, ITO (Indium Tin Oxide), and phthalocyanine between the anode electrode and the cathode electrode. And a light emitting layer formed of an organic material such as trisaluminum complex, benzoquinolinolato, and beryllium complex, and the holes and electrons injected into the light emitting layer are recombined. Has the function of generating light.

  The drive transistor Td and the threshold voltage detection transistor Tth are composed of thin film transistors. Note that, in each drawing referred to below, the type (n-type or p-type) of each thin film transistor channel is not specified, but it is either n-type or p-type. Shall be followed.

  The first and second power supply lines 10 and 11 supply power to the drive transistor Td. The scanning line 12 supplies a signal for controlling the threshold voltage detection transistor Tth. The image signal line 13 supplies an image signal.

  The holding capacitor Cs is a capacitor element that holds the image data potential supplied from the image signal line 13, and includes a first capacitor electrode (right side in the figure) and a second capacitor electrode (left side in the figure). As shown in FIG. 1, the first capacitor electrode is connected to the gate electrode of the drive transistor and the source electrode of the threshold voltage detection transistor.

  In FIG. 2, CgsTd and CgdTd are parasitic capacitances of the drive transistor Td, CgsTth and CgdTth are parasitic capacitances of the threshold voltage detection transistor Tth, and Coled is a capacitance of the organic light emitting diode OLED.

[Display device substrate]
3 is a plan view showing an example of a substrate for a display device when the pixel circuit of FIG. 1 is actually realized. FIG. 4A is a cross-sectional view taken along the line AA ′ of FIG. 3, and FIG. FIG. 4 is a sectional view taken along line BB ′ of FIG. In FIG. 3, the horizontal direction is the x-axis direction, and the vertical direction is the y-axis direction.

  As shown in these drawings, the display device substrate 100 according to this embodiment includes a substrate 1, a first capacitor electrode 2 formed on the upper surface of the substrate 1, a gate electrode 3 of a thin film transistor, and a first capacitor electrode. 2 and the gate electrode 3, and a source electrode 5, a drain electrode 6, and a second capacitor electrode 7 formed on the insulating layer 4.

  For example, plastic or glass can be used as the substrate 1, but in the case of a top emission type display device, a substrate that does not have translucency can also be employed.

  On the upper surface of the substrate 1, various electrodes such as a first capacitor electrode 2 of a storage capacitor Cs, a gate electrode 3a of a drive transformer Td, a gate electrode 3b of a threshold voltage detection transistor Tth, a scanning line 12, and a second power supply line 11 The wiring is formed in a predetermined shape. In the present embodiment, the gate electrode 3a of the drive transistor Td is formed integrally with the first capacitor electrode 2 of the storage capacitor Cs, and the gate electrode 3b of the threshold voltage detection transistor Tth is formed integrally with the scanning line 12. ing.

  An insulating layer 4 is formed on the substrate 1 on which the first capacitor electrode 2 and the gate electrode 3 of the storage capacitor Cs are formed so as to cover the first capacitor electrode 2 and the gate electrode 3. The insulating layer 4 is made of, for example, SiN and functions as a gate insulating film of a thin film transistor. In the display device substrate of the present invention, as shown in FIG. 4, the thickness of the insulating layer 4 located between the first capacitor electrode 2 and the second capacitor electrode 7 of the storage capacitor Cs is made thinner than the other portions. Yes. As a result, the capacitance value of the storage capacitor Cs increases, and the influence of the parasitic capacitance of the drive transistor Td and the threshold voltage detection transistor Tth on the image data writing efficiency can be reduced. The reason for this will be described in more detail below.

  In the pixel circuit shown in FIG. 1, when the gate potential with respect to the source of the driving transistor Td at the time of light emission is Vgs, Vgs is expressed by the following formula (1), where a and d are constants, and the current Ids flowing through the driving transistor Td is ( It is expressed by the following formula (2) using the formula (1).

Vgs = Vth + aVdata + d (1)
Ids = (β / 2) (Vgs−Vth) ²
= (Β / 2) (a · Vdata + d) ² (2)
Here, the coefficient a that gives the ratio of the amplitude of Vgs to the amplitude of the image signal line is called write efficiency. The write efficiency a is expressed by the following equation (3) if there is no parasitic capacitance of the drive transistor Td and the threshold voltage detection transistor Tth, and is expressed by the following equation (4) when the parasitic capacitance is taken into consideration.

a = Coled / (Cs + Coled) (3)
a = {(Coled + CgdTth) / (Coled + Cs + CgsTth
+ CgdTth + CgsTd)} · {Cs / (Cs + CgsTth)
+ CgsTd + CgdTd)} (4)
The term {(Coled + CgdTth) / (Coled + Cs + CgsTth + CgdTth + CgsTd)} in the above equation (4) is smaller than other values (CgdTth, CgsTth, CgdTth, CgsTd) compared to the magnitudes of Coled and Cs. It is almost equal to (Cs + Coled)}.

  On the other hand, the term {Cs / (Cs + CgsTth + CgsTd + CgdTd)} in the above equation (4) is clearly smaller than 1, which indicates that the writing efficiency is lowered. As can be seen from this equation, the degree of influence of the parasitic capacitances of the drive transistor Td and the threshold voltage detection transistor Tth on the write efficiency is determined by the relative size with respect to the capacitance value of the storage capacitor Cs. Therefore, a decrease in write efficiency can be suppressed by increasing the capacitance value of the storage capacitor Cs with respect to the parasitic capacitance of the drive transistor Td and the threshold voltage detection transistor Tth. That is, the display device substrate of the present invention increases the capacity of the storage capacitor Cs by reducing the thickness of the insulating layer 4 located between the first capacitor electrode 2 and the second capacitor electrode 7 of the storage capacitor Cs. This prevents the write efficiency from being lowered. Specifically, the thickness dimension T1 between the first capacitor electrode 2 and the second capacitor electrode 7 of the storage capacitor Cs is 0.25 ≦≦ the thickness dimension T2 between the gate electrode 3 and the semiconductor layer 8 of the thin film transistor. It is preferable to set in the range of T1 / T2 ≦ 0.75.

  Note that the thickness dimension in the present invention refers to the distance between the first capacitor electrode 2 and the second capacitor electrode 7 of the storage capacitor Cs on the cut surface when the display device is cut in the vertical direction (perpendicular to the display surface). Average value when the thickness of the insulating layer between the gate electrode 3 and the source / drain electrodes 5 and 6 constituting the thin film transformer electrically connected to the insulating layer and the storage capacitor Cs is measured by SEM at three locations, respectively. It is.

  On the upper surface of the insulating layer 4, the source electrode 5 of the thin film transistor (the source electrode 5 a of the driving transistor Td and the source electrode 5 b of the threshold voltage detecting transistor Tth), the drain electrode 6 of the thin film transistor (the drain electrode 6 a of the driving transistor Td). And the drain electrode 6b of the threshold voltage detecting transistor Tth), the semiconductor layer 8 of the thin film transistor (the semiconductor layer 8a of the driving transistor Td and the semiconductor layer 8b of the threshold voltage detecting transistor Tth), the second capacitor electrode 7 of the storage capacitor Cs, and the image. A signal line 13 and the like are formed.

  The second capacitor electrode 7 is disposed so that substantially the entire surface thereof is opposed to the first capacitor electrode 2 with the insulating layer 4 interposed therebetween, thereby forming a capacitor of the storage capacitor Cs.

  The source electrode 5 and the drain electrode 6 together with the semiconductor layer 8 and the gate electrode 3 constitute a thin film transistor. A part of the source electrode 5 and the drain electrode 6 are opposed to the gate electrode 3 via the insulating layer 4, and this opposed part is a parasitic capacitance of the thin film transistor.

The semiconductor layer 8 includes an amorphous silicon layer serving as an operation layer of the thin film transistor and an n ⁺ type amorphous silicon layer serving as an ohmic layer.

  The insulating layer 4 is provided with a contact hole 9 formed through the insulating layer 4 in the thickness direction. The contact hole 9 is for connecting an electrode or wiring formed on the upper surface of the substrate 1 and an electrode or wiring formed on the upper surface of the insulating layer 4, for example, as shown in FIG. The first capacitor electrode 2 and the source electrode 5b of the threshold voltage detecting transistor Tth are connected to each other through a conductor provided on the inner surface of the contact hole 9.

  A passivation film 10 made of SiN or the like is formed on the upper surface of the insulating layer 4 so as to cover various electrodes and wirings such as the second capacitor electrode 7 and the image signal line 13.

[Display device]
Next, a display device according to an embodiment of the present invention using the above-described display device substrate will be described. FIG. 5 is a cross-sectional view of a main part of a display device according to an embodiment of the present invention.

  As shown in the figure, a planarizing film 11 is formed on the passivation film 10 of the display device substrate 100. The planarizing film 11 is for reducing the influence of unevenness due to the difference in height of the thin film transistor and the storage capacitor Cs provided on the upper surface of the substrate 1 when the organic light emitting diode OLED is formed. It is formed of a resin material such as resin.

  On the planarizing film 11, an organic light emitting diode OLED which is a light emitting element is formed. The organic light emitting diode OLED includes a lower electrode 13, a light emitting functional layer 14 formed on the lower electrode 13, and an upper electrode 15 formed on the light emitting functional layer 14.

  The lower electrode 13 is formed over substantially the entire display area of the display device across adjacent pixels. In the present embodiment, the lower electrode 13 functions as an anode electrode of the organic light emitting diode OLED, and is formed of a conductive material such as aluminum, silver, or indium.

  A light emitting functional layer 14 is formed on the lower electrode 13. The light emitting functional layer 14 includes at least a light emitting layer having a function of emitting light. For example, a hole injection layer, a hole transport layer, a light emitting layer, a charge transport layer, and a charge injection layer are stacked in this order. It has a structure.

  An upper electrode 15 is formed on the upper surface of the light emitting functional layer 14. The upper electrode 15 is formed by being divided for each pixel. Since this embodiment is a top emission type display device and it is necessary to extract light to the upper electrode side, the upper electrode 15 is made of an electrode material that transmits light or a non-transparent metal material is deposited very thinly. Thus, it is formed so as to transmit light. The upper electrode 15 functions as a cathode electrode of the organic light emitting diode OLED, and is formed of, for example, ITO or IZO. The upper electrode 15 is connected to the drain electrode of the driving transistor Td through a conductor deposited on the inner surface of the second contact hole 12 provided in the planarizing film 11.

  An interlayer insulating film 16 is provided on the upper surface of the lower electrode 13 and along the boundary between adjacent pixels, and the light emitting functional layer 14 is formed on the lower electrode 13 exposed from the interlayer insulating film 16. . The interlayer insulating film 16 has a function of preventing a short circuit between the lower electrode 13 and the upper electrode 15. The interlayer insulating film 16 is formed of an organic resin material such as acrylic resin, polyimide resin, or phenol resin, for example.

  A partition wall 17 is provided on the interlayer insulating film 16. The partition wall 17 functions as a spacer for placing a vapor deposition mask used for vapor deposition of the light emitting functional layer 14 for each pixel. Further, the partition wall 17 is formed in a reverse taper shape, and when the upper electrode 15 is deposited, the upper electrode 15 is disconnected at the partition wall 17 portion, and the upper electrode 15 is divided for each pixel. Become. The partition wall 17 is made of, for example, a novolac or acrylic photosensitive organic material, and is formed by a conventionally known photolithography method.

A protective film 18 is formed on the upper electrode 15. The protective film 18 protects the organic light emitting diode OLED from moisture and outside air, and is an inorganic material such as a silicon oxide film (SiN, SiO ₂ , SiON, etc.), a silicon nitride film (Si ₃ N ₄ , SiNx, etc.). And is formed by conventionally known vapor deposition, sputtering, CVD, or the like.

  The display device according to the present embodiment includes a sealing substrate 19 disposed to face the substrate 1. The sealing substrate 19 is a frame-shaped sealing material formed in an annular shape along the outer periphery of the substrate 1 so as to surround all pixels, or a planar sealing material filled between the protective film 18 and the sealing substrate 19. (Not shown) and bonded to the display device substrate 100. The sealing substrate 19 is formed of a light-transmitting substrate such as plastic or glass. The sealing material is formed using an acrylic resin, an epoxy resin, a urethane resin, a silicon resin, or the like.

  According to the display device substrate and the display device using the same according to the present invention described above, the thickness dimension of the insulating layer 4 positioned between the first capacitor electrode 2 and the second capacitor electrode 7 of the storage capacitor Cs is as follows. The insulating layer 4 is formed so as to be smaller than the thickness dimension of the insulating layer 4 located between the gate electrode 5 and the gate electrode 3 constituting the thin film transistor and between the source electrode 6 and the gate electrode 3. Thus, the influence of the parasitic capacitance of the thin film transistor can be reduced, and the writing efficiency of the image data can be improved. Accordingly, even when the parasitic capacitance of the thin film transistor exists, the luminance reduction of the display device can be suppressed to a small level.

[First Manufacturing Method of Display Device Substrate]
Next, a first method for manufacturing a display device substrate according to an embodiment of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 6A, the gate electrode 3 of the thin film transistor and the first capacitor electrode 2 electrically connected to the gate electrode 3 are formed on the upper surface of the substrate 1. These electrodes are formed by depositing a conductive material such as chromium, molybdenum, or aluminum on the upper surface of the substrate 1 to a thickness of 100 nm to 300 nm by sputtering, and then patterning it into a predetermined shape by photolithography.

Next, as shown in FIG. 6B, an insulating layer 4 is formed on the substrate 1 so as to cover the gate electrode 3 and the first capacitor electrode 2. The insulating layer 4 is formed by depositing an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx) to a thickness of 200 nm to 500 nm on the entire upper surface of the substrate 1 by plasma CVD (Chemical Vapor Deposition). It is formed. Note that SiH ₄ , NH ₃ , N _2, or the like can be used as a gas for forming the insulating layer 4 by the CVD method. Subsequently, as shown in FIG. 6C, an amorphous silicon film 8 ′ to be the semiconductor layer 8 is formed on substantially the entire upper surface of the insulating layer 4 using a gas such as SiH ₄ or H ₂ by plasma CVD. The amorphous silicon film 8 ′ includes an n ⁺ type amorphous silicon layer formed by doping the amorphous silicon film 8 ′ with impurities. The insulating layer 4 and the amorphous silicon layer 8 ′ are formed so that the etching rates thereof are different, more specifically, the etching rate of the insulating layer 4 is larger than the etching rate of the amorphous silicon layer 8 ′. The etching rate of the insulating layer 4 is 900 Å / min, and the etching rate of the amorphous silicon layer 8 ′ is 300 Å / min.

  Next, the amorphous silicon film 8 'is patterned. In the process of patterning the amorphous silicon film 8 ′, processing for removing the upper portion of the insulating layer 4 located on the first capacitor electrode 2 is performed. This process is shown in FIG. The patterning of the amorphous silicon film 8 'is performed by photolithography. First, as shown in FIG. 7A, a portion of the amorphous silicon film 8 ′ that becomes the semiconductor layer 8 is covered with a resist layer 50. In this state, etching is performed as shown in FIG. By this etching, a portion of the amorphous silicon layer 8 ′ that is not covered with the resist layer 50 is removed. Normally, the etching conditions in this step are set so that only the amorphous silicon film 8 ′ is removed, in other words, the etching conditions are set so that the etching is completed when the insulating layer 4 is exposed. In the method for manufacturing a display device substrate according to the above, etching is continuously performed after the amorphous silicon film 8 'is removed. Etching is continued even after the amorphous silicon film 'is removed in this manner, whereby the upper portion of the insulating layer 4 located on the first capacitor electrode 2 not covered with the resist layer 50 is removed. As a result, the thickness of the insulating layer 4 located on the first capacitor electrode 2 of the storage capacitor Cs becomes thinner than the thickness of the insulating layer 4 located on the gate electrode 3 of the thin film transistor.

Etching in the process shown in FIG. 7 is performed by dry etching. As the type of gas, fluorine and oxygen gases such as SF ₆ / O ₂ or CF ₄ / O ₂ and fluorine gases such as CH ₃ F are suitable. Used. The gas pressure is set to 1 to 50 Pa, and the RF power density is set to 0.01 to 2.0 W / cm ² .

  After removing the resist layer 50, a contact hole 9 is formed in the insulating layer 4 as shown in FIG. The contact hole 9 is formed by providing a through hole in the insulating layer 4 at a predetermined position by photolithography.

  Next, as shown in FIG. 8B, various electrodes and wirings such as the source electrode 5, the drain electrode 6, the second capacitor electrode 7, and the image signal line 23 are formed. These electrodes and wirings are formed by depositing a conductor material such as molybdenum or aluminum by a PVD (Physical Vapor Deposition) method and then patterning it into a predetermined shape by a photolithography method.

  Finally, as shown in FIG. 8C, a passivation film 10 made of silicon nitride or the like is formed on the upper surface of the upper surface of the substrate 1 by a CVD method to complete the display device substrate 100.

[Second Manufacturing Method of Display Device Substrate]
Next, a second method for manufacturing a display device substrate according to an embodiment of the present invention will be described with reference to FIGS. In addition, about the part which overlaps with a 1st manufacturing method, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  From the step of forming the gate electrode 3 and the first capacitor electrode 2 of the thin film transistor on the upper surface of the substrate 1 to the step of forming the amorphous silicon film 8 ′ to be the semiconductor layer 8 on substantially the entire upper surface of the insulating layer 4, FIG. ) To (c), which is the same as the first manufacturing method.

  In the subsequent process of forming the semiconductor layer 8, the amorphous silicon film 8 'other than the portion that becomes the semiconductor layer 8 is removed as usual, and the etching is finished when the insulating layer 4 is exposed (FIG. 9).

  Next, contact holes 9 are formed in the insulating layer 4. In the second manufacturing method, processing for removing the upper portion of the insulating layer 4 located on the first capacitor electrode 2 of the storage capacitor Cs in the step of forming the contact hole 9 is also performed. This process is shown in FIG. First, as shown in FIG. 10A, a resist layer 50 is applied to substantially the entire upper surface of the substrate 1. In the present embodiment, a novolac photosensitive resin is used as the resist layer 50.

  Next, as shown in FIG. 10B, the resist layer 50 is exposed. In the present embodiment, the resist layer 50 is exposed in three regions: a region A corresponding to the contact hole 9 formation region, a region B corresponding to the region above the first capacitor electrode 2 of the storage capacitor Cs, and the other region C. The amount is changing. For example, when the resist layer 50 is a positive photoresist, the region A is directly irradiated with exposure light, the region B is irradiated with exposure light weaker than the region A, and the region C is irradiated. Avoid exposure light. In this way, by adjusting the exposure amount of light applied to the resist layer 50 for each region and developing the resist layer 50, the resist layer 50 having a different thickness for each region is formed as shown in FIG. Specifically, the resist layer 50 in the region A is removed, the resist layer 50 in the region C remains the original thickness, and the thickness of the resist layer 50 in the region B is equal to the thickness of the resist layer in the region A and the resist in the region C. The thickness is intermediate to the thickness of the layer.

  In order to adjust the exposure amount for each region, a mask capable of adjusting the exposure amount such as a slit mask or a halftone mask may be used. Here, the slit mask is a mask whose exposure amount can be adjusted by using a diffraction pattern, in which a large number of stripe-shaped patterns having finer intervals than the resolution limit value of the exposure apparatus are arranged on the mask. Can be used. By making the pattern finer than the resolution limit value of the exposure apparatus, the exposure light that has passed through the slit portion is exposed on average with an exposure amount smaller than the exposure amount before passing. A halftone mask is a mask in which the exposure amount can be adjusted by forming a mask using a material having a predetermined transmittance, and a material whose transmittance with respect to the wavelength of exposure light is known. By forming the mask while adjusting the thickness, a mask having an arbitrary transmittance with respect to the exposure light can be obtained. In the present embodiment, as shown in FIG. 10B, a slit mask 51 is used, and the region A where the contact hole 9 is formed is exposed to light L1 that is almost 100% transmitted, and the first of the storage capacitor Cs. The region B corresponding to the upper region of the capacitive electrode 2 is exposed to relatively weak light L2. In addition to the method using a mask capable of adjusting the exposure amount, the thickness of the resist layer 50 after the development processing is performed for each of the regions A to C by performing double exposure using two types of masks having different opening patterns. It is also possible to change.

  After forming the resist layers 50 having different thicknesses as described above, etching is performed to remove the insulating layer 4 in the region exposed from the resist layer 50, thereby forming the contact holes 9. Further, by this etching, the resist layer 50 on the first capacitor electrode 2 and the upper portion of the insulating layer 4 on the first capacitor electrode 2 having a reduced thickness are removed. As a result, as shown in FIG. 11A, the thickness of the insulating layer 4 located on the first capacitor electrode 2 is larger than the thickness of the insulating layer 4 located on the gate electrode 3 at the same time when the contact hole 9 is formed. A thin insulating layer 4 can be formed.

As conditions for performing such etching, for example, the insulating layer 4 is formed at an etching rate of 900 Å / min and a thickness of 3600 、, and the resist layer 50 is formed at an etching rate of 3600 Å / min and a thickness of 27000 Å. The resist layer 50 is adjusted to the exposure amount as described above and developed to make the thickness of the resist layer 50 in the region B 16000 mm. Under this state, dry etching is performed. Etching conditions are, for example, that the gas type of the etching gas is SF ₆ and O ₂ , the gas pressure is 1 to 50 Pa, and the RF power density is 0.1 to 1.0 W / cm ² . Under this condition, for example, etching is performed for 6.0 minutes. As a result, the resist layer 50 in the region C is etched by 21600 Å (= 3600 Å / min × 6.0 min). On the other hand, the resist layer 50 in the region B is removed in about 4 minutes, and the insulating layer 4 in the region B is exposed, and then the insulating layer 4 is etched for about 2 minutes. Thereby, the insulating layer 4 can be thinned from the original thickness of 3600 mm to about half the thickness (1400 mm to 1800 mm).

  Next, as shown in FIG. 11B, various electrodes and wirings such as the source electrode 5, the drain electrode 6, the second capacitor electrode 7, and the image signal line 23 are formed, and finally, as shown in FIG. 11C. Then, a passivation film 10 made of silicon nitride or the like is formed on the upper surface of the substrate 1 to complete the display device substrate 100.

  In addition, this invention is not limited to the above-mentioned embodiment, A various change, improvement, etc. are possible in the range which does not deviate from the summary of this invention.

  For example, in the above-described embodiment, the case of a pixel circuit having two thin film transistors (the drive transistor Td and the threshold voltage detection transistor Tth) has been described. However, the pixel circuit to which the present invention is applicable is not limited to this. As shown in FIG. 12, the present invention can be applied to a pixel circuit having two or more thin film transistors including switching transistors Ts and Tm in addition to the drive transistor Td and the threshold voltage detection transistor Tth.

It is a figure which shows an example of a structure of the pixel circuit corresponding to 1 pixel of the display apparatus of this invention. FIG. 2 is a diagram in which parasitic capacitance is drawn in the pixel circuit of FIG. 1. It is a top view of the board | substrate for display apparatuses concerning one Embodiment of this invention. (A) is A-A 'sectional drawing of FIG. 3, (b) is B-B' sectional drawing of FIG. It is principal part sectional drawing of the display apparatus concerning one Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method concerning one Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method concerning one Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method concerning one Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method concerning other embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method concerning other embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method concerning other embodiment of this invention. It is a figure which shows an example of a structure of the other pixel circuit corresponding to 1 pixel of the display apparatus of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... 1st capacity electrode 3 ... Gate electrode 4 ... Insulating layer 5 ... Source electrode 6 ... Drain electrode 7 ... 2nd capacity electrode 8 ... Semiconductor Layer 9 ... Contact hole 10 ... Passivation film 11 ... Planarization film 12 ... Second contact hole 13 ... Lower electrode 14 ... Light emitting functional layer 15 ... Upper electrode 16 ... Interlayer insulating film 17 ... partition 18 ... protective film 19 ... sealing substrate

Claims (7)

First and second capacitor electrodes constituting a storage capacitor for holding an image data potential;
In a display device substrate having a gate electrode, a source electrode, and a drain electrode constituting a transistor electrically connected to the storage capacitor,
A substrate on which the gate electrode and the first capacitor electrode electrically connected to the gate electrode are formed;
An insulating layer formed on the substrate so as to cover the gate electrode and the first capacitor electrode;
The source electrode partially facing the gate electrode through the insulating layer;
The drain electrode partially facing the gate electrode through the insulating layer;
The second capacitor electrode facing the first capacitor electrode through the insulating layer,
The insulating layer positioned between the first capacitor electrode and the second capacitor electrode has a thickness dimension between the gate electrode and the source electrode and between the gate electrode and the drain electrode. rather smaller than the thickness of the insulating layer, the second capacitor electrode, characterized in that the outer peripheral with overlaps the first capacitor electrode in a plan view is located inside the outer periphery of the first capacitor electrode Substrate for display device.   The display device substrate according to claim 1, wherein a semiconductor layer is formed between the source electrode and the insulating layer and between the drain electrode and the insulating layer.   The display device substrate according to claim 1, wherein a contact hole penetrating the insulating layer is formed in the insulating layer. A substrate for a display device according to any one of claims 1 to 3,
A light emitting element connected to the drain electrode or the source electrode;
A display device comprising:   The display device according to claim 4, wherein the light emitting element is an organic light emitting diode. Forming a gate electrode and a first capacitor electrode electrically connected to the gate electrode on a substrate;
Forming an insulating layer on the substrate so as to cover the gate electrode and the first capacitor electrode;
Forming a semiconductor layer so as to cover the insulating layer;
Removing a portion of the semiconductor layer located on the first capacitor electrode by etching and removing the upper portion of the insulating layer located on the first capacitor electrode by performing etching; and
A source electrode and a drain electrode that are partially opposed to the gate electrode through the insulating layer are formed, and the first electrode is viewed in plan so as to face the first capacitor electrode through the insulating layer . Forming a second capacitor electrode so as to overlap the capacitor electrode and to have an outer periphery positioned inside the outer periphery of the first capacitor electrode . Forming a gate electrode and a first capacitor electrode electrically connected to the gate electrode on a substrate;
Forming an insulating layer on the substrate so as to cover the gate electrode and the first capacitor electrode;
After forming the resist layer that covers the insulating layer, the resist layer is exposed and developed to remove the portion of the resist layer corresponding to the contact hole and remove a portion of the insulating layer from the resist layer. Removing the upper portion of the resist layer until the resist layer located on the first capacitor electrode has a predetermined thickness,
A portion of the insulating layer exposed from the resist layer is removed by etching to form a contact hole penetrating the insulating layer, and a top of the resist layer and the insulating layer located on the first capacitor electrode by the etching. Removing the
A source electrode and a drain electrode that are partially opposed to the gate electrode through the insulating layer are formed, and the first electrode is viewed in plan so as to face the first capacitor electrode through the insulating layer . Forming a second capacitor electrode so as to overlap the capacitor electrode and to have an outer periphery positioned inside the outer periphery of the first capacitor electrode .

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