KR101948171B1 - Organic Light Emitting diode display and method of manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor device comprising: a semiconductor pattern on a substrate; a first storage electrode made of the same material as the semiconductor pattern and doped with impurity ions; A gate insulating layer formed on the semiconductor pattern and the first storage electrode; A second storage electrode formed on the gate insulating layer and corresponding to the first storage electrode and made of a first conductive layer; a gate electrode corresponding to a channel region of the semiconductor pattern and including multiple layers including the first conductive layer; An interlayer insulating film formed on the second storage electrode and the gate electrode; A source electrode and a drain electrode connected to a source region and a drain region of the semiconductor pattern on the interlayer insulating film; a third storage electrode corresponding to the third storage electrode and electrically connected to the first storage electrode; A first protective layer formed on the source electrode and the drain electrode and on the third storage electrode; A connection electrode connected to the drain electrode on the first protective film, a fourth storage electrode corresponding to the third storage electrode and electrically connected to the second storage electrode; And an organic light emitting diode (OLED) connected to the connection electrode.

Description

[0001] The present invention relates to an organic light emitting diode (OLED) display device and a method of manufacturing the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OLED display, and more particularly, to an OLED display and a method of manufacturing the same.

2. Description of the Related Art [0002] As an information-oriented society develops, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as organic light emitting diode (OLED) display devices have been utilized.

Of these flat panel display devices, organic light emitting element display devices have recently been widely used because they have advantages of miniaturization, weight reduction, thinness, and low power driving.

As an organic light emitting diode display device, an active matrix type organic light emitting diode display device in which a switching transistor is formed in each of pixels arranged in a matrix form is widely used.

In the pixel region, a driving transistor and an organic light emitting diode are formed, and a storage capacitor for holding a voltage applied to the gate electrode of the driving transistor is formed.

Conventionally, in constructing a storage capacitor, a single or dual capacitor structure, that is, a maximum dual capacitor structure is adopted. The single capacitor structure is a structure using two storage electrodes, and the double capacitor structure is a structure using three storage electrodes.

Such a storage electrode is constituted by using a metal thin film or the like stacked in an organic light emitting diode display device.

The storage capacitor capacity becomes larger as the area becomes larger. Therefore, when a maximum bipolar capacitor structure is used as in the prior art, it is inevitable to enlarge the area in order to secure a sufficient capacitor capacity. This means that the area occupied by the storage area in the pixel area must be large.

As a result, the aperture ratio is reduced, which hinders development of a high-resolution display device.

Disclosure of the Invention Problems to be Solved by the Invention An object of the present invention is to provide an organic light emitting element display device and a method of manufacturing the same that can reduce the storage area and improve the aperture ratio.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor pattern on a substrate; a first storage electrode made of the same material as the semiconductor pattern and doped with impurity ions; A gate insulating layer formed on the semiconductor pattern and the first storage electrode; A second storage electrode formed on the gate insulating layer and corresponding to the first storage electrode and made of a first conductive layer; a gate electrode corresponding to a channel region of the semiconductor pattern and including multiple layers including the first conductive layer; An interlayer insulating film formed on the second storage electrode and the gate electrode; A source electrode and a drain electrode connected to a source region and a drain region of the semiconductor pattern on the interlayer insulating film; a third storage electrode corresponding to the third storage electrode and electrically connected to the first storage electrode; A first protective layer formed on the source electrode and the drain electrode and on the third storage electrode; A connection electrode connected to the drain electrode on the first protective film, a fourth storage electrode corresponding to the third storage electrode and electrically connected to the second storage electrode; And an organic light emitting diode (OLED) connected to the connection electrode.

The storage electrode may include a bridge electrode formed on the same layer as the source electrode and the drain electrode and electrically connecting the second and fourth storage electrodes.

The first conductive layer may have a thickness of 200 ANGSTROM to 500 ANGSTROM.

A first bridge contact hole for connection between the second storage electrode and the bridge pattern is formed in the interlayer insulating film and a second bridge contact hole for connection between the bridge electrode and the fourth story electrode is formed in the first protective film, .

And a second protective layer having a connection contact hole for connection between the connection electrode and the organic light emitting diode.

In another aspect, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a semiconductor pattern on a substrate and a first storage electrode made of the same material as the semiconductor pattern; Forming a gate insulating film on the semiconductor pattern and the first storage electrode; A second storage electrode formed on the gate insulating layer and corresponding to the first storage electrode and made of a first conductive layer; and a gate electrode formed of multiple layers corresponding to the channel region of the semiconductor pattern and including the first conductive layer ; Doping the first storage electrode with impurity ions by performing a doping process using the gate electrode with a doping mask; Forming an interlayer insulating film on the second storage electrode and the gate electrode; A source electrode and a drain electrode connected to a source region and a drain region of the semiconductor pattern on the interlayer insulating film and a third storage electrode corresponding to the third storage electrode and electrically connected to the first storage electrode, ; Forming a first protective film on the source electrode and the drain electrode and on the third storage electrode; Forming a connection electrode connected to the drain electrode on the first protective film and a fourth storage electrode corresponding to the third storage electrode and electrically connected to the second storage electrode; And forming an organic light emitting diode connected to the connection electrode.

Here, the formation of the source electrode and the drain electrode may include forming a bridge electrode electrically connecting the second and fourth storage electrodes.

The first conductive layer may have a thickness of 200 ANGSTROM to 500 ANGSTROM.

The gate electrode may include a second conductive layer positioned on the first conductive layer, and the first conductive layer and the second conductive layer may be etched with different etchants.

The first conductive layer may be made of a transparent conductive material or MoTi, and the second conductive layer may be made of Mo.

Forming a first bridge contact hole for connection between the second storage electrode and the bridge pattern on the interlayer insulating film; And forming a second bridge contact hole in the first passivation layer for connection between the bridge electrode and the fourth story electrode.

And forming a second protective layer having a connection contact hole for connection between the connection electrode and the organic light emitting diode.

In the present invention, the first to fourth storage electrodes can be configured to realize a storage capacitor having a triple structure. As a result, the storage capacity can be improved compared to the area. Therefore, the area occupied by the storage area can be reduced as compared with the prior art, and as a result, the aperture ratio can be improved.

1 is a circuit diagram schematically illustrating an organic light emitting diode display device according to an embodiment of the present invention.
2 is a plan view schematically illustrating an organic light emitting diode display device according to an embodiment of the present invention.
3 is a cross-sectional view taken along line AA and BB in Fig.
4 is a cross-sectional view illustrating a storage capacitor of an OLED display according to an exemplary embodiment of the present invention.
5A to 5G are cross-sectional views illustrating a method of manufacturing an OLED display device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram schematically illustrating an OLED display according to an embodiment of the present invention. FIG. 2 is a plan view schematically illustrating an OLED display according to an embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a storage capacitor of an OLED display according to an embodiment of the present invention. Referring to FIG.

In the embodiment of the present invention, for convenience of explanation, a 3T1C structure including three transistors and one capacitor in each pixel region is taken as an example. Of course, the present invention may be applied to other structures such as 2T1C, 4T1C, 5T1C, 6T1C and the like as an example.

The three transistors formed in the pixel region have substantially the same structure. The driving transistor will be mainly described, and the same reference numerals can be used for the constituent elements constituting the three transistors. Also, FIG. 2 shows the storage capacitor as a center.

Referring to FIGS. 1 to 3, a plurality of pixel regions P arranged in a matrix are defined in the OLED display 100 according to the embodiment of the present invention. The switching transistor Ts, the driving transistor Td, the emission control transistor Te, the organic light emitting diode OD, and the storage capacitor Cst having a triple structure may be formed in each pixel region P.

The switching transistor Ts is connected to the corresponding gate wiring and data wiring 140 and 160 and is turned on according to a gate signal applied to the gate wiring 140. When the switching transistor Ts is turned on, the data voltage transferred through the data line 160 is applied to the gate electrode 142 of the driving transistor Td in synchronism therewith.

Accordingly, the driving transistor Td is turned on, and a light emission current flows through the channel region CH. Here, the magnitude of the light emission current is determined according to the magnitude of the applied data voltage. For example, the magnitude of the light emission current is determined in proportion to the data voltage.

When the light emission current is supplied to the organic light emitting diode OD, light having a corresponding luminance is emitted according to the magnitude of the light emission current.

On the other hand, the emission control transistor Te controls the turn-on / turn-off of the organic light emitting diode OD. That is, since the driving voltage Vdd can be applied to the driving transistor Td when the emission control transistor Te is turned on, a light emission current corresponding to the data voltage can be generated and supplied to the organic light emitting diode OD do. On the other hand, when the emission control transistor Te is turned off, the driving voltage Vdd can not be applied to the driving transistor Td, so that no light emission current is generated and the organic light emitting diode OD is turned off.

The gate wirings 140 and the data wirings 140 and 160 are configured to cross each other. For example, the gate wirings 140 extend in the first direction and the data wirings 160 extend in the second direction.

On the other hand, a light emission control wiring 145 connected to the light emission control transistor Te may further be provided. The light emission control wiring 145 may be formed of the same material as the gate wiring 140 and may extend along the first direction and be spaced apart from the gate wiring 140. However, the present invention is not limited thereto.

A power supply wiring 165 for transferring the driving voltage Vdd may further be provided. The power supply line 165 may be formed of the same material as the data line 160, extend along the second direction, and be spaced apart from the data line 160. However, the present invention is not limited thereto.

The switching transistor Ts, the driving transistor Td, and the emission control transistor Te described above are formed in substantially the same structure. In this regard, the driving transistor Td will be described as an example.

The driving transistor Td includes a semiconductor pattern 120, a gate electrode 142, and source and drain electrodes 161 and 163. The semiconductor pattern 120 is formed on the substrate 110 and may be made of crystalline silicon. The semiconductor pattern 120 may include a channel region CH, a source region, and a drain region S, D. The channel region CH is located at a central portion of the semiconductor pattern 120 and may be composed of pure crystalline silicon as a region of a hole or electron movement. On the other hand, the source region and the drain region are located at both sides of the channel region CH, and may be composed of crystalline silicon doped with impurity ions such as n + or p + ions.

A gate insulating layer 130 may be formed on the semiconductor pattern 120 and a gate electrode 142 may be formed on the gate insulating layer 130 to correspond to the channel region CH.

An interlayer insulating layer 150 may be formed on the gate electrode 142 and source and drain electrodes 161 and 163 may be formed on the interlayer insulating layer 150. Source and drain contact holes 510 and 520 may be formed in the interlayer insulating film 150 to expose the source and drain regions S and D, respectively. Through the source contact holes and the drain contact holes 510 and 520, the source and drain electrodes 161 and 163 can contact the corresponding source and drain regions S and D, respectively.

The organic light emitting diode OD electrically connected to the driving transistor Td may include first and second electrodes 210 and 240 and an organic light emitting layer 230 formed between the electrodes.

The first electrode 210 is connected to the drain electrode 163 of the driving transistor Td. According to the embodiment of the present invention, the connection electrode 180 may be formed for connection therebetween.

The connection electrode 180 is formed on the first passivation layer 170 and a first connection contact hole 560 is formed in the first passivation layer 170 to expose the drain electrode 180 of the driving transistor Td. Can be formed. Through the first connection contact hole 560, the connection electrode 180 can contact the drain electrode 163.

On the other hand, the second protective layer 190 may be formed on the connection electrode 180. The second passivation layer 190 may function as a planarization layer so that the first electrode 210 formed on the second passivation layer 190 may be formed substantially flat. A second connection contact hole 570 may be formed in the second protective film 190. Through the second connection contact hole 570, the first electrode 210 can contact the connection electrode 180.

Through the above configuration, the organic light emitting diode OD can be electrically connected to the driving transistor Td.

On the other hand, the bank layer 220 may be formed on the first electrode 210 along the boundary of the pixel region P. Referring to FIG. The bank layer 220 may have an opening 221 and the organic light emitting layer 230 may be formed in the opening 221. The organic light emitting layer 230 may extend from the opening 221 to overlap the bank layer 220 and the end.

The second electrode 240 may be formed on the organic light emitting layer 230 substantially over the entire surface of the substrate 110. That is, the first electrode and the organic light emitting layers 210 and 230 may be patterned for each pixel region, and the second electrode 240 may be integrally formed over all the pixel regions P.

Meanwhile, in the embodiment of the present invention, the storage capacitor Cst is formed in a triple structure, which will be described in more detail.

The storage capacitor Cst according to the embodiment of the present invention may include first to fourth storage electrodes 121, 144, 167, and 181.

The first storage electrode 121 may be formed on the same layer as the semiconductor pattern 120. The first storage electrode 121 is formed of a semiconductor material and the first storage electrode 121 is formed of a source region and a drain region so as to have sufficient conductivity that the first storage electrode 121 can function as an electrode. And may be made of crystalline silicon doped with impurities such as regions S and D.

The second storage electrode 144 is configured to correspond to the first storage electrode 121 with the gate insulating film 130 interposed therebetween. The second storage electrode 144 may be formed on the same layer as the gate electrode 142. Here, the gate electrode 142 may have a multi-layered structure, for example, a double layer structure, and the second storage electrode 144 may have a single-layer structure using the lowermost layer of the gate electrode 142.

In this regard, when the gate electrode 142 has a double-layer structure, it is preferable that the first conductive layer 141a, which is a lower layer, is formed so that impurity ions can be transmitted through the doping process. The second conductive layer 141b, which is an upper layer, may be made of a low-resistance conductive material. In this case, the second storage electrode 144 can be formed of the first conductive layer 141a of the gate electrode 142. [

In this regard, the first conductive layer 141a is formed to have a small thickness so that impurity ions can be transmitted therethrough. For example, the first conductive layer 141a may have a thickness of 200 ANGSTROM to about 500 ANGSTROM.

The second conductive layer 141b is preferably made of a metal material having a lower resistance than the first conductive layer 141a. It is preferable that the first conductive layer 141a and the second conductive layer 141b are made of materials having different etching characteristics. That is, the first and second conductive layers 141a and 141b are preferably etched with different etchants.

In this regard, for example, the first conductive layer 141a may be formed of indium-tin-oxide (ITO), indium-zinc-oxide (ITO), indium-tin- (molybdenum titanium), but the present invention is not limited thereto. The second conductive layer 141b may be formed of Mo (molybdenum), but the present invention is not limited thereto.

On the other hand, the gate wiring and the emission control wirings 140 and 145 are formed in the same multi-layer structure as the gate electrode 142.

The third storage electrode 167 is configured to correspond to the second storage electrode 144 with the interlayer insulating layer 150 therebetween. The third storage electrode 144 may be formed of the same material as the source and drain electrodes 161 and 163 in the same layer.

The fourth storage electrode 181 is configured to correspond to the third storage electrode 167 with the first protective film 170 interposed therebetween. The fourth storage electrode 181 may be formed of the same material as the connection electrode 180 in the same layer.

The first and second storage electrodes 121 and 144 and the second and third storage electrodes 144 and 167 and the third and fourth storage electrodes 144 and 167 in the first to fourth storage electrodes 121 to 144, The storage capacitors Cst1 to Cst3 may be formed between the storage electrodes 167 and 181. For convenience of explanation, the storage capacitors thus formed are divided into first to third storage capacitors Cst1 to Cst3 ).

The first and third storage electrodes 121 and 167 may be electrically connected and the second and fourth storage electrodes 144 and 181 may be electrically connected. According to this connection relationship, the first and third storage electrodes 121 and 167 function as one storage electrode and the second and fourth storage electrodes 144 and 181 function as one opposing story electrode, The storage capacitor Cst according to the embodiment can be configured. That is, by configuring the three sub-storage capacitors Cst1 to Cst3, it is possible to realize the triple-structure storage capacitor Cst.

As described above, according to the embodiment of the present invention, the storage capacitor Cst can be formed by using the four storage electrodes 121, 144, 167, and 181, so that the area of the storage region can be reduced. In other words, as compared with the conventional one using a single or dual structure, in the embodiment of the present invention, since the distance between the storage electrodes is reduced by adopting the triple structure, the capacity of the storage area can be improved. Therefore, in realizing the same capacity as the conventional one, less area can be used compared with the conventional one. As a result, the area of the storage region is reduced, and as a result, the aperture ratio of the pixel region is increased.

In the embodiment of the present invention, the first and third storage electrodes 121 and 167 are connected to the source electrode 161 side of the driving transistor Td, and the second and fourth storage electrodes 144 and 181 And is connected to the gate electrode 142 side of the driving transistor Td.

Here, the connection between the first and third storage electrodes 121 and 167 may be performed through the contact hole formed in the gate insulating film and the interlayer insulating film 130 and 150. Meanwhile, in the embodiment of the present invention, the source contact hole 510 of the driving transistor Td may function as a contact hole connecting the first and third storage electrodes 121 and 167.

The first storage electrode 121 may extend from the semiconductor pattern 120 of the driving transistor Td and the third storage electrode 167 may extend from the source electrode 161 of the driving transistor Td. As shown in FIG. Accordingly, the first and third storage electrodes 121 and 167 can be connected through the connection of the source region S and the source electrode 161 through the source contact hole 510.

The drain electrode 163 of the emission control transistor Te is connected to the source electrode 161 of the driving transistor Td. In the embodiment of the present invention, the source electrode 161 of the driving transistor Td is controlled to emit light And is also used as the drain electrode 163 of the transistor Te as an example. The semiconductor pattern 120 of the emission control transistor Te may extend from the first storage electrode 121.

The connection between the second and fourth storage electrodes 144, 181 may be via a bridge pattern 169 located therebetween, for example. The bridge pattern 169 may be formed of the same material as the source and drain electrodes 161 and 163 and may be formed of the same material as the source and drain electrodes 161 and 163 through the first and second bridge contact holes 530 and 540, , 181). The first bridge contact hole 530 is formed in the interlayer insulating layer 150 so that the bridge pattern 169 can contact the second storage electrode 144. The second bridge contact hole 540 is formed in the first protective film 170 so that the bridge pattern 169 can contact the fourth storage electrode 181. Here, the bridge pattern 169 may be formed extending from the drain electrode 163 of the switching transistor Ts.

On the other hand, the bridge pattern 169 and the fourth storage electrode 181 may be in contact with each other on the gate wiring 140, and a second bridge contact hole 530 may be formed on the gate wiring 140. In such a configuration, it is possible to prevent the storage area from being reduced by securing an area for connection between the bridge pattern 169 and the fourth storage electrode 181. That is, the storage area can be secured more efficiently.

On the other hand, the second bridge contact hole 530 may be formed in an area other than the gate wiring 140. In such a case, it is preferable that the gate insulating film is formed close to the gate wiring 140 in terms of the storage area securing.

The gate electrode 142 of the driving transistor Td is connected to the drain electrode 163 of the switching transistor Ts and the gate electrode 142 of the driving transistor Td is connected to the drain electrode 163 of the switching transistor Ts, 169 so as to be connected to the drain electrode 163 of the switching transistor Ts. A gate contact hole 550 may be formed in the interlayer insulating layer 150 to expose the gate electrode 142 of the driving transistor Td and the gate pattern of the bridge pattern 169 and the gate of the driving transistor Td may be formed through the gate contact hole 550. [ The electrode 142 may be configured to contact.

The gate electrode 142 of the driving transistor Td may be connected to the second storage electrode 144. In this case, the second storage electrode 144 and the gate electrode 142 of the driving transistor Td are separately patterned. May be formed extending from the electrode (144). In such a case, the drain electrode 163 of the switching transistor Ts and the gate electrode 142 of the driving transistor Td can be electrically connected through the first bridge contact hole 530. That is, the first bridge contact hole 530 can also serve as the gate contact hole 550.

As described above, according to the embodiment of the present invention, the first to fourth storage electrodes 121, 144, 167 and 181 can be formed to realize a storage capacitor Cst having a triple structure. As a result, the storage capacity can be improved compared to the area. Therefore, the area occupied by the storage area can be reduced as compared with the prior art, and as a result, the aperture ratio can be improved.

In this regard, reference may be made to Table 1 below.

Conventional (double structure) Example (triple structure) Storage capacity 240 pF 240 pF Part 1 Storage Capacity - 97 pF Part 2 Storage Capacity
(Conventional first sub storage capacity) 108 pF 65 pF Part 3 Storage Capacity
(Conventional Second Part Storage Capacity) 132 pF 79 pF Storage area 670 ㎡ 400 ㎡ Storage area ratio 100% 60% Storage area ratio to pixel area 13% 8%

Table 1 shows the simulation results in a 7-inch HD (high definition) model.

As a result, it can be seen that, in order to secure a storage capacity of approximately 240 pF, the storage area of the embodiment is required to be approximately 60% of the conventional storage area. Accordingly, the storage area occupies about 8% of the pixel area, and the aperture ratio of about 5% is increased compared to the conventional case.

As described above, according to the embodiment of the present invention, the storage area can be reduced and the aperture ratio can be improved.

Hereinafter, a method of manufacturing an OLED display according to an embodiment of the present invention will be described with reference to FIGS. 5A to 5G.

5A to 5G are cross-sectional views illustrating a method of manufacturing an OLED display device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 5A, amorphous silicon is deposited on a substrate 110 to form a semiconductor layer. On the other hand, a buffer layer may be formed before forming the semiconductor layer, and a semiconductor layer may be formed thereon.

Next, the semiconductor layer is subjected to a crystallization process to form a semiconductor layer made of crystalline silicon. Next, the semiconductor layer 120 and the first storage electrode 121 are formed by performing a mask process on the semiconductor layer and patterning the same.

Next, a gate insulating layer 130 is formed on the semiconductor pattern 120 and the first storage electrode 121. A gate insulating film 130 can be used, for example silicon oxide (SiO ₂₎ or silicon nitride (SiNx) as an inorganic insulating material.

Next, as shown in FIG. 5B, a first conductive layer and a second conductive layer 140a and 140b are sequentially formed on the gate insulating layer 130, and a photoresist layer 300 is deposited thereon .

Here, it is preferable that the first conductive layer 140a has a thickness thin enough to allow impurity ions to permeate during a subsequent doping process. For this, the first conductive layer 140a may be formed to a thickness of 200 ANGSTROM to 500 ANGSTROM.

The second conductive layer 140b may be formed of a metal material having a lower resistance than the first conductive layer 140a.

Next, the photomask 400 is placed on top of the photoresist layer 300. The photomask 400 may include a transmissive portion TA, a semi-transmissive portion HTA, and a blocking portion BA. The transmissive portion TA transmits the incident light, the blocking portion BA blocks the incident light, and the transflective portion HTA partially transmits the incident light. The semi-transmissive portion (HTA) may be composed of a slit or a semi-permeable membrane. As such, the photomask 400 having a semi-transmissive portion (HTA) is referred to as a slit mask or a hlaftone mask.

Meanwhile, in the embodiment of the present invention, for convenience of explanation, a case where a positive type photoresist layer 300 is used will be exemplified.

In such a case, the blocking portion BA may be positioned corresponding to the region where the gate electrode (see 142 in FIG. 5C) is to be formed as the central portion of the semiconductor pattern 120, and the gate wiring and the emission control wiring 140 and 145 of FIG. 1) may be located corresponding to the region to be formed. The transflective portion HTA may be positioned corresponding to the storage region as a region where the second storage electrode (see 144 in FIG. 5D) is to be formed. The transmissive portion TA is disposed at a portion other than the portion where the blocking portion BA and the transflective portion HTA are disposed.

In this way, the exposure process is performed in a state where the photomask 400 is disposed, and then the photoresist layer 300 is developed.

5C, a first photoresist pattern 301 having a first thickness is formed in a region corresponding to the blocking portion BA, and a first photoresist pattern 301 having a first thickness is formed in a region corresponding to the half-transparent portion HTA, A second photoresist pattern 302 having a second thickness smaller than the thickness is formed.

Next, the first etching process is performed using the first and second photoresist patterns 301 and 302 as an etching mask. The exposed first and second conductive layers 140a and 140b are removed so that the patterned first and second conductive layers 141a and 141b are left under the first and second photoresist patterns 301 and 302 do. The patterned first and second conductive layers 141a and 141b under the first photoresist pattern 301 constitute the gate electrode 142 and the gate wiring 140 and the light emission control wiring 145 are formed . On the other hand, the patterned first and second conductive layers 141a and 141b under the second photoresist pattern 302 constitute the storage pattern 143.

Next, as shown in FIG. 5D, an ashing process is performed on the first and second photoresist patterns 301 and 302. Accordingly, the second photoresist pattern 302 is removed, and the storage pattern 143 under the second photoresist pattern 302 is exposed. On the other hand, the first photoresist pattern 301 is left with its thickness reduced.

Next, the second etching process is performed using the ashed first photoresist pattern 301 as an etching mask. As a result, the second conductive layer 141b of the storage pattern 143 is removed and the first conductive layer 141a is left. The first conductive layer 141a thus left corresponds to the second storage electrode 144. [

Through the single mask process as described above, the gate electrode 142 of the double-layer structure can be formed and the second storage electrode 144 of the single-layer structure can be formed.

On the other hand, as another example, the gate electrode and the second storage electrode 142 and 144 can be formed through two mask processes. In this case, after the first conductive layer 140a is deposited, a first mask process is performed to form a patterned first conductive layer 141a and a second storage electrode 144 as a lower layer of the gate electrode 142 The second conductive layer 140b may be deposited and then the second mask process may be performed to form the patterned second conductive layer 141b as an upper layer of the gate electrode 142. [

Meanwhile, it is preferable that the first and second conductive layers 140a, 141a and 140b and 141b are etched into different etchants. If the first conductive layer 141b is etched to remove the second conductive layer 141b in the second etching process, the second conductive layer 141b may be etched according to the overheating angle of the first conductive layer 141b. ) Can not be formed in the desired form. Accordingly, it is preferable that the etchant for the first conductive layer does not react with the second conductive layers 140b and 141b and the etchant for the second conductive layer does not react with the first conductive layers 140a and 141b.

Next, when the second etching process is completed, a strip process is performed to remove the first photoresist pattern 301.

Next, as shown in FIG. 5E, a doping process using impurity ions such as n + or p + ions is performed. In the doping process, the second conductive layer 141b, which is an upper layer of the gate electrode 142, functions as a doping mask. Therefore, the impurity ions are doped to both side portions of the semiconductor pattern 120 not covered by the gate electrode 142, so that both side portions of the semiconductor pattern 120 are formed as source and drain regions S and D Function. On the other hand, the central portion of the undoped semiconductor pattern 120 functions as a channel region CH.

On the other hand, in the doping process, the first storage electrode 121 is also doped with impurity ions to have conductive characteristics. In this regard, a second storage electrode 144 is formed on the first storage electrode 121, and the second storage electrode 144 is formed of a first conductive layer having a thickness thin enough to allow the impurity ions to pass therethrough The first storage electrode 121 can be sufficiently doped with impurity ions.

Meanwhile, in the above description, the doping process proceeds after the first photoresist pattern 301 is removed. As another example, the above-described doping process may be performed with the first photoresist pattern 301 left on the gate electrode 142. [

Next, as shown in FIG. 5F, an interlayer insulating film 150 is formed on the gate electrode 142. Next, as shown in FIG. The interlayer insulating film 150 is the same, as the inorganic insulating material may be formed of a silicon oxide (SiO ₂₎ or a single layer or double layer structure using them with a silicon nitride (SiNx).

Next, source and drain contact holes 510 and 520 for exposing the source and drain regions S and D are formed in the gate insulating film and the interlayer insulating films 130 and 150 by the mask process. In the mask process, a first bridge contact hole 530 exposing a part of the second storage electrode 144 is formed in the interlayer insulating film 150. In the mask process, a gate contact hole (550 in FIG. 2) that exposes the gate electrode 142 of the driving transistor Td may be formed in the interlayer insulating film 150.

Next, a metal material is deposited on the interlayer insulating layer 150, and then a mask process is performed to form a bridge pattern 169 with the source and drain electrodes 161 and 163 and the third storage electrode 167 . On the other hand, in this process, the data wiring 160 and the power wiring 165 are formed.

The driving transistor Td including the semiconductor pattern 120, the gate electrode 142, the source electrode and the drain electrode 161 and 163 can be formed through the above-described process, And a light emitting control transistor (see Ts and Te in Fig. 2) can be formed.

Each of the source and drain electrodes 161 and 163 is allowed to contact the source and drain regions S and D through the source and drain contact holes 510 and 520. [

The third storage electrode 167 is electrically connected to the first storage electrode 121. In this regard, the third storage electrode 167 is connected to the source electrode 161 of the driving transistor Td, and the first storage electrode 121 is connected to the source region S of the driving transistor Td The first and third storage electrodes 121 and 167 can be electrically connected through the connection of the source electrode 161 and the source region S through the source contact hole 510. [ Alternatively, a separate contact hole for directly connecting the first and third storage electrodes 121 and 167 may be formed, which may be formed in the formation of the source contact hole 510.

The bridge pattern 169 is brought into contact with the second storage electrode 144 through the first bridge contact hole 530.

Next, a first protective film 170 is formed on the source and drain electrodes 161 and 163. The first protective film 150 as is, as the inorganic insulating material may be formed of a silicon oxide (SiO ₂₎ or a single layer or double layer structure using them with a silicon nitride (SiNx).

Next, a mask process is performed to form a first connection contact hole 560 exposing the drain electrode 163 of the driving transistor Td and a second bridge contact hole 540 exposing the bridge pattern 169, 1 protective film 150 as shown in FIG.

Next, a metal material is deposited on the first protective film 150, and then the masking process is performed to form the connection electrode 180 and the fourth storage electrode 181.

The connection electrode 180 is in contact with the drain electrode 163 through the first connection contact hole 560.

The fourth storage electrode 181 is in contact with the bridge electrode 169 through the second bridge contact hole 540. Accordingly, the fourth storage electrode 181 can be electrically connected to the second storage electrode 144 through the bridge electrode 169.

Through the above-described process, the first to fourth storage electrodes 121, 144, 167 and 181 can be formed to form a triple-structure storage capacitor Cst.

Next, as shown in FIG. 5G, a second protective film 190 is formed on the connection electrode 180. Next, as shown in FIG. The second protective layer 190 may function as a planarizing layer for reducing the stepped portion of the substrate 110 on which the connection electrode 180 is formed. The second passivation layer 190 may be formed of, for example, an organic insulating material.

Next, a mask process is performed on the second protective film 190 to form a second connection contact hole 570 exposing the connection electrode 180.

Next, a first electrode 210 is formed on the second protective film 190 for each pixel region P.

Next, the bank layer 220 is formed along the boundary of the pixel region P on the first electrode 210. The bank layer 220 may be formed with an opening 221 for exposing the first electrode 210.

Next, the organic light emitting layer 230 is formed along the opening 221 on the first electrode 210. Next, a second electrode 240 is formed on the organic light emitting layer 230.

The first and second electrodes 210 and 240 and the organic light emitting layer 230 between them constitute an organic light emitting diode (OD).

Through the above-described process, an array substrate for an organic light emitting diode display can be formed.

On the other hand, an encapsulation substrate, for example, may be attached as an array substrate and an opposing substrate manufactured as described above to complete an organic light emitting diode display.

As described above, according to the embodiment of the present invention, the first to fourth storage electrodes can be formed to realize a triple-structure storage capacitor. As a result, the storage capacity can be improved compared to the area. Therefore, the area occupied by the storage area can be reduced as compared with the prior art, and as a result, the aperture ratio can be improved.

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and equivalents thereof.

100: organic light emitting diode display device 120: semiconductor pattern
121: first storage electrode 140: gate wiring
142: gate electrode 144: second storage electrode
145: light emission control wiring 160: data wiring
161: source electrode 163: drain electrode
165: power supply wiring 167: third storage electrode
169: Bridge electrode 180: Connection electrode
181: fourth storage electrode 510: source contact hole
520: drain contact hole 530: first bridge contact hole
540: second bridge contact hole 550: gate contact hole
560: first connection contact hole 570: second connection contact hole
Ts: switching transistor Td: driving transistor]
Te: emission control transistor

Claims (12)

A first storage electrode made of the same material as the semiconductor pattern and doped with impurity ions;
A gate insulating film formed on the semiconductor pattern and the first storage electrode;
A second storage electrode made of a first conductive layer and disposed on a gate insulating film in a region corresponding to the first storage electrode and a second storage electrode formed on the gate insulating film in a region corresponding to a channel region of the semiconductor pattern, A gate electrode disposed on the gate insulating film;
An interlayer insulating film formed on the second storage electrode and the gate electrode;
A source electrode and a drain electrode which are disposed on the interlayer insulating film and are connected to the source region and the drain region of the semiconductor pattern, and an interlayer insulating film which is disposed on the interlayer insulating film in a region corresponding to the second storage electrode, A third storage electrode;
A first protective layer formed on the source electrode and the drain electrode and on the third storage electrode;
A fourth storage electrode disposed on the first protective film and connected to the drain electrode, and a fourth storage electrode disposed on the first protective film in a region corresponding to the third storage electrode and electrically connected to the second storage electrode;
A second protective layer formed on the connection electrode and the fourth storage electrode;
And an organic light emitting diode formed on the second protective film,
The organic light emitting diode includes a first electrode connected to the connection electrode, a second electrode and an organic light emitting layer between the first electrode and the second electrode. The first electrode extends to an upper portion of the fourth storage electrode, And the second protective film is interposed therebetween.
The method according to claim 1,
And a bridge electrode formed on the same layer as the source electrode and the drain electrode and electrically connecting the second and fourth storage electrodes,
And an organic light emitting diode (OLED).
The method according to claim 1,
Wherein the first conductive layer has a thickness of 200 ANGSTROM to 500 ANGSTROM.
3. The method of claim 2,
A first bridge contact hole for connection between the second storage electrode and the bridge pattern is formed in the interlayer insulating film,
The first protective film is formed with a second bridge contact hole for connection between the bridge electrode and the fourth storage electrode
(OLED) display device.
The method according to claim 1,
And a second contact hole formed for connection between the connection electrode and the organic light emitting diode,
And an organic light emitting diode (OLED).
Forming a first storage electrode made of the same material as the semiconductor pattern and the semiconductor pattern on the substrate;
Forming a gate insulating film on the semiconductor pattern and the first storage electrode;
Forming a second storage electrode of a first conductive layer on a gate insulating film in a region corresponding to the first storage electrode and forming a second storage electrode on the gate insulating film in a region corresponding to a channel region of the semiconductor pattern, Forming a gate electrode layer;
Doping the first storage electrode with impurity ions by performing a doping process using the gate electrode with a doping mask;
Forming an interlayer insulating film on the second storage electrode and the gate electrode;
A source electrode and a drain electrode connected to the source region and the drain region of the semiconductor pattern are formed on the interlayer insulating film and electrically connected to the first storage electrode on the interlayer insulating film in a region corresponding to the second storage electrode Forming a third storage electrode;
Forming a first protective layer on the source electrode and the drain electrode and on the third storage electrode;
Forming a connection electrode connected to the drain electrode on the first protective film and forming a fourth storage electrode electrically connected to the second storage electrode on the first protective film in a region corresponding to the third storage electrode step;
And forming an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer therebetween, the organic light emitting diode being connected to the connection electrode,
Wherein the first electrode extends to an upper portion of the fourth storage electrode, and the first electrode and the fourth storage electrode are disposed with a second protective film interposed therebetween.
The method according to claim 6,
Forming a bridge electrode electrically connecting the second and fourth storage electrodes when forming the source electrode and the drain electrode,
Wherein the organic electroluminescent display device comprises a first electrode and a second electrode.
The method according to claim 6,
Wherein the first conductive layer has a thickness of 200 ANGSTROM to 500 ANGSTROM.
The method according to claim 6,
Wherein the gate electrode comprises a second conductive layer located on the first conductive layer, and the first conductive layer and the second conductive layer are etched into etchant different from each other.
10. The method of claim 9,
Wherein the first conductive layer is made of a transparent conductive material or MoTi, and the second conductive layer is made of Mo.
8. The method of claim 7,
Forming a first bridge contact hole for connection between the second storage electrode and the bridge pattern on the interlayer insulating film;
Forming a second bridge contact hole in the first protective film for connection between the bridge electrode and the fourth story electrode;
Wherein the organic electroluminescent display device comprises a first electrode and a second electrode.
The method according to claim 6,
Forming a second protective layer having a connection contact hole for connection between the connection electrode and the organic light emitting diode
Wherein the organic electroluminescent display device comprises a first electrode and a second electrode.

Images