KR20140013166A - Organic light emitting diode display and method of manufacturing the same - Google Patents

Abstract

The present invention provides an organic light emitting diode display comprising: a semiconductor pattern, and a first storage electrode composed of the same material as the semiconductor pattern and doped with impurity ions, disposed on a substrate; a gate insulating film disposed on the semiconductor pattern and the first storage electrode; a second storage electrode corresponding to the first storage electrode and made of a first conductive layer, and a gate electrode corresponding to the channel area of the semiconductor pattern and made of multilayers including the first conductive layer, disposed on the gate insulating film; an inter-layer insulating film disposed on the second storage electrode and the gate electrode; a source electrode and a drain electrode connected to a source area and a drain area in the semiconductor pattern, respectively, and a third storage electrode corresponding to the second storage electrode and electrically connected to the first storage electrode, disposed on the inter-layer insulating film; a first passivation film disposed on the source electrode, the drain electrode and the third storage electrode; a connection electrode connected to the drain electrode, and a fourth storage electrode corresponding to the third storage electrode and electrically connected to the second storage electrode, disposed on the first passivation film; and an organic light emitting diode connected to the connection electrode.

Description

[0001] The present invention relates to an organic light emitting diode (OLED) display device and a method of manufacturing the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OLED display, and more particularly, to an OLED display and a method of manufacturing the same.

2. Description of the Related Art [0002] As an information-oriented society develops, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as organic light emitting diode (OLED) display devices have been utilized.

Of these flat panel display devices, organic light emitting element display devices have recently been widely used because they have advantages of miniaturization, weight reduction, thinness, and low power driving.

As an organic light emitting diode display device, an active matrix type organic light emitting diode display device in which a switching transistor is formed in each of pixels arranged in a matrix form is widely used.

The pixel region includes a driving transistor and an organic light emitting diode, and a storage capacitor for maintaining a voltage applied to the gate electrode of the driving transistor.

Conventionally, in constructing a storage capacitor, a single or double capacitor structure, that is, a maximum double capacitor structure is adopted. The single capacitor structure uses two storage electrodes, and the double capacitor structure uses three storage electrodes.

Such a storage electrode is constructed using a metal thin film or the like laminated in an organic light emitting display device.

The storage capacitor capacity increases as the area increases. Therefore, when a maximum double capacitor structure is used as in the prior art, the area is inevitably increased to secure sufficient capacitor capacity. This means that the area occupied by the storage area in the pixel area should be increased.

As a result, the aperture ratio is reduced, which impedes the development of high resolution display devices.

SUMMARY OF THE INVENTION An object of the present invention is to provide an organic light emitting display device and a method of manufacturing the same, which can reduce the storage area and improve the aperture ratio.

In order to achieve the above object, the present invention provides a semiconductor pattern and a first storage electrode made of the same material as the semiconductor pattern and doped with impurity ions; A gate insulating film formed on the semiconductor pattern and the first storage electrode; A second storage electrode on the gate insulating layer, the second storage electrode corresponding to the first storage electrode and formed of a first conductive layer, and a multi-layer gate electrode corresponding to the channel region of the semiconductor pattern and including the first conductive layer; An interlayer insulating film formed on the second storage electrode and the gate electrode; A source electrode and a drain electrode connected to the source region and the drain region of the semiconductor pattern, a third storage electrode corresponding to the third storage electrode and electrically connected to the first storage electrode; A first passivation layer formed on the source electrode, the drain electrode, and the third storage electrode; A connection electrode connected to the drain electrode on the first passivation layer, a fourth storage electrode corresponding to the third storage electrode and electrically connected to the second storage electrode; An organic light emitting diode display device including an organic light emitting diode connected to the connection electrode is provided.

Here, the source electrode and the drain electrode may be formed on the same layer, and may include a bridge electrode for electrically connecting the second and fourth storage electrodes.

The first conductive layer may have a thickness of 200 kPa to 500 kPa.

A first bridge contact hole is formed in the interlayer insulating layer for the connection between the second storage electrode and the bridge pattern, and a second bridge contact hole is formed in the first passivation layer for the connection between the bridge electrode and the fourth story electrode. Can be formed.

The display device may include a second passivation layer in which a connection contact hole for connecting between the connection electrode and the organic light emitting diode is formed.

In another aspect, the present invention includes forming a semiconductor pattern and a first storage electrode made of the same material as the semiconductor pattern on a substrate; Forming a gate insulating film on the semiconductor pattern and the first storage electrode; On the gate insulating layer, a second storage electrode corresponding to the first storage electrode and formed of a first conductive layer, and a gate electrode formed of multiple layers corresponding to the channel region of the semiconductor pattern and including the first conductive layer are formed. Making a step; Doping the gate electrode with a doping mask to dope the first storage electrode with impurity ions; Forming an interlayer insulating film on the second storage electrode and the gate electrode; Forming a source electrode and a drain electrode connected to the source region and the drain region of the semiconductor pattern, and a third storage electrode corresponding to the third storage electrode and electrically connected to the first storage electrode on the interlayer insulating layer; Steps; Forming a first passivation layer on the source and drain electrodes and the third storage electrode; Forming a connection electrode connected to the drain electrode on the first passivation layer, and a fourth storage electrode corresponding to the third storage electrode and electrically connected to the second storage electrode; It provides a method of manufacturing an organic light emitting display device comprising forming an organic light emitting diode connected to the connection electrode.

The method may include forming a bridge electrode electrically connecting the second and fourth storage electrodes when the source electrode and the drain electrode are formed.

The first conductive layer may have a thickness of 200 kPa to 500 kPa.

The gate electrode may include a second conductive layer on the first conductive layer, and the first conductive layer and the second conductive layer may be etched with different etchant.

The first conductive layer may be made of a transparent conductive material or MoTi, and the second conductive layer may be made of Mo.

Forming a first bridge contact hole in the interlayer insulating film to connect the second storage electrode and the bridge pattern; The method may include forming a second bridge contact hole in the first passivation layer for connecting the bridge electrode and the fourth story electrode.

The method may include forming a second passivation layer in which a connection contact hole for connection between the connection electrode and the organic light emitting diode is formed.

In the present invention, the first to fourth storage electrodes can be configured to implement a storage capacitor having a triple structure. Accordingly, the storage capacity compared to the area can be improved. Therefore, compared with the related art, the area occupied by the storage area can be reduced, and consequently, the opening ratio can be improved.

1 is a circuit diagram schematically showing an organic light emitting display device according to an embodiment of the present invention.
2 is a plan view schematically illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.
3 is a cross-sectional view along cut lines AA and BB of FIG. 2;
4 is a cross-sectional view illustrating a storage capacitor of an organic light emitting diode display according to an exemplary embodiment of the present invention.
5A to 5G are cross-sectional views illustrating a method of manufacturing an organic light emitting display device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 is a circuit diagram schematically showing an organic light emitting diode display according to an embodiment of the present invention, FIG. 2 is a plan view schematically showing an organic light emitting diode display according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along cut lines AA and BB, and FIG. 4 is a cross-sectional view illustrating a storage capacitor of an organic light emitting diode display according to an exemplary embodiment of the present invention.

In the embodiment of the present invention, for convenience of description, a 3T1C structure including three transistors and one capacitor in each pixel region will be described as an example. Of course, this is one example, as the other various structures, for example, the embodiment of the present invention can also be applied to a structure such as 2T1C, 4T1C, 5T1C, 6T1C.

Since the three transistors in the pixel region have substantially the same structure, the description will be mainly focused on the driving transistors, and the same reference numerals may be used for components constituting the three transistors. 2 illustrates a storage capacitor.

1 to 3, the organic light emitting diode display 100 according to the exemplary embodiment of the present invention defines a plurality of pixel regions P arranged in a matrix form. In each pixel area P, a switching transistor Ts, a driving transistor Td, an emission control transistor Te, an organic light emitting diode OD, and a triple storage capacitor Cst may be configured.

The switching transistor Ts is connected to the corresponding gate wiring and data wiring 140 and 160 and is turned on according to the gate signal applied to the gate wiring 140. When the switching transistor Ts is turned on, the data voltage transmitted through the data line 160 is applied to the gate electrode 142 of the driving transistor Td in synchronization with the switching transistor Ts.

Accordingly, the driving transistor Td is turned on so that the light emission current flows through the channel region CH. The magnitude of the luminous current is determined by the magnitude of the applied data voltage. For example, the magnitude of the luminous current is determined in proportion to the data voltage.

When such a light emitting current is supplied to the organic light emitting diode OD, light having a luminance corresponding to the size of the light emitting current is emitted.

On the other hand, the light emission control transistor Te controls the turn on / off of the organic light emitting diode OD. That is, when the light emitting control transistor Te is turned on, the driving voltage Vdd can be applied to the driving transistor Td, so that a light emitting current corresponding to the data voltage can be generated and supplied to the organic light emitting diode OD. do. On the other hand, when the light emission control transistor Te is turned off, the driving voltage Vdd cannot be applied to the drive transistor Td, so that no light emission current is generated and the organic light emitting diode OD is turned off.

The gate line and the data line 140 and 160 cross each other. For example, the gate line 140 extends in the first direction and the data line 160 extends in the second direction.

Meanwhile, the emission control wiring 145 connected to the emission control transistor Te may be further provided. The emission control wiring 145 may be formed of the same material as the gate wiring 140 and may extend in the first direction and be spaced apart from the gate wiring 140, but is not limited thereto.

In addition, a power line 165 for transmitting the driving voltage Vdd may be further provided. The power line 165 may be formed of the same material on the same layer as the data line 160, may extend in the second direction, and may be spaced apart from the data line 160, but is not limited thereto.

The above-described switching transistor Ts, the driving transistor Td, and the light emission control transistor Te are formed in substantially the same structure. In this regard, the driving transistor Td will be described as an example.

The driving transistor Td includes a semiconductor pattern 120, a gate electrode 142, and source and drain electrodes 161 and 163. The semiconductor pattern 120 is formed on the substrate 110 and may be made of crystalline silicon. The semiconductor pattern 120 may include a channel region CH, a source region, and a drain region S and D. The channel region CH is positioned at the center of the semiconductor pattern 120 and may be made of pure crystalline silicon as a movement region of holes or electrons. On the other hand, the source region and the drain region are located at both sides of the channel region CH, respectively, and may be composed of crystalline silicon doped with impurity ions such as n + or p + ions.

The gate insulating layer 130 may be formed on the semiconductor pattern 120, and the gate electrode 142 may be formed on the gate insulating layer 130 corresponding to the channel region CH.

An interlayer insulating layer 150 may be formed on the gate electrode 142, and source and drain electrodes 161 and 163 may be formed on the interlayer insulating layer 150. The interlayer insulating layer 150 may include source contact holes and drain contact holes 510 and 520 exposing the source and drain regions S and D, respectively. Through the source contact hole and the drain contact hole 510 and 520, respectively, the source electrode and the drain electrode 161 and 163 may be in contact with the corresponding source region and the drain region S and D.

The organic light emitting diode OD electrically connected to the driving transistor Td may include first and second electrodes 210 and 240 and an organic light emitting layer 230 disposed between the electrodes.

The first electrode 210 is connected to the drain electrode 163 of the driving transistor Td. According to the exemplary embodiment of the present invention, the connection electrode 180 may be configured for connection therebetween.

In this regard, the connection electrode 180 is formed on the first passivation layer 170, and the first connection contact hole 560 exposing the drain electrode 180 of the driving transistor Td is formed in the first passivation layer 170. This can be formed. Through the first connection contact hole 560, the connection electrode 180 may be in contact with the drain electrode 163.

The second passivation layer 190 may be formed on the connection electrode 180. The second passivation layer 190 may function as a planarization layer. Accordingly, the first electrode 210 formed on the second passivation layer 190 may be formed to be substantially flat. A second connection contact hole 570 may be formed in the second passivation layer 190. Through the second connection contact hole 570, the first electrode 210 may be in contact with the connection electrode 180.

Through the above configuration, the organic light emitting diode OD may be electrically connected to the driving transistor Td.

Meanwhile, the bank layer 220 may be formed on the first electrode 210 along the boundary of the pixel region P. FIG. The bank layer 9220 may include an opening 221, and an organic light emitting layer 230 may be formed in the opening 221. On the other hand, the organic light emitting layer 230 may be formed to extend from the opening 221 so that the bank layer 220 and the end overlap.

The second electrode 240 may be configured on the organic light emitting layer 230 substantially over the entire surface of the substrate 110. That is, the first electrode and the organic light emitting layers 210 and 230 may be patterned for each pixel region, and the second electrode 240 may be integrally formed over all the pixel regions P. FIG.

Meanwhile, in the embodiment of the present invention, the storage capacitor Cst has a triple structure, which will be described in more detail.

The storage capacitor Cst according to the embodiment of the present invention may include first to fourth storage electrodes 121, 144, 167, and 181.

The first storage electrode 121 may be formed on the same layer as the same material as the semiconductor pattern 120. As such, the first storage electrode 121 is formed of a semiconductor material, and the first storage electrode 121 has a source region and a drain so that the first storage electrode 121 has a conductivity sufficient to function as an electrode. Like the regions (S, D), it may be made of crystalline silicon doped with impurities.

The second storage electrode 144 is configured to correspond to the first storage electrode 121 with the gate insulating layer 130 interposed therebetween. The second storage electrode 144 may be formed on the same layer as the gate electrode 142. Here, the gate electrode 142 may have a multilayer structure, for example, a double layer structure, and the second storage electrode 144 may have a single layer structure using a lowermost layer of the gate electrode 142.

In this regard, when the gate electrode 142 has a double layer structure, the first conductive layer 141a, which is a lower layer, is preferably formed to allow impurity ions to pass through during the doping process. The upper conductive layer 141b may be made of a low resistance conductive material. In this case, the second storage electrode 144 may be formed of the first conductive layer 141a of the gate electrode 142.

In this regard, the first conductive layer 141a is configured to have a thin thickness so that impurity ions can be transmitted. For example, the first conductive layer 141a is preferably configured to have a thickness of about 200 kPa to about 500 kPa.

In addition, the second conductive layer 141b is preferably made of a metal material having a lower resistance than the first conductive layer 141a. In addition, the first conductive layer 141a and the second conductive layer 141b may be formed of materials having different etching characteristics. That is, the first and second conductive layers 141a and 141b are preferably etched with different etchant.

In this regard, for example, the first conductive layer 141a may be a transparent conductive material such as indium-tin-oxide (ITO), indium-zinc-oxde (IZO), or indium-tin-zinc-oxide (ITZO), or MoTi. (molybdenum titanium), but is not limited thereto. The second conductive layer 141b may use Mo (molybdenum), but is not limited thereto.

On the other hand, the gate wiring and the light emission control wiring 140 and 145 have the same multilayer structure as the gate electrode 142.

The third storage electrode 167 is configured to correspond to the second storage electrode 144 with the interlayer insulating film 150 interposed therebetween. The third storage electrode 144 may be formed of the same material as the source electrode and the drain electrode 161 and 163 on the same layer.

The fourth storage electrode 181 is configured to correspond to the third storage electrode 167 with the first passivation layer 170 interposed therebetween. The fourth storage electrode 181 may be formed of the same material on the same layer as the connection electrode 180.

In the above-described first to fourth storage electrodes 121, 144, 167, and 181, between the first and second storage electrodes 121 and 144, between the second and third storage electrodes 144 and 167, and between the third and fourth storage electrodes 121, 144, and 181. Storage capacitors Cst1 to Cst3 may be formed between each of the storage electrodes 167 and 181. For convenience of description, the storage capacitors formed as described above may include first to third storage capacitors Cst1 to Cst3. It is called).

The first and third storage electrodes 121 and 167 may be electrically connected to each other, and the second and fourth storage electrodes 144 and 181 may be electrically connected to each other. According to such a connection relationship, the first and third storage electrodes 121 and 167 function as one storage electrode and the second and fourth storage electrodes 144 and 181 function as one opposite story electrode. The storage capacitor Cst according to the embodiment can be configured. That is, the three storage capacitors Cst1 to Cst3 may be configured to implement a storage capacitor Cst having a triple structure.

As described above, in the embodiment of the present invention, since the storage capacitor Cst can be configured by using the four storage electrodes 121, 144, 167, and 181, the area of the storage area can be reduced. That is, compared to the conventional one using a single or double structure, according to the embodiment of the present invention by adopting a triple structure, the distance between the storage electrodes is reduced, so that the capacity to the area of the storage area can be improved. Therefore, in realizing the same capacity as in the prior art, a smaller area can be used than in the prior art. Accordingly, the area of the storage area is reduced, and as a result, the effect of increasing the aperture ratio of the pixel area can be exerted.

Meanwhile, in the embodiment of the present invention, the first and third storage electrodes 121 and 167 are connected to the source electrode 161 side of the driving transistor Td, and the second and fourth storage electrodes 144 and 181 are connected to each other. It is connected to the gate electrode 142 side of the driving transistor Td.

Here, the connection between the first and third storage electrodes 121 and 167 may be made through contact holes formed in the gate insulating film and the interlayer insulating films 130 and 150. Meanwhile, in the exemplary embodiment of the present invention, the source contact hole 510 of the driving transistor Td may function as a contact hole connecting the first and third storage electrodes 121 and 167.

In this regard, the first storage electrode 121 may extend from the semiconductor pattern 120 of the driving transistor Td, and the third storage electrode 167 may be the source electrode 161 of the driving transistor Td. It can be formed extending from. Accordingly, the first and third storage electrodes 121 and 167 may be connected to each other by connecting the source region S and the source electrode 161 through the source contact hole 510.

On the other hand, the drain electrode 163 of the light emission control transistor Te is connected to the source electrode 161 of the driving transistor Td. In the embodiment of the present invention, the source electrode 161 of the driving transistor Td is light emission control. The case of serving as the drain electrode 163 of the transistor Te is illustrated as an example. The semiconductor pattern 120 of the emission control transistor Te may extend from the first storage electrode 121.

The connection between the second and fourth storage electrodes 144 and 181 may be made through, for example, a bridge pattern 169 positioned therebetween. The bridge pattern 169 may be formed of the same material as the source and drain electrodes 161 and 163, and the second and fourth storage electrodes 144 through the first and second bridge contact holes 530 and 540, respectively. , 181). Here, the first bridge contact hole 530 is formed in the interlayer insulating layer 150, through which the bridge pattern 169 may contact the second storage electrode 144. In addition, the second bridge contact hole 540 is formed in the first passivation layer 170, through which the bridge pattern 169 may contact the fourth storage electrode 181. The bridge pattern 169 may extend from the drain electrode 163 of the switching transistor Ts.

The bridge pattern 169 and the fourth storage electrode 181 may be in contact with each other on the gate line 140, and for this purpose, the second bridge contact hole 530 may be formed on the gate line 140. In this case, it is possible to prevent the storage area from being reduced by securing an area for connecting the bridge pattern 169 and the fourth storage electrode 181. That is, the storage area can be secured more efficiently.

On the other hand, the second bridge contact hole 530 may be formed in a region other than the gate wiring 140. In this case, the storage area is preferably formed in close proximity to the gate wiring 140.

The gate electrode 142 of the driving transistor Td is connected to the drain electrode 163 of the switching transistor Ts. In this regard, for example, the gate electrode 142 of the driving transistor Td is a bridge pattern (Td). 169 may be configured to be connected to the drain electrode 163 of the switching transistor Ts. To this end, a gate contact hole 550 exposing the gate electrode 142 of the driving transistor Td may be formed in the interlayer insulating layer 150, through which the bridge pattern 169 and the gate of the driving transistor Td are formed. The electrode 142 may be configured to be in contact.

Meanwhile, in the above case, the second storage electrode 144 and the gate electrode 142 of the driving transistor Td are separately patterned. In contrast, the gate electrode 142 of the driving transistor Td is the second storage. It may be formed extending from the electrode 144. In this case, the drain electrode 163 of the switching transistor Ts and the gate electrode 142 of the driving transistor Td may be electrically connected through the first bridge contact hole 530. That is, the first bridge contact hole 530 may also function as the gate contact hole 550.

As described above, according to the embodiment of the present invention, the first to fourth storage electrodes 121, 144, 167, and 181 may be configured to implement the storage capacitor Cst having a triple structure. Accordingly, the storage capacity compared to the area can be improved. Therefore, compared with the related art, the area occupied by the storage area can be reduced, and consequently, the opening ratio can be improved.

In this regard, reference may be made to Table 1 below.

Conventional (double structure) Example (Triple Structure) Storage capacity 240 pF 240 pF First storage capacity - 97 pF Second storage capacity
(Primary first storage capacity) 108 pF 65 pF Part 3 Storage Capacity
(Conventional second storage capacity) 132 pF 79 pF Storage area 670u㎡ 400u㎡ Storage area ratio 100% 60% Storage area ratio to pixel area 13% 8%

Table 1 shows the simulation results in a 7 inch high definition (HD) model.

Looking at this, in securing a storage capacity of approximately 240 pF, it can be seen that the storage area of the embodiment is required about 60% of the conventional storage area. Accordingly, the storage area occupies about 8% of the pixel area, and the aperture ratio of about 5% is increased.

As described above, according to the embodiment of the present invention, the storage area can be reduced, and the opening ratio can be improved.

Hereinafter, a method of manufacturing an organic light emitting diode display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 5A to 5G.

5A through 5G are cross-sectional views illustrating a method of manufacturing an organic light emitting display device according to an embodiment of the present invention.

First, as shown in FIG. 5A, amorphous silicon is deposited on the substrate 110 to form a semiconductor layer. Meanwhile, the buffer layer may be formed before the semiconductor layer is formed, and the semiconductor layer may be formed thereon.

Next, a crystallization process is performed on the semiconductor layer to form a semiconductor layer made of crystalline silicon. Next, the semiconductor layer 120 and the first storage electrode 121 are formed by patterning the semiconductor layer by performing a mask process.

Next, a gate insulating layer 130 is formed on the semiconductor pattern 120 and the first storage electrode 121. For example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) may be used as the inorganic insulating material.

Next, as shown in FIG. 5B, the first conductive layer and the second conductive layer 140a and 140b are sequentially formed on the gate insulating film 130, and the photoresist layer 300 is deposited thereon. .

Here, the first conductive layer 140a preferably has a thickness that is thin enough to allow impurity ions to pass through during the subsequent doping process. To this end, the first conductive layer 140a may be formed to a thickness of 200 kPa to 500 kPa.

The second conductive layer 140b may be formed of a metal material having a lower resistance than that of the first conductive layer 140a.

Next, the photomask 400 is positioned on the photoresist layer 300. The photomask 400 may include a transmissive part TA, a transflective part HTA, and a blocking part BA. The transmissive part TA transmits incident light, the blocking part BA blocks the incident light, and the transflective part HTA partially transmits the incident light. The transflective portion (HTA) may be composed of a slit or a transflective membrane. As such, the photomask 400 having the transflective portion HTA is called a slit mask or a halftone mask.

Meanwhile, in the embodiment of the present invention, for convenience of description, a case in which a positive type photoresist layer 300 is used is taken as an example.

In such a case, the blocking part BA may be positioned as a center part of the semiconductor pattern 120 to correspond to an area in which the gate electrode (see 142 of FIG. 5C) is to be formed, and also the gate wiring and the emission control wiring (FIG. 2). 140 and 145) may be positioned corresponding to the region to be formed. The transflective portion HTA is an area in which the second storage electrode (see 144 of FIG. 5D) is to be formed and may correspond to the storage area. The permeation | transmission part TA is arrange | positioned in parts other than the part where the blocking part BA and the transflective part HTA are arrange | positioned.

As described above, the exposure process proceeds in a state where the photomask 400 is disposed, and then the photoresist layer 300 is developed.

Accordingly, as shown in FIG. 5C, a first photoresist pattern 301 having a first thickness is formed in a region corresponding to the blocking part BA, and a first photoresist in a region corresponding to the transflective part HTA. A second photoresist pattern 302 having a second thickness smaller than the thickness is formed.

Next, a first etching process is performed using the first and second photoresist patterns 301 and 302 as an etching mask. Accordingly, the exposed first and second conductive layers 140a and 140b are removed to leave the patterned first and second conductive layers 141a and 141b under the first and second photoresist patterns 301 and 302. do. Here, the patterned first and second conductive layers 141a and 141b below the first photoresist pattern 301 constitute the gate electrode 142, and also constitute the gate wiring 140 and the emission control wiring 145. Done. Meanwhile, the patterned first and second conductive layers 141a and 141b below the second photoresist pattern 302 constitute a storage pattern 143.

Next, as shown in FIG. 5D, an ashing process is performed on the first and second photoresist patterns 301 and 302. Accordingly, the second photoresist pattern 302 is removed to expose the storage pattern 143 below. On the other hand, the first photoresist pattern 301 is left in a reduced thickness.

Next, a second etching process is performed using the ashed first photoresist pattern 301 as an etching mask. Accordingly, the second conductive layer 141b of the storage pattern 143 is removed and the first conductive layer 141a below is left. The first conductive layer 141a left in this manner corresponds to the second storage electrode 144.

As described above, the gate electrode 142 having a double layer structure may be formed, and the second storage electrode 144 having a single layer structure may be formed through one mask process.

As another example, the gate electrodes and the second storage electrodes 142 and 144 may be formed through two mask processes. In this case, after the first conductive layer 140a is deposited, the first mask process is performed to form the patterned first conductive layer 141a and the second storage electrode 144, which are lower layers of the gate electrode 142. Next, after the second conductive layer 140b is deposited, a second mask process may be performed to form the patterned second conductive layer 141b, which is an upper layer of the gate electrode 142.

Meanwhile, the first and second conductive layers 140a, 141a, 140b, and 141b described above may be etched with different etchant. In this regard, in removing the second conductive layer 141b in the second etching process, if the first conductive layer 141b is etched, the second storage electrode 144 may be over-etched according to the over-etching of the first conductive layer 141b. ) Will not be formed in the desired shape. Therefore, it is preferable that the first conductive layer etchant does not react with the second conductive layers 140b and 141b and the second conductive layer etchant does not react with the first conductive layers 140a and 141b.

Next, when the second etching process is completed, the strip process is performed to remove the first photoresist pattern 301.

Next, as shown in FIG. 5E, a doping process using impurity ions such as n + or p + ions is performed. In the doping process, the second conductive layer 141b, which is the upper layer of the gate electrode 142, functions as a doping mask. Therefore, the impurity ions are doped to both sides of the semiconductor pattern 120 which are not covered by the gate electrode 142, and thus both sides of the semiconductor pattern 120 are referred to as source and drain regions S and D. Function. Meanwhile, the central portion of the undoped semiconductor pattern 120 functions as the channel region CH.

On the other hand, during the doping process, the first storage electrode 121 is also doped with impurity ions to have conductive properties. In this regard, a second storage electrode 144 is formed on the first storage electrode 121, and the second storage electrode 144 has a first conductive layer having a thickness thin enough to allow impurity ions to pass therethrough. 141a, the first storage electrode 121 can be sufficiently doped with impurity ions.

Meanwhile, as described above, the doping process is performed after removing the first photoresist pattern 301. As another example, the aforementioned doping process may be performed while the first photoresist pattern 301 remains on the gate electrode 142.

Next, as shown in FIG. 5F, an interlayer insulating film 150 is formed on the gate electrode 142. The interlayer insulating film 150 may be formed in a single layer using a silicon oxide (SiO ₂ ) or silicon nitride (SiNx) as an inorganic insulating material or a double layer structure using the same.

Next, a mask process is performed to form source contact holes and drain contact holes 510 and 520 exposing the source and drain regions S and D in the gate insulating film and the interlayer insulating films 130 and 150. In the mask process, the first bridge contact hole 530 exposing a part of the second storage electrode 144 is formed in the interlayer insulating film 150. In the mask process, a gate contact hole (550 of FIG. 2) exposing the gate electrode 142 of the driving transistor Td may be formed in the interlayer insulating layer 150.

Next, a metal material is deposited on the interlayer insulating film 150, and then a mask process is performed to form source and drain electrodes 161 and 163, a third storage electrode 167, and a bridge pattern 169. . Meanwhile, in such a process, the data wiring 160 and the power wiring 165 are formed.

Through the above-described process, the driving transistor Td including the semiconductor pattern 120, the gate electrode 142, the source electrode, and the drain electrodes 161 and 163 can be formed. The switching transistor and the light emission control transistor (see Ts and Te in FIG. 2) can be formed.

Each of the source and drain electrodes 161 and 163 may be in contact with the source and drain regions S and D through the source and drain contact holes 510 and 520.

The third storage electrode 167 is electrically connected to the first storage electrode 121. In this regard, the third storage electrode 167 is connected to the source electrode 161 of the driving transistor Td, and the first storage electrode 121 is connected to the source region S of the driving transistor Td. Therefore, the first and third storage electrodes 121 and 167 may be electrically connected through the connection between the source electrode 161 and the source region S through the source contact hole 510. Alternatively, a separate contact hole for directly connecting the first and third storage electrodes 121 and 167 may be provided, which may be formed when the source contact hole 510 is formed.

The bridge pattern 169 is in contact with the second storage electrode 144 through the first bridge contact hole 530.

Next, the first passivation layer 170 is formed on the source and drain electrodes 161 and 163. The first passivation layer 150 may be formed of a single layer using a silicon oxide (SiO ₂ ) or silicon nitride (SiNx) as an inorganic insulating material or a double layer structure using the same.

Next, a mask process may be performed to remove the first connection contact hole 560 exposing the drain electrode 163 of the driving transistor Td and the second bridge contact hole 540 exposing the bridge pattern 169. 1 is formed in the protective film 150.

Next, a metal material is deposited on the first passivation layer 150, and then a mask process is performed to form the connection electrode 180 and the fourth storage electrode 181.

The connection electrode 180 is in contact with the drain electrode 163 through the first connection contact hole 560.

The fourth storage electrode 181 is in contact with the bridge electrode 169 through the second bridge contact hole 540. Accordingly, the fourth storage electrode 181 may be electrically connected to the second storage electrode 144 through the bridge electrode 169.

Through the above-described process, the first to fourth storage electrodes 121, 144, 167, and 181 may be formed to form a storage capacitor Cst having a triple structure.

Next, as shown in FIG. 5G, a second passivation layer 190 is formed on the connection electrode 180. The second passivation layer 190 may function as a planarization layer for alleviating the step difference between the substrate 110 on which the connection electrode 180 is formed. The second passivation layer 190 may be made of, for example, an organic insulating material.

Next, a mask process is performed on the second passivation layer 190 to form a second connection contact hole 570 exposing the connection electrode 180.

Next, the first electrode 210 is formed for each pixel area P on the second passivation layer 190.

Next, the bank layer 220 is formed on the first electrode 210 along the boundary of the pixel region P. Referring to FIG. An opening 221 exposing the first electrode 210 may be formed in the bank layer 220.

Next, the organic light emitting layer 230 is formed along the opening 221 on the first electrode 210. Next, the second electrode 240 is formed on the organic light emitting layer 230.

The first and second electrodes 210 and 240 and the organic light emitting layer 230 therebetween constitute an organic light emitting diode OD.

Through the above-described process, an array substrate for an organic light emitting display device can be formed.

On the other hand, the organic light emitting device display device can be completed by bonding the encapsulation substrate as the array substrate and the counter substrate manufactured as described above, for example.

As described above, according to the embodiment of the present invention, the first to fourth storage electrodes may be configured to implement a triple storage capacitor. Accordingly, the storage capacity compared to the area can be improved. Therefore, compared with the related art, the area occupied by the storage area can be reduced, and consequently, the opening ratio can be improved.

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and equivalents thereof.

100: organic light emitting display device 120: semiconductor pattern
121: first storage electrode 140: gate wiring
142: gate electrode 144: second storage electrode
145: light emission control wiring 160: data wiring
161: source electrode 163: drain electrode
165: power supply wiring 167: third storage electrode
169: bridge electrode 180: connecting electrode
181: fourth storage electrode 510: source contact hole
520: drain contact hole 530: first bridge contact hole
540: second bridge contact hole 550: gate contact hole
560: first connection contact hole 570: second connection contact hole
Ts: switching transistor Td: driving transistor]
Te: light emission control transistor

Claims (12)

A first storage electrode formed of a semiconductor pattern on the substrate and of the same material as the semiconductor pattern and doped with impurity ions;
A gate insulating film formed on the semiconductor pattern and the first storage electrode;
A second storage electrode on the gate insulating layer, the second storage electrode corresponding to the first storage electrode and formed of a first conductive layer, and a multi-layer gate electrode corresponding to the channel region of the semiconductor pattern and including the first conductive layer;
An interlayer insulating film formed on the second storage electrode and the gate electrode;
A source electrode and a drain electrode connected to the source region and the drain region of the semiconductor pattern, a third storage electrode corresponding to the third storage electrode and electrically connected to the first storage electrode;
A first passivation layer formed on the source electrode, the drain electrode, and the third storage electrode;
A connection electrode connected to the drain electrode on the first passivation layer, a fourth storage electrode corresponding to the third storage electrode and electrically connected to the second storage electrode;
An organic light emitting diode connected to the connection electrode
And an organic light emitting diode.
The method of claim 1,
A bridge electrode formed on the same layer as the source electrode and the drain electrode and electrically connecting the second and fourth storage electrodes.
And an organic light emitting diode (OLED).
The method of claim 1,
The first conductive layer has an organic light emitting device display device having a thickness of 200 ~ 500Å.
3. The method of claim 2,
A first bridge contact hole for connecting between the second storage electrode and the bridge pattern is formed in the interlayer insulating film,
A second bridge contact hole is formed in the first passivation layer for connection between the bridge electrode and the fourth story electrode.
Organic light emitting display device.
The method of claim 1,
A second passivation layer formed with a connection contact hole for connection between the connection electrode and the organic light emitting diode
And an organic light emitting diode (OLED).
Forming a semiconductor pattern on the substrate and a first storage electrode made of the same material as the semiconductor pattern;
Forming a gate insulating film on the semiconductor pattern and the first storage electrode;
On the gate insulating layer, a second storage electrode corresponding to the first storage electrode and formed of a first conductive layer, and a gate electrode formed of multiple layers corresponding to the channel region of the semiconductor pattern and including the first conductive layer are formed. Making a step;
Doping the gate electrode with a doping mask to dope the first storage electrode with impurity ions;
Forming an interlayer insulating film on the second storage electrode and the gate electrode;
Forming a source electrode and a drain electrode connected to the source region and the drain region of the semiconductor pattern, and a third storage electrode corresponding to the third storage electrode and electrically connected to the first storage electrode on the interlayer insulating layer; Steps;
Forming a first passivation layer on the source and drain electrodes and the third storage electrode;
Forming a connection electrode connected to the drain electrode on the first passivation layer, and a fourth storage electrode corresponding to the third storage electrode and electrically connected to the second storage electrode;
Forming an organic light emitting diode connected to the connection electrode
Wherein the organic electroluminescent display device comprises a first electrode and a second electrode.
The method according to claim 6,
Forming a bridge electrode electrically connecting the second and fourth storage electrodes when the source electrode and the drain electrode are formed;
Wherein the organic electroluminescent display device comprises a first electrode and a second electrode.
The method according to claim 6,
The first conductive layer has a thickness of 200 kV to 500 mW.
The method according to claim 6,
The gate electrode includes a second conductive layer positioned on the first conductive layer, wherein the first conductive layer and the second conductive layer are etched with different etchant.
The method of claim 9,
The first conductive layer is made of transparent conductive material or MoTi, and the second conductive layer is made of organic light emitting display device.
The method of claim 7, wherein
Forming a first bridge contact hole in the interlayer insulating film to connect the second storage electrode and the bridge pattern;
Forming a second bridge contact hole in the first passivation layer for connecting the bridge electrode and the fourth story electrode;
Wherein the organic electroluminescent display device comprises a first electrode and a second electrode.
The method according to claim 6,
Forming a second passivation layer having a connection contact hole for connection between the connection electrode and the organic light emitting diode;
Wherein the organic electroluminescent display device comprises a first electrode and a second electrode.

Images