KR20170078075A - Organic light emitting diode display device - Google Patents

Abstract

The present invention relates to an OLED display device capable of reducing power consumption and improving storage capacitor capacity. In an OLED display according to an embodiment, each pixel circuit includes a first storage electrode on a gate insulating layer connected to a gate electrode of a driving transistor, a second storage electrode connected to a source electrode of the driving transistor, And a third storage electrode connected to the second storage electrode and overlapping the first storage electrode and the gate insulating layer or overlapped with the gate insulating layer and the buffer layer interposed therebetween.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode (OLED) display device capable of increasing the capacity of a storage capacitor and ensuring a sufficient wiring interval.

The display device includes a liquid crystal display (LCD), an organic light emitting diode (OLED), an electrophoretic display (EPD), and an electro wetting display.

Of these, OLED display devices are self-luminous devices that emit organic light-emitting layers by recombination of electrons and holes, and are expected to be a next generation display device because of their high brightness, low driving voltage and thin film. OLED display devices are applicable to various applications such as portable terminals, TV sets, flexible displays, and transparent displays.

Each of the plurality of pixels constituting the OLED display device includes an OLED element composed of an organic light emitting layer between the anode and the cathode, and a pixel circuit independently driving the OLED element. The pixel circuit includes a switching thin film transistor (TFT) that supplies a data voltage to the storage capacitor, a driving TFT that controls the driving current according to the driving voltage charged to the storage capacitor and supplies the OLED element to the OLED element, The device generates light proportional to the driving current.

Recently, TFTs applied to display devices have higher mobility than amorphous silicon TFTs, have a lower temperature than polycrystalline silicon TFTs, are easy to apply for large-area applications, and have an oxide semiconductor (Oxide Semiconductor ) TFT (hereinafter, referred to as an oxide TFT) is attracting attention.

OLED display devices are required to have a capacity to increase the capacity of a storage capacitor within a limited pixel circuit area because the pixel circuit area of each pixel is reduced along with the size of each pixel as the resolution is increased.

In addition, as the number of wirings increases, an OLED display device applied to small and medium-sized flexible display devices is required to secure a gap between wirings in a limited non-display area.

The present invention provides an OLED display device capable of increasing a storage capacitor capacity and sufficiently securing a wiring interval.

In an OLED display according to an embodiment of the present invention, each pixel circuit includes an active layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer stacked on a buffer layer, and an interlayer insulating layer disposed on the interlayer insulating layer, A plurality of thin film transistors each including a source electrode and a drain electrode, and a shield metal layer overlapping one of the plurality of thin film transistors under the buffer layer.

Each pixel circuit includes a first storage electrode on the gate insulating layer connected to the gate electrode of the driving transistor, a second storage electrode connected to the source electrode of the driving thin film transistor and overlapping the first storage electrode through the interlayer insulating layer, And a third storage electrode connected to the second storage electrode and overlapping the first storage electrode and the gate insulating layer or overlapping the gate insulating layer and the buffer layer.

An OLED display device according to an embodiment further includes a display area and a plurality of link wires connecting the drive circuit. The plurality of link wirings are disposed on the interlayer insulating layer like the source electrode and the drain electrode, and have a first link wiring composed of the same material as the source electrode and the drain electrode, a second link wiring located on the same layer as the third storage electrode, And a second link wiring composed of the same material as the first link wiring.

The active layer is composed of an oxide semiconductor layer, and a multi-barrier layer in which a plurality of insulating layers are stacked below the buffer layer and a flexible substrate below the multi-barrier layer may be additionally provided.

An OLED display according to an embodiment of the present invention uses an oxide TFT having a coplanar structure capable of reducing power consumption as a switching element of a pixel circuit and also has a structure in which a first storage electrode on a gate insulating layer is made of a The first storage electrode overlaps with the first storage electrode and the second storage electrode overlaps with the first storage electrode with the gate insulating layer interposed therebetween or the first storage electrode overlaps the first storage electrode with the gate insulating layer therebetween, The capacity of the storage capacitor can be improved without increasing the area within the limited pixel circuit area by providing the storage capacitor in a parallel structure of the second capacitors formed by the second capacitor.

In the OLED display according to the embodiment of the present invention, the first link interconnection in the same layer as the data line and the second interconnection interconnection in the same layer as the third storage electrode are alternately arranged in the non-display region, The interval between the link wirings in the limited non-display area including the wirings can be sufficiently secured and the reliability can be improved.

1 illustrates an OLED display using an oxide TFT according to an embodiment of the present invention and a pixel.
2 is a cross-sectional view illustrating a pixel circuit according to an embodiment of the present invention.
3 is a cross-sectional view illustrating a pixel circuit according to another embodiment of the present invention.
4A to 4C are cross-sectional views sequentially illustrating a method of forming a third storage electrode and an active layer according to an embodiment of the present invention.
5 is a simplified view of the link wires of an OLED display according to an embodiment of the present invention.
6 is a cross-sectional view showing a link wiring portion according to an embodiment of the present invention.
7 is a cross-sectional view illustrating a link wiring portion according to another embodiment of the present invention.

FIG. 1 is a diagram illustrating a structure of a pixel and an OLED display using an oxide TFT according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 1, an OLED display includes a display panel 100, a gate driver 200, a data driver 300, and the like.

The display panel 100 displays an image through a pixel array AA in which pixels are arranged in a matrix form.

Each pixel SP includes an OLED element connected between a high potential power supply (EVDD) line and a low potential power supply (EVSS) line, a first and a second switching TFTs ST1 and ST2 for independently driving the OLED element, And a pixel circuit including a driver TFT (DT) and a storage capacitor (Cst). Since the pixel circuit configuration is varied, the structure is not limited to the structure of FIG. The switching TFTs (ST1, ST2) and the driving TFT (DT) of each pixel (P) use an oxide TFT. Since the oxide TFT has a small off-current, the turn-on time is short and the turn-off time can be kept long and stable, low power consumption driving is possible.

The OLED element includes an anode connected to the driving TFT DT, a cathode connected to the low potential voltage EVSS, and a light emitting layer between the anode and the cathode to emit light proportional to the amount of current supplied from the driving TFT DT Occurs.

The first switching TFT ST1 is driven by the gate signal of one gate line GLa to supply the data voltage from the corresponding data line DL to the gate node of the driving TFT DT and the second switching TFT ST2 Is driven by the gate signal of the other gate line GLb to supply a reference voltage from the reference line RL to the source node of the driver TFT DT. The second switching TFT ST2 is further used as a path for outputting the current from the driving TFT DT to the reference line R in the sensing mode.

The storage capacitor Cst connected between the gate electrode and the source electrode of the driving TFT DT receives the data voltage supplied to the gate electrode of the driving TFT DT through the first switching TFT ST1 and the data voltage supplied to the second switching TFT ST2 to the source electrode of the driving TFT DT and supplies the charged voltage to the driving TFTs (ST1, ST2) during the period in which the first and second switching TFTs ST1, ST2 are turned off DT).

The driving TFT DT controls the current supplied from the high potential power supply EVDD according to the driving voltage supplied from the storage capacitor Cst to supply a current proportional to the driving voltage to the OLED element to emit the OLED element.

The data driver 300 converts image data from a timing controller (not shown) into analog data signals using gamma voltages, and supplies analog data signals to the data lines DL of the display panel 100, respectively.

The gate driver 200 drives the plurality of gate lines of the display panel 100, respectively. The gate driver 200 supplies a gate-on voltage to the respective gate lines in a corresponding scan period, and supplies a gate-off voltage in the remaining periods. The gate driver 200 is formed on the thin film transistor array substrate (backplane substrate) together with the thin film transistors constituting each pixel P of the pixel array AA in the non-display region of the display panel 100, ). The switching TFTs constituting the gate driver 200 incorporated in the display panel 100 may also be an oxide TFT.

FIG. 2 is a cross-sectional view of a pixel circuit according to an embodiment of the present invention, showing a structure of a driving TFT DT and a storage capacitor Cst in the pixel circuit shown in FIG.

The driving TFT DT shown in Fig. 2 includes a shielding metal layer BSM on the substrate SUB under the buffer layer BUF, an active layer ACT stacked on the buffer layer, a gate insulating layer GI, a gate electrode GE, An interlayer insulating layer ILD covering the laminated structure of the active layer ACT, the gate insulating layer GI and the gate electrode GE on the buffer layer BUF and a contact hole H1 A source electrode SE and a drain electrode DE respectively connected to the source region SA and the drain region DA of the active layer ACT via the source electrode SE and the drain electrode H2, SE, and a drain electrode DE.

The storage capacitor Cst overlaps the first storage electrode CE1 on the gate insulating layer GI and the first storage electrode CE1 with the interlayer insulating layer ILD to form the first capacitor C1 A second storage electrode CE2 on the interlayer insulating layer ILD overlaps the first storage electrode CE1 with the gate insulating layer GI and the buffer layer BUF to form a second capacitor C2 And a third storage electrode CE3 on the buffer layer BUF connected to the second storage electrode CE2 through a contact hole H3 penetrating the interlayer insulating layer ILD and the buffer layer BUF. Since the first and second capacitors C1 and C2 are connected in parallel while overlapping each other, the capacitance of the storage capacitor Cst can be increased within a limited pixel circuit area.

The pixel circuit shown in Fig. 2 exemplifies a backplane substrate structure applied to a flexible OLED display device. The pixel circuit shown in Fig. 2 includes a glass substrate SUB, a flexible substrate P1 laminated on the buffer layer BUF, and a multi- MB), and the glass substrate (SUB) is for maintaining rigidity during the manufacturing process, and is removed when the OLED display is completed in a subsequent process.

The flexible substrate P1 is a flexible plastic film which is made of a copolymer including a polyester or a polyester, a copolymer containing a polyimide or a polyimide, an olefin copolymer, a polyacrylic acid ) Or a copolymer comprising polyacrylic acid, a copolymer comprising polystyrene or polystyrene, a copolymer comprising polysulfate or polysulfate, a copolymer comprising polycarbonate or polycarbonate, A copolymer including a polyamic acid or a polyamic acid, a copolymer including a polyamine and a polyamic acid, a polyvinyl alcohol, and a polyallyamine. And may include a polymer compound.

The multi-barrier layer (MB) laminated on the flexible substrate (PI) is for blocking external moisture or gas to be introduced from the outside of the flexible substrate (PI), and is formed by stacking an organic insulating layer and an inorganic insulating layer alternately Or an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx), or the like.

The shielding metal layer BSM on the multi-barrier layer MB is formed of a metal material having a light-shielding function so as to block external light that changes the characteristics of the oxide active layer ACT from entering the active layer ACT, The third storage electrode CE3 is formed of the same material in the same layer together with the shielding metal layer BSM. The shield metal layer BSM may be any of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), titanium (Ti), nickel (Ni), neodymium (Nd), and copper Or a single layer or a multi-layer structure composed of an alloy thereof. The shield metal layer BSM may overlap with at least one of the active layers of the TFTs constituting the pixel circuit.

The buffer layer BUF covering the shield metal layer BSM and the third storage electrode CE3 on the substrate SUB prevents hydrogen from flowing into the oxide active layer ACT from the multi-barrier layer MB. The buffer layer BUF is formed by stacking a single insulating layer or a plurality of insulating layers and is formed of an oxide insulating material such as silicon oxide (SiOx), aluminum oxide (AlOx), or the like to prevent the characteristic change of the active layer (ACT) .

The active layer ACT stacked on the buffer layer BUF has a channel region CH and a low resistance source region SA and a drain region DA which are conductively processed to reduce the offset resistance. The active layer ACT is formed of an oxide semiconductor containing at least one of In, Ga, Zn, Al, Sn, Zr, Hf, Cd, Ni and Cu. The source and drain regions SA and DA of the active layer ACT are exposed to plasma, ultraviolet (UV), or etchant in the subsequent process so that the active layer ACT is partially removed by oxygen to become conductive.

A gate insulating layer GI and a gate electrode GE overlapping the channel region CH are formed in a laminated structure on the active layer ACT and a gate insulating layer GI and a first storage The electrode CE1 is formed in a laminated structure. The gate insulating layer GI may be formed of a single layer or a multilayer structure of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx) and the like. The gate insulating layer GI may be formed of an oxide-based insulating material to prevent a change in characteristics of the active layer ACT using an oxide semiconductor. The gate metal layer used as the gate electrode GE and the first storage electrode CE1 may be at least one selected from the group consisting of Mo, Al, Cr, W, Ti, Ni, (Nd), and copper (Cu), or an alloy thereof. The first storage electrode CE1 overlaps the third storage electrode CE3 with the buffer layer BUF therebetween to form the second capacitor C2.

An interlayer insulating layer ILD covering the active layer ACT, the gate insulating layer GI and the gate electrode GE and the first storage electrode CE1 is formed on the buffer layer BUF, Contact holes H1 and H2 penetrating through the interlayer insulating layer ILD and the buffer layer BUF are formed. The ILD may be formed of a single layer or a multilayer structure or an organic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx), or the like.

A source electrode SE and a drain electrode DE are formed on the interlayer dielectric layer ILD and overlap the first storage electrode CE1 to form a first capacitor C1 and a third storage electrode CE3, The second storage electrode CE2 is formed. The source electrode SE is connected to the source region SA of the active layer ACT via the contact hole H1 and the drain electrode DE is connected to the drain region of the active layer ACT through the contact hole H2 DA. The second storage electrode CE2 is connected to the third storage electrode CE3 through the contact hole H3. The source / drain metal layer used as the source electrode SE and the drain electrode DE and the second storage electrode CE2 may be formed of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W) ), Nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

A passivation layer PAS covering the source electrode SE and the drain electrode DE and the second storage electrode CE2 is formed on the interlayer insulating layer ILD. The ILD may be formed of a single layer or a multilayer structure of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx), or the like.

The storage capacitor Cst according to an embodiment of the present invention includes a first storage electrode CE1 on the gate insulating layer GI, a second storage electrode CE2 on the interlayer insulating layer ILD, a buffer layer BUF, Since the first and second storage capacitors C1 and C2 are overlapped and connected in parallel with each other by overlapping the third storage electrode CE3 on the storage capacitor Cst, . At this time, since the third storage electrode CE2 is formed of the same material as the shielding metal layer BSM in the same layer, a separate manufacturing process is not required, thereby enhancing cost competitiveness.

On the other hand, in the buffer layer BUF, the buffer layer BUF must be relatively thick, for example, a thickness of 600 nm or more in order to suppress the inflow of hydrogen from the multi-barrier layer MB to the oxide active layer ACT. Because of this, the distance between the first storage electrode CE1 and the third storage electrode CE3 must be 700 nm or more due to the thickness of the buffer layer BUF and the gate insulating layer GI, so that the capacity of the storage capacitor Cst There is a limit.

To improve this, a pixel circuit according to another embodiment of the present invention proposes a structure in which a third storage electrode CE3 'is formed on a buffer layer BUF as shown in FIG.

Referring to FIG. 3, the first storage electrode CE1 and the third storage electrode CE3 'are sandwiched between the gate insulating layer GI by placing the third storage electrode CE3' on the buffer layer BUF And overlap each other to form the second capacitor C2 '. Accordingly, the second capacitor C2 'shown in FIG. 3 is electrically connected to the first storage electrode CE1 (FIG. 3) in comparison with the second capacitor C2 in FIG. 2 in which the third storage electrode CE3 is formed on the buffer layer BUF. And the third storage electrode CE3 'is reduced to the thickness of the gate insulating layer GI, thereby maximizing the storage capacity increase.

The third storage electrode CE3 is formed on the buffer layer BUF, which is the same layer as the active layer ACT, but is formed of a metal layer different from the active layer ACT. The method of forming the active layer ACT on the third layer of the third storage electrode CE3 is as follows.

4A, a third storage electrode CE3 is first formed on the buffer layer BUF using a mask process, and a third storage electrode CE3 is formed on the buffer layer BUF as shown in FIG. 4B, (OSL) is deposited on the entire surface. Then, the active layer (ACT) is formed by patterning the oxide semiconductor layer (OSL) by a photolithography process and an etching process using a mask. At this time, both the mixed oxide and the OZ acid can be used in the etching of the oxide semiconductor layer (OSL), but the oxide semiconductor layer (the oxide semiconductor layer) can be used by using OZ acid, which is mainly used as an etchant such as ITO and IGZO, It is possible to prevent the third storage electrode CE3 'from being etched during the etching of the second storage electrode OSL.

5 is a simplified view of the link wires of an OLED display according to an embodiment of the present invention.

Referring to FIG. 5, a data line (not shown) of the display area AA is connected to a data pad PD formed in the pad area via the data links LKa and LKb formed in the non-display area. The data pads DP are portions to be connected to the driving IC.

The data links LKa and LKb include a first data link LKa formed of the same source / drain metal layer on the same layer as the data line and connected to the first data line, And a second data link LKb formed of the same metal layer on the same layer as the data lines CE3 and CE 'and connected to the second data line via the contact portion CT. The first data link LKa and the second data link LKb formed on different layers are alternately arranged in the non-display area, and the first and second data lines alternately arranged in the display area are separately provided Respectively. Accordingly, the interval between the data links (LKa and LKb) can be sufficiently secured in the limited non-display area including the plurality of data links (LKa and LKb), thereby improving the reliability.

FIG. 6 is a cross-sectional view illustrating a link wiring portion according to an embodiment of the present invention, and FIG. 7 is a cross-sectional view illustrating a link wiring portion according to another embodiment of the present invention.

Referring to FIG. 6, the first data link LKa is formed on the interlayer insulating layer ILD, which is the same layer as the data line DL, and the second data link LKb is formed on the third storage Is formed on the multi-barrier layer (MB) in the same layer and the same material as the electrode CE3 and the shield metal layer (BSM). The second data link LKb on the multi-barrier layer MB is connected to the data line DL through the contact hole LH through the buffer layer BUF and the interlayer insulating layer ILD in the contact portion CT . Accordingly, since the interval between the data links (LKa, LKb) can be sufficiently secured in the limited non-display area including the plurality of data links (LKa, LKb), reliability can be improved and a separate mask process is required The cost increase can be prevented.

7, the first data link LKa is formed on the interlayer insulating layer ILD, which is the same layer as the data line DL, and the second data link LKb is formed on the third storage Is formed on the buffer layer BUF in the same layer as the electrode CE3 'and the same material. The second data link LKb on the buffer layer BUF is connected to the data line DL through the contact hole LH through the buffer layer BUF in the contact portion CT. Accordingly, since the interval between the data links (LKa, LKb) can be sufficiently secured in the limited non-display area including the plurality of data links (LKa, LKb), reliability can be improved and a separate mask process is required The cost increase can be prevented.

As described above, an OLED display according to an embodiment of the present invention uses an oxide TFT having a coplanar structure that can reduce power consumption, as a switching element of a pixel circuit, and a first storage electrode on a gate insulating layer The first storage electrode overlaps with the second storage electrode on the interlayer insulating layer and the third storage electrode connected to the second storage electrode overlaps the first storage electrode with the gate insulating layer therebetween or the gate insulating layer and the buffer layer The capacity of the storage capacitor can be improved without increasing the area in the limited pixel circuit area by providing the storage capacitor in a parallel structure of the second capacitor formed by overlapping with each other.

In the OLED display according to the embodiment of the present invention, the first link interconnection in the same layer as the data line and the second interconnection interconnection in the same layer as the third storage electrode are alternately arranged in the non-display region, The interval between the link wirings in the limited non-display area including the wirings can be sufficiently secured and the reliability can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

SUB: substrate PI: flexible substrate
MB: Multi-barrier layer BSM: Shield metal layer
CE1, CE2, CE3, CE3 ': storage electrode ACT: active layer
CH: channel region SA: source region
DA: drain region GI: gate insulating layer
GE: gate electrode SE: source electrode
DE: drain electrode PAS: passivation layer
H1, H2, H3, H3 ', LH: Contact holes

Claims (8)

A plurality of thin film transistors each including an active layer, a gate insulating layer, a gate electrode and an interlayer insulating layer stacked on a buffer layer, a source electrode and a drain electrode which are located on the interlayer insulating layer and are connected to the active layer through contact holes, ,
A shield metal layer which overlaps with at least one of the plurality of thin film transistors under the buffer layer,
A first storage electrode on the gate insulating layer connected to a gate electrode of a driving transistor among the plurality of thin film transistors,
A second storage electrode connected to the source electrode of the driving transistor and overlapping the first storage electrode with the interlayer insulating layer interposed therebetween,
And a third storage electrode connected to the second storage electrode and overlapping the first storage electrode and the gate insulating layer or overlapping the gate insulating layer and the buffer layer, And an organic light emitting diode (OLED) display device. The method according to claim 1,
The third storage electrode
Wherein the shielding metal layer is formed of the same material as the shielding metal layer and is connected to the second storage electrode through a contact hole passing through the buffer layer and the interlayer insulating layer. The method of claim 2,
Further comprising: a display region in which a plurality of pixels including the pixel circuit are located; and a plurality of link wirings connecting the driver circuit,
The plurality of link wirings
A first wiring line located on the interlayer insulating layer like the source electrode and the drain electrode and made of the same material as the source electrode and the drain electrode,
And a second link wiring which is located under the buffer layer in the same manner as the shield metal layer and the third storage electrode and is formed of the same material as the shield metal layer and the third storage electrode,
And the first and second link wirings are alternately arranged in the non-display area. The method of claim 3,
A plurality of data lines arranged on the interlayer insulating layer in the same manner as the source electrode and the drain electrode in the display region and having first and second data lines alternately arranged with the same material as the source electrode and the drain electrode, Respectively,
The second data line is directly connected to the first link wiring,
And the second data line is connected to the second link wiring via a link contact hole passing through the interlayer insulating layer and the buffer layer. The method according to claim 1,
The third storage electrode
Wherein the active layer is formed of a metal layer different from the active layer and is connected to the second storage electrode through a contact hole passing through the interlayer insulating layer. The method of claim 5,
Further comprising: a display region in which a plurality of pixels including the pixel circuit are located; and a plurality of link wirings connecting the driver circuit,
The plurality of link wirings
A first wiring line located on the interlayer insulating layer like the source electrode and the drain electrode and made of the same material as the source electrode and the drain electrode,
And a second link wiring located on the buffer layer in the same manner as the third storage electrode and composed of the same material as the third storage electrode,
And the first and second link wirings are alternately arranged in the non-display area. The method of claim 6,
A plurality of data lines arranged on the interlayer insulating layer in the same manner as the source electrode and the drain electrode in the display region and having first and second data lines alternately arranged with the same material as the source electrode and the drain electrode, Respectively,
The second data line is directly connected to the first link wiring,
And the second data line is connected to the second link wiring through a link contact hole penetrating the interlayer insulating layer. The method according to any one of claims 1 to 7,
Wherein the active layer is composed of an oxide semiconductor layer,
And a multi-barrier layer in which a plurality of insulating layers are stacked under the buffer layer.

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