CN219513106U - Display panel and display device - Google Patents

Abstract

The disclosure relates to the technical field of display, and provides a display panel, a preparation method thereof and a display device. The display panel comprises a substrate base plate, a shading layer, an active layer, a gate metal layer, a flattening layer and a source drain metal layer, wherein the active layer is arranged on one side of the shading layer, which is away from the substrate base plate, and comprises a plurality of active parts which are respectively used for forming a channel region, a first pole and a second pole of a driving transistor; the gate metal layer is positioned on one side of the active layer, which is away from the substrate, and comprises a gate part used for forming a gate of the driving transistor, and the orthographic projection of the gate part on the substrate covers the orthographic projection of the corresponding active part on the substrate; the flattening layer is positioned on one side of the gate metal layer, which is away from the substrate base plate; the source-drain metal layer is positioned on one side of the planarization layer, which is away from the substrate, and comprises a plurality of conductive parts, and the conductive parts are connected with the corresponding active parts through the through holes.

Description

Display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display panel and a display device.

Background

With the development of display technology, the mobility of conventional oxide transistors has not been able to meet the product requirements, and in the related art, an effective device structure is lacking to enhance the mobility of oxide transistors.

Disclosure of Invention

The present disclosure is directed to overcoming the drawbacks of the prior art and providing a display panel and a display device.

According to an aspect of the present disclosure, there is provided a display panel including a pixel driving circuit including a driving transistor in a display region, the display panel further including: a substrate base; a light shielding layer located on one side of the substrate base plate, the light shielding layer including a light shielding portion; an active layer located at a side of the light shielding layer facing away from the substrate base plate, the active layer including a plurality of active portions for forming a channel region, a first pole, and a second pole of the driving transistor, respectively; the gate metal layer is positioned on one side of the active layer, which is away from the substrate, and comprises a gate part used for forming the gate of the driving transistor, and the orthographic projection of the gate part on the substrate covers the orthographic projection of the corresponding active part on the substrate; the flattening layer is positioned on one side of the gate metal layer, which is away from the substrate base plate; the source-drain metal layer is positioned on one side of the planarization layer, which is away from the substrate, and comprises a plurality of conductive parts, and the conductive parts are connected with the corresponding active parts through the through holes.

In an exemplary embodiment of the present disclosure, the planarization layer has a thickness of 1.5 microns or more.

In an exemplary embodiment of the present disclosure, the planarization layer is an organic material layer.

In an exemplary embodiment of the present disclosure, the display panel includes a wiring region located in a non-display region of the display panel; the light shielding layer, the gate metal layer and the source drain metal layer comprise a plurality of signal lines, and each signal line is positioned in the wiring area; the wiring period of each signal wire in the source-drain metal layer is correspondingly the same as the wiring period of each signal wire in the gate metal layer and the shading layer.

In an exemplary embodiment of the present disclosure, the plurality of active portions includes a first active portion for forming a first pole of the driving transistor, a second active portion for forming a channel region of the driving transistor, and a third active portion for forming a second pole of the driving transistor, which are sequentially connected; the plurality of conductive parts comprise a first conductive part and a second conductive part, the first conductive part is connected with the first active part through a via hole, the second conductive part is connected with the third active part through a via hole, the first conductive part is used for forming a first pole of the driving transistor, and the second conductive part is used for forming a second pole of the driving transistor; the orthographic projection of the grid part on the substrate base plate covers the orthographic projection of the second active part on the substrate base plate; the orthographic projection of the light shielding part on the substrate base plate at least covers the orthographic projection of the second active part on the substrate base plate.

In an exemplary embodiment of the present disclosure, the display panel further includes a storage capacitor, a first electrode of the storage capacitor and a first electrode of the driving transistor are both connected to a pixel electrode; the display panel further includes: the first electrode layer is arranged on the same layer as the source-drain metal layer, and comprises: and a first electrode structure electrically connected to the first conductive portion, the first electrode structure being for forming the pixel electrode and a first pole of the storage capacitor.

In an exemplary embodiment of the present disclosure, a second pole of the storage capacitor is connected to a common electrode; the display panel further includes: the second electrode layer is positioned on one side of the source-drain metal layer, which is away from the substrate base plate, and comprises: and the second electrode structure is used for forming a common electrode and a second pole of the storage capacitor, and the orthographic projection of the second electrode structure on the substrate is overlapped with the orthographic projection part of the first electrode structure on the substrate.

In an exemplary embodiment of the present disclosure, the common electrode is connected to a contact electrode line; the source-drain metal layer further comprises the touch electrode wire; the display panel further includes: a second passivation layer located between the planarization layer and the second electrode layer and covering the source drain metal layer and the first electrode layer; the second electrode structure is connected with the touch electrode wire through a via hole.

In an exemplary embodiment of the present disclosure, the display panel further includes: a buffer layer located between the active layer and the light shielding layer and covering the light shielding layer; a gate insulating layer between the channel region and the gate portion; and a first passivation layer between the buffer layer and the planarization layer and covering the gate portion, the first active portion, and the third active portion.

According to a second aspect of the present disclosure, there is also provided a method for manufacturing a display panel according to any embodiment of the present disclosure, the method including: providing a substrate; forming a light shielding layer on one side of the substrate base plate, wherein the light shielding layer comprises a light shielding part; forming an active layer on a side of the light shielding layer facing away from the substrate base plate, wherein the active layer comprises a plurality of active parts respectively used for forming a channel region, a first pole and a second pole of the driving transistor; forming a gate metal layer on one side of the active layer, which is away from the substrate, wherein the gate metal layer comprises a gate part, and the orthographic projection of the gate part on the substrate covers orthographic projection of the active part on the substrate, and the gate part is used for forming a gate of the driving transistor; forming a planarization layer on one side of the gate metal layer away from the substrate base plate; and forming a source-drain metal layer on one side of the planarization layer, which is away from the substrate, wherein the source-drain metal layer comprises a plurality of conductive parts, and the conductive parts are connected with the active parts at corresponding positions through the through holes.

In an exemplary embodiment of the present disclosure, the method further comprises: forming a buffer layer on the substrate by using a deposition process, wherein the buffer layer covers the light shielding layer; forming a first passivation layer on the buffer layer by using a deposition process, wherein the first passivation layer covers the gate metal layer; depositing a planarization layer on the first passivation layer; forming a via hole in the planarization layer and the first passivation layer by using the planarization layer as a mask and using an etching process; and depositing a metal material in the via hole and on the flat layer to form the source-drain metal layer.

In an exemplary embodiment of the present disclosure, the plurality of conductive parts includes a first conductive part, and the source drain metal layer includes a touch electrode line; the method further comprises the steps of: depositing a first electrode structure on one side of the planarization layer, which is positioned on the first conductive part, wherein the first electrode structure is electrically connected with the first conductive part and is used for forming a pixel electrode and a first pole of a storage capacitor; depositing a second passivation layer on one side of the planarization layer away from the substrate base plate, wherein the second passivation layer covers the gate metal layer and the first electrode layer; and depositing and forming a second electrode layer on the second passivation layer, wherein the second electrode layer comprises a second electrode structure for forming the common electrode, and the second electrode structure is connected with the touch electrode line through a via hole.

According to a third aspect of the present disclosure, there is also provided a display device including the display panel according to any embodiment of the present disclosure.

The display panel provided by the disclosure has the planarization layer between the gate metal layer and the source drain metal layer, namely the gate metal layer and the source drain metal layer are positioned on two sides of the planarization layer, so that the separation distance between the source drain metal layer and the gate metal layer can be increased by utilizing the planarization layer, namely the separation distance between the source drain metal layer and the shading layer is increased, therefore, when the shading part is electrically connected with the gate metal layer to improve the mobility of the transistor, the capacitance formed between the source drain metal layer and the shading layer is greatly reduced, and the load of a data signal line can be effectively controlled and the overall low power consumption of the display panel can be controlled while the mobility of the transistor is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a schematic circuit configuration diagram of a pixel driving circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic structural view of a display panel according to an embodiment of the present disclosure;

fig. 3 is a sectional view taken along the direction CC in fig. 2;

FIG. 4 is a schematic structural view of a first electrode structure according to one embodiment of the present disclosure;

FIG. 5 is a schematic structural view of a second electrode structure according to one embodiment of the present disclosure;

fig. 6 to 12 are flowcharts of the preparation of a display panel according to an embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.

Fig. 1 is a schematic circuit configuration diagram of a pixel driving circuit according to an embodiment of the present disclosure. The pixel driving circuit may include a driving transistor T and a storage capacitor Cst, wherein a Gate electrode of the driving transistor T is connected to a Gate driving signal terminal Gate, a first electrode is connected to a data signal terminal Vdata, and a second electrode is connected to a pixel electrode Vpixel. The storage capacitor Cst has a first electrode connected to the pixel electrode Vpixel and a second electrode connected to the common electrode Vcom.

Fig. 2 is a schematic structural view of a display panel according to an embodiment of the present disclosure, and fig. 3 is a cross-sectional view along CC in fig. 2, and as shown in fig. 2 and 3, the display panel may include a display area AA and a non-display area surrounding the display area AA, and the display area AA may include a pixel driving circuit, and the pixel driving circuit may be shown in fig. 1. The display panel may further include a substrate BP, a light shielding layer LS including a light shielding portion LS1, an active layer ACT, a gate metal layer GAT, a planarization layer PLN, and a source drain metal layer SD; the active layer ACT is located at one side of the light shielding layer LS away from the substrate BP, and includes a plurality of active portions for forming a channel region, a first pole and a second pole of the driving transistor T, respectively; the gate metal layer GAT is located on one side of the active layer ACT, which faces away from the substrate BP, and the gate metal layer GAT comprises a gate portion GAT1 for forming a gate of the driving transistor T, and the orthographic projection of the gate portion GAT1 on the substrate BP covers the orthographic projection of the corresponding active portion on the substrate BP; the flattening layer PLN is positioned on one side of the gate metal layer GAT, which faces away from the substrate base plate BP; the source-drain metal layer SD is located at a side of the planarization layer PLN facing away from the substrate BP, and the source-drain metal layer SD includes a plurality of conductive portions, where the conductive portions are connected to the corresponding active portions through vias.

The display panel provided by the disclosure has the planarization layer PLN between the gate metal layer GAT and the source drain metal layer SD, that is, the gate metal layer GAT and the source drain metal layer SD are located at two sides of the planarization layer PLN, so that the separation distance between the source drain metal layer SD and the gate metal layer GAT, that is, the separation distance between the source drain metal layer SD and the light shielding layer LS can be increased by using the planarization layer PLN, therefore, when the light shielding part LS1 is electrically connected with the gate metal layer GAT to improve the mobility of the transistor, the capacitance formed between the source drain metal layer SD and the light shielding layer LS is greatly reduced, thereby realizing the improvement of the mobility of the transistor, and simultaneously, effectively controlling the load of the Data signal line Data and the overall low power consumption of the display panel.

The material of the active layer ACT of the present disclosure may be a high mobility material such as a metal oxide, for example IGZO, IGTO, ITZO, and accordingly, the driving transistor T formed by the present disclosure is an N-type metal oxide thin film transistor, and the N-type oxide transistor has a smaller leakage current.

The planarization layer PLN is located between the source and drain metal layers SD and GAT, in other words, the source and drain metal layers SD and GAT are located at both sides of the planarization layer PLN, whereby the distance between the gate metal layer GAT and the source and drain metal layer SD can be increased by the planarization layer PLN, and accordingly, the distance between the light shielding layer LS and the source and drain metal layer SD can be made larger, whereby after the light shielding portion LS1 and the gate portion GAT1 are connected, the capacitance between the metal structure in the light shielding layer LS and the metal structure in the source and drain metal layer SD is small, so that not only the overall power consumption of the panel can be reduced, but also the RC load of the Data signal line Data in the source and drain metal layer SD can be reduced.

The thickness of the planarizing layer PLN of the present disclosure may be 1.5 μm or more, for example, may be 1.5 μm,1.6 μm,1.8 μm,2.0 μm,2.5 μm, or the like. The thickness of the planarization layer PLN may be greater than that of other insulating layers, so that the thickness of the planarization layer PLN is used to increase the distance between the source drain metal layer SD and the light shielding layer LS, thereby sufficiently reducing the capacitance between the source drain metal layer SD and the light shielding layer LS.

The planarization layer PLN may be an organic insulating layer formed of an organic material or an inorganic insulating layer formed of an inorganic material, and the organic material may include polymethyl methacrylate (PMMA), polystyrene (PS), a phenol-based polymer derivative, an acryl-based polymer, an imide-based polymer, an arylene-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylyl polymer, a vinyl alcohol-based polymer, or any combination thereof. The inorganic material may include SiO2, siNx, siON, al2O3, and the like. Further, the planarization layer PLN of the present disclosure may be preferably an organic insulating layer, and the stress of the planarization layer PLN may be limited while increasing the thickness of the planarization layer PLN to avoid overstressing the planarization layer PLN with increasing thickness.

The plurality of active portions in the active layer ACT may include a conductive portion subjected to a conductive process for forming a channel region of the driving transistor T and a semiconductor portion not subjected to a conductive process for connecting source and drain electrodes of the driving transistor T.

The light shielding layer LS is disposed on the substrate BP, and the light shielding layer LS can prevent stray light from adversely affecting the semiconductor layer. The front projection of the light shielding layer LS on the substrate BP covers the front projection of the corresponding active portion on the substrate BP, specifically, the light shielding portion LS1 is disposed corresponding to the active portion forming the channel region of the driving transistor T, so that the channel region can be shielded by the light shielding portion LS1, thereby improving the light stability of the oxide transistor and further improving the display effect of the panel. The material of the light shielding layer LS is metal, and in some embodiments, the light shielding layer LS may have a double-layer metal structure to reduce resistance and also improve resistance characteristics and electromagnetic compatibility characteristics. Of course, the light shielding layer LS may also be a single-layer metal structure, a three-layer metal structure or other suitable multi-layer metal structure, which may be determined according to practical requirements, and the embodiments of the present disclosure are not limited thereto.

The present disclosure may connect the light shielding portion LS1 with the gate portion GAT1, so that the light shielding portion LS1 forms a bottom gate structure of the driving transistor T, so that the driving transistor T has a double gate structure, thereby improving carrier mobility of the driving transistor T, so that mobility of the oxide transistor meets product requirements.

It should be understood that the orthographic projection of a certain structure a on the substrate BP and another structure B on the substrate BP described in the present disclosure may be understood that the outline of the projection of B on the plane of the substrate BP is completely located inside the outline of the projection of a on the same plane.

As shown in fig. 3, the display panel of the present disclosure may include a transfer region TF and a wiring region DP in a non-display region, and each film layer of a light shielding layer LS, a gate metal layer GAT, a source drain metal layer SD, and the like may extend from the display region AA to the wiring region DP, where the transfer region TF may perform signal transfer, for example, in the transfer region TF, the light shielding layer LS may include a first transfer portion TF1 connected to the light shielding portion LS1, the gate metal layer GAT may include a second transfer portion TF2 connected to the gate portion GAT1, the source drain metal layer SD may include a third transfer portion TF3, and the third transfer portion TF3 may be connected to the first transfer portion TF1 and the second transfer portion TF2 through a via hole, so that the light shielding layer LS may be connected to the gate portion GAT1 through each transfer portion of the transfer region TF. Of course, the transfer area TF can also be used for transfer of other signals, which are not spread out one by one.

The wiring region DP may be laid with the signal lines DL bound with the pins of the chip, so that three-layer wiring may be performed in the wiring region DP using the three conductive layers of the light shielding layer LS, the gate metal layer GAT, and the source drain metal layer SD, thereby reducing the frame size of the wiring region DP by using the space of the panel in the thickness direction.

As shown in fig. 3, in the present exemplary embodiment, the wiring period of each signal line DL in the source-drain metal layer SD corresponds to the same wiring period as each signal line DL in the gate metal layer GAT and the light shielding layer LS. The wiring period may be understood as the sum of the line width of the signal line DL and the wiring pitch between the signal line DL and the adjacent signal line DL, in other words, in the present exemplary embodiment, the line width of the signal line DL of the wiring region DP in the source-drain metal layer SD is the same as the line width of the corresponding signal line DL in the light shielding layer LS and the gate metal layer GAT, and the wiring pitch of the adjacent signal line DL in the source-drain metal layer SD is the same as the wiring pitch of the corresponding signal line DL in the light shielding layer LS and the gate metal layer GAT. In the present exemplary embodiment, the corresponding signal lines DL located at different conductive layers may be understood as signal lines DL located at different conductive layers and transmitting the same kind of signals.

As shown in fig. 3, the planarization layer PLN extends from the display area AA to the wiring area DP, and the planarization layer PLN may planarize the signal lines DL of the gate metal layer GAT and the light shielding layer LS, so that the signal lines DL of the wiring area DP in the source/drain metal layer SD are not affected by the shapes of the respective wirings in the light shielding layer LS and the gate metal layer GAT, and thus, in this exemplary embodiment, the light shielding layer LS, the gate metal layer GAT, and the source/drain metal layer SD may all use a limited wiring period, that is, perform wiring with the lowest line width and the smallest wiring pitch, that is, perform limited wiring on the wiring area DP, to achieve the minimization of the widening size of the wiring area DP.

As shown in fig. 3, in an exemplary embodiment, the plurality of active portions of the active layer ACT may include a first active portion ACT1, a second active portion ACT2, and a third active portion ACT3 connected in sequence, the second active portion ACT2 being for forming a channel region of the driving transistor T, and the first active portion ACT1 and the third active portion ACT3 may be subjected to a conductive process and connect the first conductive portion SD1 and the second conductive portion SD2 of the source-drain metal layer SD.

As shown in fig. 3, the orthographic projection of the gate portion GAT1 on the substrate BP covers the orthographic projection of the second active portion ACT2 on the substrate BP. The gate portion GAT1 in the gate metal layer GAT may be used to form a gate of the driving transistor T. The gate metal layer GAT may be made of one or an alloy of molybdenum, aluminum, copper, titanium, and niobium, or a molybdenum/titanium alloy or a stack. In this exemplary embodiment, the active layer ACT may be subjected to a conductive process using the gate metal layer GAT as a mask, the active layer ACT covered by the gate metal layer GAT forms a channel region of the transistor, and a region not covered by the gate metal layer GAT forms a conductive structure, specifically, the active layer ACT covered by the gate portion GAT1, that is, the second active portion ACT2, may form a channel region of the driving transistor T using the gate portion GAT1 as a mask, and the active layer ACT not covered by the gate portion GAT1 reduces resistance to form the first active portion ACT1 and the second active portion ACT2, so that self alignment of the active layer ACT channel and the gate portion GAT1 of the gate metal layer GAT may be achieved.

In the present exemplary embodiment, the conductive treatment of the active layer ACT includes, but is not limited to, high-power plasma such as Ar, he, H bombardment, ion implantation, and the like, to reduce the resistance of the first active portion ACT1 and the second active portion ACT2, which are not covered by the gate portion GAT1, to a conductive level.

As shown in fig. 3, in an exemplary embodiment, the display panel may further include a gate insulating layer GI between the gate metal layer GAT and the active layer ACT to insulate the gate portion GAT1 and the active layer ACT. The gate insulating layer GI may be formed using an inorganic material such as SiNx or SiO2, al2O3, or the like. The thickness of the gate insulating layer GI may beFor example, it may be +.>Etc. In the present exemplary embodiment, the gate insulating layer GI may be deposited entirely on the active layer ACT, then patterned with the gate metal layer GAT as a mask, and the gate electrode portion GAT1 and the gate electrode portion are formed in the display area AAAnd forming an insulating part between the gate metal layer GAT corresponding structure and the Buffer layer Buffer in the non-display region.

As shown in fig. 3, in an exemplary embodiment, the display panel may further include a Buffer layer Buffer that may reduce penetration of impurities into the driving circuit layer through the substrate BP. The Buffer layer Buffer may entirely cover the substrate BP and cover the light shielding layer LS to form a flat surface. Accordingly, the Buffer layer Buffer may include a material capable of forming a flat surface. For example, the Buffer layer Buffer may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, titanium oxide, or titanium nitride. Of course the Buffer layer Buffer may also comprise organic materials, such as polyimide, polyester or acrylic. The Buffer layer Buffer may have a single-layer structure or a multi-layer structure, and when the Buffer layer Buffer has a multi-layer structure, the multi-layer structure may be selected from any of the above inorganic materials or combinations of organic materials.

As shown in fig. 3, in an exemplary embodiment, the display panel may further include a first passivation layer PVX1, the first passivation layer PVX1 being formed on the Buffer layer Buffer and covering the active layer ACT and the gate metal layer GAT.

The first passivation layer PVX1 is located between the planarization layer PLN and the Buffer layer Buffer, and since the first passivation layer PVX1 needs to be formed with a via hole to expose the first active portion ACT1 and the second active portion ACT2 in the active layer ACT, in this exemplary embodiment, the planarization layer PLN is used as a mask to perform via hole etching on the first passivation layer PVX1, so a mask process can be saved as a whole. Of course, in other embodiments, the mask may be used to perform via etching on the first passivation layer PVX1, so that the optical performance of the display panel is prevented from being affected by the damage of the planarization layer PLN, which falls within the protection scope of the present disclosure.

As shown in fig. 3, in an exemplary embodiment, the first conductive part SD1 in the source-drain metal layer SD may be used to form a first pole of the driving transistor T, the second conductive part SD2 may be used to form a second pole of the driving transistor T, the first conductive part SD1 may be connected to the first active part ACT1 corresponding thereto through a via hole to connect the first pole of the driving transistor T to the channel region, and the second conductive part SD2 may be connected to the third active part ACT3 corresponding thereto through a via hole to connect the second pole of the driving transistor T to the channel region.

The source-drain metal layer SD may further include a Data signal line Data and a touch electrode line Tx, and the touch electrode line Tx may be the same as the extension direction of the Data signal line Data. The Data signal line Data is connected to the first conductive portion SD1 to connect to the first pole of the driving transistor T.

The touch electrode line Tx may be connected with the second electrode structure Com in the second electrode layer ITO2 to connect the common electrode Vcom.

As shown in fig. 3, in an exemplary embodiment, the display panel may further include a first electrode layer ITO1, the first electrode layer ITO1 being disposed in the same layer as the source and drain metal layer SD, the first electrode layer ITO1 may include a first electrode structure Pix electrically connected to the second conductive part SD2, and the first electrode structure Pix may be used to form the pixel electrode Vpixel and the first electrode of the storage capacitor Cst. In this exemplary embodiment, the first electrode layer ITO1 and the source drain metal layer SD are disposed on the same layer, so that the first electrode structure Pix can be directly electrically connected with the second conductive portion SD2 on the same layer through a manner such as overlapping, compared with a structure in which the first electrode layer ITO1 and the source drain metal layer SD are located on different conductive layers and a via hole is required to connect the first electrode structure Pix and the second conductive portion SD2, in this exemplary embodiment, the first electrode structure Pix and the second conductive portion SD2 can be directly overlapped without a via hole connection, and it can be known that forming the via hole needs to occupy a certain panel space, so that this exemplary embodiment can save the space for forming these via holes, and the saved space can be used to increase the effective display area of the display area AA, thereby improving the aperture ratio of the display panel.

In the present exemplary embodiment, the first electrode is made of a transparent conductive material, which may be made of ITO (indium tin oxide) material, but is not limited thereto, and may be made of a transparent material such as IZO (indium zinc oxide), znO (zinc oxide), or the like.

In this exemplary embodiment, the first electrode structure Pix may be an electrode block, and fig. 4 is an exemplary structural diagram of the first electrode structure according to one embodiment of the present disclosure, and as shown in fig. 4, the first electrode structure Pix may include a first electrode portion Pix1 and a second electrode portion Pix2, an extending direction of the first electrode portion Pix1 intersects an extending direction of the second electrode portion Pix2, and the first electrode portion Pix1 and the second electrode portion Pix2 intersect at a first bending portion Pix3. As shown in fig. 4, the first electrode portion Pix1 and the second electrode portion Pix2 may each extend at an angle away from the column direction Y so as to be connected at the first bent portion Pix3. In the present exemplary embodiment, the extending direction of the first electrode portion Pix1 and the column direction Y may have a first angle α, the extending direction of the second electrode portion Pix2 and the column direction Y may have a second angle β, the first angle α may be the same as the second angle β, and the extending length of the first electrode portion Pix1 may be the same as the extending length of the second electrode portion Pix2, whereby the first electrode portion Pix1 and the second electrode portion Pix2 intersect at a bending portion Pix3 at an intermediate position of the first electrode structure Pix along the column direction Y. It should be noted that the extension length of the first electrode portion Pix1 is the same as the extension length of the second electrode portion Pix2 in the present exemplary embodiment, which may be that the extension length of the first electrode portion Pix1 is identical to the extension length of the second electrode portion Pix2, or may be that the extension length of the first electrode portion Pix1 is very close to the extension length of the second electrode portion Pix2, for example, the ratio of the extension length of the first electrode portion Pix1 to the extension length of the second electrode portion Pix2 is between 0.8 and 1.2, or, for example, the absolute value of the difference between the extension lengths of the first electrode portion Pix1 and the second electrode portion Pix2 is within a set redundancy range, which may be considered as the extension length of the first electrode portion Pix1 is identical to the extension length of the second electrode portion Pix 2. Of course, in other embodiments, the first electrode structure Pix may also be other structures, for example, may be slit electrodes or the like.

As shown in fig. 3, in an exemplary embodiment, the display panel may further include a second passivation layer PVX2, the second passivation layer PVX2 being formed on the planarization layer PLN, the second passivation layer PVX2 having a via hole therein exposing a portion of the touch electrode line Tx to connect the common electrode Vcom located at the second electrode layer ITO2 therethrough.

As shown in fig. 3, in an exemplary embodiment, the display panel may further include a second electrode layer ITO2, the second electrode layer ITO2 being located at a side of the second passivation layer PVX2 facing away from the substrate BP, the second electrode layer ITO2 may include a second electrode structure Com, which may be used to form the common electrode Vcom and a second pole of the storage capacitor Cst. The orthographic projection of the second electrode structure Com on the substrate BP overlaps the orthographic projection of the first electrode structure Pix on the substrate BP to form the storage capacitor Cst. Since the first electrode structure Pix may form the first pole of the storage capacitor Cst and the second electrode structure Com may form the second pole of the storage capacitor Cst, the overlapping area of the orthographic projection of the first electrode structure Pix and the second electrode structure Com on the substrate BP determines the size of the storage capacitor Cst, and thus, the storage capacitor Cst may be adjusted by adjusting the overlapping area of the first electrode structure Pix and the second electrode structure Com.

As shown in fig. 3, in the present exemplary embodiment, only one second passivation layer PVX2 is disposed between the second electrode layer ITO2 and the source/drain metal layer SD, and the second electrode structure Com in the second electrode layer ITO2 may be directly connected to the touch electrode line Tx in the source/drain metal layer SD through the via hole, without performing transfer through other conductive layers, and obviously, compared with a structure in which via hole transfer is performed through other conductive layers, the area of the via hole formed on only one insulating layer is relatively smaller, in other words, the present exemplary embodiment reduces the area of the via hole required for connecting the common electrode Vcom to the touch electrode line Tx, so that panel space can be saved, and the saved space can be used to increase the effective display area of the display area AA, thereby further improving the aperture ratio of the panel. The second electrode layer ITO2 in the present exemplary embodiment is made of a transparent conductive material, which may include, for example, ITO (indium tin oxide), indium Zinc Oxide (IZO), zinc oxide (ZnO), or the like.

Fig. 5 is a schematic structural view of a second electrode structure according to an embodiment of the present disclosure, and in the present exemplary embodiment, the second electrode structure Com may include slit electrodes, specifically, the slit electrodes may include slit portions Com1 and stripe electrode portions Com2 located between adjacent slit portions Com1, the stripe electrode portions Com2 may include a plurality of first stripe portions Com21 and a plurality of second stripe portions Com22, an extending direction of the first stripe portions Com21 intersects an extending direction of the second stripe portions Com22, and the first stripe portions Com21 and the second stripe portions Com22 are connected at second bending portions Com 4. Similar to the first bent portion Pix3 in the first electrode structure Pix, the second bent portion Com4 may be located at an intermediate position of the second electrode structure Com in the column direction Y, and orthographic projections of the second bent portion Com4 and the first bent portion Pix3 in the first electrode structure Pix may coincide with each other in the substrate BP. Of course, in other embodiments, the second electrode structure Com may also be other structures, such as an electrode block or the like.

The disclosure further provides a method for preparing a display panel, which is used for preparing the display panel according to any of the above embodiments of the disclosure, and the method may include the following steps:

s110, as shown in fig. 6, a substrate base plate BP is provided.

S120, as shown in fig. 6, forming a light shielding layer LS on one side of the substrate BP by a deposition process, wherein the light shielding layer LS includes a light shielding portion LS1;

a metal material may be deposited on the substrate BP to form an entire light shielding layer LS, and then the light shielding layer LS may be patterned to form a light shielding portion LS1, a transfer portion TF1 located in the transfer region TF, and each signal line DL located in the wiring region DP. The wiring period of each signal line DL of the wiring region DP of the present disclosure is wired with a limit wiring period, and the description of the wiring period is referred to the above embodiment, and will not be described in detail here.

In some embodiments, after the light shielding layer LS is formed, a Buffer layer Buffer may be further deposited on the substrate BP, where a material of the Buffer layer Buffer may include a material such as SiO, siO/SiN composite film, al2O3, and the like. The Buffer layer Buffer covers the light shielding layer LS.

S130, as shown in fig. 7, an active layer ACT is formed on a side of the light shielding layer LS facing away from the substrate BP, where the active layer ACT includes a plurality of active portions for forming a channel region, a first pole, and a second pole of the driving transistor T, respectively.

As described above, the Buffer layer Buffer may be formed on the substrate BP, and thus, this step may be further optimized to form the active layer ACT on the Buffer layer Buffer.

S140, as shown in fig. 7, forming a gate metal layer GAT on a side of the active layer ACT facing away from the substrate BP, where the gate metal layer GAT includes a gate portion GAT1 for forming a gate of the driving transistor T, and a front projection of the gate portion GAT1 on the substrate BP covers a front projection of the corresponding active portion on the substrate BP;

in an exemplary embodiment, a gate insulating layer GI may be formed on the active layer ACT by deposition, and the material of the gate insulating layer GI may include SiO, al2O3, and the like, before step S140. The thickness of the gate insulating layer GI may beFor example, it may be +.> Etc.

Accordingly, in step S140, a metal material is deposited on the gate insulating layer GI to form a gate metal layer GAT, and patterning is performed to form a top gate control electrode.

Further, the wiring period of the wiring region DP in the gate metal layer GAT is the same as the wiring period of the light shielding layer LS, and the wiring is performed with the limit wiring period.

As shown in fig. 8, in an exemplary embodiment, the gate metal layer GAT may be used as a mask to etch the gate insulating layer GI, and the exposed active layer ACT may be subjected to a conductive treatment, including but not limited to high-power plasma such as Ar, he, H bombardment, ion implantation, and the like, to reduce the resistance of the exposed position to a conductive level, that is, to form the conductive first active portion ACT1 and the third active portion ACT3 at both sides of the channel region.

As shown in fig. 9, a planarization layer PLN is formed on a side of the gate metal layer GAT facing away from the substrate BP.

In some embodiments, as shown in fig. 9, before forming the planarization layer PLN, a first passivation layer PVX1 may be deposited on the Buffer layer Buffer, where the first passivation layer PVX1 covers the gate metal layer GAT and the active layer ACT. Then, a planarization layer PLN is formed on the first passivation layer PVX 1.

In the present exemplary embodiment, the planarization layer PLN may be formed of an organic material so that the thickness of the planarization layer PLN satisfies the requirement while also limiting the stress thereof so that the planarization layer PLN has a stress buffering effect. For the material, structure and principle of action of the planarizing layer PLN, reference is made to the description of the above embodiments, and will not be described in detail here.

It should be noted that, in the present exemplary embodiment, the planarization layer PLN may be used as a mask to perform via etching on the first passivation layer PVX1, so that one masking procedure may be saved. Of course, in other embodiments, the Buffer layer Buffer and the first passivation layer PVX1 may be etched by using a mask, so that the structural integrity of the planarization layer PLN may be protected, and the influence on the display effect may be reduced.

As shown in fig. 10, a source-drain metal layer SD is deposited on a side of the planarization layer PLN facing away from the substrate BP, where the source-drain metal layer SD includes a plurality of conductive portions, and the conductive portions are connected to the corresponding active portions through vias.

A metal material is deposited on the planarization layer PLN to form a source-drain metal layer SD, and patterned to form a source-drain electrode of the driving transistor T, a Data signal line Data, a touch electrode line Tx, a transfer portion located in the transfer region TF, a signal line DL located in the wiring region DP, and the like.

Note that, since the source-drain metal layer SD is formed on the planarization layer PLN, the signal line DL of the source-drain metal layer SD in the wiring region DP is not affected by the topography of the underlying structure, and thus the present exemplary embodiment can route the signal line DL in the source-drain metal layer SD at the limit wiring period.

In the exemplary embodiment, as shown in fig. 11, after the corresponding structure of the source-drain metal layer SD is formed, the first electrode layer ITO1 may be formed on the planarization layer PLN by a deposition process, and the first electrode layer ITO1 may be patterned to form the first electrode structure Pix, so that the first electrode layer ITO1 and the source-drain metal layer SD are arranged in the same layer, so that the first electrode structure Pix may be directly connected to the first conductive portion SD1 of the source-drain metal layer SD, which forms the first electrode of the driving transistor T, compared with the scheme that the first electrode layer ITO1 and the source-drain metal layer SD are located in different conductive layers and need to be connected through vias, the present exemplary embodiment saves the via area, thereby increasing the effective display panel of the display panel, that is, improving the aperture ratio of the display panel.

In an exemplary embodiment, as shown in fig. 12, after the first electrode layer ITO1 is formed, a second passivation layer PVX2 may be further deposited on the planarization layer PLN, the second passivation layer PVX2 covers the source drain metal layer SD and the first electrode layer ITO1, an opening is formed on the second passivation layer PVX2 through an etching process, and then a second electrode layer ITO2 is deposited on the second passivation layer PVX2 and patterned to form a second electrode structure Com, where the second electrode structure Com may be connected to the touch electrode line Tx of the source drain metal layer SD through a via hole of the second passivation layer PVX 2. In the present exemplary embodiment, since only one insulating layer is spaced between the second electrode layer ITO2 and the source drain metal layer SD, compared with the scheme in which the second electrode layer ITO2 and the source drain metal layer SD are spaced by multiple insulating layers, the via hole area required in the present exemplary embodiment is smaller, so that the effective display area of the display panel can be further increased, that is, the aperture ratio of the display panel can be further improved.

After the second electrode layer ITO2 is formed, the second electrode layer ITO2 may be patterned such that the second electrode structure Com has a slit portion, i.e., the second electrode structure Com is a slit electrode.

The disclosure also provides a display device, including the display panel according to any of the above embodiments of the disclosure.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This utility model is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (10)

1. A display panel comprising a pixel drive circuit in a display region, the pixel drive circuit comprising a drive transistor, the display panel further comprising:

a substrate base;

a light shielding layer located on one side of the substrate base plate, the light shielding layer including a light shielding portion;

an active layer located at a side of the light shielding layer facing away from the substrate base plate, the active layer including a plurality of active portions for forming a channel region, a first pole, and a second pole of the driving transistor, respectively;

the gate metal layer is positioned on one side of the active layer, which is away from the substrate, and comprises a gate part used for forming the gate of the driving transistor, and the orthographic projection of the gate part on the substrate covers the orthographic projection of the corresponding active part on the substrate;

the flattening layer is positioned on one side of the gate metal layer, which is away from the substrate base plate;

the source-drain metal layer is positioned on one side of the planarization layer, which is away from the substrate, and comprises a plurality of conductive parts, and the conductive parts are connected with the corresponding active parts through the through holes.

2. The display panel according to claim 1, wherein a thickness of the planarizing layer is 1.5 μm or more.

3. The display panel of claim 2, wherein the planarization layer is an organic material layer.

4. The display panel of claim 1, wherein the display panel comprises a routing area, the routing area being located in a non-display area of the display panel;

the light shielding layer, the gate metal layer and the source drain metal layer comprise a plurality of signal lines, and each signal line is positioned in the wiring area;

the wiring period of each signal wire in the source-drain metal layer is correspondingly the same as the wiring period of each signal wire in the gate metal layer and the shading layer.

5. The display panel according to claim 1, wherein the plurality of active portions includes a first active portion for forming a first pole of the driving transistor, a second active portion for forming a channel region of the driving transistor, and a third active portion for forming a second pole of the driving transistor, which are sequentially connected;

the plurality of conductive parts comprise a first conductive part and a second conductive part, the first conductive part is connected with the first active part through a via hole, the second conductive part is connected with the third active part through a via hole, the first conductive part is used for forming a first pole of the driving transistor, and the second conductive part is used for forming a second pole of the driving transistor;

the orthographic projection of the grid part on the substrate base plate covers the orthographic projection of the second active part on the substrate base plate;

the orthographic projection of the light shielding part on the substrate base plate at least covers the orthographic projection of the second active part on the substrate base plate.

6. The display panel according to claim 5, further comprising a storage capacitor, wherein a first electrode of the storage capacitor and a first electrode of the driving transistor are connected to a pixel electrode; the display panel further includes:

the first electrode layer is arranged on the same layer as the source-drain metal layer, and comprises:

and a first electrode structure electrically connected to the first conductive portion, the first electrode structure being for forming the pixel electrode and a first pole of the storage capacitor.

7. The display panel of claim 6, wherein a second pole of the storage capacitor is connected to a common electrode; the display panel further includes:

the second electrode layer is positioned on one side of the source-drain metal layer, which is away from the substrate base plate, and comprises:

and the second electrode structure is used for forming a common electrode and a second pole of the storage capacitor, and the orthographic projection of the second electrode structure on the substrate is overlapped with the orthographic projection part of the first electrode structure on the substrate.

8. The display panel of claim 7, wherein the common electrode is connected to a touch electrode line;

the source-drain metal layer further comprises the touch electrode wire;

the display panel further includes:

a second passivation layer located between the planarization layer and the second electrode layer and covering the source drain metal layer and the first electrode layer;

the second electrode structure is connected with the touch electrode wire through a via hole.

9. The display panel according to claim 2, wherein the plurality of active portions includes a first active portion for forming a first pole of the driving transistor, a second active portion for forming a channel region of the driving transistor, and a third active portion for forming a second pole of the driving transistor, which are sequentially connected; the display panel further includes:

a buffer layer located between the active layer and the light shielding layer and covering the light shielding layer;

a gate insulating layer between the channel region and the gate portion;

and a first passivation layer between the buffer layer and the planarization layer and covering the gate portion, the first active portion, and the third active portion.

10. A display device comprising the display panel of any one of claims 1-9.