KR101188868B1 - Thin film transistor plate and method of fabricating the same - Google Patents

Abstract

Provided are a thin film transistor substrate having no deterioration in performance and good process efficiency, and a method of manufacturing the same. The thin film transistor substrate includes a gate insulating pattern composed of a double layer, and an upper portion of both sidewalls of the gate insulation pattern positioned at an upper portion is formed at both sidewalls of the gate electrode, and a lower portion of both sidewalls is formed at a low concentration doping region, source region, and drain region. The concentration of the lightly doped region located below the gate insulation pattern substantially aligned with each of the boundary portions gradually changes.

Liquid crystal display, low concentration doping region, inclined portion, double layer

Description

Thin film transistor plate and method of manufacturing the same {Thin film transistor plate and method of fabricating the same}

1 is a schematic structural diagram of a thin film transistor substrate according to an embodiment of the present invention.

2 is a layout diagram illustrating a structure of a pixel part of a thin film transistor substrate according to an exemplary embodiment of the present invention.

3 is a cross-sectional view of the thin film transistor substrate of FIG. 2 taken along the line III-III '.

4 through 6 are cross-sectional views of a thin film transistor substrate including a thin film transistor according to example embodiments.

7, 10, 14, 16, and 18 are layout diagrams at an intermediate stage of the method of manufacturing the pixel portion of the thin film transistor substrate shown in Figs. 2 and 3, respectively, according to an embodiment of the present invention.

8 and 9 are cross-sectional views illustrating the thin film transistor substrate of FIG. 7 taken along the line VIII-VIII ′.

11 to 13 are cross-sectional views illustrating the thin film transistor substrate of FIG. 10 taken along the line XI-XI ′.

FIG. 15 is a cross-sectional view of the thin film transistor substrate of FIG. 14 taken along the line XV-XV ′.

17 is a cross-sectional view of the thin film transistor substrate of FIG. 16 taken along the line XVII-XVII ′.

19 is a cross-sectional view of the thin film transistor substrate of FIG. 18 taken along the line XIX-XIX ′.

20-22 are cross-sectional views at intermediate stages of a method of manufacturing in accordance with embodiments of the present invention.

<Description of the symbols for the main parts of the drawings>

110: substrate 124: gate electrode

150: semiconductor layer 152: low concentration doped region

153: source region 154: channel region

155: drain region 401: first gate insulation pattern

402: second gate insulation pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor substrate and a method of manufacturing the same having no deterioration in performance and good process efficiency.

Background Art Recently, in liquid crystal display devices used as display devices such as notebook-type personal computers and portable devices, the driving method proceeds from a simple matrix method to an active matrix method, and in particular, many thin film transistors on a glass substrate; A thin film transistor active matrix driving method in which TFTs are formed is mainstream.

The thin film transistor includes a gate electrode, which is part of a gate line, and a semiconductor layer forming a channel, a source electrode, which is a part of a data line, and a drain electrode that faces the source electrode with respect to the semiconductor layer. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

In this case, the semiconductor layer is made of amorphous silicon, polycrystalline silicon, or the like, and the thin film transistor may be divided into a top gate method and a bottom gate method according to a position relative to the gate electrode. In the case of the polycrystalline silicon thin film transistor, a top gate method in which the gate electrode is located on the upper portion of the semiconductor layer is mainly used.

Since the driving speed of the polysilicon thin film transistor is much faster than that of the amorphous silicon thin film transistor, there is an advantage in that a driving circuit for operating it together with the thin film transistor of the pixel can be formed together. It is preferable to form a lightly doped region between the channel region and the source region and the drain region.

In the conventional method of forming a low concentration doped region, a gate electrode is first patterned as a double conductive layer on a semiconductor layer, one conductive layer serving as a mask defining a low concentration doped region, and the other conductive layer forming a low concentration doped region. It is then used as a defining mask to form the source and drain regions. However, it is difficult to define the width of the lightly doped region, such as the process of forming two conductive layers in different patterns in one photolithography process. In addition, the process time is lengthened thereby, the production yield is lowered.

An object of the present invention is to provide a thin film transistor substrate without deterioration in performance.

Another technical problem to be achieved by the present invention is to provide a method for manufacturing a thin film transistor substrate having no deterioration in performance and good process efficiency.

Technical problems to be achieved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A thin film transistor substrate according to an embodiment of the present invention for achieving the technical problem is formed on the substrate, the substrate, the low concentration doped region adjacent to each side of the channel region and the source region and drain region adjacent to the low concentration doped region, respectively A semiconductor layer comprising: a gate electrode formed on the channel region of the semiconductor layer; a first gate insulating pattern formed between the semiconductor layer and the gate electrode; and formed between the first gate insulating pattern and the gate electrode. A second gate insulating pattern substantially aligned with both sidewalls of the gate electrode and upper portions of both sidewalls, and lower portions of both sidewalls and substantially aligned with boundaries between the lightly doped region and the source and drain regions; An interlayer insulating film formed on the resultant and the interlayer insulating film formed on the resultant , It includes a first and second source and drain electrodes are respectively electrically connected to the source region and the drain region through the contact hole of the interlayer insulating film.

According to another aspect of the present invention, a method of manufacturing a thin film transistor substrate includes forming a semiconductor layer on a substrate, and sequentially forming a first insulating film, a second insulating film, and a metal film on the semiconductor layer. Forming a gate electrode by patterning the metal layer using the photoresist pattern formed on the metal layer as an etch mask, and patterning the second insulating layer using the photoresist pattern as an etch mask to form a second gate insulating pattern, Forming a second gate insulating pattern such that its thickness decreases from a portion exposed by the gate electrode to both sidewalls of the second gate insulating pattern, and using the gate electrode and the second gate insulating pattern as an ion implantation mask; Impurity ions are implanted to correspond to the lower portion of the gate electrode of the semiconductor layer. A channel region is formed in a region, a lightly doped region is formed in a region corresponding to a lower portion of the second gate insulation pattern exposed by the gate electrode, and a source region and a drain are formed in a region corresponding to a lower portion outside the second gate insulation pattern. Forming a region, forming an interlayer insulating film on the resultant, and source and drain electrodes electrically connected to the source region and the drain region through first and second contact holes of the interlayer insulating layer, respectively. Forming on an interlayer insulating film.

The details of other embodiments are included in the detailed description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various other forms, and it should be understood that the present embodiment is intended to be illustrative only and is not intended to be exhaustive or to limit the invention to the precise form disclosed, To fully disclose the scope of the invention to a person skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 19.

A thin film transistor substrate according to an exemplary embodiment of the present invention will be described with reference to FIG. 1. 1 is a schematic structural diagram of a thin film transistor substrate according to an embodiment of the present invention. As illustrated in FIG. 1, the thin film transistor substrate includes a pixel unit 10, a gate driver 20, and a data driver 30.

The pixel portion 10 includes a plurality of pixels connected to a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm, and each pixel includes a plurality of gate lines G1 to Gn and a plurality of pixels. And a switching element M connected to the data lines D1 to Dm, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto.

The plurality of gate lines G1 to Gn formed in the row direction transmit a scan signal to the switching element M, and the plurality of data lines D1 to Dm formed in the column direction are imaged on the switching element M. The gray voltage corresponding to the signal is transmitted. The switching element M is a three-terminal element, the control terminal is connected to the gate lines G1 to Gn, the input terminal is connected to the data lines D1 to Dm, and the output terminal is the liquid crystal capacitor Clc. And one terminal of the storage capacitor Cst. The liquid crystal capacitor Clc is connected between the output terminal of the switching element M and the common electrode (not shown), and the storage capacitor Cst is connected between the output terminal of the switching element M and the common electrode (independent wiring). Method) or a connection (shear gate method) between the output terminal of the switching element M and the gate lines G1 to Gn directly above.

The gate driver 20 is connected to the plurality of gate lines G1 to Gn, and provides a scan signal for activating the switching element M to the plurality of gate lines G1 to Gn, and the data driver 30 It is connected to a plurality of data lines D1 to Dm.

Here, the MOS transistor is used as the switching element M, and the MOS transistor may be implemented as a thin film transistor having polycrystalline silicon as a channel region. In addition, the gate driver 20 and the data driver 30 may also be configured as MOS transistors. The MOS transistor may be implemented as a thin film transistor having polycrystalline silicon as a channel region.

2 and 3, a thin film transistor substrate having polycrystalline silicon as a channel region will be described. 2 is a layout diagram illustrating a structure of a pixel portion of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view of the thin film transistor substrate of FIG. 2 taken along line III-III ′.

2 and 3, a blocking layer 111 made of silicon oxide or silicon nitride is formed on the transparent insulating substrate 110, and, for example, a high concentration of n-type impurity ions is formed on the blocking layer 111. The semiconductor layer 150 is formed of polycrystalline silicon of a thin film transistor including a source region and a drain region 153 and 155 implanted into the channel region and a channel region 154 interposed therebetween with no impurity ions implanted therein. . For example, a low concentration doped region 152 is formed between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154, for example, where n-type impurity ions are injected at low concentration. have. Here, the blocking layer 111 may be omitted to prevent diffusion of impurities and the like from the substrate 110 to the semiconductor layer 150.

Gate insulating patterns 140d and 140q are formed on the substrate 110 including the semiconductor layer 150 made of polycrystalline silicon. The gate insulating layer patterns 140d and 140q include a first insulating pattern 401 made of silicon oxide and a second insulating pattern 402 made of silicon nitride. In order to reduce the threshold voltage Vth of the thin film transistor including the semiconductor layer made of polycrystalline silicon, it is necessary to reduce the thickness of the gate insulating pattern. In the case of forming a gate insulating pattern with a single layer of a silicon oxide film, the dielectric constant of the silicon oxide film is only about 3.9, which limits the reduction of Vth, and the breakdown voltage when the thickness of the gate insulating pattern is reduced to reduce the Vth. ), The increase in defects caused by static electricity was feared. Therefore, in the thin film transistor according to the exemplary embodiment of the present invention, the double layer structure as the gate insulating pattern, that is, the silicon oxide film as the first gate insulating pattern 401 and the dielectric constant of the silicon oxide film as the second gate insulating pattern 402 are about. By using the silicon nitride film having a double value, it is possible to reduce the threshold voltage Vth and to improve the performance of the thin film transistor.

The first gate insulating pattern 401 is formed in the form of a first insulating film on the entire surface of the transparent insulating substrate 110 on which the semiconductor layer 150 made of polycrystalline silicon is formed. In this case, first and second contact holes are formed in the first insulating layer as a tube for electrically connecting the source region 153 and the drain region 154 of the semiconductor layer 150 to the source electrode and the data electrode, which will be described later. have. In addition, both sidewalls of the second gate insulating pattern 402 may be formed to substantially align the boundary between the lightly doped region 152 and the source and drain regions 153 and 155 of the semiconductor layer 150. The pattern 402 insulates the semiconductor layer 150 made of polycrystalline silicon, the gate electrode 124, and the storage electrode 133, respectively. In addition, when implanting impurity ions for forming a source region and a drain region, which will be described later, it also serves as an ion implantation mask. 152 and the source and drain regions 153 and 155 are divided, so that both sidewalls of the second gate insulating pattern 402 are in a low concentration doped region 152 and the source region of the semiconductor layer 150. The boundary portions of the drain regions 153 and 155 are formed to be substantially aligned.

Gate lines 121 elongated in one direction are formed on the gate insulation pattern 140d, and a part of the gate lines 121 extend to overlap the channel region 154 of the semiconductor layer 150 made of polycrystalline silicon. A portion of the overlapping gate line 121 is used as the gate electrode 124 of the thin film transistor substrate. In addition, a storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 on the gate insulating layer pattern 140q and is formed on the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 made of polycrystalline silicon becomes the storage electrode 133, and the semiconductor layer 150 made of polycrystalline silicon overlapping the storage electrode 133 has a storage electrode region ( 157, the lightly doped regions 152 are formed on both sides of the sustain electrode region 157, and the heavily doped regions 158 are positioned on one side of the sustain electrode region 157. One end portion of the gate line 121 may be formed wider than the width of the gate line 121 to be connected to an external circuit, and may be directly connected to an output terminal of the gate driving circuit.

A first interlayer insulating film 601 is formed on the gate insulating film patterns 140d and 140q on which the gate line 121, the storage electrode line 131, the gate electrode 124 are formed, and the semiconductor layer 150. The first interlayer insulating layer 601 includes first and second contact holes 141 and 142 exposing source and drain regions 153 and 155, respectively.

A data line 171 is formed on the first interlayer insulating layer 601 to cross the gate line 121 and define a pixel area. A portion or the branched portion of the data line 171 is connected to the source region 153 through the first contact hole 141 and the portion connected to the source region 153 is the source electrode 173 of the thin film transistor substrate. Used as One end of the data line 171 may be formed wider than the width of the data line 171 to be connected to an external circuit (not shown), and may be directly connected to an output terminal of the data driving circuit.

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173d and connected to the drain region 155 through the second contact hole 142.

A second interlayer insulating film 602 is formed on the first interlayer insulating film 601 including the source electrode 173, the drain electrode 175, and the data line 171. The second interlayer insulating layer 602 has a third contact hole 143 exposing the drain electrode 175. The pixel electrode 190 connected to the drain electrode 175 through the third contact hole 143 is formed in each pixel area on the second interlayer insulating layer 602.

Subsequently, a thin film transistor substrate according to another exemplary embodiment of the present invention will be described with reference to FIG. 4. 4 is a cross-sectional view of a thin film transistor substrate according to another exemplary embodiment of the present invention. In the thin film transistor substrate according to another exemplary embodiment, upper portions of both sidewalls of the second gate insulating pattern 402 may be substantially aligned with both sidewalls of the gate electrode 124, and lower portions of both sidewalls may be formed of the lightly doped region 152. ) And a thin film transistor substrate according to an embodiment of the present invention except that the thin film transistor substrate is substantially aligned at the boundary between the source region and the drain region 153 and 155, and the boundary between the lightly doped region 152 and the heavily doped region 158. Since it is the same as, the description of duplicate parts will be omitted for convenience. As described above, upper portions 124 of both sidewalls of the second gate insulation pattern 402 are substantially aligned with both sidewalls of the gate electrode 124, and lower portions of both sidewalls are formed of the lightly doped region 152 and the source region; By substantially aligning the boundary between the drain regions 153 and 155, the boundary between the lightly doped region 152 and the heavily doped region 158, the surfaces connecting the upper and lower portions of both sidewalls of the second gate insulation pattern 402. Slopes. The concentration of impurity ions in the lightly doped region 152, which is the region of the semiconductor layer 150 corresponding to the lower portion of the inclined portion including the inclined surface, may be defined as a boundary between the lightly doped region 152 and the source and drain regions 153 and 155. It gradually increases toward the boundary between the lightly doped region 152 and the lightly doped region 158. This will be described in detail in the method of manufacturing a thin film transistor substrate.

Next, a thin film transistor substrate according to still another embodiment of the present invention will be described with reference to FIG. 5. 5 is a cross-sectional view of a thin film transistor transistor substrate according to still another embodiment of the present invention. In the thin film transistor substrate according to another exemplary embodiment, both sidewalls of the second gate insulating pattern 402 may have a boundary between the lightly doped region 152 and the source and drain regions 153 and 155 of the semiconductor layer 150. And substantially aligned with the boundary between the lightly doped region 152 and the heavily doped region 158, and both sidewalls of the first gate insulation pattern 401 are substantially aligned with both sidewalls of the second gate insulation pattern 402. Except that, since the same as the thin film transistor substrate according to an embodiment of the present invention, the overlapping portions will be omitted for convenience.

Subsequently, a thin film transistor substrate according to still another embodiment of the present invention will be described with reference to FIG. 6. 6 is a cross-sectional view of a thin film transistor substrate including a thin film transistor substrate according to another exemplary embodiment of the present invention. In the thin film transistor substrate according to another exemplary embodiment, upper portions of both sidewalls of the second gate insulation pattern 402 may be substantially aligned with both sidewalls of the gate electrode 124, and lower portions of both sidewalls may be formed of a lightly doped region. 152 and the boundary between the source and drain regions 153 and 155 and the boundary between the lightly doped region 152 and the heavily doped region 158 are substantially aligned, and both sidewalls of the first gate insulating pattern 401 are formed. Since it is the same as the thin film transistor substrate according to the exemplary embodiment of the present invention except that the two gate insulating patterns 402 are substantially aligned with the lower portions of both sidewalls, overlapping portions will be omitted for convenience.

A method of manufacturing a thin film transistor substrate according to embodiments of the present invention described above will be described in detail with reference to the accompanying drawings.

7, 10, 14, 16, and 18 are layout diagrams at an intermediate stage of the method of manufacturing the pixel portion of the thin film transistor substrate shown in Figs. 2 and 3, respectively, according to an embodiment of the present invention; 8 and 9 are cross-sectional views of the thin film transistor substrate of FIG. 7 taken along the line VIII-VIII ', and FIGS. 11 to 13 are views illustrating the thin film transistor substrate of FIG. 15 is a cross-sectional view of the thin film transistor substrate of FIG. 14 taken along the line XV-XV ', and FIG. 17 is a cross-sectional view of the thin film transistor substrate of FIG. 16 taken along the line XVI-XVI'. 19 is a cross-sectional view of the thin film transistor substrate of FIG. 20 taken along the line XIX-XIX '.

First, as shown in FIGS. 7 and 8, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer 111 may be formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx). The blocking layer 111 may be omitted to prevent diffusion of impurities and the like from the substrate 110 to the semiconductor layer 150. An amorphous silicon film is deposited on the blocking layer 111 to form an amorphous silicon film.

Thereafter, the amorphous silicon film is crystallized into amorphous silicon through laser annealing, furnace annealing, or solid crystallization, and then patterned by photolithography to form a semiconductor layer 150 made of polycrystalline silicon.

Subsequently, as shown in FIG. 9, an insulating material of silicon oxide and silicon nitride is sequentially deposited on the substrate 110 on which the semiconductor layer 150 made of polycrystalline silicon is formed, thereby depositing a first insulating film 401 and a second insulating film. 402 is formed. The gate metal film 120 is formed by depositing a single film or a multilayer film made of aluminum, chromium, molybdenum, or an alloy thereof on the second insulating film 402. In this case, the thicknesses of the first insulating film 401, the second insulating film 402, and the gate metal film 120 are not particularly limited, and may have various thicknesses depending on device characteristics. Subsequently, a photoresist film is formed on the gate metal film 120, and the photoresist film is exposed and developed by a photolithography process using a photomask to form photoresist patterns 53 and 54. The photoresist patterns 53 and 54 are not only used as etching masks for patterning the gate metal film 120 as gate electrodes, but also as etching masks for patterning a second insulating film or a first insulating film, which will be described later, into a gate insulating pattern. Can be used. For example, the photoresist patterns 53 and 54 may be heat shrinked after patterning the photoresist film into a predetermined shape so that the cross section is trapezoidal, and the cross section is hemispherical by heating using a molten photosensitive film. It can be formed to have a variety of shapes as shown.

The gate metal film 120 for forming the gate electrode 124 may include two films having different physical properties. One film can be made of low resistivity metals or aluminum-based metals such as aluminum (Al) or aluminum alloys, such as aluminum-neodymium (AlNd) alloys, to reduce the delay or voltage drop of the scan signal. It is not limited to this. In contrast, other membranes are materials that have good physical, chemical, and electrical contact properties with other materials, Indium Zinc Oxide (IZO) or Indium Tin Oxide (ITO), molybdenum (Mo), molybdenum alloys, e.g. For example, it may be made of molybdenum-tungsten (MoW) alloy, chromium (Cr) and the like, but is not limited thereto. For example, a metal film of aluminum-neodymium (AlNd) is an aluminum etchant that can be etched while giving a side slope to all aluminum, such as CH ₃ COOH (8-15%) / HNO ₃ (5-8%) / H ₃ PO ₄ ( 50-60%) / H ₂ O (rest) can be used for wet etching. Such an etchant can be etched with respect to the conductive film of molybdenum-tungsten (MoW) while giving the side inclination under the same etching conditions, so that the two conductive films can be etched while continuously giving the side inclination.

Next, as shown in FIGS. 10 and 11, the gate metal layer 120 having the gate electrode 124 is patterned by using the photoresist patterns 53 and 54 as a mask to pattern the gate metal layer 120 to have an undercut structure by isotropic etching. ) And the sustain electrode line 131 having the sustain electrode 133. The sidewalls of the cut surfaces of the gate line 121 and the storage electrode line 131 are preferably formed to be inclined to increase adhesion to the upper layer formed later.

Next, as shown in FIG. 12, the second insulating film 402 is anisotropically etched using the photoresist patterns 53 and 54 as an etch mask to form a width slightly wider than that of the gate electrode 124 and the storage electrode 133. The branches form a second gate insulating pattern 402. In this case, the second gate insulating pattern 402 is disposed between the semiconductor layer 150 made of polycrystalline silicon, the gate electrode 124, and the storage electrode 133, respectively, and the semiconductor layer 150 made of polycrystalline silicon and the gate electrode. The insulating layer 124 and the sustain electrode 133 are insulated from each other, and at the same time, the impurity ions are formed to form a source region and a drain region, which will be described later.

Next, as shown in FIG. 13, after removing the photoresist patterns 53 and 54, for example, a plasma immersion may be performed using the gate electrode 124, the sustain electrode 133, and the gate insulation patterns 140d and 140q as a mask. n-type impurity ion implantation is performed, for example, using an immersion method. The dose may be, for example, 1.0 × 10 ¹⁵ to 5.0 × 10 ¹⁵ particles per unit cm 2, but is not limited thereto, and the dose may vary depending on the thickness of the gate insulation pattern, the characteristics of the device, and the like. Accordingly, a thin film transistor structure is formed in which the lightly doped region 152, the source region, and the drain regions 153 and 155 are formed by only one ion implantation. That is, the lightly doped region 152 is formed in the semiconductor layer 150 in which ion implantation is prevented by the second gate insulating pattern 402 exposed by the gate electrode 124 and the sustain electrode 133. Since the semiconductor layer 150 is not covered by the second gate insulating pattern 402, most of the ions are projected and injected through the silicon oxide film, so that the source region, the drain region 153, 155, and the highly doped region 158 are formed. Is formed. In addition, since the impurity ions are not implanted into the semiconductor layer 150 disposed under the gate electrode 124 and the sustain electrode 133, the channel region 154 and the sustain electrode region 157 are formed, respectively, and the source region 153. ), The drain region 155 and the heavily doped region 158 are separated. As described above, the thin film transistor structure including the low concentration doped region 152, the source region, and the drain regions 153 and 155 may be formed by only one impurity ion implantation since the high concentration n-type impurity ion implantation is made of low energy. Do.

14 and 15, an insulating material is stacked on the entire surface of the substrate 110 to cover the semiconductor layer 150 made of polycrystalline silicon to form a first interlayer insulating film 601. Thereafter, the first interlayer insulating layer 601 is patterned by a photolithography process using a mask to form first contact holes 141 and second contact holes 142 exposing source and drain regions 153 and 155.

Next, as shown in FIGS. 16 and 17, a data metal film is formed on the first interlayer insulating film 601 and patterned by a photolithography process using a mask to form the data line 171, the drain electrode 175, and the source. An electrode 173 is formed. The source electrode 173 is connected to the source region 153 through the first contact hole 141, and the drain electrode 175 is connected to the drain region 155 through the second contact hole 142, respectively.

The data line 171 is formed by depositing a plurality of conductive materials including a single layer of an aluminum-containing metal such as aluminum or an aluminum alloy, molybdenum or molybdenum alloy, an aluminum alloy layer, and a chromium (Cr) or molybdenum (Mo) alloy layer. The metal film for data is formed and then patterned. In this case, the data metal film may also be patterned using the same conductive material and etching method as the gate metal film, and the cut surfaces of the data line 171 and the drain electrode 175 may have a tapered structure having a constant inclination for adhesion to the upper layer. It is preferable to form.

As shown in FIGS. 18 and 19, an organic material having excellent planarization characteristics and photosensitivity, and the like, are stacked on the first interlayer insulating layer 601 including the data line 171 and the drain electrode 175. A second interlayer insulating film 602 is formed. Thereafter, the second interlayer insulating layer 602 is patterned by a photolithography process using a mask to form a third contact hole 143 exposing the drain electrode 175.

2 and 3, an indium tin oxide or indium zinc oxide, which is a transparent material, is deposited on the second interlayer insulating layer 602 including the inside of the third contact hole 143, and then patterned to form a pixel electrode. A connection member (not shown) for electrically connecting the 190 and the plurality of signal lines is formed. The pixel electrode 190 is connected to the drain electrode 175 through the third contact hole 143. The contact auxiliary member may extend over the fourth contact hole (not shown) formed over the first and second interlayer insulating layers 601 and 602, the first and second interlayer insulating layers 601 and 102, and the gate insulating layer 140. The fifth contact hole (not shown) is connected to a connection part electrically connected to the data line 171 and the gate line 121, respectively.

In the method of manufacturing a thin film transistor substrate according to the exemplary embodiment of the present invention, an insulating film is patterned using a photosensitive film pattern for patterning a gate electrode to form a gate insulating film pattern. Without using a photolithography process, the gate insulating layer pattern is used as an ion implantation mask to define a low concentration doped region, a source region, and a drain region. Forming at the same time can simplify the manufacturing process, thereby minimizing the manufacturing cost.

Subsequently, a method of manufacturing a thin film transistor substrate according to another embodiment of the present invention will be described. 20 is a cross-sectional view at an intermediate stage of a method of manufacturing a thin film transistor substrate according to another embodiment of the present invention. As shown in FIG. 20, a method of manufacturing a thin film transistor substrate according to another exemplary embodiment of the present inventive concept is based on photoresist patterns 54 and 53 used as an etch mask of the gate electrode 124 and the storage electrode 133. Except that the insulating layer is patterned so that both sidewalls of the second gate insulating pattern 402 are reduced in thickness from the portions exposed by the gate electrode 124 and the sustain electrode 133 toward both sidewalls. A thin film transistor as shown in FIG. 4 is manufactured using the manufacturing method according to the embodiment of FIG. That is, by using the photosensitive film patterns 54 and 53 used as etching masks for forming the gate electrode 124 and the sustain electrode 133, for example, an area exposed by the gate electrode 124 is etched out of the second insulating film. As the gas, the inclined surface is formed outward from the region where the gate electrode 124 is formed by an anisotropic etching process using SF ₆ + O ₂ .

As described above, the second gate insulating pattern 402 serves as an ion implantation mask for forming the lightly doped region 152, the source and drain regions 153 and 155, and the heavily doped region 158. The impurity ion concentration injected into the semiconductor layer 150 corresponding to the inclined portion including the inclined surface of the second gate insulating pattern 402 is gradually increased toward both sidewalls of the second gate insulating pattern 402 due to the thickness difference of the inclined portion. Becomes higher, and the change in concentration of such impurity ions is determined by the shape of the inclined portion. The concentration of impurity ions injected into the low concentration doped region 152 is gradually changed by the inclination inclination (change in thickness) of the inclined portion. The thin film transistor substrate manufactured by the manufacturing method according to another embodiment of the present invention includes a low concentration doped region 152 having a gradual change in concentration as described above, so that leakage current is suppressed and the performance of the thin film transistor is not degraded.

Meanwhile, in the above embodiments, only one insulating film of the double insulating films is used as an ion implantation mask to define the source region, the drain region and the low concentration doping region, but the double insulating layer is patterned to form a gate insulating pattern. This will be described.

A method of manufacturing a thin film transistor substrate according to still another embodiment of the present invention will be described. 21 is a cross-sectional view at an intermediate stage of a method of manufacturing a thin film transistor substrate according to still another embodiment of the present invention. As shown in FIG. 21, a method of manufacturing a thin film transistor substrate according to another exemplary embodiment of the present inventive concept is based on the photoresist patterns 54 and 53 used as etching masks of the gate electrode 124 and the storage electrode 133. The insulating film is patterned to form a second gate insulating pattern 402 having a width slightly wider than that of the gate electrode 124 and the storage electrode 133, and the first photoresist film patterns 54 and 53 are used as etching masks. The insulating film is patterned to form a first gate insulating pattern 401 on both sidewalls of the second gate insulating pattern 402 so that both sidewalls of the first gate insulating pattern 401 are substantially aligned. A thin film transistor as shown in FIG. 5 is manufactured using the same method as the manufacturing method according to an embodiment. In the thin film transistor substrate manufactured according to another exemplary embodiment of the present invention, the first gate insulating pattern 401 is formed only on the channel region 154 and the lightly doped region 152, thereby forming impurity ions in the lightly doped region 152. It is easier to control the concentration to the desired concentration, so that the leakage current can be suppressed, thereby improving the performance of the thin film transistor.

Subsequently, a method of manufacturing a thin film transistor substrate according to still another embodiment of the present invention will be described. 22 is a cross-sectional view at an intermediate stage of a method of manufacturing a thin film transistor substrate according to still another embodiment of the present invention. As illustrated in FIG. 22, a method of manufacturing a thin film transistor substrate according to another exemplary embodiment of the present inventive concept is based on the photoresist patterns 54 and 53 used as etching masks of the gate electrode 124 and the sustain electrode 133. The insulating film is patterned so that both sidewalls of the second gate insulating pattern 402 are reduced from the portion exposed by the gate electrode 124 and the storage electrode 133 to both sidewalls, and the same photoresist pattern 54 , Except that 53 is used as an etch mask to pattern the first insulating film to form a first gate insulating pattern 401 in which both lower sidewalls of both sidewalls of the second gate insulating pattern 402 are substantially aligned. A thin film transistor as shown in FIG. 6 is manufactured using the manufacturing method according to an embodiment of the present invention. In the thin film transistor substrate manufactured by the fabrication method according to another embodiment of the present invention, the lightly doped region 152 and the first gate insulating pattern 401 having the gradual concentration change may be formed in the channel region 154 and the lightly doped region ( By forming only on 152, it is easier to control the impurity ion concentration of the low concentration doped region 152 to a desired concentration, and the leakage current can be suppressed, so that the performance of the thin film transistor can be improved.

Although the thin film transistor formed by n-type impurity ion doping has been described above, it goes without saying that the present invention is applicable to the case where p-type impurity ions are used.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains can realize that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

According to the present invention as described above, by patterning the gate electrode and the double gate insulating pattern by one photosensitive film pattern, and simultaneously forming a source region and a drain region and a low concentration doped region by one impurity ion implantation process, It is possible to provide a thin film transistor which simplifies the manufacturing process and increases process efficiency, while suppressing leakage current, thereby reducing performance.

Claims (15)

Board; A semiconductor layer formed on the substrate and including a low concentration doped region adjacent to both sides of the channel region and a source region and a drain region respectively adjacent to the low concentration doped region; A gate electrode formed on the channel region of the semiconductor layer; A first gate insulating pattern formed between the semiconductor layer and the gate electrode; A second gate insulating pattern formed on the first gate insulating pattern, wherein the second gate insulating pattern includes a first portion and a second portion, wherein the first portion is between the first gate insulating pattern and the gate electrode; And upper portions of both sidewalls of the first portion are substantially aligned with both sidewalls of the gate electrode, and lower portions of both sidewalls of the first portion are boundary portions between the lightly doped region and the source region and the drain region. The second gate insulating pattern substantially aligned with; A sustain electrode formed on the second portion; An interlayer insulating layer formed on the semiconductor layer, the gate electrode and the sustain electrode; And And a source electrode and a drain electrode formed on the interlayer insulating layer and electrically connected to the source region and the drain region, respectively, through the first and second contact holes of the interlayer insulating layer. The thin film transistor substrate of claim 1, wherein the first gate insulating pattern is a silicon oxide film. The thin film transistor substrate of claim 1, wherein the second gate insulating pattern is a silicon nitride film. The thin film transistor substrate of claim 1, wherein the lightly doped region gradually increases impurity ion concentration from an interface between the channel region and the lightly doped region toward an interface between the lightly doped region and the source region and the drain region. The thin film transistor substrate of claim 1, wherein the first gate insulating layer includes first and second contact holes together with the interlayer insulating layer. The thin film transistor substrate of claim 1, wherein both sidewalls of the first gate insulation pattern are substantially aligned with lower portions of both sidewalls of the second gate insulation pattern. The thin film transistor substrate of claim 1, further comprising a blocking layer between the substrate and the semiconductor layer. Forming a semiconductor layer on the substrate; Sequentially forming a first insulating film, a second insulating film, and a metal film on the semiconductor layer; Forming a gate electrode by patterning the metal layer using an photoresist pattern formed on the metal layer as an etching mask; The second insulating layer is patterned by using the photoresist pattern as an etch mask to form a second gate insulating pattern, the thickness of which is reduced from the portion exposed by the gate electrode toward both sidewalls of the second gate insulating pattern. Forming a gate insulation pattern; Impurity ions are implanted into the gate electrode and the second gate insulating pattern using an ion implantation mask to form a channel region in a region corresponding to the lower portion of the gate electrode of the semiconductor layer, and the second gate insulation exposed by the gate electrode. Forming a lightly doped region in a region corresponding to a lower portion of the pattern, and a source region and a drain region in a region corresponding to the lower portion of the outer side of the second gate insulating pattern; Forming an interlayer insulating film on the semiconductor layer and the gate electrode; And Forming a source electrode and a drain electrode on the interlayer insulating layer, the source electrode and the drain electrode electrically connected to the source region and the drain region, respectively, through the first and second contact holes of the interlayer insulating layer. The method of claim 8, wherein the first gate insulating pattern is a silicon oxide film. The method of claim 8, wherein the second gate insulating pattern is a silicon nitride film. The method of claim 8, wherein the second gate insulating pattern is formed by patterning the second insulating layer by anisotropic etching. The method of claim 11, wherein the anisotropic etching uses SF 6 and O 2 as an etching gas. The thin film transistor of claim 8, wherein the lightly doped region gradually increases the impurity ion concentration from the boundary between the channel region and the lightly doped region to the boundary between the lightly doped region and the source region and the drain region. Method of manufacturing a substrate. The method of claim 8, further comprising: forming a first gate insulation pattern that substantially aligns the first insulating layer with lower portions of both sidewalls of the second gate insulation pattern after the forming of the second gate insulation pattern. Method of manufacturing a thin film transistor substrate. The method of claim 8, further comprising forming a blocking layer on the substrate before forming the semiconductor layer.

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