CN113641051B - Array substrate and display panel - Google Patents
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- CN113641051B CN113641051B CN202111200792.3A CN202111200792A CN113641051B CN 113641051 B CN113641051 B CN 113641051B CN 202111200792 A CN202111200792 A CN 202111200792A CN 113641051 B CN113641051 B CN 113641051B
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- 239000000758 substrate Substances 0.000 title claims abstract description 92
- 239000000463 material Substances 0.000 claims abstract description 123
- 239000004020 conductor Substances 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 19
- 239000012212 insulator Substances 0.000 claims abstract description 18
- 238000002161 passivation Methods 0.000 claims description 14
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 12
- 239000011810 insulating material Substances 0.000 claims description 10
- 229920001940 conductive polymer Polymers 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims description 8
- 239000002041 carbon nanotube Substances 0.000 claims description 6
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 6
- 229910021389 graphene Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229920000642 polymer Polymers 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000002064 nanoplatelet Substances 0.000 claims description 4
- 229920000767 polyaniline Polymers 0.000 claims description 3
- 229920000123 polythiophene Polymers 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 8
- 230000008707 rearrangement Effects 0.000 description 7
- 230000009471 action Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000001125 extrusion Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000000178 monomer Substances 0.000 description 2
- -1 polytetrafluoroethylene Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 239000002055 nanoplate Substances 0.000 description 1
- 239000002135 nanosheet Substances 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The application relates to the technical field of display, in particular to an array substrate and a display panel. The array substrate includes: the pixel structure comprises a substrate, and a first electrode and a second electrode which are formed on the substrate, wherein the first electrode is a pixel electrode, and the second electrode is a common electrode or a ground electrode; the first electrode and the second electrode are connected through at least one force-sensitive resistance material layer, and the force-sensitive resistance material layer is extruded to be changed into a conductor through an insulator or a semiconductor. The force sensitive resistance material layer in the array substrate is extruded and then becomes a conductor through an insulator or a semiconductor, the conductive force sensitive resistance material layer enables the first electrode to be communicated with the second electrode in a short circuit mode, liquid crystal molecules at the pressed part can be prevented from being rearranged, the phenomenon of uneven brightness of scratches can be avoided, and the product quality is finally improved.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to an array substrate and a display panel.
Background
Trace Mura (indentation) is understood as a scratch uneven brightness phenomenon, which is a phenomenon that Mura (uneven brightness) appears on a display along a line of a scratching position after a surface of the display is scratched by a hard member without damaging a surface film layer, and the Mura cannot disappear in a short time. The principle of Trace Mura is that when the display panel is stressed, the liquid crystal molecules with large inclination angles at the stressed positions are extruded and rearranged to change the light transmittance, and after the stress is removed, the rearranged liquid crystal molecules can not return to the original positions in a short time under the action of an electric field, so that the display effect is influenced, and the product quality is finally influenced.
Disclosure of Invention
An object of the present application is to provide an array substrate and a display panel, which aim to solve the technical problem of how to reduce the Trace Mura phenomenon.
In order to achieve the purpose of the application, the technical scheme adopted by the application is as follows:
in a first aspect, the present application provides an array substrate, including:
the touch screen comprises a substrate, and a first electrode and a second electrode which are formed on the substrate, wherein the first electrode is a pixel electrode, the second electrode is a common electrode or a ground electrode, the first electrode and the second electrode are connected through at least one layer of force sensitive resistance material layer, and the force sensitive resistance material layer is changed into a conductor from an insulator or a semiconductor after being extruded.
In one embodiment, the array substrate further includes:
a gate formed on the substrate;
a gate insulating layer formed on the substrate and covering the gate;
an active layer formed on the gate insulating layer;
the source and drain electrodes are formed on the active layer;
the passivation layer is formed on the source and drain electrodes;
the first electrode is located on the passivation layer, the second electrode is located between the substrate and the grid insulating layer, a force-sensitive resistance material layer is arranged between the first electrode and the passivation layer, a force-sensitive resistance material layer is arranged between the second electrode and the grid insulating layer, and the first electrode is in contact with the force-sensitive resistance material layer on the second electrode through a through hole.
In one embodiment, the array substrate further includes:
a gate formed on the substrate;
a gate insulating layer formed on the substrate and covering the gate;
an active layer formed on the gate insulating layer;
the source and drain electrodes are formed on the active layer;
the passivation layer is formed on the source and drain electrodes;
the color resistance layer is formed on the passivation layer;
a flat layer formed on the color resist layer;
the first electrode and the second electrode are on the same layer, and the second electrode is a common electrode; the first electrode and the second electrode are arranged on the flat layer at intervals, and the force-sensitive resistance material layer covers the first electrode and the second electrode so as to connect the first electrode and the second electrode; or the force-sensitive resistance material layer is arranged on the flat layer, the first electrode and the second electrode are arranged on the force-sensitive resistance material layer at intervals, and connection is realized through the force-sensitive resistance material layer.
In one embodiment, the material of the force-sensitive resistive material layer is selected from at least one of a silicon semiconductor, a conductive polymer, an organic insulating material containing a conductive material.
In one embodiment, the conductive polymer is selected from at least one of polythiophene-based polymer and polyaniline-based polymer;
and/or the conductive material in the organic insulating material is selected from at least one of carbon nanotubes and graphene nanoplatelets.
In one embodiment, the material of the force-sensitive resistance material layer is selected from organic insulating materials containing conductive materials, and the thickness of the force-sensitive resistance material layer is 200 nm-1500 nm.
In one embodiment, the conductive material comprises 40% to 60% of the volume fraction of the force-sensitive resistive material layer.
In one embodiment, a contact portion of the force-sensitive resistive material layer with the first electrode or the second electrode is provided with a conductive tip-like material, a tip of the tip-like material facing the force-sensitive resistive material layer.
The array substrate provided by the application is provided with at least one layer of force sensitive resistance material layer, the force sensitive resistance material layer is connected with a first electrode, namely a pixel electrode, and a second electrode, namely a common electrode or a ground electrode, the resistance value of the force sensitive resistance material layer is reduced along with the increase of external force, when no external force exists, the force sensitive resistance material layer is an insulator or a semiconductor, the display effect is not influenced, the first electrode and the second electrode are connected through the force sensitive resistance material layer, therefore, the resistance of the force sensitive resistance material layer is reduced after being extruded and can be changed into a conductor through the insulator or the semiconductor, the first electrode is communicated with the second electrode in a short circuit mode through the conductive force sensitive resistance material layer, the rearrangement of liquid crystal molecules at the pressed part can be avoided, the phenomenon of Trace Mura can be avoided, and the quality of the product is finally improved.
In a second aspect, the present application provides a display panel comprising: the liquid crystal display panel comprises an array substrate, a color film substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color film substrate.
In one embodiment, the color film substrate is provided with a black matrix, and the force-sensitive resistance material layer is arranged opposite to the black matrix.
The application provides a display panel includes this application specific array substrate, and this array substrate is equipped with distinctive force sensitive resistance material layer and connects first electrode and second electrode, and the extrusion back resistance of force sensitive resistance material layer diminishes and can become the conductor by insulator or semiconductor to make first electrode and second electrode short circuit intercommunication, can avoid the liquid crystal molecule rearrangement at pressurized position like this, thereby can avoid producing Trace Mura phenomenon, finally promote this display panel's product quality.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to a first embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an array substrate according to a first embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an array substrate according to a second embodiment of the present application;
fig. 4 is a schematic structural diagram of an array substrate according to a third embodiment of the present application;
fig. 5 is a schematic structural diagram of a display panel according to a fourth embodiment of the present application;
fig. 6 is a schematic structural diagram of a display panel according to a fourth embodiment of the present application;
wherein, in the figures, the respective reference numerals:
the manufacturing method comprises the following steps of 10-a substrate, 11-a first electrode, 12-a second electrode, 13-a force sensitive resistance material layer, 14-a grid electrode, 15-a grid electrode insulating layer, 16-an active layer, 17-a source and drain electrode, 18-a passivation layer, 19-a color resistance layer, 20-a flat layer, 21-a through hole, 30-a liquid crystal layer, 31-liquid crystal molecules, 40-a color film substrate and 41-a black matrix.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application more clearly apparent, the present application is further described in detail below with reference to the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In this application, the term "and/or" describes an association relationship of associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a is present alone, A and B are present simultaneously, and B is present alone. Wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
In the present application, "at least one" means one or more, "plural" means two or more. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items.
It should be understood that, in various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, some or all of the steps may be executed in parallel or executed sequentially, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The terms "first" and "second" are used for descriptive purposes only and are used for distinguishing purposes such as substances from one another, and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. For example, a first XX may also be referred to as a second XX, and similarly, a second XX may also be referred to as a first XX, without departing from the scope of embodiments of the present application. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
The first embodiment:
the present embodiment provides an array substrate, as shown in fig. 1 and 2, the array substrate includes:
a substrate 10;
a first electrode 11 formed on the substrate 10;
a second electrode 12 formed on the substrate 10;
the first electrode 11 is a pixel electrode, and the second electrode 12 is a common electrode or a ground electrode;
the first electrode 11 and the second electrode 12 are connected through at least one force sensitive resistance material layer 13, and the force sensitive resistance material layer 13 is pressed to be changed into a conductor by an insulator or a semiconductor.
The array substrate provided by this embodiment is provided with at least one force-sensitive resistance material layer 13, the force-sensitive resistance material layer 13 connects the first electrode 11, i.e. the pixel electrode, and the second electrode 12, i.e. the common electrode or the ground electrode, the resistance value of the force-sensitive resistance material layer 13 decreases with the increase of an external force, when no external force is applied, the force-sensitive resistance material layer 13 is an insulator or a semiconductor, and the display effect is not affected, because the force-sensitive resistance material layer 13 connects the first electrode and the second electrode, therefore, when the resistance of the force-sensitive resistance material layer 13 decreases after being squeezed, the insulator or the semiconductor can be changed into a conductor, the conductive force-sensitive resistance material layer 13 connects the first electrode 11 and the second electrode 12 in short circuit, so as to eliminate the high voltage difference between the first electrode 11 and the second electrode 12 at the squeezed position, avoid the rearrangement of liquid crystal molecules at the squeezed position, and avoid the generation of Trace Mura phenomenon, finally, the product quality is improved.
In this embodiment, the first electrode 11 and the second electrode 12 may be in the same layer and located on the same side of the force-sensitive resistance material layer 13, and the force-sensitive resistance material layer 13 may be located above the first electrode 11 and the second electrode 12, or 13 may be located below the first electrode 11 and the second electrode 12; as shown in fig. 1, the force sensitive resistance material layer 13 covers the first electrode 11 and the second electrode 12 to connect the first electrode 11 and the second electrode 12, and the second electrode 12 may be a common electrode. Of course, the first electrode 11 and the second electrode 12 may be different layers, respectively located on both sides of the force-sensitive resistance material layer 13, as shown in fig. 2, the force-sensitive resistance material layer 13 connects the first electrode 11 and the second electrode 12 between the first electrode 11 and the second electrode 12, in which case the second electrode 12 may be a common electrode or a ground electrode.
Specifically, the array substrate provided by this embodiment is an array substrate for a liquid crystal display panel, the material of the force-sensitive resistance material layer 13 on the array substrate has a force-sensitive resistance property, and the resistance value thereof changes with the change of an external force action, specifically, the resistance of the force-sensitive resistance material decreases with the increase of an action force, and the external force action changes the force-sensitive resistance material layer 13 from a non-conductive insulator or semiconductor into a conductor, so that the first electrode 11 and the second electrode 12 are communicated at an extrusion position, thereby avoiding the rearrangement of liquid crystal molecules at the pressing part of the display panel, avoiding the generation of Trace Mura, and improving the product quality.
It should be noted that the term force or compression in this application refers generally to the external force that is currently capable of producing Mura, which corresponds to a threshold value. When the force-sensitive resistance material layer 13 is not affected by external force or the external force is smaller than the threshold value, the force-sensitive resistance material layer 13 in the array substrate of the embodiment of the application is a non-conductive insulator or semiconductor; when the external force is greater than or equal to the threshold value, the force-sensitive resistance material layer 13 is changed from an insulator or a semiconductor into a conductor, and when the external force is removed again, the insulation is performed again; therefore, the display effect of the display panel in normal use is not influenced, and the phenomenon of Trace Mura can be avoided.
Specifically, the material of the force-sensitive resistance material layer 13 on the array substrate is selected from at least one of a silicon semiconductor, a conductive polymer, and an organic insulating material containing a conductive material. The conductive polymer is a polymer formed by chemical polymerization of a conductive monomer and some resin monomers, and can be at least one selected from polythiophene polymers and polyaniline polymers. The silicon semiconductor and the conductive polymer have force-sensitive resistance performance, and after the force-sensitive resistance material layer 13 is manufactured, the silicon semiconductor and the conductive polymer are not conductive when not extruded, and become conductors when external force with a certain threshold value is received.
In the organic insulating material containing the conductive material, the conductive material is selected from at least one of carbon nanotubes and graphene nanoplatelets, and the graphene nanoplatelets and the carbon nanotubes are dispersed in the organic insulating material. The organic insulating material may be polytetrafluoroethylene, silicone rubber, acryl resin, or the like. When not squeezed, the material layer 13 is an insulator, and when the force-sensitive resistance material layer 13 is acted by an external force with a certain threshold value, the conductive material parts in the material layer are contacted with each other, so that the force-sensitive resistance material layer 13 is changed into a conductor from the insulator.
Specifically, the thickness of the force-sensitive resistance material layer 13 is 200 nm-1500 nm. In the force-sensitive resistance material layer 13, the size of the dispersed carbon nanotubes can be 2nm × 100 nm-100 nm × 1 μm, and the size of the graphene nanosheets can be 2nm × 200 nm-20 nm × 1 μm. The force-sensitive resistance material layer 13 with the thickness of 200 nm-1500 nm is more conductive after the action of external force with a certain threshold value. Further, the volume percentage of the conductive material (such as carbon nanotubes or graphene nanoplates) in the force-sensitive resistance material layer 13 is 40% to 60% of the force-sensitive resistance material layer 13. Under the above volume ratio condition, the force-sensitive resistance material layer 13 is pressed to make the conductive material contact better, thereby becoming a conductor. The nanoscale material referred to in the present application may be a material having a size of 1nm to 1000 nm.
Specifically, the contact portion of the force-sensitive resistance material layer 13 with the first electrode 11 is provided with a conductive tip structure, the tip of which is directed toward the force-sensitive resistance material layer 13. Alternatively, the contact portion of the force-sensitive resistance material layer 13 with the second electrode 12 is conductively provided with a conductive tip structure, the tip of which is directed toward the force-sensitive resistance material layer 13. Specifically, the tip structure is a layer of conductive tip-like material, disposed between the force-sensitive resistive material layer 13 and the first electrode 11 or the second electrode 12, with the tip of the tip structure facing the force-sensitive resistive material layer 13. When the force-sensitive resistance material layer 13 is pressed under the action of an external force, at least parts of the conductive materials are in mutual contact, so that the force-sensitive resistance material layer 13 is changed from an insulator into a conductor, and meanwhile, the tip structure can pierce through the surface of the force-sensitive resistance material layer 13 and is in contact conduction with the conductive materials, so that the conductivity of the force-sensitive resistance material layer 13 and the first electrode 11 or the second electrode 12 can be further increased.
Second embodiment:
the present embodiment provides an array substrate, as shown in fig. 3, the array substrate further includes:
a substrate 10;
a gate 14 formed on the substrate 10;
a gate insulating layer 15 formed on the substrate 10 and covering the gate 14;
an active layer 16 formed on the gate insulating layer 15;
a source/drain electrode 17 formed on the active layer 16;
a passivation layer 18 formed on the source/drain electrode 17;
the first electrode 11 and the second electrode 12 are different layers, the first electrode 11 is located on a passivation layer 18, the second electrode 12 is located between a substrate 10 and a gate insulating layer 15, a force-sensitive resistance material layer 13 is arranged between the first electrode 11 and the passivation layer 18, a force-sensitive resistance material layer 13 is arranged between the second electrode 12 and the gate insulating layer 15, and the first electrode 11 is in contact with the force-sensitive resistance material layer 13 on the second electrode 12 through a through hole 21. Wherein, the first electrode 11 is a pixel electrode, and the force sensitive resistance material layer 13 on the passivation layer 18 can connect the sub-pixel electrodes; the second electrode 12 is a common electrode or a ground electrode, and the force sensitive resistance material layer 13 on the second electrode 12 can connect the first electrode 11 and the second electrode 12, thus realizing that each sub-pixel electrode is connected with the second electrode 12. When the force-sensitive resistance material layer 13 is changed into a conductor after being subjected to an external force with a certain threshold value, the conductive force-sensitive resistance material layer 13 connects and conducts the first electrode 11 and the second electrode 12, so that the pixel electrode and the common electrode or the ground electrode are in short circuit connection and communication at the extrusion position, and the high pressure difference between the two electrodes at the extrusion position is eliminated, thereby avoiding the rearrangement of liquid crystal molecules at the compression part in more pixel unit areas, avoiding the generation of Trace Mura phenomenon, and finally improving the product quality. In which, the material and thickness of the force-sensitive resistance material layer 13 of the first embodiment can be selected according to the array substrate shown in fig. 3.
The third embodiment:
the array substrate provided in this embodiment is a coa (color Filter On array) substrate, and the color resistance layer is integrally formed On one side of the array substrate, and specifically, as shown in fig. 4, the array substrate further includes:
a substrate 10;
a gate 14 formed on the substrate 10;
a gate insulating layer 15 formed on the substrate 10 and covering the gate 14;
an active layer 16 formed on the gate insulating layer 15;
a source/drain electrode 17 formed on the active layer 16;
a passivation layer 18 formed on the source and drain electrodes 17;
a color resist layer 19 formed on the passivation layer 18;
a flat layer 20 formed on the color resist layer 19;
the first electrode 11 and the second electrode 12 are on the same layer, the first electrode 11 is a pixel electrode, and the second electrode 12 is a common electrode; the first electrode 11 and the second electrode 12 are disposed on the planarization layer 20 at an interval, and the force-sensitive resistance material layer 13 covers the first electrode 11 and the second electrode 12 to connect the first electrode 11 and the second electrode 12. The structure is beneficial to the preparation of the force-sensitive resistance material layer 13, the process is simple, the force-sensitive resistance material layer 13 becomes a conductor after being subjected to an external force with a certain threshold value, the conductive force-sensitive resistance material layer 13 connects and conducts the first electrode 11 and the second electrode 12, and the pixel electrode and the common electrode are in short circuit communication at the extrusion position, so that the rearrangement of liquid crystal molecules at the pressed part can be avoided, the Trace Mura phenomenon is avoided, and the product quality is finally improved. In which, the material and thickness of the force-sensitive resistance material layer 13 of the first embodiment can be selected according to the array substrate shown in fig. 4.
In addition, the force-sensitive resistance material layer 13 may also be provided on the planarization layer 20, and the first electrode 11 and the second electrode 12 are provided on the force-sensitive resistance material layer 13 at an interval, through which the connection is made.
The fourth embodiment:
the present embodiment provides a display panel, as shown in fig. 5 and 6, the display panel including: the liquid crystal display panel comprises an array substrate, a color film substrate 40 arranged opposite to the array substrate, and a liquid crystal layer 30 positioned between the array substrate and the color film substrate 40; specifically, the array substrate includes: a substrate 10, a first electrode 11 and a second electrode 12 formed on the substrate 10; the first electrode 11 is a pixel electrode, and the second electrode 12 is a common electrode or a ground electrode; the first electrode 11 and the second electrode 12 are connected through at least one force sensitive resistance material layer 13, and the force sensitive resistance material layer 13 is pressed to be changed into a conductor by an insulator or a semiconductor.
Wherein the first electrode 11 and the second electrode 12 may be in the same layer, and located on the same side of the force-sensitive resistance material layer 13, as shown in fig. 5; of course, the first electrode 11 and the second electrode 12 may be located on two sides of the force-sensitive resistance material layer 13 in different layers, as shown in fig. 6.
The display panel that this embodiment provided includes the peculiar array substrate of this application embodiment, and this array substrate is equipped with peculiar force sensitive resistance material layer 13 and connects first electrode 11 and second electrode 12, and the resistance diminishes can become the conductor by insulator or semiconductor after force sensitive resistance material layer 13 extrudes to make first electrode 11 and second electrode 12 short circuit intercommunication, can avoid the rearrangement of liquid crystal molecule 31 in the pressurized position liquid crystal layer 30 like this, thereby can avoid producing Trace Mura phenomenon, finally promote this display panel's product quality.
Specifically, the color filter substrate 40 of the display panel is provided with a black matrix 41, and the force sensitive resistor material layer is arranged opposite to the black matrix 41. The force-sensitive resistance material is generally a transparent material and has a small light-shielding effect, however, the force-sensitive resistance material layer 13 is disposed opposite to the black matrix 41 as in the embodiment of the present application, so that the light-shielding effect can be further reduced, and the display panel has a better display effect.
Specifically, the display panel provided in the embodiment of the present application may be provided with the array substrates provided in the first embodiment, the second embodiment, and the third embodiment, and therefore, all solutions selectable by the array substrate may be used in the display panel, and the display panel has all advantages of the array substrates provided in the embodiments, and details are not repeated herein.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (9)
1. An array substrate comprising a substrate and a first electrode and a second electrode formed on the substrate, the first electrode being a pixel electrode, the second electrode being a common electrode or a ground electrode, characterized in that: the first electrode and the second electrode are connected through at least one force-sensitive resistance material layer, and the force-sensitive resistance material layer is extruded and then changed into a conductor through an insulator or a semiconductor.
2. The array substrate of claim 1, wherein the array substrate further comprises:
a gate formed on the substrate;
a gate insulating layer formed on the substrate and covering the gate;
an active layer formed on the gate insulating layer;
the source and drain electrodes are formed on the active layer;
the passivation layer is formed on the source and drain electrodes;
the color resistance layer is formed on the passivation layer;
a flat layer formed on the color resist layer;
the first electrode and the second electrode are on the same layer, and the second electrode is a common electrode; the first electrode and the second electrode are arranged on the flat layer at intervals, and the force-sensitive resistance material layer covers the first electrode and the second electrode so as to connect the first electrode and the second electrode; or the force-sensitive resistance material layer is arranged on the flat layer, the first electrode and the second electrode are arranged on the force-sensitive resistance material layer at intervals, and connection is realized through the force-sensitive resistance material layer.
3. The array substrate of any of claims 1-2, wherein the material of the force sensitive resistive material layer is selected from at least one of a silicon semiconductor, a conductive polymer, and an organic insulating material containing a conductive material.
4. The array substrate according to claim 3, wherein the conductive polymer is at least one selected from the group consisting of polythiophene polymers and polyaniline polymers;
and/or the conductive material in the organic insulating material is selected from at least one of carbon nanotubes and graphene nanoplatelets.
5. The array substrate according to any one of claims 1-2, wherein the material of the force-sensitive resistance material layer is selected from organic insulating materials containing conductive materials, and the thickness of the force-sensitive resistance material layer is 200 nm-1500 nm.
6. The array substrate of claim 5, wherein the conductive material is 40% to 60% by volume of the force sensitive resistive material layer.
7. The array substrate of claim 5, wherein a contact portion of the force-sensitive resistive material layer with the first electrode or the second electrode is provided with a conductive tip-like material, a tip of the tip-like material facing the force-sensitive resistive material layer.
8. A display panel, comprising the array substrate of any one of claims 1 to 7, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
9. The display panel according to claim 8, wherein the color filter substrate is provided with a black matrix, and the force-sensitive resistive material layer is arranged opposite to the black matrix.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111200792.3A CN113641051B (en) | 2021-10-15 | 2021-10-15 | Array substrate and display panel |
| PCT/CN2022/122195 WO2023061226A1 (en) | 2021-10-15 | 2022-09-28 | Array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111200792.3A CN113641051B (en) | 2021-10-15 | 2021-10-15 | Array substrate and display panel |
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| CN113641051B true CN113641051B (en) | 2022-02-08 |
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| CN113641051B (en) * | 2021-10-15 | 2022-02-08 | 惠科股份有限公司 | Array substrate and display panel |
| CN114706239B (en) * | 2022-03-30 | 2023-07-18 | 绵阳惠科光电科技有限公司 | Display device and binding state detection method |
| CN114879396B (en) * | 2022-05-23 | 2023-03-31 | 惠科股份有限公司 | Pixel driving structure, preparation method and display panel |
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| GB0319910D0 (en) * | 2003-08-23 | 2003-09-24 | Koninkl Philips Electronics Nv | Touch-input active matrix display device |
| JP4677727B2 (en) * | 2004-03-03 | 2011-04-27 | セイコーエプソン株式会社 | Semiconductor device, electro-optical device and electronic apparatus |
| TWI501215B (en) * | 2009-02-27 | 2015-09-21 | Au Optronics Corp | Method for improving pooling mura on liquid crystal display apparatus and liquid crystal display apparatus |
| CN101494041B (en) * | 2009-03-13 | 2012-07-18 | 友达光电股份有限公司 | Method for reducing daggle ghost phenomena of liquid crystal display and liquid crystal display |
| CN102654681B (en) * | 2012-02-23 | 2016-09-28 | 京东方科技集团股份有限公司 | A kind of display panels and manufacture method thereof and display device |
| CN103616784A (en) * | 2013-12-10 | 2014-03-05 | 友达光电股份有限公司 | Liquid crystal display device |
| CN104597669B (en) * | 2014-12-30 | 2017-10-03 | 深圳市华星光电技术有限公司 | Liquid crystal display panel |
| CN104765208B (en) * | 2015-03-17 | 2017-10-17 | 深圳市华星光电技术有限公司 | Liquid crystal display panel |
| CN105911774B (en) * | 2016-06-30 | 2019-07-12 | 京东方科技集团股份有限公司 | Spacer material and its manufacturing method, display device |
| CN107402478B (en) * | 2017-08-17 | 2021-01-08 | 惠科股份有限公司 | Display device, display panel and manufacturing method thereof |
| CN108172182A (en) * | 2017-12-25 | 2018-06-15 | 昆山龙腾光电有限公司 | Black picture is inserted into circuit, display device and electronic equipment |
| CN108447433B (en) * | 2018-02-28 | 2024-07-02 | 厦门天马微电子有限公司 | Curved surface display panel and stress detection and voltage regulation method thereof |
| CN111276521A (en) * | 2020-02-11 | 2020-06-12 | 深圳市华星光电半导体显示技术有限公司 | Flexible display module and display device |
| CN113485039B (en) * | 2021-05-31 | 2022-04-19 | 惠科股份有限公司 | Array substrate and display panel |
| CN113641051B (en) * | 2021-10-15 | 2022-02-08 | 惠科股份有限公司 | Array substrate and display panel |
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| WO2023061226A1 (en) | 2023-04-20 |
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