JP2007173803A - Thin film forming device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film forming device capable of simplifying a manufacturing process, contributing to shorter TAT or lower manufacturing cost. <P>SOLUTION: The thin film forming device comprises a first film forming chamber 33 for forming a polycrystal silicon film on a substrate, a second film forming chamber 34 for forming an insulating film on the polycrystal silicon film, and a third film forming chamber 35 for forming a conductive film on the insulating film. These three film forming chambers are provided in communication via a substrate transportation chamber 32, being airtight against atmosphere. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a thin film deposition apparatus, and more particularly to a thin film deposition apparatus for realizing the manufacture of a thin film transistor using a polycrystalline silicon film as a semiconductor layer that does not undergo annealing treatment after deposition.

  In an active matrix substrate that constitutes a liquid crystal display panel, a plurality of source lines and a plurality of gate lines are arranged in a matrix and are surrounded by two adjacent source lines and two adjacent gate lines Constitutes each pixel. Each pixel is provided with a pixel electrode, and a switching element for controlling signal writing to the pixel electrode is provided. As this switching element, a thin film transistor (hereinafter abbreviated as TFT) is frequently used. In particular, an example of a top gate TFT will be described below.

  As shown in FIG. 11, the top gate TFT includes an island-shaped semiconductor layer 105 having a source region 102, a drain region 104, and a channel region 103 on a transparent substrate 101, and a gate insulating film on the channel region 103. 106 is provided, and a gate electrode 107 is provided over the gate insulating film 106. An interlayer insulating film 108 is provided so as to cover the gate electrode 107 and the semiconductor layer 105, and a source electrode 110 connected to the source region 102 of the semiconductor layer 105 through the contact hole 109 is provided on the interlayer insulating film 108 and a contact is provided. A drain electrode 112 connected to the drain region 104 of the semiconductor layer 105 through the hole 111 is provided. When this TFT is used as a switching element for each pixel of the active matrix substrate, a passivation film 113 is provided on the interlayer insulating film 108 so as to cover the source electrode 110 and the drain electrode 112. A pixel electrode 115 connected to the drain electrode 112 through the contact hole 114 is provided.

In the TFT structure, as an example of a material constituting each layer, the semiconductor layer 105 is made of polycrystalline silicon (poly-Si), and the source electrode 110, the drain electrode 112, and the gate electrode 107 are made of a conductive metal material. The pixel electrode 115 is made of a transparent conductive film such as indium tin oxide (hereinafter abbreviated as ITO). Insulating films such as the gate insulating film 106 and the interlayer insulating film 108 are made of a silicon oxide film (SiO ₂ film), and the passivation film 113 is made of a silicon nitride film (SiN _x film). This TFT functions as a switching element by turning on and off the current flowing between the source and the drain by controlling the electric charge induced in the channel region 103 by the action of an electric field when a voltage is applied to the gate electrode 107.

As exemplified above, in recent years, in a TFT used as a switching element for an active matrix substrate or the like of a liquid crystal display panel, polycrystalline silicon has been frequently used as the semiconductor layer. The reason is that polycrystalline silicon has higher carrier mobility than amorphous silicon, and amorphous silicon has a mobility of about 0.3 to ¹ cm ² / V · sec, whereas polycrystalline silicon has a mobility. Is about 10 to 100 cm ² / V · sec. As described above, the so-called polycrystalline silicon TFT has the advantage that the carrier mobility is larger than that of the amorphous silicon TFT, so that the driving capability is large and high speed operation is possible.

  Incidentally, in the TFT manufacturing process, the polycrystalline silicon film forming the semiconductor layer has been formed through the following steps. First, an amorphous silicon film is formed on a substrate using a low pressure thermal CVD apparatus. At this time, since the structure of the amorphous silicon film contains hydrogen, subsequently, the substrate is heated using a thermal annealing apparatus such as an electric furnace type to perform dehydrogenation treatment of the amorphous silicon film. Thereafter, the amorphous silicon film after dehydrogenation was polycrystallized by using a gas laser annealing apparatus using a halogen gas such as XeCl, ArF, ArCl, XeF, etc. to convert the amorphous silicon film into a polycrystalline silicon film. . A technique for converting an amorphous silicon film into a polycrystalline silicon film is disclosed in, for example, Japanese Patent Application Laid-Open No. 10-242469.

  This method is a method of forming a polycrystalline silicon film generally called a solid phase growth method. In addition, although it is possible to directly form a polycrystalline silicon film by using a low pressure CVD method, a sputtering method, etc., conventionally, in the case of a polycrystalline silicon film directly formed in this way, the crystal grain size is small, The mobility did not increase too much. In view of this, a method was employed in which an amorphous silicon film was formed once at a relatively low temperature, and then a higher temperature heat treatment (annealing process) was applied to grow a polycrystalline silicon film having a crystal grain size of several μm. .

JP-A-10-242469

  However, in the conventional method for forming a polycrystalline silicon film, hydrogen-containing amorphous silicon (hereinafter referred to as hydrogenated amorphous silicon) is formed, the hydrogenated amorphous silicon film is dehydrogenated, and the amorphous silicon film is polycrystallized. The process and the film formation process are complicated, which causes an increase in TAT (Turn Around Time). In addition, the manufacturing cost has increased. Furthermore, when the substrate is transported between apparatuses, the substrate is exposed to the atmosphere, and there is a problem that a natural oxide film is formed on the surface of the substrate, or contaminants such as particles and organic matter are attached, There was a risk that the yield and reliability of the TFT would be reduced. Furthermore, when a natural oxide film removal process or a cleaning process is added to solve this problem, there is a problem that TAT is further deteriorated. As a manufacturing apparatus, a low-pressure thermal CVD apparatus, a thermal annealing apparatus, a laser annealing apparatus, and an expensive apparatus are separately required, leading to an increase in equipment costs and an increase in the space occupied by the apparatus in the manufacturing line.

  The present invention has been made to solve the above-mentioned problems, and can simplify the manufacturing process and realize a thin film formation that realizes a TFT manufacturing method that can contribute to shortening TAT and reducing manufacturing cost. An object is to provide a membrane device.

  The TFT manufacturing method related to the present invention includes a step of forming a polycrystalline silicon film on a substrate having at least an insulating surface, a step of forming an insulating film on the surface of the polycrystalline silicon film, and then an insulating film. A process of forming a conductive film on the surface, and then processing the conductive film into a gate electrode by subjecting the conductive film to a photolithography process and an etching process. An implantation process is performed, and then a photolithography process and an etching process are performed on the insulating film and the polycrystalline silicon film to process the polycrystalline silicon film into a semiconductor layer having a source region, a drain region, and a channel region, and the insulating film is polycrystalline And a step of remaining as a gate insulating film on the upper surface of the silicon film.

  In the conventional method for manufacturing a polycrystalline silicon TFT, after forming amorphous silicon, an annealing process is performed to polycrystallize amorphous silicon to form a semiconductor layer made of polycrystalline silicon. In polycrystalline silicon that has not been subjected to a heat treatment such as annealing directly after film formation (this polycrystalline silicon is hereinafter referred to as as-depo.polycrystalline silicon), the carrier mobility is not so high, and amorphous silicon. Because it was equivalent. On the other hand, as a result of intensive studies by the present applicant, the mobility does not reach 100 if the polycrystalline silicon film is formed by a specific film forming method, but the as-depo. It was discovered that polycrystalline silicon can provide a sufficiently large mobility compared to amorphous silicon.

  Therefore, a method of manufacturing a TFT related to the present invention is described in this as-depo. The polycrystalline silicon film is used as it is for the semiconductor layer of the TFT. First, a polycrystalline silicon film, an insulating film, and a conductive film are sequentially formed, and then the conductive film is processed into a gate electrode by performing a photolithography process and an etching process. Next, after the selective ion implantation process is performed on the polycrystalline silicon film, the insulating film and the polycrystalline silicon film are subjected to a photolithography process and an etching process so that the polycrystalline silicon film has a source region, a drain region, and a channel region. While processing into the semiconductor layer, the insulating film is left as a gate insulating film on the upper surface of the polycrystalline silicon film.

  According to this manufacturing method, since the annealing process conventionally performed after the amorphous silicon film formation is not required, the film formation process of the three layers of the polycrystalline silicon film, the insulating film, and the conductive film can be continuously performed. it can. Therefore, the TAT can be shortened and the manufacturing cost can be reduced as compared with the conventional method for manufacturing a polycrystalline silicon TFT in which an annealing process is essential.

  In the above-described TFT manufacturing method, the polycrystalline silicon film forming process, the insulating film forming process, and the conductive film forming process are described as being continuously performed. It is desirable to form a film continuously without exposure. According to this configuration, it is possible to avoid the conventional problem that a natural oxide film is formed on the surface of the substrate or a contaminant such as particles or organic substances adheres, so that the yield of TFT and the improvement of reliability are aimed at. be able to. Further, it is not necessary to add a natural oxide film removal process or a cleaning process during the film formation process.

  As described above, a sputtering method can be used as a method for forming a polycrystalline silicon film related to the present invention having a certain degree of mobility. In particular, it is desirable to use a dual frequency excitation sputtering method using helium gas as the sputtering gas. The “dual frequency excitation sputtering method” is a method in which high-frequency power is applied to both the upper electrode side holding the target and the lower electrode side holding the substrate to perform sputtering.

  An active matrix substrate related to the present invention includes a semiconductor layer made of a polycrystalline silicon film having a channel region interposed between a source region and a drain region, and a gate insulation made of an insulating film formed on the upper surface of the semiconductor layer. A thin film transistor having a film and a gate electrode made of a conductive film formed above the channel region with a gate insulating film interposed therebetween, and formed below the gate wiring made of the conductive film and connected to the gate electrode The polycrystalline silicon film and the insulating film are laminated in order from the bottom.

  The active matrix substrate related to the present invention is obtained by the above-described TFT manufacturing method. In the above-described TFT manufacturing method, after a polycrystalline silicon film, an insulating film, and a conductive film are stacked, only the conductive film is patterned to be processed into a gate electrode, and the insulating film and the polycrystalline silicon film are patterned to obtain polycrystalline silicon. The film is processed into a semiconductor layer and the insulating film is left as a gate insulating film on the upper surface of the polycrystalline silicon film. Therefore, the location of the gate wiring has to be the same laminated structure as the location of the TFT. That is, as-depo. Is below the gate wiring connected to the gate electrode. A structure in which a polycrystalline silicon film and an insulating film are sequentially stacked from the bottom is adopted. This wiring structure is unique when the above-described TFT manufacturing method is used.

  The thin film deposition apparatus of the present invention includes a first deposition chamber for depositing a polycrystalline silicon film on a substrate, a second deposition chamber for depositing an insulating film on the polycrystalline silicon film, and an insulating film. A third film formation chamber on which a conductive film is formed is connected to the atmosphere through the substrate transfer chamber so as to be kept airtight. By using this thin film forming apparatus, it is possible to continuously form a three-layer film of a polycrystalline silicon film, an insulating film, and a conductive film without exposing to the atmosphere. And rationalization of a film-forming apparatus can be achieved, and it can contribute to the reduction of equipment cost and the space-saving of a manufacturing line.

  Among the thin film deposition apparatuses described above, in particular, the first film formation chamber and the second film formation chamber have specific configurations, for example, the first film formation chamber is a sputter film formation chamber and the second film formation chamber. May be a plasma CVD film forming chamber, or a structure in which the first film forming chamber is a radial line slot antenna type plasma CVD film forming chamber and the second film forming chamber is a plasma CVD film forming chamber. it can.

  According to the present invention, as-depo. The polycrystalline silicon film is used as it is for the semiconductor layer of the TFT, and the annealing process conventionally performed after the amorphous silicon film formation is unnecessary, so that the three layers of the polycrystalline silicon film, the insulating film, and the conductive film are formed. Can be performed continuously. Therefore, the TAT can be shortened and the manufacturing cost can be reduced as compared with the conventional manufacturing method in which the annealing process is essential. In addition, when a polycrystalline silicon film, an insulating film, and a conductive film are continuously formed without exposing the substrate to the atmosphere, a natural oxide film is formed at the interface between these films, particles, organic substances, etc. Since contaminants do not adhere, yield and reliability can be improved. Further, the first film formation chamber, the second film formation chamber, and the third film formation chamber for forming the polycrystalline silicon film, the insulating film, and the conductive film, respectively, can be provided so that one film forming apparatus can be provided. This can contribute to reduction of equipment costs and space saving of the production line.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view showing the configuration of an active matrix substrate having TFTs obtained by the TFT manufacturing method of the present embodiment. This active matrix substrate constitutes one of the two substrates facing each other across the liquid crystal of the liquid crystal display panel, for example.

  As shown in FIG. 1, the active matrix substrate 1 includes a plurality of source lines 2 and a plurality of gate lines 3 arranged in a matrix, two adjacent source lines 2 and two adjacent gate lines 3. A region surrounded by is one pixel 4. Each pixel 4 is provided with a pixel electrode 5, and a switching element for controlling signal writing to the pixel electrode 5 is provided. This switching element is a TFT 6 having a top gate structure (also referred to as a forward stagger type).

  The cross-sectional structure of the TFT is shown on the right side of the broken line in FIG. 3G. The right side of the broken line in FIG. 3G is a cross-sectional view taken along the line RR in FIG. An island-like semiconductor layer 11 made of a polycrystalline silicon film having a source region 8 and a drain region 9 in which n-type impurities are diffused and a channel region 10 is formed on the upper surface of a transparent substrate 7 such as glass. A gate insulating film 12 is formed on the upper surface of the semiconductor layer 11, and a gate electrode 13 is formed above the channel region 10 via the gate insulating film 12. An interlayer insulating film 14 is formed so as to cover the gate electrode 13 and the semiconductor layer 11, and contact holes 15 and 16 penetrating the interlayer insulating film 14 and reaching the source region 8 and the drain region 9 of the semiconductor layer 11 are formed. Yes. A source electrode 17 electrically connected to the source region 8 of the semiconductor layer 11 is formed on the contact hole 15, and a drain electrically connected to the drain region 9 of the semiconductor layer 11 is formed on the contact hole 16. An electrode 18 is formed. Then, a passivation film 19 is formed on the interlayer insulating film 14 so as to cover the source electrode 17 and the drain electrode 18, and the pixel electrode 5 electrically connected to the drain electrode 18 through the contact hole 20 of the passivation film 19 is formed. ing.

  As shown in FIG. 1, the gate electrode 13 and the source electrode 17 of the TFT 6 of the present embodiment are formed integrally with the gate line 3 and the source line 2, and branch from the gate line 3 and the source line 2, respectively. It is a thing. In the present embodiment, for example, the gate insulating film 12 and the interlayer insulating film 14 are insulating films such as a silicon oxide film, the gate line 3 and the gate electrode 13, the source line 2, the source electrode 17 and the drain electrode 18 are a metal film such as aluminum. (Conductive film), the passivation film 19 is formed of an insulating film such as a silicon nitride film, and the pixel electrode 5 is formed of a transparent conductive film such as ITO.

  The cross-sectional structure of the gate line 3 is shown on the left side of the broken line in FIG. 3G. 3G is a cross-sectional view taken along line LL in FIG. 1. A polycrystalline silicon film 22, an insulating film 23, and a metal film 24 constituting the gate line 3 are laminated on the upper surface of the transparent substrate 7, and these three laminated films are covered with an interlayer insulating film 14 and a passivation film 19. The polycrystalline silicon film 22 constitutes the semiconductor layer 11 of the TFT 6, the insulating film 23 constitutes the gate insulating film 12 of the TFT 6, and the metal film 24 constitutes the gate electrode 13 of the TFT 6. Only the metal film 24 constitutes the gate line 3. When a conventional TFT manufacturing method is used, the gate wiring structure is such that only a gate line made of a metal film passes through a transparent substrate. However, the use of such a laminated gate wiring structure is unique to the present invention. Is.

  Next, the steps for manufacturing the active matrix substrate 1 are shown in FIGS. 2 and 3 which are process sectional views, FIGS. 4 and 5 which are process plan views, and FIGS. 6 to 10 which show the configuration of a thin film deposition apparatus. The description will be given with reference. In the process cross-sectional views of FIGS. 2 and 3, as described above, the right side of the break line indicates the TFT portion, and the left side of the break line indicates the gate line portion.

  First, as shown in FIG. 2A, on a transparent substrate 7 such as a glass substrate, a polycrystalline silicon film 22 that will later become the semiconductor layer 11 of the TFT 6, an insulating film 23 such as a silicon oxide film that will become the gate insulating film 12, a gate electrode A metal film 24 of aluminum or the like to be 13 is continuously formed.

  Here, a thin film deposition apparatus used when these three layers are continuously deposited will be described. FIG. 6 is a schematic configuration diagram showing a thin film deposition apparatus 31 according to the present embodiment. Three film deposition chambers 33, 34, 35, one loader chamber 36, and the like are disposed around a substantially pentagonal substrate transfer chamber 32. One unloader chamber 37 is continuously provided. The three film forming chambers are divided into a first film forming chamber 33 for forming the polycrystalline silicon film 22, a second film forming chamber 34 for forming the insulating film 23 such as a silicon oxide film, and a metal such as aluminum. A third film formation chamber 35 in which the film 24 is formed.

  Next, the configuration of each film forming chamber will be described. FIG. 7 is a diagram showing a schematic configuration of the first film forming chamber 33, and the first film forming chamber 33 is a two-frequency excitation type sputter film forming chamber for forming the polycrystalline silicon film 22.

  The first film forming chamber 33 shown in FIG. 7 has a chamber 39 that can be held in a reduced pressure state, and is connected to the side of the substrate transfer chamber 32 shown in FIG. . An upper electrode 41 is provided on the upper portion of the chamber 39, and a silicon target 42 is detachably mounted on the lower surface of the upper electrode 41. A lower electrode 43 is provided on the lower portion of the chamber 39, and the upper surface of the lower electrode 43 is transparent. A substrate 7 is detachably mounted. For mounting the silicon target 42 or the transparent substrate 7, known mounting means such as an electrostatic chuck is used.

  A first high-frequency power source 44 is connected to the upper electrode 41, and a matching circuit 45 is incorporated between the upper electrode 41 and the first high-frequency power source 44, so that a high-frequency reflected wave is zero. Has an effect. A DC power supply 47 is connected to the upper electrode 41 via a band pass filter 46 such as an impedance adjusting low pass filter. The band pass filter 46 adjusts the impedance of the circuit to infinity so that no high frequency is applied to the DC power supply 47. Further, a second high frequency power supply 48 is connected to the lower electrode 43, and a matching circuit 49 having the same effect as the matching circuit 45 is incorporated between the lower electrode 43 and the second high frequency power supply 48. ing. The first film forming chamber 33 includes an evacuation unit 50 for evacuation and gas evacuation, a gas supply mechanism 51 into the chamber 39, etc., but these are shown in a simplified manner in FIG.

  When the polycrystalline silicon film 22 is formed using the first film forming chamber 33, the inside of the chamber 39 is in a helium gas atmosphere, the silicon target 42 is mounted on the upper electrode 41, and the transparent substrate 7 is mounted on the lower electrode 43. In this state, high-frequency power is supplied to the upper electrode 41 from the first high-frequency power supply 44, load DC power is supplied from the DC power supply 47, and high-frequency power is supplied to the lower electrode 43 from the second high-frequency power supply 48. Thereby, the silicon target 42 is sputtered by helium ions, and the polycrystalline silicon film 22 is formed on the transparent substrate 7.

  As the first film forming chamber 33 for forming the polycrystalline silicon film 22, a radial line slot antenna type plasma CVD film forming chamber can be used instead of the above-described sputter film forming chamber. FIG. 9 shows a schematic configuration of a radial line slot antenna type plasma CVD film forming chamber 53, which is a microwave plasma excitation type film forming chamber provided with a radial line slot antenna 54 that radiates microwaves. FIG. 10 is a plan view of the radial line slot antenna 54.

  As shown in FIG. 9, a radial line slot antenna 54 is installed in the upper part of the chamber 55, and a susceptor 56 for supporting the transparent substrate 7 is installed in the lower part of the chamber 55 so as to face this. . Therefore, the upper part of the transparent substrate 7 becomes a plasma forming space 57, and microwaves are radiated from the radial line slot antenna 54 toward the plasma forming space 57. The surface of the radial line slot antenna 54 is provided with a number of slot holes for microwave radiation (not shown in FIG. 9), and 2.45 GHz microwaves generated by the microwave generation system 58 are guided. Power is supplied from the back side of the antenna 54 through the tube 59 and the coaxial waveguide converter 60.

In the radial line slot antenna 54, a microwave slow waveguide forming body 62 made of a dielectric material such as AlN or Al ₂ O ₃ is fixed to the lower surface of a disk-shaped conductor 61, and the lower surface of the slow waveguide forming body 62 is fixed. A slot body 64 made of a metal plate such as aluminum having a large number of slot holes 63 is arranged. Furthermore, a pressing body 65 made of a dielectric material such as AlN or Al ₂ O ₃ having a property of transmitting microwaves is fixed to the lower surface of the slot body 64. The pressing body 65 is fixed to the conductor 61 by a screw 66 at the peripheral edge thereof. Therefore, the slot body 64 is fixed in a state of being sandwiched between two dielectric plates forming the slow waveguide forming body 62 and the pressing body 65. Has been.

  The planar arrangement of the slot holes 63 of the radial line slot antenna 54 is as shown in FIG. 10, and a number of pairs of slot holes 63 are arranged concentrically, and microwaves are radiated from the slot holes 63 into the space. The In addition, the code | symbol 67 in FIG. 10 is a screw hole. Further, a cooling pipe (not shown) for flowing cooling water for preventing heating by microwave power feeding is inserted into the conductor 61 of the radial line slot antenna 54.

  As shown in FIG. 9, a gas introduction port 68 is provided at the peripheral edge of the upper portion of the chamber 55, and a reaction gas supplied from a reaction gas supply source (not shown) passes through a pipe 69 to form a plasma formation space 57 in the chamber 55. To be supplied. On the other hand, an exhaust port 70 is provided in the lower part of the chamber 55, and the inside of the chamber 55 is decompressed by a vacuum exhaust source (not shown) such as a vacuum pump connected to the exhaust port 70. Further, a load lock chamber 71 for carrying the transparent substrate 7 in and out of the chamber transfer chamber 32 without opening the chamber 55 to the atmosphere is provided on the side of the chamber 55.

In the radial line slot antenna type plasma CVD film forming chamber 53 having the above-described configuration, a reaction gas required for film formation, such as SiH ₄ and PH ₃ , is supplied into the chamber 55 from the gas introduction port 68. Then, plasma is generated in the plasma formation space 57 by the 2.45 GHz microwaves radiated from the radial line slot antenna 54, and the radicals generated by the dissociation of the reaction gas cause a chemical reaction on the substrate surface. A film 22 is formed.

  FIG. 8 is a diagram showing a schematic configuration of the second film forming chamber 34. The second film forming chamber 34 is a two-frequency excitation type plasma CVD film forming chamber for forming an insulating film 23 such as a silicon oxide film. is there.

  As shown in FIG. 8, a high frequency electrode 75 and a shower plate 76 are provided on the upper portion of the chamber 74, and a susceptor electrode 77 on which the transparent substrate 7 is placed is provided on the lower portion of the chamber 74 so as to face the shower plate 76. Yes. The high-frequency electrode 75 is connected to a first high-frequency power source 81 via a high-frequency electrode side matching box 80 in which a matching circuit 79 is housed inside a housing 78 made of a conductor. In addition, a space 82 is formed by the high-frequency electrode 75 and the shower plate 76, and a gas introduction pipe 83 for introducing a reaction gas into the space 82 is provided. The reaction gas introduced into the space 82 through the gas introduction pipe 83 is supplied into the chamber 74 through a large number of holes 76 a of the shower plate 76. Reference numeral 84 denotes an insulator that insulates the wall portion of the chamber 74 from the high-frequency electrode 75.

  A susceptor shield 85 is provided around the susceptor electrode 77, and the susceptor electrode 77 and the susceptor shield 85 are configured to be movable up and down by a bellows 86. With this configuration, the distance between the high-frequency electrode 75 and the susceptor electrode 77 can be adjusted. The susceptor electrode 77 is connected to a second high frequency power supply 88 via a susceptor electrode side matching box 87 in which a matching circuit is housed.

  The high frequency electrode side matching box 80 is provided with a matching circuit 79 for matching the impedance between the first high frequency power supply 81 and the high frequency electrode 75 inside the housing 78, and the high frequency power from the first high frequency power supply 81 is provided. Is supplied to the high-frequency electrode 75 via the power supply line 89 via the matching circuit 79. The configuration of the matching circuit 79 is such that a coil 90 and a tuning capacitor 91 are connected in series to a first high-frequency power source 81, a load capacitor 92 is connected in parallel, and one end is grounded. Then, by adjusting the capacitance of the tuning capacitor 91, the impedance between the first high frequency power supply 81 and the high frequency electrode 75 is adjusted.

  The side wall of the housing 78 of the high frequency electrode side matching box 80 is formed non-parallel to the power supply line 89. As a result, the flow direction of the forward current and the backward current of the high-frequency current that flows during power feeding becomes non-parallel, and an increase in mutual inductance can be prevented. As a result, the power consumption efficiency in the second film forming chamber 34 is greatly improved, and the silicon oxide film forming speed can be increased and the film quality can be improved.

  When the silicon oxide film is formed in the second film formation chamber 34 having the above-described configuration, the transparent substrate 7 is placed on the susceptor electrode 77, and the high frequency electrode 75 is supplied from the first and second high frequency power supplies 81 and 88. A high frequency power is applied to both the susceptor electrode 77 and a reactive gas containing monosilane or the like from the gas introduction pipe 83 through the shower plate 76 into the chamber 74 to generate plasma, and silicon is formed on the transparent substrate 7. An oxide film is formed.

  The third film forming chamber 35 is a sputter film forming chamber for forming a general metal film such as aluminum, and a description of the third film forming chamber 35 is omitted because it may be configured by a very general sputtering apparatus. Of course, the same configuration as that of the first film forming chamber 33 may be used.

  A loader cassette (not shown) and an unloader cassette (not shown) are detachably provided in the loader chamber 36 and the unloader chamber 37 shown in FIG. These two cassettes can accommodate a plurality of transparent substrates 7, the substrate 7 before film formation is accommodated in the loader cassette, and the film-formed substrate 7 is accommodated in the unloader cassette. A substrate transfer robot 94 is installed in the substrate transfer chamber 32 located at the center of the three film forming chambers 33, 34, 35, the loader chamber 36 and the unloader chamber 37. The substrate transport robot 94 has an arm 95 having a telescopic link mechanism at the upper part thereof. The arm 95 is rotatable and can be lifted and lowered, and the substrate 7 is supported and transported by the tip of the arm 95. ing.

  The thin film deposition apparatus 31 having the above-described configuration is such that the operation of each unit is controlled by a control unit (not shown) except that the operator sets various processing conditions and processing sequences such as film deposition conditions in the respective film deposition chambers 33, 34, and 35. ) And is configured to automatically operate. Therefore, when the thin film deposition apparatus 31 is used, the substrate 7 before processing is set in the loader cassette, and if the operator operates the start switch, the substrate transfer robot 94 causes the deposition chambers 33, The substrate 7 is transported into 34 and 35, and a series of film forming processes of forming a polycrystalline silicon film, forming a silicon oxide film, and forming an aluminum film in each of the film forming chambers 33, 34, and 35 are automatically performed in sequence. Then, the substrate is transferred to the unloader cassette by the substrate transfer robot 94.

  At that time, a load lock chamber, a gate valve, and the like are installed between the film forming chambers 33, 34, and 35, the loader chamber 36, the unloader chamber 37, and the substrate transfer chamber 32, and an airtight state is maintained with respect to the atmosphere. The substrate 7 once introduced into the thin film deposition apparatus 31 is deposited without being exposed to the atmosphere at all. Therefore, a natural oxide film does not grow on the interface of the three layers of the polycrystalline silicon film, the insulating film, and the metal film, and particles and contaminants do not enter, and a clean interface can be obtained.

  Next, after the continuous deposition of the three layers of the polycrystalline silicon film 22, the insulating film 23, and the metal film 24 is completed, the gate lines 3 and the gate electrodes 13 are formed by photolithography as shown in FIG. 2B. A resist pattern (not shown) is formed, and an etching process is performed using an etchant capable of etching only the metal film 24, whereby only the uppermost metal film 24 is patterned to form the gate line 3 and the gate electrode 13. To do. At this time, the planar shape is as shown in FIG. 4B. Similarly, FIG. 4D is a plan view at the time of FIG. 2D, FIG. 5F is FIG. 3F, and FIG.

  Next, as shown in FIG. 2C, n-type impurities such as phosphorus and arsenic are ion-implanted from above the gate line 3 and the gate electrode 13, thereby forming the gate line 3 and the gate electrode 13 in the polycrystalline silicon film 22. A region excluding the region below (the region that becomes the channel region 10) is referred to as an n-type impurity diffusion region 25. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 2D, a resist pattern (not shown) having an island shape of the semiconductor layer 11 is formed by photolithography, and an etchant capable of etching the insulating film 23 and the polycrystalline silicon film 22 is formed. By using the etching process, the insulating film 23 and the polycrystalline silicon film 22 are patterned to form the semiconductor layer 11 having the source region 8 and the drain region 9. Here, a channel region 10 is formed between the source region 8 and the drain region 9. The insulating film 23 remains on the upper surface of the semiconductor layer 11 with the same shape as that of the semiconductor layer 11 and becomes the gate insulating film 12. The gate line 3 is in a state in which three layers of a polycrystalline silicon film 22, an insulating film 23, and a metal film 24 are stacked from below. The planar shape is as shown in FIG. 4D. In the portion of the gate line 3, the laminated film of three layers extends linearly, and in the portion of the semiconductor layer 11 of the TFT 6, the two layers of the polycrystalline silicon film 22 and the insulating film 23 protrude outward in the direction perpendicular to the gate line 3. It becomes a shape.

  The following steps are the same as the conventional manufacturing process. As shown in FIG. 3E, an interlayer insulating film 14 made of a silicon oxide film is formed on the entire surface. Next, the interlayer insulating film 14 is patterned by photolithography and etching to form contact holes 15 and 16 that reach the source region 8 and the drain region 9 of the semiconductor layer 11, respectively.

  Next, as shown in FIGS. 3F and 5F, a metal film such as Al is formed on the entire surface, and this is patterned to form the source line 2, the source electrode 17, and the drain electrode 18, respectively.

  Next, as shown in FIGS. 3G and 5G, after a passivation film 19 made of a silicon nitride film is formed on the entire surface, the passivation film 19 is patterned by a photolithography process and an etching process to reach the drain electrode 18. 20 is formed. Next, a transparent conductive film such as ITO is formed on the entire surface, and patterning is performed by photolithography and etching, thereby forming the pixel electrode 5. Through the above steps, the active matrix substrate 1 having the TFT 6 connected to the pixel electrode 5 is completed.

  The manufacturing method in the present embodiment is as-depo. Since the polycrystalline silicon film is used as it is for the semiconductor layer 11 of the TFT 6 and the annealing process conventionally performed after the amorphous silicon film formation is not required, the polycrystalline silicon film 22, the insulating film 23, and the metal film 24 are formed. The layers can be continuously formed. Therefore, the TAT can be shortened and the manufacturing cost can be reduced as compared with the conventional manufacturing method in which the annealing process is essential.

  Further, since the polycrystalline silicon film 22, the insulating film 23, and the metal film 24 are continuously formed without exposing the substrate to the atmosphere, a natural oxide film is formed at the interface between these films, The conventional problem of adhering contaminants such as particles and organic matter can be avoided. As a result, TFT yield and reliability can be improved.

  A thin film deposition apparatus provided with a first deposition chamber 33, a second deposition chamber 34, and a third deposition chamber 35 for depositing the polycrystalline silicon film 22, the insulating film 23, and the metal film 24, respectively. Since 31 is used, a single film forming apparatus can be provided, which can contribute to reduction of equipment costs and space saving of a production line.

  The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the specific types of films constituting each part of the TFT, the specific configuration of the thin film forming apparatus, and the like can be appropriately changed.

  The present invention can be widely applied to the manufacture of thin film transistors.

It is a top view which shows the structure of the active matrix substrate which has TFT obtained by the manufacturing method of TFT in one embodiment of this invention. FIG. 6 is a process cross-sectional view illustrating the TFT manufacturing method in order. It is a continuation of the process cross-sectional view. FIG. 6 is a process plan view illustrating the TFT manufacturing method in order. It is a continuation of the process plan view. It is a schematic block diagram which shows the thin film film-forming apparatus by one embodiment of this invention. It is a schematic block diagram which shows the 1st film-forming chamber of a thin film film-forming apparatus similarly. It is a schematic block diagram which shows a 2nd film-forming chamber. It is a schematic block diagram which shows the other example of a 1st film-forming chamber same as the above. FIG. 6 is a plan view of a radial line slot antenna used in another example of the first film formation chamber. It is sectional drawing which shows one structural example of the conventional top gate type TFT.

Explanation of symbols

1 active matrix substrate, 2 source line, 3 gate line, 6 thin film transistor (TFT), 7 transparent substrate, 8 source region, 9 drain region, 10 channel region, 11 semiconductor layer, 12 gate insulating film, 13 gate electrode, 17 source Electrode, 18 Drain electrode, 22 Polycrystalline silicon film, 23 Insulating film, 24 Metal film (conductive film), 31 Thin film deposition apparatus, 32 Substrate transfer chamber, 33 First deposition chamber, 34 Second deposition chamber, 35 Third deposition chamber

Claims (3)

A first film formation chamber for forming a polycrystalline silicon film on the substrate, a second film formation chamber for forming an insulating film on the polycrystalline silicon film, and a conductive film on the insulating film And a third film forming chamber connected to the atmosphere through the substrate transfer chamber so as to be kept airtight. 2. The thin film deposition apparatus according to claim 1, wherein the first deposition chamber is a sputter deposition chamber and the second deposition chamber is a plasma CVD deposition chamber. 2. The thin film deposition apparatus according to claim 1, wherein the first deposition chamber is a radial line slot antenna type plasma CVD deposition chamber, and the second deposition chamber is a plasma CVD deposition chamber. .

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